Data Sheet
AD5259
Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer
FEATURES
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FUNCTIONAL BLOCK DIAGRAMS
Nonvolatile memory maintains wiper settings
256-position
Thin LFCSP-10 (3 mm x 3 mm x 0.8 mm) package
Compact MSOP-10 (3 mm × 4.9 mm × 1.1 mm) package
I2C-compatible interface
VLOGIC pin provides increased interface flexibility
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEPROM (0.1% accuracy)
Power-on EEPROM refresh time < 1ms
Software write protect command
Address Decode Pin AD0 and Pin AD1 allow 4 packages per bus
100-year typical data retention at 55°C
Wide operating temperature −40°C to +125°C
3 V to 5 V single supply
Figure 1. Block Diagram
APPLICATIONS
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LCD panel VCOM adjustment
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
Fiber to the home systems
Electronics level settings
Figure 2. Block Diagram Showing Level Shifters
CONNECTION DIAGRAM
Figure 3. Pinout
GENERAL DESCRIPTION
The AD5259 provides a compact, nonvolatile LFCSP-10 (3 mm ×
3 mm) or MSOP-10 (3 mm × 4.9 mm) packaged solution for
256-position adjustment applications. These devices perform the
same electronic adjustment function as mechanical potentiometers
or variable resistors, but with enhanced resolution and solid-state
reliability. The terms digital potentiometer, VR (variable resistor),
and RDAC are used interchangeably.
The wiper settings are controllable through an I2C‑compatible digital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM, providing an end-to-end tolerance accuracy of 0.1%.
A separate VLOGIC pin delivers increased interface flexibility. For
users who need multiple parts on one bus, Address Bit AD0 and
Address Bit AD1 allow up to four devices on the same bus.
Rev. E
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
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change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
AD5259
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagrams....................................1
Connection Diagram..............................................1
General Description...............................................1
Specifications........................................................ 3
Electrical Characteristics.................................... 3
Timing Characteristics........................................4
Absolute Maximum Ratings...................................6
ESD Caution.......................................................6
Pin Configuration and Function Descriptions........ 7
Typical Performance Characteristics..................... 8
Test Circuits......................................................... 13
Theory of Operation.............................................14
Programming the Variable Resistor..................14
Programming the Potentiometer Divider.......... 14
2
I C-Compatible Interface..................................... 15
Writing.............................................................. 15
Storing/Restoring..............................................15
Reading............................................................ 15
I2C-Compatible Format........................................16
Generic Interface..............................................16
Write Modes..................................................... 16
Read Modes..................................................... 17
Store/Restore Modes....................................... 17
Tolerance Readback Modes.............................17
ESD Protection of Digital Pins and Resistor
Terminals........................................................ 18
Power-Up Sequence........................................ 18
Layout and Power Supply Bypassing ..............19
Multiple Devices on One Bus........................... 19
Evaluation Board.............................................. 19
Display Applications............................................ 20
Circuitry............................................................ 20
Outline Dimensions............................................. 21
Ordering Guide.................................................21
RAB (Ω) Options................................................22
Evaluation Boards............................................ 22
REVISION HISTORY
10/2022—Rev. D to Rev. E
Changes to Table 2.......................................................................................................................................... 4
5/2022—Rev. C to Rev. D
Updated Outline Dimensions......................................................................................................................... 21
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Rev. E | 2 of 22
Data Sheet
AD5259
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
DC CHARACTERISTICS: RHEOSTAT MODE
Resistor Differential Nonlinearity
R-DNL
RWB, VA = no connect
Min
Typ1
Max
LSB
5 kΩ
–1
±0.2
+1
10 kΩ
−1
±0.1
+1
−0.5
±0.1
+0.5
50 kΩ/100 kΩ
Resistor Integral Nonlinearity
R-INL
RWB, VA = no connect
LSB
5 kΩ
–4
±0.3
+4
10 kΩ
−2
±0.2
+2
−1
±0.4
+1
50 kΩ/100 kΩ
Nominal Resistor Tolerance
Resistance Temperature Coefficient
Total Wiper Resistance
DC CHARACTERISTICS: POTENTIOMETER
DIVIDER MODE
Differential Nonlinearity
ΔRAB
(ΔRAB × 106)/(RAB
× ΔT)
RWB
TA = 25°C, VDD = 5.5 V
–30
+30
Code = 0x00/0x80
500/15
Code = 0x00
75
350
DNL
–1
±0.2
+1
−0.5
±0.1
+0.5
−0.5
±0.2
+0.5
50 kΩ/100 kΩ
INL
LSB
5 kΩ
–1
±0.2
+1
10 kΩ
−0.5
±0.1
+0.5
−0.5
±0.1
+0.5
50 kΩ/100 kΩ
VWFSE
Ω
LSB
10 kΩ
Full-Scale Error
%
ppm/°C
5 kΩ
Integral Nonlinearity
Unit
Code = 0xFF
LSB
5 kΩ
−7
−3
0
10 kΩ
−4
−1.5
0
−1
−0.4
0
0
2.5
4
LSB
6
LSB
3
LSB
4
LSB
50 kΩ/100 kΩ
Zero-Scale Error
VWZSE
5 kΩ
Code = 0x00
−40°C < TA < +85°C
+85°C < TA < +125°C
10 kΩ
−40°C < TA < +85°C
0
1
+85°C < TA < +125°C
50 kΩ/100 kΩ
Voltage Divider Temperature Coefficient
0
(∆VW × 106)/(VW ×
∆T)
Code = 0x00/0x80
0.2
0.5
60/5
LSB
ppm/°C
RESISTOR TERMINALS
Voltage Range
VA, B, W
Capacitance A, B
CA, B
f = 1 MHz, measured to GND, code =
0x80
45
pF
Capacitance W
CW
f = 1 MHz, measured to GND, code =
0x80
60
pF
Common-Mode Leakage
ICM
VA = VB = VDD/2
10
nA
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GND
VDD
V
Rev. E | 3 of 22
Data Sheet
AD5259
SPECIFICATIONS
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
0.7 × VL
VL + 0.5
V
Input Logic Low
VIL
−0.5
0.3 × VL
V
Leakage Current
IIL
µA
SDA, AD0, AD1
VIN = 0 V or 5 V
SCL – Logic High
VIN = 0 V
SCL – Logic Low
Input Capacitance
−2.5
VIN = 5 V
CIL
0.01
±1
−1.3
+1
0.01
±1
5
pF
POWER SUPPLIES
Power Supply Range
VDD
Positive Supply Current
IDD
Logic Supply
VLOGIC
Logic Supply Current
ILOGIC
2.7
0.1
2.7
5.5
V
2
µA
5.5
V
VIH = 5 V or VIL = 0 V
−40°C < TA < +85°C
3
+85°C < TA < +125°C
6
µA
9
µA
Programming Mode Current (EEPROM)
ILOGIC(PROG)
VIH = 5 V or VIL = 0 V
35
Power Dissipation
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
15
40
mA
µW
Power Supply Rejection Ratio
PSRR
VDD = +5 V ± 10%, code = 0x80
±0.005
±0.06
%/%
BW
Code = 0x80
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB
1
Total Harmonic Distortion
THDW
VW Settling Time
tS
Resistor Noise Voltage Density
eN_WB
RAB = 5 kΩ
2000
kHz
RAB = 10 kΩ
800
kHz
RAB = 50 kΩ
160
kHz
RAB = 100 kΩ
RAB = 10 kΩ, VA = 1 V rms, VB = 0,
f = 1 kHz
RAB = 10 kΩ, VAB = 5 V, ±1 LSB error
band
RWB = 5 kΩ, f = 1 kHz
80
kHz
0.01
%
500
ns
9
nV/√Hz
Typical values represent average readings at 25°C and VDD = 5 V.
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
400
kHz
I2C INTERFACE TIMING CHARACTERISTICS1
SCL Clock Frequency
fSCL
tBUF Bus Free Time Between Stop and Start
t1
tHD;STA Hold Time (Repeated Start)
t2
0
After this period, the first clock pulse is generated.
1.3
µs
0.6
µs
tLOW Low Period of SCL Clock
t3
1.3
µs
tHIGH High Period of SCL Clock
t4
0.6
µs
tSU;STA Setup Time for Repeated Start Condition
t5
0.6
tHD;DAT Data Hold Time
t6
0
analog.com
µs
0.9
µs
Rev. E | 4 of 22
Data Sheet
AD5259
SPECIFICATIONS
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
300
ns
300
ns
tSU;DAT Data Setup Time
t7
tF Fall Time of Both SDA and SCL Signals
t8
100
ns
tR Rise Time of Both SDA and SCL Signals
t9
tSU;STO Setup Time for Stop Condition
t10
EEPROM Data Storing Time2
tEEMEM_STORE
26
ms
EEPROM Data Restoring Time at Power-On3
tEEMEM_RESTORE1
VDD rise time dependent. Measure without decoupling
capacitors at VDD and GND.
300
µs
EEPROM Data Restoring Time upon Restore
Command3
tEEMEM_RESTORE2
VDD = 5 V.
300
µs
EEPROM Data Rewritable Time4
tEEMEM_REWRITE
540
µs
0.6
µs
FLASH/EE MEMORY RELIABILITY
Endurance5
100
Data Retention6
1
Standard I2C mode operation guaranteed by design.
2
No I2C transaction must take place during the EEPROM data storing time to guarantee that every I2C transaction is executed.
3
During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
4
Delay time after power-on PRESET prior to writing new EEPROM data.
700
kCycles
100
Years
5
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +125°C; typical endurance at +25°C is 700,000 cycles.
6
Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with
junction temperature.
Figure 4. I2C Interface Timing Diagram
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Rev. E | 5 of 22
Data Sheet
AD5259
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Value
VDD, VLOGIC to GND
−0.3 V to +7 V
VA, VB, VW to GND
GND − 0.3 V, VDD + 0.3 V
IMAX
Pulsed1
±20 mA
Continuous
±5 mA
Digital Inputs and Output Voltage to GND
0 V to 7 V
Operating Temperature Range
−40°C to +125°C
Maximum Junction Temperature (TJMAX)
150°C
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance2 θJA: MSOP-10
−65°C to +150°C
300°C
200°C/W
1
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.
2
Package power dissipation = (TJMAX – TA)/θJA.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
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Rev. E | 6 of 22
Data Sheet
AD5259
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin
Mnemonic
Description
1
W
W Terminal, GND ≤ VW ≤ VDD.
2
ADO
Programmable Pin 0 for Multiple Package Decoding. State is registered on power-up.
3
AD1
Programmable Pin 1 for Multiple Package Decoding. State is registered on power-up.
4
SDA
Serial Data Input/Output.
5
SCL
Serial Clock Input. Positive edge triggered.
6
VLOGIC
Logic Power Supply.
7
GND
Digital Ground.
8
VDD
Positive Power Supply.
9
B
B Terminal, GND ≤ VB ≤ VDD.
10
A
A Terminal, GND ≤ VA ≤ VDD.
11
EPAD
Exposed Pad. The exposed pad should be connected to GND or left floating.
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Rev. E | 7 of 22
Data Sheet
AD5259
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = VLOGIC = 5.5 V, RAB = 10 kΩ, TA = +25°C; unless otherwise noted.
analog.com
Figure 6. R-INL vs. Code vs. Supply Voltage
Figure 9. DNL vs. Code vs. Temperature
Figure 7. R-DNL vs. Code vs. Supply Voltage
Figure 10. INL vs. Supply Voltages
Figure 8. INL vs. Code vs. Temperature
Figure 11. DNL vs. Code vs. Supply Voltage
Rev. E | 8 of 22
Data Sheet
AD5259
TYPICAL PERFORMANCE CHARACTERISTICS
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Figure 12. R-INL vs. Code vs. Temperature
Figure 15. Zero-Scale Error vs. Temperature
Figure 13. R-DNL vs. Code vs. Temperature
Figure 16. Supply Current vs. Temperature
Figure 14. Full-Scale Error vs. Temperature
Figure 17. Logic Supply Current vs. Temperature vs. VDD
Rev. E | 9 of 22
Data Sheet
AD5259
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 18. Rheostat Mode Tempco (ΔRAB × 106)/(RAB × ΔT) vs. Code
Figure 21. Total Resistance vs. Temperature
Figure 19. Potentiometer Mode Tempco (ΔVW × 106)/(VW × ΔT) vs. Code
Figure 22. Gain vs. Frequency vs. Code, RAB = 5 kΩ
Figure 20. RWB vs. Temperature
Figure 23. Gain vs. Frequency vs. Code, RAB = 10 kΩ
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Rev. E | 10 of 22
Data Sheet
AD5259
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 24. Gain vs. Frequency vs. Code, RAB = 50 kΩ
Figure 27. Logic Supply Current vs. Input Voltage
Figure 25. Gain vs. Frequency vs. Code, RAB = 100 kΩ
Figure 28. PSRR vs. Frequency
Figure 26. −3 dB Bandwidth @ Code = 0x80
Figure 29. Digital Feedthrough
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Rev. E | 11 of 22
Data Sheet
AD5259
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 30. Midscale Glitch, Code 0x7F to 0x80
Figure 31. Large Signal Settling Time
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Rev. E | 12 of 22
Data Sheet
AD5259
TEST CIRCUITS
Figure 32 through Figure 37 illustrate the test circuits that define the test conditions used in the product Specifications tables.
Figure 32. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 36. Test Circuit for Gain vs. Frequency
Figure 33. Test Circuit for Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 37. Test Circuit for Common-Mode Leakage Current
Figure 34. Test Circuit for Wiper Resistance
Figure 35. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
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Rev. E | 13 of 22
Data Sheet
AD5259
THEORY OF OPERATION
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A produces a digitally
controlled complementary resistance, RWA. The resistance value
setting for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value.
The general equation for this operation is
The AD5259 is a 256-position digitally-controlled variable resistor
(VR) device. EEPROM is pre-loaded at midscale from the factory,
and initial power-up is, accordingly, at midscale.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance (RAB) of the RDAC between Terminal A and
Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The
nominal resistance of the VR has 256 contact points accessed by
the wiper terminal. The 8-bit data in the RDAC latch is decoded to
select one of 256 possible settings.
RWA(D) =
256 − D
256
× RAB + 2 × RW
(2)
Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. For this reason, resistance tolerance is
stored in the EEPROM, enabling the user to know the actual RAB
within 0.1%.
PROGRAMMING THE POTENTIOMETER
DIVIDER
Voltage Output Operation
Figure 38. Rheostat Mode Configuration
The general equation determining the digitally programmed output
resistance between Wiper W and Terminal B is
RWB(D) =
D
256
× RAB + 2 × RW
The digital potentiometer easily generates a voltage divider at
Wiper W to Terminal B and Wiper W to Terminal A proportional to
the input voltage at Terminal A to Terminal B. Unlike the polarity of
VDD to GND, which must be positive, voltage across Terminal A to
Terminal B, Wiper W to Terminal A, and Wiper W to Terminal B can
be at either polarity.
(1)
where:
D is the decimal equivalent of the binary code loaded in the 8‑bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the ON resistance of each
internal switch.
Figure 40. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at Wiper W to Terminal B starting at 0 V
up to 1 LSB less than 5 V. The general equation defining the output
voltage at VW with respect to ground for any valid input voltage
applied to Terminal A and Terminal B is
VW(D) =
D
256 VA
VW(D) =
RWB(D)
RAB VA
+
256 − D
256 VB
(3)
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
Figure 39. AD5259 Equivalent RDAC Circuit
+
RWA(D)
RAB VB
(4)
Operation of the digital potentiometer in the divider mode results
in a more accurate operation over temperature. Unlike the rheostat
mode, the output voltage is dependent mainly on the ratio of the
Internal Resistors RWA and RWB and not the absolute values.
In the zero-scale condition, there is a relatively low value finite
wiper resistance. Care should be taken to limit the current flow
between Wiper W and Terminal B in this state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation or
destruction of the internal switch contact can occur.
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Rev. E | 14 of 22
Data Sheet
AD5259
I2C-COMPATIBLE INTERFACE
The master initiates data transfer by establishing a start condition,
which is when a high-to-low transition on the SDA line occurs while
SCL is high (see Figure 4). The next byte is the slave address byte,
which consists of the slave address (first 7 bits) followed by an R/W
bit (see Table 6). When the R/W bit is high, the master reads from
the slave device. When the R/W bit is low, the master writes to the
slave device.
The slave address of the part is determined by two configurable
address pins, Pin AD0 and Pin AD1. The state of these two pins
is registered upon power-up and decoded into a corresponding I2C
7-bit address (see Table 5). The slave address corresponding to
the transmitted address bits responds by pulling the SDA line low
during the ninth clock pulse (this is termed the slave acknowledge
bit). At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read from, its
serial register.
WRITING
In the write mode, the last bit (R/W) of the slave address byte is
logic low. The second byte is the instruction byte. The first three
bits of the instruction byte are the command bits (see Table 6). The
user must choose whether to write to the RDAC register, EEPROM
register, or activate the software write protect (see Table 7 to Table
10). The final five bits are all zeros (see Table 13 to Table 14). The
slave again responds by pulling the SDA line low during the ninth
clock pulse.
The final byte is the data byte MSB first. With the write protect
mode, data is not stored; rather, a logic high in the LSB enables
write protect. Likewise, a logic low disables write protect. The slave
again responds by pulling the SDA line low during the ninth clock
pulse.
STORING/RESTORING
In this mode, only the address and instruction bytes are necessary.
The last bit (R/W) of the address byte is logic low. The first three
bits of the instruction byte are the command bits (see Table 6). The
two choices are transfer data from RDAC to EEPROM (store), or
from EEPROM to RDAC (restore). The final five bits are all zeros
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(see Table 13 to Table 14). In addition, users should issue an NOP
command immediately after restoring the EEMEM setting to RDAC,
thereby minimizing supply current dissipation.
READING
Assuming the register of interest was not just written to, it is necessary to write a dummy address and instruction byte. The instruction
byte will vary depending on whether the data that is wanted is the
RDAC register, EEPROM register, or tolerance register (see Table
11 and Table 17).
After the dummy address and instruction bytes are sent, a repeat
start is necessary. After the repeat start, another address byte
is needed, except this time the R/W bit is logic high. Following
this address byte is the readback byte containing the information
requested in the instruction byte. Read bits appear on the negative
edges of the clock.
The tolerance register can be read back individually (see Table 15)
or consecutively (see Table 17). Refer to the Read Modes section
for detailed information on the interpretation of the tolerance bytes.
After all data bits have been read or written, a stop condition
is established by the master. A stop condition is defined as a
low-to-high transition on the SDA line while SCL is high. In write
mode, the master pulls the SDA line high during the tenth clock
pulse to establish a stop condition (see Figure 46). In read mode,
the master issues a no acknowledge for the ninth clock pulse (that
is, the SDA line remains high). The master then brings the SDA
line low before the tenth clock pulse, and then raises SDA high to
establish a stop condition (see Figure 47).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowledged
its slave address and instruction bytes in the write mode, the RDAC
output is updated on each successive byte until a stop condition is
received. If different instructions are needed, the write/read mode
has to start again with a new slave address, instruction, and data
byte. Similarly, a repeated read function of the RDAC is also
allowed.
Rev. E | 15 of 22
Data Sheet
AD5259
I2C-COMPATIBLE FORMAT
The following generic, write, read, and store/restore control registers for the AD5259 all refer to the device addresses listed in Table
5; the mode/condition reference key (S, P, SA, MA, NA, W, R, and
X) is listed below.
R = Read
S = Start Condition
Table 5. Device Address Lookup
P = Stop Condition
AD1 Address Pin
AD0 Address Pin
I2C Device Address
0
0
0011000
1
0
0011010
0
1
1001100
1
1
1001110
X = Don’t Care
AD1 and AD0 are two-state address pins.
SA = Slave Acknowledge
MA = Master Acknowledge
NA = No Acknowledge
W = Write
GENERIC INTERFACE
Table 6. Generic Interface Format
7-Bit Device Address
S
(See Table 5)
R/W
SA
Slave Address Byte
C2
C1
C0
A4
A3
A2
A1
A0
Instruction Byte
SA
D7
D6
D5
D4
D3
D2
D1
D0
SA
P
Data Byte
Table 7. RDAC-to-EEPROM Interface Command Descriptions
C2
C1
C0
Command Description
0
0
0
Operation Between Interface and RDAC.
0
0
1
Operation Between Interface and EEPROM.
0
1
0
Operation Between Interface and Write Protection Register. See Table 10.
1
0
0
NOP.
1
0
1
Restore EEPROM to RDAC.1
1
1
0
Store RDAC to EEPROM.
1
This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.
WRITE MODES
Table 8. Writing to RDAC Register
7-Bit Device Address
S (See Table 5)
0
Slave Address Byte
Table 9. Writing to EEPROM Register
7-Bit Device Address
S (See Table 5)
Slave Address Byte
SA 0
0
0
0
0
0
0
Instruction Byte
0
SA 0
0
1
1
0
Instruction Byte
SA D7
D6
D5
D4
D3
D2
D1
D0
SA P
D5
D4
D3
D2
D1
D0
SA
0
0
0
0
0
WP SA P
Data Byte
0
0
0
0
0
Instruction Byte
Table 10. Activating/Deactivating Software Write Protect
7-Bit Device Address
S (See Table 5)
0
SA 0
Slave Address Byte
0
SA D7
D6
P
Data Byte
0
0
0
0
0
SA 0
0
Data Byte
In order to activate the write protection mode, the WP bit in Table 10 must be logic high. To deactivate the write protection, the command must
be sent again, except with the WP in logic zero state. WP is reset to the deactivated mode if power is cycled off and on.
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Rev. E | 16 of 22
Data Sheet
AD5259
I2C-COMPATIBLE FORMAT
reads a register previously written to. For example, if the EEPROM
was just written to, the user can then skip the two dummy bytes
and proceed directly to the slave address byte, followed by the
EEPROM readback data.
READ MODES
Read modes are referred to as traditional because the first two
bytes for all three cases are dummy bytes, which function to place
the pointer towards the correct register; this is the reason for the
repeat start. Theoretically, this step can be avoided if the user
Table 11. Traditional Readback of RDAC Register Value
7-Bit Device Address
S (See Table 5)
0 SA
0 0 0 0 0 0 0 0 SA
Slave Address Byte
1
Instruction Byte
1 SA
D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address Byte
Read Back Data
Repeated start.
Table 12. Traditional Readback of Stored EEPROM Value
7-Bit Device Address
S (See Table 5)
0 SA 0 0 1 0 0 0 0 0
Slave Address Byte
1
7-Bit Device Address
S1 (See Table 5)
SA
7-Bit Device Address
S1 (See Table 5)
Instruction Byte
1 SA D7 D6
Slave Address Byte
D5
D4 D3 D2 D1 D0 NA P
Read Back Data
Repeated start.
STORE/RESTORE MODES
Table 13. Storing RDAC Value to EEPROM
S 7-Bit Device Address (See Table 5)
0
SA
Slave Address Byte
1
1
0
0
0
0
1
0
0
0
0
0
SA
P
Instruction Byte
Table 14. Restoring EEPROM to RDAC1
S 7-Bit Device Address (See Table 5)
0
Slave Address Byte
SA
1
0
0
0
SA
P
Instruction Byte
TOLERANCE READBACK MODES
Table 15. Traditional Readback of Tolerance (Individually)
7-Bit Device Address
S (See Table 5)
0 SA 0 0 1 1 1 1 1 0 SA S1
Slave Address Byte
1
Slave Address Byte
1 SA D7
D6
D5
D4
D3
D2
D1
D0
NA
P
D3
D2
D1
D0
NA
P
Sign + Integer Byte
Repeated start.
Table 16.
7-Bit Device Address
S (See Table 5)
Slave Address Byte
1
Instruction Byte
7-Bit Device Address
(See Table 5)
0 SA 0 0 1 1 1 1 1 1 SA S1
Instruction Byte
7-Bit Device Address
(See Table 5)
Slave Address Byte
1 SA D7
D6
D5
D4
Decimal Byte
Repeated start.
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Rev. E | 17 of 22
Data Sheet
AD5259
I2C-COMPATIBLE FORMAT
Table 17. Traditional Readback of Tolerance (Consecutively)
7-Bit Device
7-Bit Device
S
S
Address (See
Address (See
S Table 5)
0 A 0 0 1 1 1 1 1 0 A S1 Table 5)
Slave Address Byte
1
Instruction Byte
S D D D D D D D
1 A 7 6 5 4 3 2 1
Slave Address
Byte
Sign + Integer Byte
D M
0 A
D D D D D D D D
7 6 5 4 3 2 1 0
N
A
P
Decimal Byte
Repeated start.
Calculating RAB Tolerance Stored in Read-Only
Memory
Figure 41. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. (Unit is Percent. Only Data Bytes are Shown.)
The AD5259 features a patented RAB tolerance storage in the
nonvolatile memory. The tolerance is stored in the memory during
factory production and can be read by users at any time. The
knowledge of stored tolerance allows users to accurately calculate
RAB. This feature is valuable for precision, rheostat mode, and
open-loop applications where knowledge of absolute resistance is
critical.
The stored tolerance resides in the read-only memory and is expressed as a percentage. The tolerance is stored in two memory
location bytes in sign magnitude binary form (see Figure 41).
The two EEPROM address bytes are 11110 (sign + integer)
and 11111 (decimal number). The two bytes can be individually accessed with two separate commands (see Table 15). Alternatively,
readback of the first byte followed by the second byte can be
done in one command (see Table 17). In the latter case, the
memory pointer will automatically increment from the first to the
second EEPROM location (increments from 11110 to 11111) if read
consecutively. In the first memory location, the MSB is designated
for the sign (0 = + and 1= −) and the seven LSBs are designated
for the integer portion of the tolerance. In the second memory
location, all eight data bits are designated for the decimal portion of
tolerance. Note the decimal portion has a limited accuracy of only
0.1%. For example, if the rated RAB = 10 kΩ and the data readback
from Address 11110 shows 0001 1100, and Address 11111 shows
0000 1111, then the tolerance can be calculated as
MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2–8 = 0.06
Tolerance = +28.06%
Rounded Tolerance = +28.1% and therefore,
RAB_ACTUAL = 12.810 kΩ
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ESD PROTECTION OF DIGITAL PINS AND
RESISTOR TERMINALS
The AD5259 VDD, VLOGIC, and GND power supplies define the
boundary conditions for proper 3-terminal and digital input operation. Supply signals present on Terminal A, Terminal B, and Terminal W that exceed VDD or GND are clamped by the internal forward
biased ESD protection diodes (see Figure 42). Digital Input SCL
and Digital Input SDA are clamped by ESD protection diodes with
respect to VLOGIC and GND as shown in Figure 43.
Figure 42. Maximum Terminal Voltages Set by VDD and GND
Figure 43. Maximum Terminal Voltages Set by VLOGIC and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 42), it
is important to power GND/VDD/VLOGIC before applying any voltage
to Terminal A, Terminal B, and Terminal W; otherwise, the diode is
forward biased, so the VDD and VLOGIC are powered unintentionally
Rev. E | 18 of 22
Data Sheet
AD5259
I2C-COMPATIBLE FORMAT
and may affect the user’s circuit. The ideal power-up sequence is
in the following order: GND, VDD, VLOGIC, digital inputs, and then
VA, VB, VW. The relative order of powering VA, VB, VW, and the
digital inputs is not important as long as they are powered after
GND/VDD/VLOGIC.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to use compact, minimum lead length layout
design. The leads to the inputs should be as direct as possible
with minimum conductor length. Ground paths should have low
resistance and low inductance.
Figure 45. AD5259 Evaluation Board Software
Similarly, it is also good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the device
should be bypassed with disc or chip ceramic capacitors of 0.01 µF
to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors
should also be applied at the supplies to minimize any transient
disturbance and low frequency ripple (see Figure 44). The digital
ground should also be joined remotely to the analog ground at one
point to minimize the ground bounce.
Figure 44. Power Supply Bypassing
MULTIPLE DEVICES ON ONE BUS
The AD5259 has two configurable address pins, Pin AD0 and Pin
AD1. The state of these two pins is registered upon power-up and
decoded into a corresponding I2C-compatible 7-bit address (see
Table 5). This allows up to four devices on the bus to be written to
or read from independently.
EVALUATION BOARD
An evaluation board, with all necessary software, is available
to program the AD5259 from any PC running Windows® 98/ 2000/
XP. The graphical user interface, as shown in Figure 45, is straightforward and easy to use. More detailed information is available in
the board’s user manual.
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Rev. E | 19 of 22
Data Sheet
AD5259
DISPLAY APPLICATIONS
CIRCUITRY
A special feature of the AD5259 is its unique separation of the VLOGIC and VDD supply pins. The separation provides greater flexibility
in applications that do not always provide needed supply voltages.
In particular, LCD panels often require a VCOM voltage in the range
of 3 V to 5 V. The circuit in Figure 46 is the rare exception in which
a 5 V supply is available to power the digital potentiometer.
draw of VDD will not affect that node’s bias because it is only on the
order of microamps. VLOGIC is tied to the MCU’s 3.3 V digital supply
because VLOGIC will draw the 35 mA that is needed when writing
to the EEPROM. It would be impractical to try and source 35 mA
through the 70 kΩ resistor. Therefore, VLOGIC is not connected to
the same node as VDD.
For this reason, VLOGIC and VDD are provided as two separate supply pins that can either be tied together or treated independently;
VLOGIC supplying the logic/EEPROM with power, and VDD biasing
up the A, B, and W terminals for added flexibility.
Figure 46. VCOM Adjustment Application
In the more common case shown in Figure 47, only analog 14.4 V
and digital logic 3.3 V supplies are available. By placing discrete
resistors above and below the digital potentiometer, VDD can now
be tapped off the resistor string itself. Based on the chosen resistor
values, the voltage at VDD in this case equals 4.8 V, allowing the
wiper to be safely operated all the way up to 4.8 V. The current
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Figure 47. Circuitry When a Separate Supply is Not Available for VDD
For a more detailed look at this application, refer to the article,
“Simple VCOM Adjustment uses any Logic Supply Voltage” in the
September 30, 2004 issue of EDN magazine.
Rev. E | 20 of 22
Data Sheet
AD5259
OUTLINE DIMENSIONS
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
Updated: April 22, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
AD5259BCPZ100-R7
AD5259BCPZ10-R7
AD5259BCPZ50-R7
AD5259BCPZ5-R7
AD5259BRMZ10
AD5259BRMZ100
AD5259BRMZ100-R7
AD5259BRMZ10-R7
AD5259BRMZ5
AD5259BRMZ50
AD5259BRMZ50-R7
AD5259BRMZ5-R7
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
10-Lead LFCSP (3mm x 3mm)
10-Lead LFCSP (3mm x 3mm)
10-Lead LFCSP (3mm x 3mm)
10-Lead LFCSP (3mm x 3mm)
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
1
Reel, 1000
Reel, 1000
Reel, 1000
Reel, 1000
Package
Option
Marking Code
CP-10-9
CP-10-9
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
D4S
D4Q
D4R
D4P
D4Q
D4S
D4S
D4Q
D4P
D4R
D4R
D4P
Z = RoHS Compliant Part.
analog.com
Rev. E | 21 of 22
Data Sheet
AD5259
OUTLINE DIMENSIONS
RAB (Ω) OPTIONS
Model1
RAB (Ω)
AD5259BCPZ100-R7
AD5259BCPZ10-R7
AD5259BCPZ50-R7
AD5259BCPZ5-R7
AD5259BRMZ10
AD5259BRMZ100
AD5259BRMZ100-R7
AD5259BRMZ10-R7
AD5259BRMZ5
AD5259BRMZ50
AD5259BRMZ50-R7
AD5259BRMZ5-R7
100 k
10 k
50 k
5k
10 k
100 k
100 k
10 k
5k
50 k
50 k
5k
1
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model1
Description
EVAL-AD5259DBZ
Evaluation Board2
1
Z = RoHS Compliant Part.
2
The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2005-2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. E | 22 of 22
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