a
FEATURES
256 Positions
AD5260 – 1-Channel
AD5262 – 2-Channel (Independently Programmable)
Potentiometer Replacement
20 k⍀, 50 k⍀, 200 k⍀
Low Temperature Coefficient 35 ppm/ⴗC
4-Wire SPI-Compatible Serial Data Input
5 V to 15 V Single-Supply; ⴞ5.5 V Dual-Supply Operation
Power ON Mid-Scale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Stereo Channel Audio Level Control
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Low Resolution DAC Replacement
1-/2-Channel
15 V Digital Potentiometers
AD5260/AD5262
FUNCTIONAL BLOCK DIAGRAMS
A
W
B
SHDN
AD5260
VDD
RDAC
REGISTER
VSS
VL
CS
POWER-ON
RESET
LOGIC
PR
8
CLK
SDI
SDO
SERIAL INPUT REGISTER
GND
A1
W1 B1
A2
W2 B2
SHDN
The AD5260/AD5262 provide a single- or dual-channel, 256position, digitally controlled variable resistor (VR) device.* These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5260/
AD5262 contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by a digital code loaded
into the SPI-compatible serial-input register. The resistance between
the wiper and either end point of the fixed resistor varies linearly
with respect to the digital code transferred into the VR latch. The
variable resistor offers a completely programmable value of resistance,
between the A terminal and the wiper or the B terminal and the wiper.
The fixed A to B terminal resistance of 20 kW, 50 kW, or 200 kW has
a nominal temperature coefficient of 35 ppm/∞C. Unlike the majority
of the digital potentiometers in the market, these devices can operate
up to 15 V or ±5 V provided proper supply voltages are furnished.
Each VR has its own VR latch, which holds its programmed resistance
value. These VR latches are updated from an internal serial-to-parallel
shift register, which is loaded from a standard 3-wire serial-input
digital interface. The AD5260 contains an 8-bit serial register
while the AD5262 contains a 9-bit serial register. Each bit is clocked
into the register on the positive edge of the CLK. The AD5262
address bit determines the corresponding VR latch to be loaded
with the last 8 bits of the data word during the positive edging of
CS strobe. A serial data output pin at the opposite end of the serial
register enables simple daisy chaining in multiple VR applications
without additional external decoding logic. An optional reset pin
(PR) forces the wiper to the mid-scale position by loading 80H into
the VR latch.
VDD
RDAC1 REGISTER
VSS
RDAC2 REGISTER
VL
CS
POWER-ON
RESET
LOGIC
PR
8
CLK
SDI
SERIAL INPUT REGISTER
GND
AD5262
SDO
100
RWA
PERCENT OF NOMINAL
END-TO-END RESISTANCE – % RAB
GENERAL DESCRIPTION
RWB
75
50
25
0
0
64
128
192
256
CODE – Decimal
Figure 1. RWA and RWB vs. Code
REV. 0
The AD5260/AD5262 are available in thin surface-mount TSSOP-14
and TSSOP-16 packages. All parts are guaranteed to operate over
the extended industrial temperature range of –40∞C to +85∞C.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
*The terms digital potentiometers, VR, and RDAC are used interchangeably.
V, V = 0 V or, V = +5 V, V = –5 V, V = +5 V, V = +5 V,
AD5260/AD5262–SPECIFICATIONS (VV ==0 +15
V, – 40ⴗC < T < +85ⴗC unless otherwise noted.)
DD
SS
B
DD
SS
L
A
A
ELECTRICAL CHARACTERISTICS 20 kW, 50 kW, 200 kW VERSIONS
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential NL2
R-DNL
RWB, VA = NC
R-INL
RWB, VA = NC
Resistor Nonlinearity2
RAB
TA = 25∞C
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RAB/T
Wiper = No Connect
IW = 1 V/RAB
Wiper Resistance
RW
Ch 1 and 2 RWB, DX = 80H
Channel Resistance Matching (AD5262 only) RWB/RWB
Resistance Drift
RAB
Min
Typ1
Max
Unit
–1
–1
–30
± 1/4
± 1/2
+1
+1
30
LSB
LSB
%
ppm/∞C
W
%
%
35
60
0.1
0.05
150
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution
N
8
Differential Nonlinearity4
DNL
–1
Integral Nonlinearity4
INL
–1
Code = 80H
Voltage Divider Temperature Coefficient DVW/DT
Code = FFH
–2
Full-Scale Error
VWFSE
Zero-Scale Error
VWZSE
Code = 00H
0
± 1/4
± 1/2
5
–1
1
RESISTOR TERMINALS
Voltage Range5
Capacitance6 Ax, Bx
25
V
pF
55
pF
VA, B, W
CA,B
Capacitance6 Wx
CW
Common-Mode Leakage Current
Shut Down Current7
ICM
ISHDN
DIGITAL INPUTS and OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High (SDO)
Output Logic Low (SDO)
Input Current8
Input Capacitance6
VIH
VIL
VIH
VIL
VOH
VOL
IIL
CIL
POWER SUPPLIES
Logic Supply
Power Single-Supply Range
Power Dual-Supply Range
Logic Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation9
VL
VDD RANGE
VDD/SS RANGE
IL
IDD
ISS
PDISS
Power Supply Sensitivity
PSS
VSS
f = 5 MHz,
measured to GND, Code = 80H
f = 1 MHz,
measured to GND, Code = 80H
VA =VB = VDD /2
+1
+1
+0
2
VDD
1
5
2.4
0.8
VL = 3 V, VSS = 0 V
VL = 3 V, VSS = 0 V
RPULL-UP = 2 kW to 5 V
IOL = 1.6 mA, VLOGIC = 5 V
VIN = 0 V or 5 V
2.1
0.6
4.9
5
VSS = 0 V
VL = 5 V
VIH = 5 V or VIL = 0 V
VSS = –5 V
VIH = 5 V or VIL = 0 V,
VDD = +5 V, VSS = –5 V
DVDD = +5 V, ±10%
2.7
4.5
± 4.5
0.003
0.4
±1
Bits
LSB
LSB
ppm/∞C
LSB
LSB
nA
mA
V
V
V
V
V
V
mA
pF
5.5
16.5
± 5.5
60
1
1
0.3
V
V
V
mA
mA
mA
mW
0.01
%/%
6, 10
DYNAMIC CHARACTERISTICS
Bandwidth –3 dB
Total Harmonic Distortion
BW
THDW
VW Settling Time
tS
Crosstalk11
CT
Analog Crosstalk
Resistor Noise Voltage
CTA
eN_WB
RAB = 20 kW/50 kW/200 kW
VA = 1 VRMS, VB = 0 V,
f = 1 kHz, RAB = 20 kW
VA = +5 V, VB = –5 V,
±1 LSB error band, RAB = 20 kW
VA = VDD, VB = 0 V,
Measure VW with Adjacent
RDAC Making Full-Scale
Code Change (AD5262 only)
VA1 = VDD, VB1 = 0V,
Measure VW1 with
VW2 = 5 V p-p @ f = 10 kHz,
RAB = 20 kW/200 kW (AD5262 only)
RWB = 20 kW
f = 1 kHz
–2–
310/130/30
0.014
kHz
%
5
ms
1
nV–s
–64
dB
13
nV/÷Hz
REV. 0
AD5260/AD5262
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
6, 12
INTERFACE TIMING CHARACTERISTICS apply to all parts
Clock Frequency
fCLK
Input Clock Pulsewidth
tCH, tCL
Clock level high or low
Data Setup Time
tDS
Data Hold Time
tDH
CLK to SDO Propagation Delay13
tPD
RL = 1 kΩ, CL < 20pF
CS Setup Time
tCSS
CS High Pulsewidth
tCSW
Reset Pulsewidth
tRS
CLK Fall to CS Rise Hold Time
tCSH
CS Rise to Clock Rise Setup
tCS1
20
10
10
1
5
20
50
0
10
160
NOTES
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89 mil. × 105 mil. 9,345 sq. mil.
1
Typicals represent average readings at 25°C and VDD = +5 V, VSS = –5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +5 V, VSS = –5 V.
3
VAB = VDD, Wiper (VW) = No connect.
4
INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V DD and VB = 0V. DNL
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8
Worst-case supply current consumed when input all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
9
PDISS is calculated from (IDD ⫻ VDD). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V DD = +5 V, VSS = –5 V, VL = +5 V.
11
Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change.
12
See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using V L = 5 V.
13
Propagation delay depends on value of V DD, RL, and CL.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +15 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
AX – BX, AX – WX, BX – WX
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
REV. 0
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Thermal Resistance3 θ JA
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance setting.
3
Package Power Dissipation = (T J MAX – TA)/ θ JA
–3–
AD5260/AD5262
ORDERING GUIDE
Model
RAB (kW)
Temperature
Package
Description
Package
Option
No. of Parts
per Container
Branding
Information*
AD5260BRU20
AD5260BRU20-REEL7
AD5260BRU50
AD5260BRU50-REEL7
AD5260BRU200
AD5260BRU200-REEL7
AD5262BRU20
AD5262BRU20-REEL7
AD5262BRU50
AD5262BRU50-REEL7
AD5262BRU200
AD5262BRU200-REEL7
20
20
50
50
200
200
20
20
50
50
200
200
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
96
1000
96
1000
96
1000
96
1000
96
1000
96
1000
AD5260B20
AD5260B20
AD5260B50
AD5260B50
AD5260B200
AD5260B200
AD5262B20
AD5262B20
AD5262B50
AD5262B50
AD5262B200
AD5262B200
*Line 1 contains part number, line 2 contains differentiating detail by part type and ADI logo symbol, line 3 contains date code YWW.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5260/AD5262 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD5260/AD5262
Table I. AD5260 8-Bit Serial-Data Word Format
DATA
B7
SDI
CS
VOUT
ADDR
DATA
B6
B5
B4
B3
B2
B1
B0
B8
B7
B6
B5
B4
B3
B2
B1
B0
D7 D6
MSB
27
D5
D4
D3
D2
D1
D0
LSB
20
A0
D7 D6
MSB
27
D5
D4
D3
D2
D1
D0
LSB
20
28
1
0
CLK
Table II. AD5262 9-Bit Serial-Data Word Format
D7
D6
D5
D4
D3
D2
D1
SDI
(DATA IN)
D0
1
Ax OR Dx
Dx
0
1
0
1
SDO
(DATA OUT)
RDAC REGISTER LOAD
tDH
tDS
1
Aⴕx OR Dⴕx
Dⴕx
0
tPD_MAX
0
1
tCH
1
tCS1
CLK
0
0
Figure 2a. AD5260 Timing Diagram
CS
tCSS
1
tCSH
tCL
tCSW
0
tS
SDI
1
0
1
CLK
CS
0
1
A0
D7
D6
D5
D4
D3
D2
D1
VOUT
D0
ⴞ1 LSB
VDD
ⴞ1 LSB ERROR BAND
0V
Figure 2c. Detail Timing Diagram
RDAC REGISTER LOAD
0
1
VOUT
PR
0
1
0
tRS
tS
VOUT VDD
0V ⴞ1 LSB ERROR BAND
Figure 2b. AD5262 Timing Diagram
ⴞ1 LSB
Figure 2d. Preset Timing Diagram
REV. 0
–5–
AD5260/AD5262
AD5260 PIN CONFIGURATION
AD5262 PIN CONFIGURATION
A 1
14
SDO
SDO 1
16
A2
W 2
13
NC
A1 2
15
W2
12
VL
W1 3
11
VSS
B1 4
B 3
VDD 4
SHDN
CLK
AD5260
TOP VIEW 10 GND
(Not to Scale)
9 PR
6
8
SHDN
CS
AD5260 PIN FUNCTION DESCRIPTIONS
Pin
Number
Mnemonic
Description
1
2
3
4
A
W
B
VDD
5
SHDN
6
CLK
7
8
SDI
CS
A Terminal
Wiper Terminal
B Terminal
Positive power supply, specified
for operation at both 5 V or 15 V.
(Sum of |VDD| + |VSS| £ 15 V)
Active low input. Terminal A
open-circuit. Shutdown controls.
Variable Resistors of RDAC.
Serial Clock Input, positive edge
triggered.
Serial Data Input
Chip Select Input, Active Low.
When CS returns high, data will
be loaded into the RDAC register.
Active low preset to mid-scale; sets
RDAC registers to 80H.
Ground
Negative Power Supply, specified
for operation from 0 V to –5 V.
Logic Supply Voltage, needs to be
same voltage as the digital logic
controlling the AD5260.
No Connect (Users should not
connect anything other than dummy
pad on this pin)
Serial Data Output, Open Drain
transistor requires pull-up resistor.
9
PR
10
11
GND
VSS
12
VL
13
NC
14
SDO
14
B2
13
VL
TOP VIEW 12 V
SS
(Not to Scale)
11 GND
6
VDD 5
5
SDI 7
AD5262
CLK 7
10
PR
SDI 8
9
CS
AD5262 PIN FUNCTION DESCRIPTIONS
–6–
Pin
Number
Mnemonic
Description
1
SDO
2
3
4
5
A1
W1
B1
VDD
6
SHDN
7
CLK
8
9
SDI
CS
10
PR
11
12
GND
VSS
13
VL
14
15
16
B2
W2
A2
Serial Data Output, Open Drain
transistor requires pull-up resistor.
A Terminal RDAC #1
Wiper RDAC #1, address A0 = 02
B Terminal RDAC #1
Positive power supply, specified for
operation at both 5 V or 15 V.
(Sum of |VDD|+|VSS|£ 15 V)
Active low input. Terminal A
open-circuit. Shutdown controls
Variable Resistors #1 through #2.
Serial Clock Input, positive edge
triggered.
Serial Data Input.
Chip Select Input, Active Low.
When CS returns high, data in
the serial input register is decoded,
based on the address Bit A0, and
loaded into the target RDAC register.
Active low preset to mid-scale sets
RDAC registers to 80H.
Ground
Negative Power Supply, specified
for operation at both 0 V or –5 V
(Sum of |VDD| + |VSS|
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