AD5262BRUZ20-RL7

1-/2-Channel 15 V Digital Potentiometer AD5260/AD5262 FEATURES FUNCTIONAL BLOCK DIAGRAMS A 256 positions AD5260: 1 channel AD5262: 2 channels (independently programmable) Potentiometer replacement 20 kΩ, 50 kΩ, 200 kΩ Low temperature coefficient: 35 ppm/°C 4-wire, SPI-compatible serial data input 5 V to 15 V single-supply; ±5.5 V dual-supply operation Power on midscale preset AD5260 VDD RDAC REGISTER VSS VL CS POWER-ON RESET LOGIC PR Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Stereo channel audio level control Programmable voltage-to-current conversion Programmable filters, delays, time constants Line impedance matching Low resolution DAC replacement GND SDO SERIAL INPUT REGISTER 02695-001 8 APPLICATIONS Figure 1. AD5260 A1 W1 B1 A2 W2 B2 SHDN VDD VSS GENERAL DESCRIPTION Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register, which is loaded from a standard 3-wire serial-input digital interface. The AD5260 contains an 8-bit serial register whereas the AD5262 contains a 9-bit serial register. Each bit is clocked into the register on the positive B SHDN CLK SDI RDAC1 REGISTER RDAC2 REGISTER VL CS POWER-ON RESET LOGIC PR 8 CLK SDI SERIAL INPUT REGISTER GND AD5262 SDO 02695-002 The AD5260/AD5262 provide a single- or dual-channel, 256position, digitally controlled variable resistor (VR) device. 1 These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5260/AD5262 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 20 Ω, 50 Ω, or 200 Ω has a nominal temperature coefficient of 35 ppm/°C. Unlike the majority of the digital potentiometers in the market, these devices can operate up to 15 V or ±5 V provided proper supply voltages are furnished. W Figure 2. AD5262 edge of the CLK pin. The AD5262 address bit determines the corresponding VR latch to be loaded with the last eight bits of the data word during the positive edging of CS strobe. A serial data output pin at the opposite end of the serial register enables simple daisy-chaining in multiple VR applications without additional external decoding logic. An optional reset pin (PR) forces the wiper to the midscale position by loading 0x80 into the VR latch. The AD5260/AD5262 are available in thin surface-mount 14-lead TSSOP and 16-lead TSSOP packages. All parts are guaranteed to operate over the extended industrial temperature range of −40°C to +85°C. 1 The terms digital potentiometers, VR, and RDAC are used interchangeably. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2010 Analog Devices, Inc. All rights reserved. AD5260/AD5262 TABLE OF CONTENTS Features .............................................................................................. 1  Layout and Power Supply Bypassing ....................................... 18  Applications....................................................................................... 1  Terminal Voltage Operating Range ......................................... 18  General Description ......................................................................... 1  Power-Up Sequence ................................................................... 18  Functional Block Diagrams............................................................. 1  RDAC Circuit Simulation Model............................................. 18  Revision History ............................................................................... 2  Macro Model Net List for RDAC ............................................. 18  Specifications..................................................................................... 3  Applications Information .............................................................. 19  Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions .. 3  Bipolar DC or AC Operation from Dual Supplies................. 19  Timing Diagrams.......................................................................... 5  Gain Control Compensation .................................................... 19  Absolute Maximum Ratings............................................................ 6  Programmable Voltage Reference ............................................ 19  ESD Caution.................................................................................. 6  8-Bit Bipolar DAC ...................................................................... 19  Pin Configurations and Function Descriptions ........................... 7  Bipolar Programmable Gain Amplifier................................... 20  Typical Performance Characteristics ............................................. 9  Programmable Voltage Source with Boosted Output ........... 20  Test Circuits..................................................................................... 14  Programmable 4 mA-to-20 mA Current Source ................... 20  Theory of Operation ...................................................................... 15  Programmable Bidirectional Current Source......................... 21  Digital Interfacing ...................................................................... 15  Programmable Low-Pass Filter ................................................ 21  Daisy-Chain Operation ............................................................. 16  Programmable Oscillator .......................................................... 21  RDAC Structure.......................................................................... 16  Resistance Scaling ...................................................................... 22  Programming the Variable Resistor......................................... 16  Outline Dimensions ....................................................................... 23  Programming the Potentiometer Divider ............................... 17  Ordering Guide .......................................................................... 24  REVISION HISTORY 8/10—Rev. 0 to Rev. A Updated Format..................................................................Universal Deleted Figure 1; Renumbered Sequentially................................. 1 Changes to General Description Section ...................................... 1 Changes to Conditions of Channel Resistance Matching (AD5262 only) Parameter, Voltage Divider Temperature Coefficient Parameter, Full-Scale Error Parameter, and ZeroScale Error Parameter, Table 1 ........................................................ 3 Changes to Table 2 and Table 3....................................................... 5 Changes to Table 4............................................................................ 6 Changes to Table 5............................................................................ 7 Changes to Table 6............................................................................ 8 Changes to Figure 11 Caption and Figure 12 ................................9 Changes to Figure 31...................................................................... 12 Changes to Figure 35 Caption ...................................................... 13 Changes to Figure 43 and Figure 46............................................. 14 Deleted Potentiometer Family Selection Guide ......................... 18 Change to Programmable Voltage Source with Boosted Output Section.............................................................................................. 20 Changes to Figure 64...................................................................... 21 Updated Outline Dimensions....................................................... 23 Changes to Ordering Guide .......................................................... 24 3/02—Revision 0: Initial Version Rev. A | Page 2 of 24 AD5260/AD5262 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS VDD = +15 V, VSS = 0 V, or VDD = +5 V, VSS = –5 V; VL = +5 V; VA = +5 V, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted. The AD5260/AD5262 contain 1968 transistors. Die size: 89 mil × 105 mil (9345 sq mil). Table 1. Parameter DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity 2 Resistor Nonlinearity2 Nominal Resistor Tolerance 3 Resistance Temperature Coefficient Wiper Resistance Channel Resistance Matching (AD5262 only) Symbol Resistance Drift DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity 4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range 5 Ax and Bx Capacitance 6 ΔRAB Wx Capacitance6 Common-Mode Leakage Current Shutdown Current 7 DIGITAL INPUTS and OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High (SDO) Output Logic Low (SDO) Input Current 8 Input Capacitance6 POWER SUPPLIES Logic Supply Power Single-Supply Range Power Dual-Supply Range Logic Supply Current Positive Supply Current Negative Supply Current Power Dissipation 9 Power Supply Sensitivity R-DNL R-INL ΔRAB ΔRAB/ΔT RW ΔRWB/RWB Conditions Specifications apply to all VRs RWB, VA = no connect RWB, VA = no connect TA = 25°C Wiper = no connect IW = 1 V/RAB Channel 1 and Channel 2 RWB, DX = 0x80 Min Typ 1 Max Unit −1 −1 −30 ±¼ ±½ +1 +1 30 LSB LSB % ppm/°C Ω % 35 60 0.1 150 0.05 % Specifications apply to all VRs N DNL INL ΔVW/ΔT WFSE VWZSE VA, B, W CA,B Code = half scale Code = full scale Code = zero scale −2 0 ±1/4 ±1/2 5 −1 1 VSS f = 5 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VB = VDD/2 CW ICM ISHDN +1 +1 +0 2 VDD V pF 55 pF 1 2.4 0.8 VL = 3 V, VSS = 0 V VL = 3 V, VSS = 0 V RPULL-UP = 2 kΩ to 5 V IOL = 1.6 mA, VLOGIC = 5 V VIN = 0 V or 5 V 2.1 0.6 4.9 0.4 ±1 5 VL VDD RANGE VDD/SS RANGE IL IDD ISS PDISS VSS = 0 V VL = 5 V VIH = 5 V or VIL = 0 V VSS= −5 V VIH = 5 V or VIL = 0 V, VDD = +5 V, VSS = –5 V ΔVDD= +5 V, ±10% Rev. A | Page 3 of 24 Bits LSB LSB ppm/°C LSB LSB 25 5 VIH VIL VIH VIL VOH VOL IIL CIL PSS 8 −1 −1 2.7 4.5 ±4.5 0.003 nA μA V V V V V V μA pF 5.5 16.5 ±5.5 60 1 1 0.3 V V V μA μA μA mW 0.01 %/% AD5260/AD5262 Parameter DYNAMIC CHARACTERISTICS6, 10 Bandwidth –3 dB Total Harmonic Distortion Symbol Conditions BW THDW RAB = 20 kΩ/50 kΩ/200 kΩ VA = 1 VRMS, VB = 0 V, f = 1 kHz, RAB = 20 kΩ VA = +5 V, VB = −5 V, ±1 LSB error band, RAB = 20 kΩ VA = VDD, VB = 0 V, measure VW with adjacent RDAC making full-scale code change (AD5262 only) VA1 = VDD, VB1 = 0 V, measure VW1 with VW2 = 5 V p-p at f = 10 kHz, RAB = 20 kΩ/200 kΩ (AD5262 only) RWB = 20 kΩ, f = 1 kHz Specifications apply to all parts VW Settling Time tS Crosstalk 11 CT Analog Crosstalk CTA Resistor Noise Voltage INTERFACE TIMING CHARACTERISTICS6, 12 Clock Frequency Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay 13 CS Setup Time eN_WB fCLK tCH, tCL tDS tDH tPD tCSS Min Typ 1 Max 310/130/30 0.014 kHz % 5 μs 1 nV-sec –64 dB 13 nV/√Hz 25 Clock level high or low RL = 1 kΩ, CL< 20 pF 20 10 10 1 5 Unit 160 MHz ns ns ns ns ns CS High Pulse Width Reset Pulse Width CLK Fall to CS Rise Hold Time tCSW 20 ns tRS tCSH 50 0 ns ns CS Rise to Clock Rise Setup tCS1 10 ns 1 Typical values represent average readings at 25°C and VDD = +5 V, VSS = −5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and VSS = −5V. 3 VAB = VDD, wiper = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode. 8 Worst-case supply current consumed when all logic-input levels set at 2.4 V, which is the standard characteristic of CMOS logic. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = +5 V, VSS = −5 V, VL = +5 V. 11 Measured at VW where an adjacent VW is making a full-scale voltage change. 12 See Figure 5 for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using VL = 5 V. 13 Propagation delay depends on value of VDD, RL, and CL. 2 Rev. A | Page 4 of 24 AD5260/AD5262 TIMING DIAGRAMS Table 2. AD5260 8-Bit Serial Data Word Format Data B7 (MSB) D7 27 B6 D6 26 B5 D5 25 B4 D4 24 B3 D3 23 B2 D2 22 B1 D1 21 B0 (LSB) D0 20 Table 3. AD5262 9-Bit Serial Data Word Format B7 (MSB) D7 27 B6 D6 26 B5 D5 25 Data B3 D3 23 B4 D4 24 B2 D2 22 B1 D1 21 1 D7 SDI D6 D5 D4 D3 D2 D1 D0 0 1 CLK 0 1 RDAC REGISTER LOAD CS 02695-004 0 1 VOUT 0 Figure 3. AD5260 Timing Diagram 1 A0 SDI D7 D6 D5 D4 D3 D2 D1 D0 0 1 CLK 0 1 RDAC REGISTER LOAD CS 02695-005 0 1 VOUT 0 Figure 4. AD5262 Timing Diagram SDI 1 (DATA IN) 0 SDO (DATA OUT) Ax OR Dx Dx tDS tDH 1 A'x OR D'x D'x 0 tPD tCH 1 tCS1 CLK 0 tCSS 1 tCSH tCL tCSW CS 0 VDD ±1 LSB ERROR BRAND 0V Figure 5. Detailed Timing Diagram PR 1 0 VDD tRS tS ±1 LSBD 0V ±1 LSB ERROR BAND Figure 6. Preset Timing Diagram Rev. A | Page 5 of 24 ±1 LSB 02695-006 VOUT tS 02695-007 ADDR B8 A0 28 B0 (LSB) D0 20 AD5260/AD5262 ABSOLUTE MAXIMUM RATINGS TA =25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Parameter VDD to GND VSS to GND VDD to VSS VL to GND VA, VB, VW to GND AX to BX, AX to WX, BX to WX Intermittent 1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJ MAX) Storage Temperature Range Lead Temperature (Soldering,10 sec) Vapor Phase (60 sec) Infrared (15 sec) Thermal Resistance 2 θJA 14-Lead TSSOP 16-Lead TSSOP Rating −0.3 V to +17 V 0 V to −7 V 17 V 0 V to +7 V VSS, VDD ±20 mA ±5 mA −0.3 V to VL + 0.3 V, or +7 V (whichever is less) −40°C to +85°C 150°C ESD CAUTION −65°C to +150°C 300°C 215°C 220°C 206°C/W 150°C/W 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance setting. 2 Package power dissipation = (TJ MAX − TA)/θJA. Rev. A | Page 6 of 24 AD5260/AD5262 A 1 14 SDO 2 13 NC AD5260 12 VL TOP VIEW (Not to Scale) 11 VSS GND W B 3 VDD 4 SHDN 5 10 CLK 6 9 PR 8 CS SDI 7 NC = NO CONNECT 02695-008 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 7. AD5260 Pin Configuration Table 5. AD5260 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic A W B VDD SHDN CLK SDI CS PR GND VSS VL NC SDO Description A Terminal. Wiper Terminal. B Terminal. Positive Power Supply. Specified for operation at both 5 V or 15 V (sum of |VDD| + |VSS| ≤ 15 V). Active Low Input. Terminal A, open-circuit. Shutdown controls variable resistor. Serial Clock Input, Positive Edge Triggered. Serial Data Input. Chip Select Input, Active Low. When CS returns high, data is loaded into the RDAC register. Active Low Preset to Midscale. Sets RDAC registers to 0x80. Ground. Negative Power Supply. Specified for operation from 0 V to −5 V. Logic Supply Voltage. Needs to be the same voltage as the digital logic controlling the AD5260. No Connect. Users should not connect anything other than a dummy pad on this pin. Serial Data Output. Open-drain transistor requires a pull-up resistor. Rev. A | Page 7 of 24 AD5260/AD5262 16 A2 2 15 W2 W1 3 AD5262 14 B2 B1 4 TOP VIEW (Not to Scale) 13 VL A1 12 VSS VDD 5 SHDN 6 11 GND CLK 7 10 PR SDI 8 9 CS 02695-009 SDO 1 Figure 8. AD5262 Pin Configuration Table 6. AD5262 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic SDO A1 W1 B1 VDD SHDN CLK SDI CS 10 11 12 13 14 15 16 PR GND VSS VL B2 W2 A2 Description Serial Data Output. Open-drain transistor requires a pull-up resistor. A Terminal RDAC 1. Wiper RDAC 1, Address A0 = 0. B Terminal RDAC 1. Positive Power Supply. Specified for operation at both 5 V or 15 V. (Sum of |VDD| + |VSS| ≤ 15 V) Active Low Input. Terminal A, open-circuit. Shutdown controls variable Resistor 1 through Resistor R2. Serial Clock Input, Positive Edge Triggered. Serial Data Input. Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the Address Bit A0, and loaded into the target RDAC register. Active Low Preset to Midscale. Sets RDAC registers to 0x80. Ground. Negative Power Supply. Specified for operation at either 0 V or −5 V (sum of |VDD| + |VSS| < 15 V). Logic Supply Voltage. Needs to be same voltage as the digital logic controlling the AD5262. B Terminal RDAC 2. Wiper RDAC 2, Address A0 = 1. A Terminal RDAC 2. Rev. A | Page 8 of 24 AD5260/AD5262 0.8 0.5 0.7 0.4 POTENTIOMETER MODE DNL (LSB) 0.6 +5V 0.5 0.4 0.3 0.2 +12V ±5V 0.1 0 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 +15V 32 64 96 128 160 CODE (Decimal) 192 224 256 0 32 0.05 0.2 POTENTIOMETER MODE INL (LSB) 0.3 0 –0.05 –0.10 –0.15 +5V ±5V +12V +15V –0.25 32 64 96 128 160 CODE (Decimal) 192 224 256 192 224 256 192 224 256 224 256 +5V ±5V +15V 0.1 0 –0.1 –0.2 –0.3 –0.4 02695-011 RHEOSTAT MODE DNL (LSB) 0.10 0 96 128 160 CODE (Decimal) Figure 12. DNL vs. Code Figure 9. R-INL vs. Code vs. Supply Voltages –0.20 64 02695-014 0 02695-010 –0.5 –0.2 02695-013 –0.4 –0.1 0 32 64 96 128 160 CODE (Decimal) Figure 13. INL vs. Code vs. Supply Voltages Figure 10. R-DNL vs. Code vs. Supply Voltages 0.5 1.0 VDD = +5V VSS = –5V RAB = 20kΩ TA = +125°C 0.6 0.4 POTENTIOMETER MODE DNL (LSB) 0.8 0.4 TA = +85°C 0.2 TA = –40°C 0 –0.2 –0.4 TA = +25°C –0.6 ±5V +15V +5V 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.8 –0.5 –1.0 0 32 64 96 128 160 CODE (Decimal) 192 224 256 02695-012 POTENTIOMETER MODE INL (LSB) VDD = +5V VSS = –5V RAB = 20kΩ TA = +85°C TA = +125°C TA = +25°C TA = –40°C 02695-015 RHEOSTAT MODE INL (LSB) TYPICAL PERFORMANCE CHARACTERISTICS 0 32 64 96 128 160 192 CODE (Decimal) Figure 14. DNL vs. Code vs. Supply Voltages Figure 11. INL vs. Code Rev. A | Page 9 of 24 AD5260/AD5262 2.5 AVG + 3σ 2.0 0.5 VDD/VSS = +15/0V AVG FSE (LSB) AVG – 3σ 0 1.5 VDD/VSS = ±5V 1.0 VDD/VSS = +5V/0V –0.5 0.5 –1.0 5 10 15 20 |VDD – VSS| (V) 0 –40 02695-016 0 Figure 15. INL vs. Supply Voltages –20 0 20 40 60 TEMPERATURE (°C) 80 100 02695-019 POTENTIOMETER MODE INL (LSB) 1.0 Figure 18. Full-Scale Error vs. Temperature 2.0 2.5 1.5 2.0 AVG VDD/VSS = +5V/0V 0.5 AVG – 3σ ZSE (LSB) RHEOSTAT MODE INL (LSB) AVG + 3σ 1.0 0 –0.5 1.5 VDD/VSS = ±5V 1.0 VDD/VSS = +15/0V –1.0 0.5 –2.0 10 5 15 20 |VDD – VSS| (V) 0 02695-017 0 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 02695-020 –1.5 Figure 19. Zero-Scale Error vs. Temperature Figure 16. R-INL vs. Supply Voltages 1 124 RON @ VDD/VSS = +5V/0V IDD/ISS SUPPLY CURRENT (µA) 84 RON @ VDD/VSS = +5V/–5V 64 44 RON @ VDD/VSS = +15V/0V 24 0.1 0.01 VDD/VSS = +15/0V –1 3 7 11 VDD (V) 15 Figure 17. Wiper On Resistance vs. Bias Voltage 0.001 –40 –7 26 59 92 TEMPERATURE (°C) Figure 20. Supply Current vs. Temperature Rev. A | Page 10 of 24 125 02695-021 4 –5 VLOGIC = 5V VIH = 5V VIL = 0V VDD/VSS = ±5V 02695-018 WIPER RESISTANCE (Ω) 104 AD5260/AD5262 120 27.5 ILOGIC (µA) 27.0 VDD/VSS = +15/0V 26.5 26.0 VDD/VSS = ±5V 25.5 24.5 –40 –7 26 59 TEMPERATURE (°C) 92 125 80 20kΩ 60 50kΩ 40 20 0 –20 200kΩ –40 –60 02695-022 25.0 100 0 Figure 21. ILOGIC vs. Temperature 32 64 96 128 160 CODE (Decimal) 192 224 256 02695-025 POTENTIOMETER MODE TEMPCO (ppm/°C) 28.0 Figure 24. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code 1000 6 TA = 25°C CODE = 0xFF 0 0x80 –6 0x40 –12 GAIN (dB) ILOGIC (µA) VDD/VSS = 5V/0V VLOGIC = 5V 100 VDD/VSS = 5V/0V VLOGIC = 3V 0x20 –18 0x10 –24 0x08 –30 0x04 –36 0x02 0x01 –42 –48 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VIH (V) –54 100k 1M 1M FREQUENCY (Hz) Figure 22. ILOGIC vs. Digital Input Voltage Figure 25. Gain vs. Frequency vs. Code, RAB = 20 kΩ 80 6 70 0 60 –6 TA = 25°C CODE = 0xFF 0x80 0x40 50 –12 20kΩ 0x20 30 GAIN (dB) 40 50kΩ 20 –18 0x10 –24 0x08 –30 0x04 10 –36 0 –42 –10 –48 0x02 0x01 200kΩ –20 0 32 64 96 128 160 CODE (Decimal) 192 224 256 02695-024 RHEOSTAT MODE TEMPCO (ppm/°C) 10k 1k 02695-026 0.5 02695-027 0 02695-023 10 Figure 23. Rheostat Mode Tempco ΔRWB /ΔT vs. Code –54 1k 10k 100k FREQUENCY (Hz) Figure 26. Gain vs. Frequency vs. Code, RAB = 50 kΩ Rev. A | Page 11 of 24 AD5260/AD5262 600 6 TA = 25°C CODE = 0xFF 0 0x80 –6 CODE 0xFF 0x40 –12 400 0x20 –18 ILOGIC (µA) 0x10 –24 0x08 –30 VDD/VSS = ±5V 200 0x04 –36 300 VDD/VSS = +5V/0V 0x02 –42 100 0x01 –48 10k 1M 100k FREQUENCY (Hz) 02695-028 1k 0 10k 10M FREQUENCY (Hz) Figure 30. ILOGIC vs. Frequency Figure 27. Gain vs. Frequency vs. Code, RAB = 200 kΩ 60 6 f–3dB = 310kHz, R = 20kΩ 0 CODE = 0x80, VA = VDD, VB = 0V f–3dB = 131kHz, R = 50kΩ 50 –6 –12 –PSRR @ V DD = ±5V DC ± 10% p-p AC 40 –18 PSRR (dB) GAIN (dB) 1M 100k f–3dB = 30kHz, R = 200kΩ –24 –30 30 20 –36 –42 +PSRR @ VDD = ±5V DC ± 10% p-p AC 10 –3dB BANDWIDTHS –54 1k VIN = 50mV rms VDD/VSS= ±5V 10k 100k 1M FREQUENCY (Hz) 02695-029 –48 0 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 28. −3 dB Bandwidth Figure 31. PSRR vs. Frequency 0.3 CODE = 0x80 VDD/VSS= ±5V TA = 25°C 0.1 0 R = 20kΩ 20mV/DIV –0.1 –0.2 –0.3 R = 50kΩ –0.4 R = 200kΩ –0.5 5V/DIV –0.7 100 1k 10k FREQUENCY (Hz) 100k 1µs/DIV Figure 32. Midscale Glitch Energy, Code 0x80 to 0x7F Figure 29. Normalized Gain Flatness vs. Frequency Rev. A | Page 12 of 24 02695-033 –0.6 02695-030 NORMALIZED GAIN FLATNESS (dB) 0.2 02695-031 CODE 0x55 –54 02695-032 GAIN (dB) 500 AD5260/AD5262 5V/DIV 5V/DIV AVG – 3σ 0 AVG –0.05 –0.10 AVG + 3σ –0.15 –0.20 02695-034 20µs/DIV CODE = 0x80 VDD/VSS= ±5V SAMPLE SIZE = 135 UNITS 0.05 0 50 100 150 200 250 300 350 400 HOURS OF OPERATION AT 150°C 450 500 Figure 36. Long-Term Resistance Drift Figure 33. Large Signal Settling Time 40 CODE SET TO MIDSCALE TA = 150°C 3 LOTS SAMPLE SIZE = 135 UNITS FREQUENCY 30 10mV/DIV 20 0 02695-035 40ns/DIV 10 RAB = 20kΩ RAB = 50kΩ RAB = 200kΩ 0 32 64 96 128 160 192 224 CODE (Decimal) 256 02695-036 THEORETICAL IWB_MAX (mA) VA = VB = OPEN TA = 25°C 0.01 –0.30 –0.20 –0.10 0 0.10 0.20 Figure 37. Channel-to-Channel Resistance Matching (AD5262) 100 0.1 –0.40 CHANNEL-TO-CHANNEL RAB MATCH (%) Figure 34. Digital Feedthrough vs. Time 1 –0.50 Figure 35. Theoretical Maximum Current vs. Code Rev. A | Page 13 of 24 02695-038 10 02695-037 CHANGE IN TERMINAL RESISTANCE (%) 0.10 AD5260/AD5262 TEST CIRCUITS Figure 38 to Figure 46 define the test conditions used in Table 1. RW = DUT CODE = 0x00 W B A VMS 02695-039 VSS TO VDD A = NC Figure 43. Incremental On Resistance Figure 38. Potentiometer Divider Nonlinearity Error (INL, DNL) NC DUT A NC NC = NO CONNECT IW VDD W A B VSS GND 02695-040 VMS ICM W DUT B VCM NC 02695-045 B 0.1V IW W V+ 02695-044 V+ = VDD 1LSB = V+/2N DUT 0.1V IW Figure 44. Common-Mode Leakage Current Figure 39. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) VLOGIC ILOGIC CS CLK DUT SDI DIGITAL INPUT VOLTAGE VMS1 RW = (VMS1 – VMS2)/IW 02695-041 B Figure 40. Wiper Resistance Figure 45. VLOGIC Current vs. Digital Input Voltage V+ = VDD ± 10% PSRR (dB) = 20 log V+ W PSS (%/%) = B ∆V ( ∆VMS ) DD NC ∆VMS% VMS +13V DUT –13V VOUT 02695-043 B VSS Figure 42. Gain vs. Frequency Rev. A | Page 14 of 24 VOUT B2 Figure 46. Analog Crosstalk W AD8610 W2 CTA = 20 log (VOUT/VIN) NC = NO CONNECT A OFFSET GND A2 RDAC2 W1 B1 ∆VDD% Figure 41. Power Supply Sensitivity (PSS, PSSR) VIN RDAC1 VIN 02695-042 A VDD A1 VA VDD 02695-046 VW W 02695-047 A VMS2 IW = VDD/RNOMINAL AD5260/AD5262 THEORY OF OPERATION The AD5260/AD5262 provide a single- or dual-channel, 256position, digitally controlled variable resistor (VR) device and operate up to 15 V maximum voltage. Changing the programmed VR settings is accomplished by clocking an 8-/9-bit serial data word into the SDI (serial data input) pin. For the AD5262, the format of this data word is one address bit. A0 represents the first bit, B8, followed by eight data bits, B7 to B0, with MSB first. Table 2 and Table 3 provide the serial register data word format. See Table 7 for the AD5262 address assignment to decode the location of the VR latch receiving the serial register data in Bit B7 through Bit B0. VR outputs can be changed one at a time in random sequence. The AD5260/AD5262 preset to a midscale, simplifying fault condition recovery at power-up. Midscale can also be achieved at any time by asserting the PR pin. Both parts have an internal power-on preset that places the wiper in a midscale preset condition at power-on. Operation of the poweron preset function depends only on the state of the VL pin. VL VDD CS A1 RDAC LATCH 1 CLK W1 B1 PR EN SDI ADDR DEC A0 SER REG D7 D6 D5 D4 D3 D2 D1 D0 B2 PR POWERON PRESET PR W2 SHDN GND VSS 02695-048 SDO A2 RDAC LATCH 2 Figure 47. AD5262 Block Diagram The AD5260/AD5262 contain a power shutdown SHDN pin that places the RDAC in an almost zero power consumption state where Terminals Ax are open circuited and the Wiper W is connected to B, resulting in only leakage currents being consumed in the VR structure. In the shutdown mode, the VR latch settings are maintained so that, when returning to operational mode from power shutdown, the VR settings return to their previous resistance values. The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. Figure 47 shows more detail of the internal digital circuitry. When CS is low, the clock loads data into the serial input register on each positive clock edge (see Table 8). Table 7. AD5262 Address Decode Table Table 8. Truth Table1 A0 0 1 CLK Low ↑ CS PR SHDN Low Low High High High High X X X ↑ High X High High Low High High High X X High High ↑ High High Low Latch Loaded RDAC1 RDAC2 DIGITAL INTERFACING The AD5260/AD5262 contain a 4-wire SPI-compatible digital interface (SDI, SDO, CS, and CLK). For the AD5260, the 8-bit serial word must be loaded with the MSB first. The format of the word is shown in Table 2. For the AD5262, the 9-bit serial word must be loaded with Address Bit A0 first, then the MSB of the data. The format of the word is shown in Table 3. 1 Register Activity No SR effect, enables SDO pin. Shift one bit in from the SDI pin. The eighth previously entered bit is shifted out of the SDO pin. Load SR data into RDAC latch. No operation. Sets all RDAC latches to half scale, wiper centered, and SDO latch cleared. Latches all RDAC latches to 0x80. Open circuits all Resistor A terminals, connects W to B, and turns off SDO output transistor. ↑ = positive edge, X = don’t care, SR = shift register. The data setup and data hold times in Table 1 determine the data valid time requirements. The AD5260 uses an 8-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. For the AD5262, the last nine bits of the data word entered into the serial register are held when CS returns high. Any extra bits are ignored. At the same time CS goes high, it gates the address decoder, enabling one of two positive edge-triggered AD5262 RDAC latches (see Figure 48). Rev. A | Page 15 of 24 AD5260/AD5262 AD5260/AD5262 CS registers, and the CS pin is then pulled high to complete the operation. RDAC1 ADDR DECODE RDAC2 VDD 02695-049 CLK SERIAL REGISTER SDI MICROCONTROLLER MOSI Figure 48. Equivalent Input Control Logic SCLK During shutdown (SHDN), the SDO output pin is forced to the off (logic high) state to disable power dissipation in the pull-up resistor. See Figure 49 for the equivalent SDO output circuit schematic. SHDN SDO CS SDI SERIAL REGISTER D Q CK RS 02695-050 CLK PR Figure 49. Detail SDO Output Schematic of the AD5260 All digital inputs are protected with a series input resistor and parallel Zener ESD structure as shown in Figure 50. This applies to the CS, SDI, SDO, PR, SHDN, and CLK digital input pins. 340Ω 02695-051 LOGIC U1 SDI SS SDO CS CLK RP 2.2kΩ AD5260 U2 SDI SDO CS CLK 02695-055 The target RDAC latch is loaded with the last eight bits of the serial data word completing one RDAC update. For the AD5262, two separate 9-bit data words must be clocked in to change both VR settings. AD5260 Figure 52. Daisy-Chain Configuration RDAC STRUCTURE The RDAC contains a string of equal resistor segments with an array of analog switches that act as the wiper connection. The number of positions is the resolution of the device. The AD5260/ AD5262 have 256 connection points, allowing it to provide better than 0.4% settability resolution. Figure 53 shows an equivalent structure of the connections between the three terminals that make up one channel of the RDAC. SWA and SWB are always on, while one of the switches SW(0) to SW(2N – 1) is on one at a time, depending on the resistance position decoded from the data bits. Because the switch is not ideal, there is a 60 Ω wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature. The lower the supply voltage is, the higher the wiper resistance becomes. Similarly, the higher the temperature is, the higher the wiper resistance becomes. Users should be aware of the contribution of the wiper resistance when accurate prediction of the output resistance is needed. Ax SHDN Figure 50. ESD Protection of Digital Pins RS A, B, W Figure 51. ESD Protection of Resistor Terminals DAISY-CHAIN OPERATION The serial data output (SDO) pin contains an open-drain Nchannel FET. This output requires a pull-up resistor to transfer data to the SDI pin of the next package. This allows for daisychaining several RDACs from a single processor serial data line. The pull-up resistor termination voltage can be larger than the VDD supply voltage. It is recommended to increase the clock period when using a pull-up resistor to the SDI pin of the following device in series because capacitive loading at the daisy-chain node connecting SDO and SDI between devices may induce time delay to subsequent devices. Users should be aware of this potential problem to achieve data transfer successfully (see Figure 52). If two AD5260s are daisy-chained, this requires a total of 16 bits of data. The first eight bits, complying with the format shown in Table 2, go to U2, and the second eight bits with the same format go to U1. The CS pin should be kept low until all 16 bits are clocked into their respective serial RDAC LATCH AND DECODE RS RS Wx RS DIGITAL CIRCUITRY OMITTED FOR CLARITY Bx RS = RAB/2N 02695-056 02695-052 VSS D7 D6 D5 D4 D3 D2 D1 D0 Figure 53. Simplified RDAC Architecture PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistances of the RDAC between Terminal A and Terminal B are available with values of 20 kΩ, 50 kΩ, and 200 kΩ. The final three digits of the part number determine the nominal resistance value, for example, 20 kΩ = 20, 50 kΩ = 50, 200 kΩ = 200. The nominal resistance (RAB) of the VR has 256 contact points Rev. A | Page 16 of 24 AD5260/AD5262 The general equation determining the digitally programmed output resistance between W and B is D × R AB + RW 256 (1) Table 10. RWA vs. Code RDAC (Dec) 256 128 1 0 RWA (Ω) 60 10,060 19,982 20,060 Output State Full scale Half scale 1 LSB Zero scale 20 RWA RWB 16 12 8 4 where D is the decimal equivalent of the binary code that is loaded in the 8-bit RDAC register and RAB is the nominal endto-end resistance. RAB = 20kΩ 0 0 64 128 192 256 CODE (Decimal) For example, when RAB = 20 kΩ, VB = 0 V, and the A terminal is open circuit, the following output resistance values of RWB are set for the RDAC latch codes shown in Table 9. The result is the same if Terminal A is tied to W. Table 9. RWB vs. Code RDAC (Dec) 256 128 1 0 RWB (Ω) 19,982 10,060 138 60 Output State Full scale (RAB – 1 LSB + RW) Midscale 1 LSB Zero-scale (wiper contact resistance) Note that in the zero-scale condition, a finite wiper resistance of 60 Ω is present. Care should be taken to limit the current flow between W and B in this state to no more than 20 mA to avoid degradation or possible destruction of the internal switches. Like the mechanical potentiometer the RDAC replaces, the AD5260/AD5262 are completely symmetrical. The resistance between Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. Figure 54 shows the symmetrical programmability of the various terminal connections. When RWA is used, the B terminal can be left floating or tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general equation for this operation is RWA (D) = 256 − D × R AB + RW 256 (2) For example, when RAB = 20 kΩ, VA = 0 V, and the B terminal is open circuit, the following output resistance values of RWA are 02695-057 RWB (D) = set for the RDAC latch codes shown in Table 10. The result is the same if Terminal B is tied to Terminal W. RWA (D), RWB (D) – kΩ accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assuming a 20 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Because there is a 60 Ω wiper contact resistance, such a connection yields a minimum of 60 Ω resistance between Terminal W and Terminal B. The second connection is the first tap point corresponding to 138 Ω (RWB = RAB/256 RW = 78 Ω + 60 Ω) for Data 0x01. The third connection is the next tap point representing 216 Ω (78 × 2 + 60) for Data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 19,982 Ω (RAB − 1 LSB + RW). The wiper does not directly connect to the B terminal. See Figure 53 for a simplified diagram of the equivalent RDAC circuit. Figure 54. AD5260/AD5262 Equivalent RDAC Circuit The typical distribution of the nominal resistance RAB from channel to channel matches within ±1%. Device-to-device matching is process lot-dependent with the worst case of ±30% variation. However, because the resistance element is processed in thin film technology, the change in RAB with temperature has a low 35 ppm/°C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates output voltages at wiper-to-B and wiper-to-A to be proportional to the input voltage at A-to-B. Ignore the effect of the wiper resistance. For example, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at W-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal A and Terminal B divided by the 256 positions of the potentiometer divider. Because the AD5260/AD5262 operate from dual supplies, the general equation defining the output voltage at VW with respect to ground for any given input voltage applied to Terminal A and Terminal B is VW (D) = D × V AB + V B 256 (3) Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent on the ratio of the internal resistors, RWA and RWB, and not the absolute values; therefore, the drift reduces to 5 ppm/°C. Rev. A | Page 17 of 24 AD5260/AD5262 LAYOUT AND POWER SUPPLY BYPASSING It is good practice to employ a compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance (see Figure 55). Note that the digital ground should also be joined remotely to the analog ground to minimize the ground bounce. C3 + VDD C4 0.1µF + 10µF C2 0.1µF VSS GND 02695-053 VSS Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 56), it is important to power VDD/VSS first before applying any voltage to the A, B, and W terminals. Otherwise, the diode becomes forward biased such that VDD/VSS are powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, VDD, VSS, VL, the digital inputs, and VA/VB/VW. The order of powering VA/VB/VW and the digital inputs is not important as long as they are powered after VDD/VSS. RDAC CIRCUIT SIMULATION MODEL The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider, the −3 dB bandwidth of the AD5260 (20 kΩ resistor) measures 310 kHz at half scale. Figure 28 provides the large signal Bode plot characteristics of the three available resistor versions 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simulation model is shown in Figure 57. The following section provides a macro model net list for the 20 kΩ RDAC. C1 10µF POWER-UP SEQUENCE Figure 55. Power Supply Bypassing TERMINAL VOLTAGE OPERATING RANGE RDAC 20kΩ The AD5260/AD5262 positive VDD and negative VSS power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 56). A B CW CA 25pF CB 25pF 55pF W VDD 02695-071 VDD voltage range of the three terminals extends from VSS to VDD regardless of the digital input level. Figure 57. RDAC Circuit Simulation Model for RDAC 20 kΩ A MACRO MODEL NET LIST FOR RDAC W PARAM D=256, RDAC=20E3 * SUBCKT DPOT (A,W,B) * CA A 0 RWA A W CW W 0 RWB W B CB B 0 * .ENDS DPOT VSS 02695-054 B Figure 56. Maximum Terminal Voltages Set by VDD and VSS The ground pin of the AD5260/AD5262 device is primarily used as a digital ground reference, which needs to be tied to the common ground of the PCB. The digital input control signals to the AD5260/AD5262 must be referenced to the device ground pin (GND), and must satisfy the logic level defined in Table 1. An internal level shift circuit ensures that the common-mode Rev. A | Page 18 of 24 25E-12 {(1-D/256)*RDAC+60} 55E-12 {D/256*RDAC+60} 25E-12 AD5260/AD5262 APPLICATIONS INFORMATION BIPOLAR DC OR AC OPERATION FROM DUAL SUPPLIES The AD5260/AD5262 can be operated from dual supplies enabling control of ground referenced ac signals or bipolar operation. The ac signal, as high as VDD/VSS, can be applied directly across Terminal A and Terminal B with output taken from Terminal W. See Figure 58 for a typical circuit connection. VDD ±2.5V p-p CLK GND MOSI For voltage divider mode operation, shown in Figure 60, it is common to buffer the output of the digital potentiometer unless the load is much larger than RWB. Not only does the buffer serve the purpose of impedance conversion, but it also allows a heavier load to be driven. ±5V p-p SDI D = 0x80 5V GND –5.0V 1 VIN 02695-058 VSS Figure 58. Bipolar Operation from Dual Supplies VO AD8601 8-BIT BIPOLAR DAC Figure 61 shows a low cost 8-bit bipolar DAC. It offers the same number of adjustable steps but not the precision of conventional DACs. The linearity and temperature coefficients, especially at low values codes, are skewed by the effects of the digital potentiometer wiper resistance. The output of this circuit is A W VO 02695-059 U1 W B Figure 60. Programmable Voltage Reference R2 200kΩ Vi A 5V A1 C2 4.7pF C1 25pF 3 GND 2 AD1582 Digital potentiometers are commonly used in gain control as in the noninverting gain amplifier shown in Figure 59. B AD5260 VOUT GAIN CONTROL COMPENSATION R1 47kΩ U1 Figure 59. Typical Noninvertng Gain Amplifier Note that when the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node, it introduces a zero for the 1/βO term with +20 dB/dec, whereas a typical op amp gain bandwidth product (GBP) has −20 dB/dec characteristics. A large R2 and finite C1 can cause this zero’s frequency to fall well below the crossover frequency. Therefore, the rate of closure becomes 40 dB/dec and the system has 0 phase margin at the crossover frequency. The output may ring or oscillate if the input is a rectangular pulse or step function. Similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input. 2D VO = ⎛⎜ − 1⎞⎟ × V REF 256 ⎝ ⎠ (4) +5V AD5260 Vi OP2177 U2 U1 VIN B VOUT TRIM R +5VREF A A2 R +5V W1 Rev. A | Page 19 of 24 –5V –5V REF GND ADR425 OP2177 A1 Depending on the op amp GBP, reducing the feedback resistor may extend the zero’s frequency far enough to overcome the problem. A better approach, however, is to include a compensation capacitor, C2, to cancel the effect caused by C1. Optimum compensation occurs when R1 × C1 = R2 × C2. This is not an option because of the variation of R2. As a result, the R1 × C1 = R2 × C2 relationship can be used, and scale C2 as if R2 is at its maximum value. Doing so may overcompensate and compromise the performance slightly when R2 is set at low values. However, VO W –5V Figure 61. 8-Bit Bipolar DAC 02695-061 CS 02695-060 SS MICROCONTROLLER SCLK Similarly, there are W and A terminal capacitances connected to the output (not shown). Fortunately, their effect at this node is less significant, and the compensation can be avoided in most cases. PROGRAMMABLE VOLTAGE REFERENCE +5.0V VDD it avoids the ringing or oscillation at the worst case. For critical applications, C2 should be found empirically to suit the need. In general, C2 in the range of a few picofarads (pF) to no more than a few tenths of pF is usually adequate for the compensation. AD5260/AD5262 BIPOLAR PROGRAMMABLE GAIN AMPLIFIER For applications that require bipolar gain, Figure 62 shows one implementation. Digital Potentiometer U1 sets the adjustment range. The wiper voltage at W2 can therefore be programmed between Vi and −KVi at a given U2 setting. Configuring A2 in the noninverting mode allows linear gain and attenuation. The transfer function is VO Vi R2 ⎞ ⎛ D2 = ⎛⎜1 + × (1 + K ) − K ⎞⎟ ⎟×⎜ 256 R1 ⎝ ⎠ ⎝ ⎠ PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT For applications that require high current adjustment such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see Figure 63). Vi VO 5V (5) R1 10kΩ P1 RBIAS A CC W N1 U1 where K is the ratio of RWB1/RWA1 set by U1. B A1 SIGNAL LO IL U1 = AD5260 A1 = AD8601, AD8605, AD8541 P1 = FDP360P, NDS9430 N1 = FDV301N, 2N7002 U2 VO OP2177 AD5262 W2 A2 B2 C1 A2 Figure 63. Programmable Boosted Voltage Source R2 VSS Vi A1 B1 W1 VDD –KVi R1 U1 AD5262 02695-062 OP2177 A1 VSS 02695-063 VDD Figure 62. Bipolar Programmable Gain Amplifier Similar to the previous example, in the simpler and more common case, where K = 1, with a single digital potentiometer, AD5260, U1 is replaced by a matched pair of resistors to apply Vi and −Vi at the ends of the digital potentiometer. The relationship becomes R2 ⎞⎛ 2D2 ⎞ VO = ⎛⎜1 + − 1 ⎟ × Vi ⎟⎜ ⎝ R1 ⎠⎝ 256 ⎠ (6) In this circuit, the inverting input of the op amp forces VO to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the P-channel FET, P1. The N-channel FET, N1, simplifies the op amp driving requirement. A1 must be the rail-to-rail input type. Resistor R1 is needed to prevent P1 from turning off once it is on. The choice of R1 is a balance between the power loss of this resistor and the output turn-off time. N1 can be any general-purpose signal FET. However, P1 is driven in the saturation state, and therefore, its power handling must be adequate to dissipate (Vi − VO) × IL power. This circuit can source a maximum of 100 mA at 5 V supply. Higher current can be achieved with P1 in a larger package. Note that a single N-channel FET can replace P1, N1, and R1 altogether. However, the output swing is limited unless separate power supplies are used. For a precision application, a voltage reference such as the ADR423, ADR292, or AD1584 can be applied at the input of the digital potentiometer. If R2 is large, a few picofarad compensation capacitors may be needed to avoid any gain peaking. PROGRAMMABLE 4 mA-TO-20 mA CURRENT SOURCE Table 11 shows the result of adjusting D, with A2 configured as a unity gain, a gain of 2, and a gain of 10. The result is a bipolar amplifier with linearly programmable gain and 256-step resolution. A programmable 4 mA-to-20 mA current source can be implemented with the circuit shown in Figure 64. REF191 is a unique low supply headroom and high current handling precision reference that can deliver 20 mA at 2.048 V. The load current is simply the voltage across Terminal B to Terminal W of the digital potentiometer, divided by RS. Table 11. Result of Bipolar Gain Amplifier D 0 64 128 192 255 R1 = ∞, R2 = 0 −1 −0.5 0 +0.5 +0.968 R1 = R2 −2 −1 0 +1 +1.937 R2 = 9 × R1 −10 −5 0 +5 +9.680 Rev. A | Page 20 of 24 IL = V REF × D RS (7) AD5260/AD5262 +5V Q= 2 VS U1 SLEEP OUTPUT 0V TO (2.048V + VL) 6 C1 1µF GND 4 B W AD5260 (11) Users can first select any convenient value for the capacitors. To achieve maximally flat bandwidth where Q = 0.707, let C1 be twice the size of C2 and let R1 = R2. As a result, users can adjust R1 and R2 to the same settings to achieve the desirable bandwidth. REF191 3 1 1 + R1C1 R2C2 A C1 +5V – –2.048 TO VL +2.5V RS 102Ω OP1177 + R1 VL RL 100Ω –5V IL A Vi 02695-064 U2 R2 B A W R B W AD8601 C2 –2.5V VO R The circuit is simple, but be aware that dual-supply op amps are ideal because the ground potential of REF191 can swing from −2.048 V at zero scale to VL at full scale of the potentiometer setting. Although the circuit works under single supply, the programmable resolution of the system is reduced. PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution (see Figure 65). If the resistors are matched, the load current is IL = (R2 A + R2 B ) R1 R2 B × VW +5V OP2177 B R2A 14.95kΩ A1 –5V VL RL 500Ω IL Figure 65. Programmable Bidirectional Current Source 2 VO = I D R2 B + V D 3 Digital Potentiometer AD5262 can be used to construct a second-order, Sallen-Key low-pass filter (see Figure 66). The design equations are Vi ωO = S2 + ωO 2 ωO Q S + ωO 2 1 R1R2C1C2 (14) When the frequency is set, the oscillation amplitude can be tuned by R2B because PROGRAMMABLE LOW-PASS FILTER = (13) balances the bridge. In practice, R2/R1 should be set slightly larger than 2 to ensure the oscillation can start. However, the alternate turn-on of the diodes, D1 and D2, ensures R2/R1 to be smaller than 2 momentarily and therefore stabilizes the oscillation. RL 50Ω –15V VO 256 − D R AB 256 R2 =2 R1 AD8016 –15V (12) At resonance, setting 02695-065 R1 150kΩ 1 1 or f O = RC 2πRC where R is equal to RWA such that A2 A W In a classic Wien-bridge oscillator (see Figure 67), the Wien network (R, R’, C, C’) provides positive feedback, whereas R1 and R2 provide negative feedback. At the resonant frequency, fo, the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. With R = R’, C = C’, and R2 = R2A//(R2B + RDIODE), the oscillation frequency is R= +15V AD5260 PROGRAMMABLE OSCILLATOR R2' 15kΩ C1 10pF +15V C2 10pF Figure 66. Sallen Key Low-Pass Filter ωO = (8) R1' 150kΩ ADJUSTED TO SAME SETTINGS 02695-066 Figure 64. Programmable 4-to-20 mA Current Source (9) (10) (15) VO, ID, and VD are interdependent variables. With proper selection of R2B, an equilibrium is reached such that VO converges. R2B can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to saturate the output. In both circuits in Figure 66 and Figure 67, the frequency tuning requires that both RDACs be adjusted to the same settings. Because the two channels are adjusted one at a time, an intermedi- Rev. A | Page 21 of 24 AD5260/AD5262 ate state occurs that may not be acceptable for certain applications. As a result, different devices can also be used in daisy-chained mode so that parts can be programmed to the same setting simultaneously. FREQUENCY ADJUSTMENT VP R' 10kΩ A B R 10kΩ A RWB _ eq = +5V D (R1 // R2) + RW 256 (16) D ⎞ RWA _ eq = ⎛⎜1 − ⎟(R1 // R2) + RW 256 ⎝ ⎠ B W W (17) A U1 VO OP1177 AD5262 R2 R2B 10kΩ R1 1kΩ W R1 –5V B W R2A 2.1kΩ D1 B R2