AD5263BRU200

FEATURES FUNCTIONAL BLOCK DIAGRAM 256-position, 4-channel End-to-end resistance 20 kΩ, 50 kΩ, 200 kΩ Pin-selectable SPI®- or I2C®-compatible interface Power-on preset to midscale Two package address decode pins AD0 and AD1 Rheostat mode temperature coefficient 30 ppm/°C Voltage divider temperature coefficient 5 ppm/°C Wide operating temperature range –40°C to +125°C 10 V to 15 V single supply; ±5 V dual supply A1 B1 A2 W2 B2 A3 W3 B3 A4 W4 B4 VSS SHDN RES/AD1 RDAC 1 REGISTER RDAC 2 REGISTER GND Mechanical potentiometer replacement Optical network adjustment Instrumentation: gain, offset adjustment Stereo channel audio level control Automotive electronics adjustment Programmable power supply Programmable filters, delays, time constants Line impedance matching Low resolution DAC/trimmer replacement Base station power amp biasing Sensor calibration RDAC 3 REGISTER RDAC 4 REGISTER 8 VL CLK/SCL SDI/SDA CS/AD0 APPLICATIONS ADDRESS DECODER SPI/I2C SELECT LOGIC AD5263 SERIAL INPUT REGISTER DIS NC/O2 SDO/O1 Figure 1. GENERAL DESCRIPTION The AD5263 is the industry’s first quad-channel, 256-position, digital potentiometer1 with a selectable digital interface. This device performs the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. Each channel of the AD5263 offers a completely programmable value of resistance between the A terminal and the wiper or between the B terminal and the wiper. The fixed A-to-B terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has a nominal temperature coefficient of ±30 ppm/°C and a ±1% channel-tochannel matching tolerance. Another key feature of this part is the ability to operate from +4.5 V to +15 V, or at ±5 V. Rev. F W1 VDD 03142-001 Data Sheet Quad, 15 V, 256-Position, Digital Potentiometer with Pin-Selectable SPI/I2C AD5263 Wiper position programming presets to midscale upon poweron. Once powered, the VR wiper position is programmed by either the 3-wire SPI or 2-wire I2C-compatible interface. In the I2C mode, additional programmable logic outputs enable users to drive digital loads, logic gates, and analog switches in their systems. The AD5263 is available in a narrow body, 24-lead TSSOP. All parts are guaranteed to operate over the automotive temperature range of –40°C to +125°C. For single- or dual-channel applications, refer to the AD5260/AD5280 or AD5262/AD5282 data sheets. 1 The terms digital potentiometer, VR, and RDAC are used interchangeably. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5263 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Multiple Devices on One Bus ................................................... 21 Applications ....................................................................................... 1 Level Shift for Negative Voltage Operation ................................ 21 Functional Block Diagram .............................................................. 1 ESD Protection ........................................................................... 21 General Description ......................................................................... 1 Terminal Voltage Operating Range ......................................... 21 Revision History ............................................................................... 2 Power-Up Sequence ................................................................... 21 Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions ....... 3 VLOGIC Power Supply ................................................................... 22 Timing Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions .......... 5 Layout and Power Supply Bypassing ....................................... 22 Absolute Maximum Ratings ............................................................ 6 RDAC Circuit Simulation Model ............................................. 22 ESD Caution .................................................................................. 6 Applications Information .............................................................. 23 Pin Configuration and Pin Function Descriptions ...................... 7 Bipolar DC or AC Operation from Dual Supplies ................. 23 Typical Performance Characteristics ............................................. 8 Gain Control Compensation .................................................... 23 Test Circuits ..................................................................................... 13 Programmable Voltage Reference ............................................ 23 SPI-Compatible Digital Interface (DIS = 0) ................................ 15 8-Bit Bipolar DAC ...................................................................... 24 Serial Data-Word Format .......................................................... 15 Bipolar Programmable Gain Amplifier ................................... 24 I C-Compatible Digital Interface (DIS = 1) ................................ 16 Programmable Voltage Source with Boosted Output ........... 24 I2C Write Mode Data-Word Format ........................................ 16 Programmable 4 to 20 mA Current Source ............................ 25 I2C Read Mode Data-Word Format ......................................... 16 Programmable Bidirectional Current Source ......................... 25 Operation ......................................................................................... 17 Programmable Low-Pass Filter ................................................ 26 Programming the Variable Resistor ......................................... 17 Programmable Oscillator .......................................................... 26 Programming the Potentiometer Divider Voltage Output Operation..................................................................................... 18 Resistance Scaling ...................................................................... 27 2 Pin-Selectable Digital Interface ................................................ 18 Resistance Tolerance, Drift, and Temperature Coefficient Mismatch Considerations ......................................................... 27 SPI-Compatible 3-Wire Serial Bus (DIS = 0) ......................... 18 Outline Dimensions ....................................................................... 28 2 I C-Compatible 2-Wire Serial Bus (DIS = 1) .......................... 19 Ordering Guide .......................................................................... 28 Additional Programmable Logic Output ................................ 20 Self-Contained Shutdown Function ........................................ 20 REVISION HISTORY 10/12—Rev. E to Rev. F Changes to Self-Contained Shutdown Function Section .......... 20 Added Table 8 and Table 9; Renumbered Sequentially ............. 20 Changes to Programmable Voltage Source with Boosted Output Section .............................................................................................. 24 7/12—Rev. D to Rev. E Changes to SD Description ........................................................... 16 4/12—Rev. C to Rev. D Change to Rheostat Operation Section ....................................... 17 Deleted Equation 4 and Accompanying Text ............................. 18 7/09—Rev. A to Rev. B Change to Features Section ..............................................................1 Change to Power Single-Supply Range Parameter........................4 Changes to Ordering Guide .......................................................... 28 11/06—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Absolute Maximum Ratings ........................................6 Changes to Ordering Guide .......................................................... 28 6/03—Revision 0: Initial Version 5/11—Rev. B to Rev. C Change to Digital Inputs and Output Voltage Parameter.............. 6 Changes to Ordering Guide .......................................................... 28 Changes to I2C Disclaimer ............................................................ 28 Rev. F | Page 2 of 28 Data Sheet AD5263 ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential NL 2 Resistor Nonlinearity2 Nominal Resistor Tolerance 3 Resistance Mode Temperature Coefficient Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity 4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range 5 Capacitance 6 Ax, Bx Capacitance6 Wx Common-Mode Leakage Shutdown Current 7 DIGITAL INPUTS Input Logic High Input Logic Low Input Logic High (SDA and SCL) Input Logic Low (SDA and SCL) Input Current Input Capacitance6 DIGITAL OUTPUTS SDA O1, O2 O1, O2 SDO SDO Three-State Leakage Current Output Capacitance6 Symbol R-DNL R-INL ∆RAB ∆RWB/∆T ∆RWA/∆T RW N DNL INL ∆VW/∆T VWFSE VWZSE VA,B,W CA,B CW ICM ISHDN VIH VIL VIH VIL IIL CIL VOL VOL VOH VOL VOH VOL IOZ COZ Conditions Specifications apply to all VRs RWB, VA = NC RWB, VA = NC TA = 25°C Min Typ 1 Max Unit −1 −1 −30 ±1/4 ±1/2 +1 +1 +30 LSB LSB % ppm/°C 30 30 60 IW = 1 V/RAB Specifications apply to all VRs −1 −1 Code = 0x80 Code = 0xFF Code = 0x00 −2 0 ±1/4 ±1/2 5 −1 +1 VSS f = 1 MHz, measured to GND, Code = 0x80 f = 1 MHz, measured to GND, Code = 0x80 VA = VB = VDD/2 150 8 +1 +1 +0 +2 VDD V pF 55 pF 1 0.02 5 0.8 VL + 0.5 0.3 × VL ±1 0.7 × VL −0.5 5 ISINK = 3 mA ISINK = 6 mA ISOURCE = 40 µA ISINK = 1.6 mA RL = 2.2 kΩ to VDD ISINK = 3 mA VIN = 0 V or +5 V 0.4 0.6 4 0.4 VDD − 0.1 3 Rev. F | Page 3 of 28 Bits LSB LSB ppm/°C LSB LSB 25 2.4 VSS = 0 V VSS = 0 V VIN = 0 V or +5 V ppm/°C Ω 0.4 ±1 8 nA µA V V V V µA pF V V V V V V µA pF AD5263 Parameter POWER SUPPLIES Logic Supply 8 Power Single-Supply Range Power Dual-Supply Range Logic Supply Current 9 Positive Supply Current Negative Supply Current Power Dissipation 10 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 11 Bandwidth (3 dB) Total Harmonic Distortion Data Sheet Symbol VL VDD RANGE VDD/SS RANGE IL IDD ISS PDISS PSS BW THDW VW Settling Time 12 tS Resistor Noise Voltage eN_WB Conditions Min VSS = 0 V 2.7 4.5 ±4.5 VL = +5 V VIH = +5 V or VIL = 0 V VSS = –5 V VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = –5 V ∆VDD = +5 V ± 10% RAB = 20 kΩ/50 kΩ/200 kΩ VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 20 kΩ VA = 10 V, VB = 0 V, ±1 LSB error band RWB = 10 kΩ, f = 1 kHz, RS = 0 1 Typ 1 Max Unit 25 5.5 16.5 ±7.5 60 1 1 0.6 V V V µA µA µA mW 0.002 0.01 %/% 300/150/35 0.05 kHz % 2 µs 9 nV/√Hz Typicals represent average readings at +25°C and VDD = +5 V, VSS = −5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and VSS = –5 V. 3 VAB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 VL is limited to VDD or 5.5 V, whichever is less. 9 Worst-case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. 10 PDISS is calculated from IDD × VDD. CMOS logic level inputs result in minimum power dissipation. 11 All dynamic characteristics use VDD = +5 V, VSS = −5 V, VL = +5 V. 12 Settling time depends on value of VDD, RL, and CL. 2 Rev. F | Page 4 of 28 Data Sheet AD5263 TIMING CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter SPI INTERFACE TIMING CHARACTERISTICS Clock Frequency Input Clock Pulse Width Data Setup Time Data Hold Time CS Setup Time CS High Pulse Width CLK Fall to CS Fall Hold Time CLK Fall to CS Rise Hold Time CS Rise to Clock Rise Setup Reset Pulse Width I2C INTERFACE TIMING CHARACTERISTICS SCL Clock Frequency tBUF Bus Free Time Between Stop and Start tHD;STA Hold Time (Repeated Start) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Start Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for Stop Condition 1 2 3 Symbol fCLK tCH, tCL tDS tDH tCSS tCSW tCSH0 tCSH1 tCS1 tRS Conditions Specifications apply to all parts 2, 3 Min Clock level high or low 20 10 10 15 20 0 0 10 5 Typ 1 Max Unit 25 MHz ns ns ns ns ns ns ns ns ns 400 kHz µs µs Specifications apply to all parts2, 3 fSCL t1 t2 After this period, the first clock pulse is generated. t3 t4 t5 t6 t7 t8 t9 t10 1.3 0.6 1.3 0.6 0.6 50 0.9 100 300 300 0.6 µs µs µs µs ns ns ns µs Typicals represent average readings at +25°C and VDD = +5 V, VSS = −5 V Guaranteed by design and not subject to production test. See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using VL = 5 V. Rev. F | Page 5 of 28 AD5263 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VSS to GND VDD to VSS VL to GND VA, VB, VW to GND Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx Pulsed1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Thermal Resistance2 θJA TSSOP-24 Value −0.3 V to +16.5 V −7.5 V to 0 V +16.5 V −0.3 V to +6.5 V VSS to VDD ±20 mA ±3 mA −0.3 V to +7 V −40°C to +85°C 150°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 260°C 20 sec to 40 sec 143°C/W 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation: (TJMAX − TA)/θJA. Rev. F | Page 6 of 28 Data Sheet AD5263 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS B1 1 24 B2 A1 2 23 A2 W1 3 22 W2 AD5263 B4 TOP VIEW A3 5 (Not to Scale) 20 A4 19 W4 W3 6 21 VDD 7 18 VSS GND 8 17 NC/O2 DIS 9 16 SDO/O1 VLOGIC 10 15 SHDN SDI/SDA 11 14 RES/AD1 CLK/SCL 12 13 CS/AD0 03142-072 B3 4 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin 1 2 3 4 5 6 7 Name B1 A1 W1 B3 A3 W3 VDD Description Resistor Terminal B1. Resistor Terminal A1 (ADDR = 00). Wiper Terminal W1. Resistor Terminal B3. Resistor Terminal A3. Wiper Terminal W3 (ADDR = 10). Positive Power Supply, specified for +5 V to +15 V operation. 8 9 10 GND DIS VLOGIC 11 12 13 14 15 16 SDI/SDA CLK/SCL CS/AD0 RES/AD1 SHDN SDO/O1 17 18 NC/O2 VSS Ground. Digital Interface Select (SPI/I2C Select). SPI when DIS = 0, I2C when DIS = 1 2.7 V to 5.5 V Logic Supply Voltage. The logic supply voltage should always be less than or equal to VDD. In addition, logic levels must be limited to the logic supply voltage regardless of VDD. SDI = 3-Wire Serial Data Input. SDA = 2-Wire Serial Data Input/Output. Serial Clock Input. Chip Select in SPI Mode. Device Address Bit 0 in I2C Mode. RESET in SPI Mode. Device Address Bit 1 in I2C Mode. Shutdown. Shorts wiper to Terminal B, opens Terminal A. Tie to +5 V supply if not used. Do not tie to VDD if VDD > 5 V. Serial Data Output in SPI Mode. Open-drain transistor requires pull-up resistor. Digital Output O1 in I2C Mode. Can be used to drive external logic. No Connection in SPI Mode. Digital Output O2 in I2C Mode. Can be used to drive external logic. Negative Power Supply. Specified for operation from 0 V to –5 V. 19 20 21 22 23 24 W4 A4 B4 W2 A2 B2 Wiper Terminal W4 (ADDR = 11). Resistor Terminal A4. Resistor Terminal B4. Wiper Terminal W2 (ADDR = 01). Resistor Terminal A2. Resistor Terminal B2. Rev. F | Page 7 of 28 AD5263 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS RAB = 20 kΩ, unless otherwise noted. 1.0 1.0 ±5V 0.8 –40°C +25°C +85°C +125°C 0.8 RHEOSTAT MODE INL (LSB) 0.6 0.4 0.2 0 –0.2 –0.4 0.6 0.4 0.2 0 –0.2 –0.4 –0.8 –1.0 0 32 64 96 128 160 192 224 03142-004 –0.6 –0.6 03142-073 RHEOSTAT MODE DNL (LSB) +15/0V –0.8 –1.0 0 256 32 64 CODE (Decimal) 224 256 1.0 1.0 ±5V +15/0V 0.8 0.6 POTENTIOMETER MODE INL (LSB) ±5V +15/0V 0.4 0.2 0 –0.2 –0.4 03142-002 –0.6 –0.8 –1.0 0 32 64 96 128 160 192 224 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 03142-005 0.8 RHEOSTAT MODE INL (LSB) 192 Figure 6. R-INL vs. Code; VDD = ±5 V Figure 3. R-DNL vs. Code vs. Supply Voltage –0.8 –1.0 0 256 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 7. INL vs. Code vs. Supply Voltage Figure 4. R-INL vs. Code vs. Supply Voltage 1.0 1.0 0.4 0.2 0 –0.2 –0.4 03142-003 –0.6 –0.8 –1.0 0 32 64 96 128 160 192 224 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 03142-007 POTENTIOMETER MODE INL (LSB) 0.6 –40°C +25°C +85°C +125°C 0.8 –40°C +25°C +85°C +125°C 0.8 RHEOSTAT MODE DNL (LSB) 160 96 128 CODE (Decimal) –0.8 –1.0 256 0 32 64 96 128 160 192 CODE (Decimal) CODE (Decimal) Figure 8. INL vs. Code vs. Supply Voltage Figure 5. R-DNL vs. Code; VDD = ±5 V Rev. F | Page 8 of 28 224 256 Data Sheet AD5263 2.0 1.0 –40°C +25°C +85°C +125°C 0.6 VDD/VSS = +4.5/0V 1.8 1.6 0.4 1.4 0.2 1.2 0 –0.2 1.0 0.8 –0.4 0.6 –0.6 0.4 –0.8 0 64 32 96 128 160 192 224 0.2 0 –40 256 –20 0 CODE (Decimal) Figure 9. INL vs. Code; VDD = ±5 V 120 VLOGIC = 5V VIH = 5V VIL = 0V 0.2 0 –0.2 –0.4 –0.6 –0.8 0 32 64 96 128 160 192 224 1 ISS @ VDD/VSS = ±5V 0.1 IDD @ VDD/VSS = +15/0V 0.01 IDD @ VDD/VSS = ±5V 0.001 –40 256 0 40 80 120 TEMPERATURE (°C) CODE (Decimal) Figure 13. Supply Current vs. Temperature Figure 10. DNL vs. Code; VDD = ±5 V 10 0 SHUTDOWN CURRENT (µA) –0.5 VDD/VSS = +16.5/0V –1.0 VDD/VSS = ±5V –1.5 VDD/VSS = +4.5/0V 1 0.1 VDD/VSS = ±5V 0.01 –2.0 03142-009 –2.5 –40 VDD/VSS = +15/0V –20 0 20 40 60 TEMPERATURE (°C) 80 100 0.001 –40 120 0 40 80 TEMPERATURE (°C) Figure 14. Shutdown Current vs. Temperature Figure 11. Full-Scale Error vs. Temperature Rev. F | Page 9 of 28 120 03142-011 IDD/ISS SUPPLY CURRENT (µA) 0.6 0.4 03142-008 POTENTIOMETER MODE DNL (LSB) 100 10 –40°C +25°C +85°C +125°C 0.8 FSE (LSB) 80 Figure 12. Zero-Scale Error vs. Temperature 1.0 –1.0 20 40 60 TEMPERATURE (°C) 03142-012 –1.0 VDD/VSS = +16.5/0V 03142-010 ZSE (LSB) VDD/VSS = ±5V 03142-007 POTENTIOMETER MODE INL (LSB) 0.8 AD5263 Data Sheet 150 ILOGIC (µA) VDD/VSS = +15/0V 25 VDD/VSS = ±5V 24 03142-013 23 22 –40 0 40 80 50 0 –50 –100 –150 –200 –250 120 20kΩ 50kΩ 200kΩ 100 03142-016 26 POTENTIOMETER MODE TEMPCO (ppm/°C) 27 0 32 64 96 TEMPERATURE (°C) Figure 15. ILOGIC vs. Temperature 160 192 224 256 Figure 18. Potentiometer Mode Tempco ∆RWB/∆T vs. Code 85 0 80 –6 RON @ VDD/VSS = +5/0V 0x80 0x40 –12 75 0x20 –18 0x10 70 GAIN (dB) WIPER RESISTANCE (Ω) 128 CODE (Decimal) RON @ VDD/VSS = ±5V 65 60 –24 0x08 –30 0x04 –36 0x02 –42 RON @ VDD/VSS = +15/0V 55 0x01 –48 45 –5 0 5 10 TA = 25°C VA = 50mV rms VDD/VSS = ±5V –54 –60 15 1k VBIAS (V) 100k 1M FREQUENCY (Hz) Figure 16. Wiper On-Resistance vs. Bias Voltage Figure 19. Gain vs. Frequency vs. Code; RAB = 20 kΩ 0 700 20kΩ 50kΩ 200kΩ 500 0x80 –6 0x40 –12 300 0x20 GAIN (dB) –18 100 –100 0x10 –24 0x08 –30 0x04 –36 0x02 –42 –300 0x01 –48 –700 0 32 64 96 128 160 192 224 256 CODE (Decimal) TA = 25°C VA = 50mV rms VDD/VSS = ±5V –54 –60 1k 10k 100k FREQUENCY (Hz) Figure 20. Gain vs. Frequency vs. Code; RAB = 50 kΩ Figure 17. Rheostat Mode Tempco ∆RWB/∆T vs. Code Rev. F | Page 10 of 28 03142-018 –500 03142-015 RHEOSTAT MODE TEMPCO (ppm/°C) 10k 03142-017 03142-014 50 1M Data Sheet AD5263 0 0x80 –6 –12 0x20 –18 0x10 –24 0x08 –30 VW 1 0x04 –36 0x02 –42 0x01 TA = 25°C VA = 50mV rms VDD/VSS = ±5V –54 –60 1k 10k 03142-022 –48 03142-0-019 GAIN (dB) CODE = 0x80 VDD/VSS = ±5.5V VB/VA= ±5V 0x40 CH1 50.0mV 100k M100ns A CH2 2.70V FREQUENCY (Hz) Figure 24. Digital Feedthrough Figure 21. Gain vs. Frequency vs. Code; RAB = 200 kΩ 0 R = 20kΩ 300kHz –6 T VDD/VSS = 5/0V VA = 5V VB = 0V –12 R = 50kΩ 150kHz GAIN (dB) –18 –24 R = 200kΩ 35kHz –30 1 –36 VW –42 –60 1k 10k 03142-020 TA = 25°C VDD/VSS = ±5V VA = 50mV rms –54 03142-023 –48 CH1 50.0mV 1M 100k T20.00% M2.00µs A CH2 2.00V FREQUENCY (Hz) Figure 25. Midscale Glitch; Code 0x80 to 0x7F (4.7 nF Capacitor Used from Wiper to Ground) Figure 22. Gain vs. Frequency at –3 db Bandwidth 80 VDD/VSS = ±5.5V VA/VB = ±5V CODE = 0x80, VA = VDD, VB = 0V VW 60 1 40 +PSRR @ VDD/VSS = ±5V DC ± 10% p-p AC CS 20 0 100 1k 10k 100k 1M 03142-024 2 03142-021 PSRR (–dB) –PSRR @ VDD/VSS = ±5V DC ± 10% p-p AC CH1 5.00V CH2 5.00V M400ns A CH1 2.70V FREQUENCY (Hz) Figure 26. Large Signal Settling Time; Code 0x00 to 0xFF Figure 23. PSRR vs. Frequency Rev. F | Page 11 of 28 AD5263 Data Sheet 1.0 2.0 RAB = 20kΩ TA = 25°C 1.0 R-INL (LSB) Avg – 3σ Avg Avg – 3σ 0 –0.5 0.5 Avg – 3σ Avg Avg – 3σ 0 –0.5 –1.0 0 5 10 |VDD – VSS| (–V) 15 –2.0 20 Figure 27. INL vs. Supply Voltage 03142-026 –1.5 03142-025 INL (LSB) 0.5 –1.0 RAB = 20kΩ TA = 25°C 1.5 0 5 10 |VDD – VSS| (V) 15 Figure 28. R-INL vs. Supply Voltage Rev. F | Page 12 of 28 20 Data Sheet AD5263 TEST CIRCUITS Figure 29 to Figure 39 define the test conditions used in the Electrical Characteristics—20 KΩ, 50 KΩ, 200 KΩ Versions section and the Timing Characteristics—20 KΩ, 50 KΩ, 200 KΩ Versions. A DUT B 5V W W OP279 B VMS OFFSET GND Figure 29. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) VOUT 03142-032 V+ DUT VIN 03142-028 A V+ = VDD 1LSB = V+/2N OFFSET BIAS Figure 33. Test Circuit for Inverting Gain 5V NO CONNECT OP279 DUT W W OFFSET GND B Figure 34. Test Circuit for Noninverting Gain +15V IW = VDD/R NOMINAL W VW W VIN OFFSET GND 2.5V Figure 31. Test Circuit for Wiper Resistance W B ΔVMS% ISW 0.1V ΔVDD% VSS TO VDD 03142-035 VMS 0.1V ISW CODE = 0x00 ΔVMS ΔV DD 03142-031 W PSS (%/%) = B RSW = DUT V+ = VDD 10% A –15V Figure 35. Test Circuit for Gain vs. Frequency VA PSRR (dB) = 20 log VOUT B 03142-034 RW = [VMS1 – VMS2]/I W 03142-030 VMS1 V+ DUT AD8610 B VDD B A DUT VMS2 DUT OFFSET BIAS Figure 30. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) A A 03142-029 VMS 03142-033 A VOUT VIN IW Figure 36. Test Circuit for Incremental On Resistance Figure 32. Test Circuit for Power Supply Sensitivity (PSS, PSRR) Rev. F | Page 13 of 28 AD5263 Data Sheet A VSS GND B W N/C ICM W1 A2 RDAC 2 W2 VIN B1 VCM 03142-036 VDD DUT VDD NC VSS CTA = 20 log [VOUT/VIN] Figure 37. Test Circuit for Common-Mode Leakage Current VOUT B2 03142-038 A1 RDAC 1 NC Figure 39. Test Circuit for Analog Crosstalk ILOGIC VLOGIC SCL 03142-037 SCA Figure 38. Test Circuit for VLOGIC Current vs. Digital Input Voltage Rev. F | Page 14 of 28 Data Sheet AD5263 SPI-COMPATIBLE DIGITAL INTERFACE (DIS = 0) SERIAL DATA-WORD FORMAT Addr B9 A1 29 B8 A0 MSB Data B7 D7 27 LSB B6 D6 B5 D5 1 CLK CS VOUT 0 1 A1 A0 D7 D6 0 1 D5 D4 B3 D3 D3 D2 D1 B2 D2 B1 D1 B0 D0 20 D0 RDAC REGISTER LOAD 0 1 03142-039 SDI B4 D4 0 Figure 40. AD5263 Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) 1 SDI (DATA IN) Dx Dx 0 tCH tDS tCS1 tCH 1 CLK 0 tCSHO tCL tCSH1 tCSS 1 CS tC-SW 0 tS 0 ±LSB Figure 41. Detailed SPI Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) Rev. F | Page 15 of 28 03142-040 VOUT VDD AD5263 Data Sheet I2C-COMPATIBLE DIGITAL INTERFACE (DIS = 1) The word format maps in this section use the following abbreviations. Abbreviation S P A AD1, AD0 A1, A0 RS SD Description Start condition. Stop condition. Acknowledge. I2C device address bits. Must match with the logic states at Pin AD1 and Pin AD0. Refer to Figure 49. RDAC channel select. Software reset wiper (A1, A0) to midscale position. Shutdown active high; ties wiper (A1, A0) to Terminal B, opens Terminal A, RDAC register contents are not disturbed. To exit shutdown, the command SD = 0 must be executed for each RDAC (A1, A0). Data to digital output pins, Pin O1 and Pin O2 in I2C mode, used to drive external logic. The logic high level is determined by VL and the logic low level is GND. Write = 0. Read = 1. Data bits. O1, O2 W R D7, D6, D5, D4, D3, D2, D1, D0 X Don’t care. I2C WRITE MODE DATA-WORD FORMAT S 0 1 0 1 1 AD1 AD0 A W X A1 A0 Slave Address Byte RS SD O1 O2 X A D7 D6 D5 D4 Instruction Byte D3 D2 D1 D0 A P Data Byte I2C READ MODE DATA-WORD FORMAT S 0 1 0 1 1 AD1 Slave Address Byte AD0 R A t8 D7 D8 D5 D4 D3 Data Byte D2 D1 D0 A P t2 t9 SCL t2 t4 t3 t8 t10 t5 t7 t9 03142-041 SDA t1 P S P S Figure 42. Detailed I2C Timing Diagram 1 9 9 1 1 9 SCL 1 0 1 1 X AD1 AD0 R/W A1 ACK BY AD5263 FRAME 1 SLAVE ADDRESS BYTE A0 RS SD O1 O2 X D7 D6 D5 ACK BY AD5263 FRAME 1 INSTRUCTION BYTE D4 D3 D2 D1 D0 ACK BY AD5263 STOP BY MASTER FRAME 1 DATABYTE Figure 43. Writing to the RDAC Register 1 9 1 9 SCL SDA START BY MASTER 0 1 0 1 1 D7 AD1 AD0 R/W FRAME 1 SLAVE ADDRESS BYTE D6 ACK BY AD5263 D5 D4 D3 D2 D1 FRAME 2 RDAC REGISTER Figure 44. Reading Data from a Previously Selected RDAC Register in Write Mode Rev. F | Page 16 of 28 D0 NO ACK BY MASTER STOP BY MASTER 03142-042 START BY MASTER 0 03142-043 SDA Data Sheet AD5263 OPERATION The AD5263 is a quad-channel, 256-position, digitally controlled, variable resistor (VR) device. To program the VR settings, refer to the SPI-Compatible Digital Interface (DIS = 0) section and the I2C-Compatible Digital Interface (DIS = 1) section. The part has an internal power-on preset that places the wiper at midscale during power-on, simplifying the fault condition recovery at power-up. In addition, the shutdown (SHDN) pin of AD5263 places the RDAC in an almost zero-power consumption state where Terminal A is open circuited and the wiper W is connected to Terminal B, resulting in only leakage current consumption in the VR structure. During shutdown, the VR latch settings are maintained or new settings can be programmed. When the part is returned from shutdown, the corresponding VR setting is applied to the RDAC. (RAB – 1 LSB + 2 × RW). Figure 45 shows a simplified diagram of the equivalent RDAC circuit, where the last resistor string is not accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. The general equation determining the digitally programmed output resistance between the W and B terminals is RWB (D) = D × RAB + 2 × RW 256 (1) where: D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on-resistance of one internal switch. Ax In summary, if RAB = 20 kΩ and the A terminal is open circuited, the RDAC latch codes in Table 5 result in the corresponding output resistance, RWB. SD BIT RS D7 D6 D5 D4 D3 D2 D1 D0 RS Table 5. Codes and Corresponding RWB Resistances D (Dec) 255 128 1 0 RS Wx RDAC Bx Output State Full-scale (RAB − 1 LSB + 2 × RW) Midscale 1 LSB + 2 × RW Zero-scale (wiper contact resistance) Note that in the zero-scale condition a finite wiper resistance of 120 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. 03142-044 LATCH AND DECODER RS RWB (Ω) 20,042 10,120 198 120 Figure 45. AD5263 Equivalent RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal B is available in 20 kΩ, 50 kΩ, and 200 kΩ. The final two or three digits of the part number determine the nominal resistance value, for example, 20 kΩ = 20; 50 kΩ = 50; 200 kΩ = 200. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assuming a 20 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Because there is a 60 Ω wiper contact resistance, such a connection yields a minimum of 2 × 60 Ω resistance between the W and B terminals. The second connection is the first tap point, and corresponds to 198 Ω (RWB = RAB/256 + RW = 78 Ω + 2 × 60 Ω) for Data 0x01. The third connection is the next tap point representing 276 Ω (RWB = 78 Ω × 2 + 2 × 60 Ω) for Data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 20,042 Ω Similar to the mechanical potentiometer, the resistance of the RDAC between the W wiper and Terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is 256 − D (2) RWA (D) = × RAB + 2 × RW 256 For RAB = 20 kΩ and the B terminal is open circuited, the RDAC latch codes in Table 6 result in the corresponding output resistance RWA. Table 6. Codes and Corresponding RWA Resistances D (Dec) 255 128 1 0 Rev. F | Page 17 of 28 RWA (Ω) 198 10,120 20,042 20,120 Output State Full scale Midscale 1 LSB + 2 × RW Zero scale AD5263 Data Sheet The typical distribution of the end-to-end resistance RAB from channel to channel matches within ±1%. Device-to-device matching is process-lot dependent, and it is possible to have ±30% variation. Because the resistance element is processed in thin film technology, the change in RAB with temperature has a very low temperature coefficient of 30 ppm/°C. PROGRAMMING THE POTENTIOMETER DIVIDER VOLTAGE OUTPUT OPERATION The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage from Terminal A and Terminal B. Unlike the polarity from VDD to VSS, which must be positive, the voltage across A to B, W to A, and W to B can be at either polarity, if VSS is powered by a negative supply. If the effect of the wiper resistance for approximation is ignored, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage from the wiper to B, starting at 0 V up to 1 LSB below 5 V. Each LSB step of voltage is equal to the voltage applied across Terminal A to Terminal B divided by the 256 positions of the potentiometer divider. Because the AD5263 can be powered by dual supplies, the general equation defining the output voltage VW with respect to ground for any valid input voltages applied to Terminal A and Terminal B is D 256 − D VA + VB 256 256 (3) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistances RWA and RWB, and not their absolute values; therefore, the temperature drift reduces to 5 ppm/°C. The AD5263 contains a 3-wire SPI-compatible digital interface (SDI, CS, and CLK). The 10-bit serial word must be loaded with address bits A1 and A0, followed by the data byte, MSB first. The format of the word is shown in the Serial Data-Word Format section and bit map. The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. When CS is low, the clock loads data into the serial register on each positive clock edge (see Figure 40). Table 7. AD5263 Address Decode Table A1 0 0 1 1 A0 0 1 0 1 Latch Loaded RDAC 1 RDAC 2 RDAC 3 RDAC 4 The data setup and data hold times in the specification table determine the valid timing requirements. The AD5263 uses a 10-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. Note that only the last 10 bits that are clocked into the register are latched into the decoder. As CS goes high, it activates the address decoder and updates the corresponding channel according to Table 7. During shutdown (SHDN), the serial data output (SDO) pin is forced to logic high in order to avoid power dissipation in the external pull-up resistor. For an equivalent SDO output circuit schematic, see Figure 46. PIN-SELECTABLE DIGITAL INTERFACE SHDN SDO The AD5263 provides the flexibility of a selectable interface. When the digital interface select (DIS) pin is tied low, the SPI mode is engaged. When the DIS pin is tied high to the VL supply, the I2C mode is engaged. CS SDI SERIAL REGISTER D CK CLK RES Q RS 03142-045 VW (D ) = SPI-COMPATIBLE 3-WIRE SERIAL BUS (DIS = 0) Figure 46. Detailed SDO Output Schematic of the AD5263 During reset (RES), the wiper is set to midscale. Note that unlike SHDN, when the part is taken out of reset, the wiper remains at midscale and does not revert to its pre-reset setting. Rev. F | Page 18 of 28 Data Sheet AD5263 Daisy-Chain Operation The serial data output (SDO) pin contains an open-drain N-channel FET. This output requires a pull-up resistor in order to transfer data to the SDI pin of the next package. This allows for daisy-chaining several RDACs from a single processor serial data line. The pull-up resistor termination voltage can be greater than the VDD supply voltage. It is recommended to increase the clock period when using a pull-up resistor to the SDI pin of the following device because capacitive loading at the daisy-chain node (SDO to SDI) between devices may induce time delay to subsequent devices. Users should be aware of this potential problem to achieve data transfer successfully (see Figure 47). If two AD5263s are daisy-chained, a total of 20 bits of data is required. The first 10 bits, complying with the format shown in the Serial Data-Word Format section and bit map, go to U2 and the second 10 bits, with the same format, go to U1. CS should be kept low until all 20 bits are clocked into their respective serial registers. After this, CS is pulled high to complete the operation and load the RDAC latch. Data appears on SDO on the negative edge of the clock, thus making it available to the input of the daisy-chained device on the rising edge of the next clock. The 2-wire I2C serial bus protocol operates as follows. 1. The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master reads from the slave device. If the R/W bit is low, the master writes to the slave device. 2. VL SPI U1 SDI SDO CS CLK RP 2.2kΩ AD5263 U2 SDI In write mode, the second byte is the instruction byte. The first bit (MSB) of the instruction byte is a don’t care. The following two bits, labeled A1 and A0, are the RDAC subaddress select bits. The fourth MSB (RS) is the midscale reset. A logic high on this bit moves the wiper of the selected channel to the center tap where RWA = RWB. This feature effectively writes over the contents of the register, so that when taken out of reset mode, the RDAC remains at midscale. SDO CS CLK 03142-046 MOSI CLK CS AD5263 The master initiates a data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 43). The following byte is the slave address byte, which consists of the 7-bit slave address followed by an R/W bit. This R/W bit determines whether data will be read from or written to the slave device. Figure 47. Daisy-Chain Configuration I2C-COMPATIBLE 2-WIRE SERIAL BUS (DIS = 1) In the I2C-compatible mode, the RDACs are connected to the bus as slave devices. Referring to the bit maps in the I2C-Compatible Digital Interface (DIS = 1) section, the first byte of the AD5263 is a slave address byte, consisting of a 7-bit slave address and a R/W bit. The five MSBs are 01011 and the following two bits are determined by the state of the AD0 and AD1 pins of the device. AD0 and AD1 allow the user to place up to four of the I2Ccompatible devices on one bus. The fifth MSB (SD) is the shutdown bit. A logic high causes the selected channel to open circuit at Terminal A while shorting the wiper to Terminal B. This operation yields almost 0 Ω in rheostat mode or 0 V in potentiometer mode. This SD bit serves the same function as the SHDN pin except that the SHDN pin reacts to active low. In addition, the SHDN pin affects all channels, as opposed to the SD bit, which affects only the channel being written to. It is important to note that the shutdown operation does not disturb the contents of the register. When brought out of shutdown, the previous setting is applied to the RDAC. The next two bits are O2 and O1. They are extra programmable logic outputs that can be used to drive other digital loads, logic gates, LED drivers, analog switches, etc. The LSB is a don’t care bit (see the bit map in the I2C Write Mode Data-Word Format section). After acknowledging the instruction byte, the last byte in write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 43). Rev. F | Page 19 of 28 AD5263 In read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, where there are eight data bits followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 44). Note that the channel of interest is the one that was previously selected in write mode. In cases where users need to read the RDAC values of both channels, they must program the first channel in write mode and then change to read mode to read the first channel value. After that, they must change back to write mode with the second channel selected and read the second channel value in read mode again. It is not necessary for users to issue the Frame 3 data byte in the write mode for subsequent readback operation. Refer to Figure 44 for the programming format. 4. After all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition (see Figure 43). In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, which goes high to establish a stop condition (see Figure 44). A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. For example, after the RDAC has acknowledged its slave address and instruction bytes in the write mode, the RDAC output updates on each successive byte. If different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed. ADDITIONAL PROGRAMMABLE LOGIC OUTPUT The AD5263 features additional programmable logic outputs, O1 and O2, which can be used to drive a digital load, analog switches, and logic gates. O1 and O2 default to Logic 0. The voltage level can swing from GND to VL. The logic states of O1 and O2 can be programmed in Frame 2 under write mode (see Figure 43). These logic outputs have adequate current driving capability to sink/source milliamperes of load. • Do not complete the write cycle by not issuing the stop, then start, slave address byte, acknowledge, instruction byte with O1 and O2 specified, acknowledge, stop. SELF-CONTAINED SHUTDOWN FUNCTION Shutdown can be activated by strobing the SHDN pin or programming the SD bit in the write mode instruction byte. In addition, shutdown can even be implemented with the device’s digital output, as shown in Figure 48. In this configuration, the device is shut down during power-up, but users are allowed to program the device. Thus, when O1 is programmed high, the device exits from the shutdown mode and responds to the new setting. This self-contained shutdown function allows absolute shutdown during power-up, which is crucial in hazardous environments, without adding extra components. O1 SHDN RPULL-DOWN AD5263 SDA 03142-047 3. Data Sheet SCL Figure 48. Shutdown by Internal Logic Output If the shutdown function is enabled by using the SD bit, see the I2C Write Mode Data-Word Format section. Table 8 and Table 9 show the sequences that can place any channel in an undesirable shutdown state. Table 8. Direct Sequence Command Sequence Write RDAC 1, SHDN RDAC 2 Write RDAC 2, SHDN RDAC 1 Write RDAC 3, SHDN RDAC 4 Write RDAC 4, SHDN RDAC 3 RDAC Shutdown RDAC1 and RDAC2 RDAC1 and RDAC2 RDAC3 and RDAC4 RDAC3 and RDAC4 To overcome the issue, employ the following sequence, as an example for the first case: • Start, slave address byte, acknowledge, instruction byte (write RDAC1), acknowledge, data byte, acknowledge, stop. • Start, slave address byte, acknowledge, instruction byte (write RDAC1), acknowledge, stop. • Start, slave address byte, acknowledge, instruction byte (SHDN RDAC2), acknowledge, data byte, acknowledge, stop. Table 9. Indirect Sequence Users can also activate O1 and O2 in three different ways without affecting the wiper settings. They may do the following: Command Sequence Write RDAC 1, SHDN RDAC 1, SHDN RDAC 4 • Start, slave address byte, acknowledge, instruction byte with O1 and O2 specified, acknowledge, Stop. Write RDAC 3, SHDN RDAC 3, SHDN RDAC 2 • Complete the write cycle with stop, then start, slave address byte, acknowledge, instruction byte with O1 and O2 specified, acknowledge, stop. To overcome this issue, swap the SHDN order command, for example, write RDAC 1, SHDN RDAC 4, and then SHDN RDAC 1. Rev. F | Page 20 of 28 RDAC Shutdown RDAC1, RDAC3, and RDAC4 RDAC1, RDAC2, and RDAC3 Data Sheet AD5263 +5V Figure 49 shows four AD5263 devices on the same serial bus. Each has a different slave address because the states of their AD0 and AD1 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device output bus line drivers are open-drain, pull-downs in a fully I2C-compatible interface. 0V VIN R3 1kΩ Q1 2N3906 Q2 2N3906 VOUT R2 10kΩ R1 10kΩ 0V –5V –5V +5V 03142-051 MULTIPLE DEVICES ON ONE BUS –5V Figure 51. Level Shift for Bipolar Potential Operation RP ESD PROTECTION SCL SDA SCL AD1 SDA SCL AD1 AD0 AD0 AD0 AD0 AD5263 AD5263 AD5263 AD5263 03142-048 SDA SCL AD1 SDA SCL AD1 5V 340Ω Figure 49. Multiple AD5263 Devices on One I2C Bus VSS Figure 52. ESD Protection of Digital Pins LEVEL SHIFT FOR NEGATIVE VOLTAGE OPERATION The digital potentiometer is popular in laser diode driver and certain telecommunication equipment level-setting applications. These applications are sometimes operated between ground and some negative supply voltage so that the systems can be biased at round to avoid large bypass capacitors that may significantly impede the ac performance. Like most digital potentiometers, the AD5263 can be configured with a negative supply (see Figure 50). VDD AD5263 VSS A,B,W VSS Figure 53. ESD Protection of Resistor Terminals TERMINAL VOLTAGE OPERATING RANGE The AD5263 positive VDD and negative VSS power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or VSS are clamped by the internal forward-biased diodes shown in Figure 54. VDD GND LEVEL SHIFTED SDA LEVEL SHIFTED SCL 03142-050 –5V LOGIC A Figure 50. Biased at Negative Voltage W However, the digital inputs must also be level shifted to allow proper operation because the ground is referenced to the negative potential. As a result, Figure 51 shows one implementtation with a couple of transistors and a few resistors. When VIN is high, Q1 is turned on and its emitter is clamped at one threshold above ground. This threshold appears at the base of Q2, which causes Q2 to turn off. In this state, VOUT approaches −5 V. When VIN is low, Q1 is turned off and the base of Q2 is pulled low, which in turn causes Q2 to turn on. In this state, VOUT approaches 0 V. Beware that proper time shifting is also needed for successful communication with the device. B VSS 03142-054 5V 5V All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 52 and Figure 53. This protection applies to digital input pins SDI/SDA, CLK/SCL, CS/AD0, RES/AD1, and SHDN. 03142-052 SDA MASTER 03142-053 RP Figure 54. Maximum Terminal Voltages Set by VDD and VSS POWER-UP SEQUENCE Because the ESD protection diodes limit the voltage compliance at the A, B, and W terminals (see Figure 54), it is important to power VDD and VSS before applying any voltage to the A, B, and W terminals; otherwise, the diodes are forward biased such that VDD and VSS are powered unintentionally and may affect the rest of the circuit. The ideal power-up sequence is in the following order: GND, VDD, VSS, VL, digital inputs, and VA/B/W. The relative order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VDD and VSS. Rev. F | Page 21 of 28 AD5263 Data Sheet VLOGIC POWER SUPPLY RDAC CIRCUIT SIMULATION MODEL The AD5263 is capable of operating at high voltages beyond the internal logic levels, which are limited to operation at 5 V. As a result, VL always needs to be tied to a separate 2.7 V to 5.5 V source to ensure proper digital signal levels. Logic levels must be limited to VL, regardless of VDD. In addition, VL should always be less than or equal to VDD. The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider, the –3 dB bandwidth of the AD5263 (20 kΩ resistor) measures 300 kHz at half scale. Figure 22 provides the large signal BODE plot characteristics of the three available resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simulation model is shown in Figure 56. The following code provides a macro model net list for the 20 kΩ RDAC. It is a good practice to employ compact, minimum-lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF ceramic disc or chip capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 55). Notice the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. VDD VDD C3 10µF + C1 0.1µF C4 10µF + C2 0.1µF AD5263 VSS GND RDAC 20kΩ B CB 25pF CA 25pF CW 55pF W Figure 56. RDAC Circuit Simulation Model for RDAC = 20 kΩ Listing 1. Macro Model Net List for RDAC .PARAM D=256, RDAC=20E3 * .SUBCKT DPOT (A,W,B) * CA A 0 25E-12 RWA A W {(1-D/256)*RDAC+60} CW W 0 55E-12 RWB W B {D/256*RDAC+60} CB B 0 25E-12 * .ENDS DPOT 03142-055 VSS A 03142-069 LAYOUT AND POWER SUPPLY BYPASSING Figure 55. Power Supply Bypassing Rev. F | Page 22 of 28 Data Sheet AD5263 APPLICATIONS INFORMATION BIPOLAR DC OR AC OPERATION FROM DUAL SUPPLIES The AD5263 can be operated from dual supplies, enabling control of ground referenced ac signals or bipolar operation. The ac signal, as high as VDD/VSS, can be applied directly across Terminal A to Terminal B, with the output taken from Terminal W. +5.0V VDD VDD µC SCLK SCL GND MCSI SDA A1 ±5V p-p ±2.5V p-p W1 B1 A2 GND D = 0x90 Depending on the op amp GBP, reducing the feedback resistor may extend the zero’s frequency far enough to overcome the problem. A better approach is to include a compensation capacitor C2 to cancel the effect caused by C1. Optimum compensation occurs when R1 × C1 = R2 × C2. This is not an option, because of the variation of R2. As a result, one may use the relationship described and scale C2 as if R2 is at its maximum value. Doing so may overcompensate and compromise the performance slightly when R2 is set at low values. However, it avoids the gain peaking, ringing, or oscillation in the worst case. For critical applications, C2 should be found empirically to suit the need. In general, C2 in the range of a few pF to no more than a few tenths of pF is usually adequate for the compensation. W2 B2 _ 5.0V 03142-056 VSS AD5263 Figure 57. Bipolar Operation from Dual Supplies GAIN CONTROL COMPENSATION A digital potentiometer is commonly used in gain control such as the noninverting gain amplifier shown in Figure 58. C2 4.7pF Similarly, there are W and A terminal capacitances connected to the output (not shown); fortunately, their effect at this node is less significant and the compensation can be disregarded in most cases. PROGRAMMABLE VOLTAGE REFERENCE For voltage divider mode operation (Figure 59), it is common to buffer the output of the digital potentiometer unless the load is much larger than RWB. Not only does the buffer serve the purpose of impedance conversion, but it also allows a heavier load to be driven. 5V R2 200kΩ B A W AD5263 1 U1 VIN VOUT R1 47kΩ AD1582 5V 3 A W GND VO VI B AD8601 A1 Figure 58. Typical Noninverting Gain Amplifier VO 03142-058 U1 03142-057 C1 25pF Figure 59. Programmable Voltage Reference Notice the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node. It introduces a zero for the 1/βo term with +20 dB/dec, whereas a typical op amp GBP has −20 dB/dec characteristics. A large R2 and finite C1 can cause this zero’s frequency to fall well below the crossover frequency. Thus, the rate of closure becomes 40 dB/dec and the system has 0° phase margin at the crossover frequency. The output may ring or oscillate if the input is a rectangular pulse or step function. Similarly, it is also likely to ring when switching between two gain values, because this is equivalent to a step change at the input. Rev. F | Page 23 of 28 AD5263 Data Sheet 8-BIT BIPOLAR DAC Figure 60 shows a low cost, 8-bit, bipolar DAC. It offers the same number of adjustable steps, but not the precision as compared to conventional DACs. The linearity and temperature coefficient, especially at low values codes, are skewed by the effects of the digital potentiometer wiper resistance. The output of this circuit is (4) +15V VI OP2177 VO A2 B 1 U1 –15V –5VREF VOUT +5VREF ADR425 TRIM 0 64 128 192 255 +15V GND V+ OP2177 V– Figure 60. 8-Bit Bipolar DAC BIPOLAR PROGRAMMABLE GAIN AMPLIFIER For applications requiring bipolar gain, Figure 61 shows one implementation similar to the previous circuit. The digital potentiometer U1 sets the adjustment range. The wiper voltage at W2 can therefore be programmed between VI and –KVI at a given U2 setting. Configuring A2 in the noninverting mode allows linear gain and attenuation. The transfer function is VI R2   D2 = 1 + × (1 + K ) − K  ×  R1   256  A2 B2 A1 B1 OP2177 V– C1 VO R2 A2 U1 AD5263 –KVI VSS VDD W1 VOUT U1 AD5263 A B +V W U2 AD8601 CC RBIAS IL SIGNAL LD –V R1 V+ OP2177 V– A1 VSS 03142-060 VI U3 2N7002 VIN In this circuit, the inverting input of the op amp forces the VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-channel FET, N1. N1 power handling must be adequate to dissipate power equal to (VIN − VOUT) × IL. This circuit can source a maximum of 100 mA with a 5 V supply. For precision applications, a voltage reference such as ADR421 or ADR03 can be applied at the A terminal of the digital potentiometer. V+ W2 –10 –5 0 5 9.680 Figure 62. Programmable Booster Voltage Source VDD U2 R2 = 9 × R1 –2 –1 0 1 1.937 For applications that require high current adjustment, such as a laser diode driver or tunable laser, a boosted voltage source can be considered. See Figure 62. (5) where K is the ratio of RWB1/RWA1 set by U1. AD5263 R1 = R2 PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT 03142-059 A1 VO R1 = ∞, R2 = 0 –1 –0.5 0 0.5 0.968 D A VIN If R2 is large, a compensation capacitor of a few pF may be needed to avoid any gain peaking. Table 10. Result of Bipolar Gain Amplifier V– W (6) Table 10 shows the result of adjusting D, with A2 configured with unity gain, gain of 2, and gain of 10. The result is a bipolar amplifier with linearly programmable gain and 256-step resolution. V+ AD5263 R2   2 × D2  VO = 1 + − 1 × V I ×  R1   256  03142-061 2D VO =  − 1 ×V REF 256   Similar to the previous example, in the simpler (and much more usual) case where K = 1, a single channel is used and U1 is replaced by a matched pair of resistors to apply VI and –VI at the ends of the digital potentiometer. The relationship becomes Figure 61. Bipolar Programmable Gain Amplifier Rev. F | Page 24 of 28 Data Sheet AD5263 PROGRAMMABLE 4 TO 20 MA CURRENT SOURCE A programmable 4–20 mA current source can be implemented with the circuit shown in Figure 63. The REF191 is a unique low supply headroom and high current handling precision reference that can deliver 20 mA at +2.048 V. The load current is simply the voltage across Terminal B to Terminal W of the digital potentiometer divided by RS: IL = V REF × D PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution (see Figure 64). If the resistors are matched, the load current is (7) RS × 2N (R2A + R2B ) R1 IL = R2B ×VW R1 150kΩ (8) R2 15kΩ +5V 3 VOUT 6 SLEEP REF191 GND 4 +15V 0 TO (2.048V + VL) B C1 1µF AD5263 +5V V+ W A OP2177 +5V RS 102Ω C2 10pF AD5263 W V+ OP8510 –5V VL –5V IL RL 100Ω V+ OP2177 V– A1 R1 150kΩ A2 R2B 50Ω –15V R2A 14.95kΩ RL 500Ω –15V 03142-062 V– V– +15V A U2 –2.048V TO VL C1 10pF VL |L 03142-063 2 U1 VIN Figure 64. Programmable Bidirectional Current Source Figure 63. Programmable 4–20 mA Current Source The circuit is simple, but beware of two things. First, dual-supply op amps are ideal because the ground potential of the REF191 can swing from −2.048 V at zero scale to VL at full scale of the potentiometer setting. Although the circuit works with a single supply, the programmable resolution of the system is reduced. For applications that demand higher current capabilities, a few changes to the circuit in Figure 63 produce an adjustable current in the range of hundreds of mA. First, the voltage reference needs to be replaced with a high current, low dropout regulator, such as the ADP3333, and the op amp needs to be swapped with a high current, dual-supply model, such as the AD5263. Depending on the desired range of current, an appropriate value for RS must be calculated. Because of the high current flowing to the load, the user must pay attention to the load impedance so as not to drive the op amp past the positive rail. R2B, in theory, can be made as small as needed to achieve the current needed within the A2 output current driving capability. In this circuit, OP2177 can deliver ±5 mA in either direction, and the voltage compliance approaches +15 V. It can be shown that the output impedance is Zo = R1′ × R 2B (R1 + R2A ) R1 × R2 ′ − R1′(R2A + R2B ) (9) This output impedance can be infinite if resistors R1′ and R2′ match precisely with R1 and R2A + R2B, respectively. On the other hand, it can be negative if the resistors are not matched. As a result, C1 in the range of 1 pF to 10 pF is needed to prevent oscillation. Rev. F | Page 25 of 28 AD5263 Data Sheet PROGRAMMABLE LOW-PASS FILTER At resonance, setting In analog-to-digital conversion applications, it is common to include an antialiasing filter to band-limit the sampling signal. Dual-channel digital potentiometers can be used to construct a second-order Sallen-Key low-pass filter (see Figure 65). The design equations are VI = ωO = Q= ωO 2 ωO S2 + (10) S + ωO 2 Q 1 R1 × R2 × C1 × C2 (11) 1 1 + R1 × C1 R2 × C2 balances the bridge. In practice, R2/R1 should be set slightly greater than 2 to ensure that the oscillation can start. On the other hand, the alternating turn-on of the diodes D1 and D2 ensures that R2/R1 is momentarily less than 2, thereby stabilizing the oscillation. Once the frequency is set, the oscillation amplitude can be tuned by R2B because 2 VO = I D × R2B + V D 3 (12) Users can first select some convenient values for the capacitors. To achieve maximally flat bandwidth where Q = 0.707, let C1 be twice the size of C2, and let R1 = R2. As a result, the user can adjust R1 and R2 to the same settings to achieve the desired bandwidth. FREQUENCY ADJUSTMENT C R2 B A W R B AD8601 R C2 C 2.2nF VO R 10kΩ A W OP1177 R1 = R1’ = R2B = AD5263 D1 = D2 = 1N4148 With R = R′, C = C′, and R2 = R2A||(R2B + RDIODE), the oscillation frequency is (13) where R is equal to RWA, such that 256 − D R AB 256 VO V– R2A R2B 2.1kΩ 10kΩ In a classic Wien bridge oscillator (Figure 66), the Wien network (R, R′, C, C′) provides positive feedback, while R1 and R2 provide negative feedback. At the resonant frequency, fO, the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. R= U1 –2.5V PROGRAMMABLE OSCILLATOR 1 1 , or f O = RC 2πRC B VN Figure 65. Sallen-Key Low-Pass Filter ωO = A W +2.5V V+ V– U1 –2.5V ADJUSTED TO SAME SETTING R’ 10kΩ B V+ W C VP 2.2nF +2.5V 03142-064 R1 A (16) VO, ID, and VD are interdependent variables. With proper selection of R2B, an equilibrium is reached such that VO converges. R2B can be in series with a discrete resistor to increase the amplitude, but the total resistance should not be so large that it saturates the output. C1 VI (15) (14) Rev. F | Page 26 of 28 R1 1kΩ B A D1 D2 W AMPLITUDE ADJUSTMENT 03142-065 VO R2 =2 R1 Figure 66. Programmable Oscillator with Amplitude Control Data Sheet AD5263 The AD5263 offers 20 kΩ, 50 kΩ, and 200 kΩ nominal resistances. Users who need a lower resistance and the same number of step adjustments can place multiple devices in parallel. For example, Figure 67 shows a simple scheme of using two channels in parallel. To adjust half of the resistance linearly per step, users need to program both channels to the same settings. VDD A1 A2 W1 B2 W2 03142-066 B1 LED Figure 67. Reduce Resistance by Half with Linear Adjustment Characteristics RESISTANCE TOLERANCE, DRIFT, AND TEMPERATURE COEFFICIENT MISMATCH CONSIDERATIONS In rheostat mode operation, such as the gain control circuit of Figure 70, the tolerance mismatch between the digital potentiometer and the discrete resistor can cause repeatability issues among various systems. Because of the inherent matching of the silicon process, it is practical to apply the multichannel device in this type of application. As such, R1 should be replaced by one of the channels of the digital potentiometer. R1 should be programmed to a specific value while R2 can be used for the adjustable gain. Although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between R1 and R2. In addition, this approach also tracks the resistance drift over time. As a result, these nonideal parameters become less sensitive to system variations. B Applicable only to the voltage divider mode, by connecting a discrete resistor in parallel as shown in Figure 68, a proportionately lower voltage appears at Terminal A. This translates into a finer degree of precision because the step size at Terminal W is smaller. The voltage can be found as  D  VDD  × (R AB || R1) VW (D ) = × 256  R2 + (R AB || R1)  R2 A W R11 C1 – AD8601 + VI (17) 1REPLACED VO U1 03142-070 RESISTANCE SCALING WITH ANOTHER CHANNEL OF RDAC Figure 70. Linear Gain Control with Tracking Resistance Tolerance and Drift VDD Notice that the circuit in Figure 71 can also be used to track the tolerance, temperature coefficient, and drift in this particular application. However, the characteristics of the transfer function change from a linear to a pseudologarithmic gain function. R2 A W R1 R R1