AD526SD/883B

a Software Programmable Gain Amplifier AD526 FEATURES Digitally Programmable Binary Gains from 1 to 16 Two-Chip Cascade Mode Achieves Binary Gain from 1 to 256 Gain Error: 0.01% Max, Gain = 1, 2, 4 (C Grade) 0.02% Max, Gain = 8, 16 (C Grade) 0.5 ppm/ⴗC Drift Over Temperature Fast Settling Time 10 V Signal Change: 0.01% in 4.5 ␮s (Gain = 16) Gain Change: 0.01% in 5.6 ␮s (Gain = 16) Low Nonlinearity: ⴞ0.005% FSR Max (J Grade) Excellent DC Accuracy: Offset Voltage: 0.5 mV Max (C Grade) Offset Voltage Drift: 3 ␮V/ⴗC (C Grade) TTL-Compatible Digital Inputs PIN CONFIGURATION DIG GND 1 16 A1 NULL 2 15 A0 14 CS VIN 3 CLK TOP VIEW ANALOG GND 2 5 (Not to Scale) 12 A2 NULL 4 AD526 13 ANALOG GND 1 6 11 B –VS 7 10 +VS VOUT SENSE 8 9 VOUT FORCE PRODUCT DESCRIPTION The AD526 is a single-ended, monolithic software programmable gain amplifier (SPGA) that provides gains of 1, 2, 4, 8 and 16. It is complete, including amplifier, resistor network and TTL-compatible latched inputs, and requires no external components. Low gain error and low nonlinearity make the AD526 ideal for precision instrumentation applications requiring programmable gain. The small signal bandwidth is 350 kHz at a gain of 16. In addition, the AD526 provides excellent dc precision. The FETinput stage results in a low bias current of 50 pA. A guaranteed maximum input offset voltage of 0.5 mV max (C grade) and low gain error (0.01%, G = 1, 2, 4, C grade) are accomplished using Analog Devices’ laser trimming technology. To provide flexibility to the system designer, the AD526 can be operated in either latched or transparent mode. The force/sense configuration preserves accuracy when the output is connected to remote or low impedance loads. The AD526 is offered in one commercial (0°C to +70°C) grade, J, and three industrial grades, A, B and C, which are specified from –40°C to +85°C. The S grade is specified from –55°C to +125°C. The military version is available processed to MILSTD 883B, Rev C. The J grade is supplied in a 16-lead plastic DIP, and the other grades are offered in a 16-lead hermetic side-brazed ceramic DIP. APPLICATION HIGHLIGHTS 1. Dynamic Range Extension for ADC Systems: A single AD526 in conjunction with a 12-bit ADC can provide 96 dB of dynamic range for ADC systems. 2. Gain Ranging Preamps: The AD526 offers complete digital gain control with precise gains in binary steps from 1 to 16. Additional gains of 32, 64, 128 and 256 are possible by cascading two AD526s. ORDERING GUIDE Model Temperature Range Package Descriptions Package Options AD526JN AD526AD AD526BD AD526CD AD526SD AD526SD/883B 5962-9089401MEA* Commercial Industrial Industrial Industrial Military Military Military 16-Lead Plastic DIP 16-Lead Cerdip 16-Lead Cerdip 16-Lead Cerdip 16-Lead Cerdip 16-Lead Cerdip 16-Lead Cerdip N-16 D-16 D-16 D-16 D-16 D-16 D-16 *Refer to official DESC drawing for tested specifications. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD526* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS View a parametric search of comparable parts. Technical Articles • Auto-Zero Amplifiers DOCUMENTATION • High-performance Adder Uses Instrumentation Amplifiers Application Notes • AN-244: A User's Guide to I.C. Instrumentation Amplifiers • Input Filter Prevents Instrumentation-amp RFRectification Errors • AN-245: Instrumentation Amplifiers Solve Unusual Design Problems • The AD8221 - Setting a New Industry Standard for Instrumentation Amplifiers • AN-282: Fundamentals of Sampled Data Systems • AN-589: Ways to Optimize the Performance of a Difference Amplifier DESIGN RESOURCES • AD526 Material Declaration • AN-671: Reducing RFI Rectification Errors in In-Amp Circuits • PCN-PDN Information Data Sheet • Symbols and Footprints • Quality And Reliability • AD526 Military Data Sheet • AD526: Software Programmable Gain Amplifier Data Sheet DISCUSSIONS View all AD526 EngineerZone Discussions. Technical Books • A Designer's Guide to Instrumentation Amplifiers, 3rd Edition, 2006 SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. 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This dynamic page may be frequently modified. AD526–SPECIFICATIONS (@ V = ⴞ15 V, R = 2 k⍀ and T = +25ⴗC unless otherwise noted) S Model Min GAIN Gain Range (Digitally Programmable) Gain Error Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain Error Drift Over Temperature G=1 G=2 G=4 G=8 G = 16 Gain Error (TMIN to TMAX) Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Nonlinearity Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Nonlinearity (TMIN to TMAX) Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 VOLTAGE OFFSET, ALL GAINS Input Offset Voltage Input Offset Voltage Drift Over Temperature Input Offset Voltage TMIN to TMAX Input Offset Voltage vs. Supply (VS ± 10%) RATED OUTPUT Voltage Current (VOUT = ± 10 V) Short-Circuit Current DC Output Resistance Load Capacitance (For Stable Operation) Max Min 1, 2, 4, 8, 16 0.5 0.5 0.5 0.5 1.0 A AD526A Typ Max Min 1, 2, 4, 8, 16 0.05 0.05 0.10 0.15 0.15 AD526B/S Typ Max 2.0 2.0 3.0 5.0 5.0 0.5 0.5 0.5 0.5 1.0 Min 1, 2, 4, 8, 16 0.02 0.03 0.03 0.07 0.07 AD526C Typ 0.5 0.5 0.5 0.5 1.0 Units 1, 2, 4, 8, 16 0.01 0.02 0.02 0.04 0.04 2.0 2.0 3.0 5.0 5.0 Max 2.0 2.0 3.0 5.0 5.0 0.5 0.5 0.5 0.5 1.0 0.01 0.01 0.01 0.02 0.02 % % % % % 2.0 2.0 3.0 5.0 5.0 ppm/°C ppm/°C ppm/°C ppm/°C ppm/°C 0.06 0.06 0.12 0.17 0.17 0.03 0.04 0.04 0.08 0.08 0.02 0.03 0.03 0.05 0.05 0.015 0.015 0.015 0.03 0.03 % % % % % 0.005 0.001 0.001 0.001 0.001 0.005 0.001 0.001 0.001 0.001 0.005 0.001 0.001 0.001 0.001 0.0035 0.001 0.001 0.001 0.001 % FSR % FSR % FSR % FSR % FSR 0.01 0.001 0.001 0.001 0.001 0.01 0.001 0.001 0.001 0.001 0.01 0.001 0.001 0.001 0.001 0.007 0.001 0.001 0.001 0.001 % FSR % FSR % FSR % FSR % FSR 0.4 1.5 0.25 0.7 0.25 0.5 0.25 0.5 mV 5 20 3 10 3 10 3 10 µV/°C 0.8 mV 2.0 80 INPUT BIAS CURRENT Over Input Voltage Range ± 10 V ANALOG INPUT CHARACTERISTICS Voltage Range (Linear Operation) Capacitance AD526J Typ L 1.0 80 50 150 0.8 84 50 150 90 50 150 dB 50 150 pA ⴞ10 ± 12 5 ⴞ10 ± 12 5 ⴞ10 ± 12 5 ⴞ10 ± 12 5 V pF ⴞ10 ± 12 ± 10 30 0.002 ⴞ10 ⴞ5 15 ± 12 ± 10 30 0.002 ⴞ10 ⴞ5 15 ± 12 ± 10 30 0.002 ⴞ10 ⴞ5 15 ± 12 ± 10 30 0.002 V mA mA Ω 700 pF 15 700 700 –2– 700 REV. D AD526 Model Min NOISE, ALL GAINS Voltage Noise, RTI 0.1 Hz to 10 Hz Voltage Noise Density, RTI f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz AD526J Typ AD526B/S Typ Max Min AD526C Typ Max Units 3 µV p-p 70 60 30 25 70 60 30 25 70 60 30 25 70 60 30 35 nV√Hz nV√Hz nV√Hz nV√Hz 4.0 2.0 1.5 0.65 0.35 4.0 2.0 1.5 0.65 0.35 4.0 2.0 1.5 0.65 0.35 4.0 2.0 1.5 0.65 0.35 MHz MHz MHz MHz MHz DIGITAL INPUTS (TMIN to TMAX) Input Current (VH = 5 V) Logic “1” Logic “0” 60 2 0 100 PACKAGE OPTIONS Plastic (N-16) Ceramic DIP (D-16) Min 3 6 24 POWER SUPPLY Operating Range Positive Supply Current Negative Supply Current AD526A Typ Max 3 4 18 TEMPERATURE RANGE Specified Performance Storage Min 3 DYNAMIC RESPONSE –3 dB Bandwidth (Small Signal) G=1 G=2 G=4 G=8 G = 16 Signal Settling Time to 0.01% (∆VOUT = ± 10 V) G=1 G=2 G=4 G=8 G = 16 Full Power Bandwidth G = 1, 2, 4 G = 8, 16 Slew Rate G = 1, 2, 4 G = 8, 16 TIMING1 (VL = 0.2 V, VH = 3.7 V) A0, A1, A2 TC TS TH B TC TS TH Max 2.1 2.5 2.7 3.6 4.1 4 5 5 7 7 2.1 2.5 2.7 3.6 4.1 0.10 0.35 4 5 5 7 7 2.1 2.5 2.7 3.6 4.1 0.10 0.35 140 6 0.8 4 18 6 24 60 2 0 100 4 5 5 7 7 2.1 2.5 2.7 3.6 4.1 0.10 0.35 140 6 0.8 4 18 6 24 60 2 0 100 140 6 0.8 4 5 5 7 7 µs µs µs µs µs 0.10 0.35 MHz MHz 4 18 6 24 V/µs V/µs 60 2 0 100 140 6 0.8 µA V V 50 30 30 50 30 30 50 30 30 50 30 30 ns ns ns 50 40 10 50 40 10 50 40 10 50 40 30 ns ns ns 0 –65 ⴞ4.5 10 10 +70 +125 –40 –65 ⴞ16.5 14 13 ⴞ4.5 +85 +150 10 10 –40/–55 –65 ⴞ16.5 ⴞ4.5 14 13 +85/+125 –40 +150 –65 10 10 ⴞ16.5 14 13 ⴞ4.5 10 10 +85 +150 °C °C ⴞ16.5 14 13 V mA mA AD526JN AD526AD AD526BD AD526SD AD526SD/883B AD526CD NOTES 1 Refer to Figure 25 for definitions. FSR = Full Scale Range = 20 V. RTI = Referred to Input. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. REV. D –3– AD526–Typical Performance Characteristics +258C RL = 2kV 10 5 0 5 10 15 SUPPLY VOLTAGE – 6V Figure 1. Output Voltage Swing vs. Supply Voltage, G = 16 20 @ VS = 615V 10 0 100 20 INPUT BIAS CURRENT – pA 15 0 20 30 OUTPUT VOLTAGE SWING – 6V OUTPUT VOLTAGE SWING – 6V 20 VIN = 0 10 5 0 1k LOAD RESISTANCE – V 10k 0 5 10 15 SUPPLY VOLTAGE – 6V 20 Figure 3. Input Bias Current vs. Supply Voltage Figure 2. Output Voltage Swing vs. Load Resistance 20 75 100nA 15 16 1nA 100pA 10pA 1pA –60 –20 Figure 4. Input Bias Current vs. Temperature GAIN = 1, 2, 4 10 5 POWER SUPPLY REJECTION – dB FULL POWER RESPONSE – V p-p GAIN = 8, 16 1 –5 0 5 INPUT VOLTAGE – V 10 100k 1M FREQUENCY – Hz 10M Figure 7. Large Signal Frequency Response 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 6. Gain vs. Frequency 1.0002 615V WITH 1V p-p SINE WAVE 80 +SUPPLY 60 40 –SUPPLY 1.0001 1.0000 0.9999 20 10 10k 2 1 25 100 20 0 1k 4 Figure 5. Input Bias Current vs. Input Voltage 25 15 50 0 –10 140 20 60 100 TEMPERATURE – 8C 8 VS = 615V NORMALIZED GAIN INPUT BIAS CURRENT 10nA GAIN INPUT BIAS CURRENT – pA 10 1 10 100 1k 10k FREQUENCY – Hz 100k Figure 8. PSRR vs. Frequency –4– 1M 0.9998 –60 –20 20 60 100 TEMPERATURE – 8C 140 Figure 9. Normalized Gain vs. Temperature, Gain = 1 REV. D AD526 0.006 0.004 NONLINEARITY – %FSR INPUT NOISE VOLTAGE – nV/ Hz 1000 100 0.002 0.000 –0.002 10 10 1k 100 10k FREQUENCY – Hz 100k Figure 10. Noise Spectral Density Figure 13. Large Signal Pulse Response and Settling Time,* G=1 Figure 16. Small Signal Pulse Response, G = 2 –0.004 –60 –20 20 60 100 TEMPERATURE – 8C Figure 11. Nonlinearity vs. Temperature, Gain = 1 Figure 14. Small Signal Pulse Response, G = 1 Figure 17. Large Signal Pulse Response and Settling Time,* G=4 *For Settling Time Traces, 0.01% = 1/2 Vertical Division REV. D –5– 140 Figure 12. Wideband Output Noise, G = 16 (Amplified by 10) Figure 15. Large Signal Pulse Response and Settling Time,* G=2 Figure 18. Small Signal Pulse Response, G = 4 AD526 Figure 19. Large Signal Pulse Response and Settling Time,* G = 8 Figure 20. Small Signal Pulse Response, G = 8 Figure 21. Large Signal Pulse Response and Settling Time,* G = 16 –70 –80 –90 –100 10 Figure 22. Small Signal Pulse Response, Gain = 16 10 PHASE DISTORTION – Dedrees TOTAL HARMONIC DISTORTION – dB –60 100 1k 10k FREQUENCY – Hz 100k Figure 23. Total Harmonic Distortion vs. Frequency Gain = 16 5 0 –5 –10 10 100 1k 10k FREQUENCY – Hz 100k Figure 24. Phase Distortion vs. Frequency, Gain = 16 OUTPUT IMPEDANCE – V 100 G = 2, 8 G = 4, 16 10 1 10k G=1 100k 1M FREQUENCY – Hz 10M Figure 25. Output Impedance vs. Frequency Figure 26. Gain Change Settling Time,** Gain Change: 1 to 2 Figure 27. Gain Change Settling Time,** Gain Change 1 to 4 *For Settling Time Traces, 0.01% = 1/2 Vertical Division **Scope Traces are: Top: Output Transition; Middle: Output Settling; Bottom: Digital Input. –6– REV. D AD526 Figure 28. Gain Change Settling Time,* Gain Change 1 to 8 +15V –15V 10mF 10mF + + Figure 29. Gain Change Settling Time,* Gain Change 1 to 16 +15V –15V 10mF + 10mF + TEKTRONIX 7000 SERIES SCOPE 7A13 PREAMP 5MHz BW AD526 G = 16 OP37 900V G = 10 100V + 10mF Vo = 160 3 e p-p +5V SHIELD NOTE: COAX CABLE 1 FT. OR LESS Figure 30. Wideband Noise Test Circuit +15V –15V 10mF 10mF + + DATA DYNAMICS 5109 (OR EQUIVALENT FLAT-TOP PULSE GENERATOR) +15V –15V 1 2 4 8 16 5.6kV 2.8kV 1.4kV 715V 348V VERROR 1pF + AD711 – 1pF RIN 10mF + AD526 2kV POT. G 10mF + 5kV + 5kV 5.6kV IN6263 RIN 50V 5pF – AD3554 5kV IN6263 10mF + 10mF + –15V +15V + 10mF + 10mF + –15V +15V Figure 31. Settling Time Test Circuit *Scope Traces are: Top: Output Transition Middle: Output Settling Bottom: Digital Input REV. D VERROR 3 5 5kV – AD3554 TEKTRONIX 7000 SERIES SCOPE 7A13 PREAMP 5MHz BW –7– TSET = TMEAS2 – TX2 1.25kV G TX 1 2 4 8 16 1.2ms 1.2ms 1.2ms 1.4ms 1.8ms AD526 THEORY OF OPERATION TRANSPARENT MODE OF OPERATION The AD526 is a complete software programmable gain amplifier (SPGA) implemented monolithically with a drift-trimmed BiFET amplifier, a laser wafer trimmed resistor network, JFET analog switches and TTL compatible gain code latches. In the transparent mode of operation, the AD526 will respond directly to level changes at the gain code inputs (A0, A1, A2) if B is tied high and both CS and CLK are allowed to float low. A particular gain is selected by applying the appropriate gain code (see Table I) to the control logic. The control logic turns on the JFET switch that connects the correct tap on the gain network to the inverting input of the amplifier; all unselected JFET gain switches are off (open). The “on” resistance of the gain switches causes negligible gain error since only the amplifier’s input bias current, which is less than 150 pA, actually flows through these switches. After the gain codes are changed, the AD526’s output voltage typically requires 5.5 µs to settle to within 0.01% of the final value. Figures 26 to 29 show the performance of the AD526 for positive gain code changes. A2 A1 A0 +VS 0.1mF +5V The AD526 is capable of storing the gain code, (latched mode), B, A0, A1, A2, under the direction of control inputs CLK and CS. Alternatively, the AD526 can respond directly to gain code changes if the control inputs are tied low (transparent mode). 16 A1 For gains of 8 and 16, a fraction of the frequency compensation capacitance (C1 in Figure 32) is automatically switched out of the circuit. This increases the amplifier’s bandwidth and improves its signal settling time and slew rate. 15 14 13 12 11 A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 OUT 9 FORCE 10 B 1 VOUT GAIN NETWORK – AD526 1 AMPLIFIER 2 + 3 4 5 6 7 8 OUT SENSE +VS –VS C2 VIN OUT FORCE N1 A1 A2 B CLK L A T C H E S C O N T R O L OUT SENSE 14kV G=8 3.4kV G=2 L O G I C Figure 33. Transparent Mode LATCHED MODE OF OPERATION N2 –VS A0 0.1mF VIN C1 The latched mode of operation is shown in Figure 34. When either CS or CLK go to a Logic “1,” the gain code (A0, A1, A2, B) signals are latched into the registers and held until both CS and CLK return to “0.” Unused CS or CLK inputs should be tied to ground . The CS and CLK inputs are functionally and electrically equivalent. RESISTOR NETWORK TIMING SIGNAL A2 A1 1kV A0 G = 16 +VS 1.7kV CS 0.1mF +5V G=4 DIGITAL GND 1kV ANALOG GND2 1.7kV 16 ANALOG GND1 A1 Figure 32. Simplified Schematic of the AD526 15 14 13 12 A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 11 10 OUT 9 FORCE B 1 VOUT GAIN NETWORK – AD526 1 2 + 3 4 5 6 7 8 OUT SENSE 0.1mF VIN –VS Figure 34. Latched Mode –8– REV. D AD526 TIMING AND CONTROL DIGITAL FEEDTHROUGH With either CS or CLK or both held high, the AD526 gain state will remain constant regardless of the transitions at the A0, A1, A2 or B inputs. However, high speed logic transitions will unavoidably feed through to the analog circuitry within the AD526 causing spikes to occur at the signal output. Table I. Logic Input Truth Table Gain Code A2 A1 A0 B X 0 0 0 0 1 X X 0 0 0 0 1 X 0 0 1 1 X X X 0 0 1 1 X X 0 1 0 1 X X X 0 1 0 1 X Control CLK (CS = 0) X 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 Condition Gain Condition Previous State 1 2 4 8 16 1 1 1 2 4 8 16 Latched Transparent Transparent Transparent Transparent Transparent Transparent Latched Latched Latched Latched Latched Latched This feedthrough effect can be completely eliminated by operating the AD526 in the transparent mode and latching the gain code in an external bank of latches (Figure 36). To operate the AD526 using serial inputs, the configuration shown in Figure 36 can be used with the 74LS174 replaced by a serial-in/parallel-out latch, such as the 54LS594. A1 A0 A2 B +5V 1mF TIMING SIGNAL 74LS174 +VS NOTE: X = Don’t Care. 0.1mF The specifications on page 3, in combination with Figure 35, give the timing requirements for loading new gain codes. 16 A1 GAIN CODE INPUTS VALID DATA 15 14 13 12 A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 11 10 OUT 9 FORCE B 1 TC VOUT GAIN NETWORK CLK OR CS – TS TC = MINIMUM CLOCK CYCLE TS = DATA SETUP TIME TH = DATA HOLD TIME TH AD526 NOTE: THRESHOLD LEVEL FOR GAIN CODE, CS, AND CLK IS 1.4V. 1 2 + 3 4 5 6 7 0.1mF VIN Figure 35. AD526 Timing 8 OUT SENSE –VS Figure 36. Using an External Latch to Minimize Digital Feedthrough REV. D –9– AD526 GROUNDING AND BYPASSING Proper signal and grounding techniques must be applied in board layout so that specified performance levels of precision data acquisition components, such as the AD526, are not degraded. Utilizing the force and sense outputs of the AD526, as shown in Figure 38, avoids signal drops along etch runs to low impedance loads. Table II. Logic Table for Figure 38 As is shown in Figure 37, logic and signal grounds should be separate. By connecting the signal source ground locally to the AD526 analog ground Pins 5 and 6, gain accuracy of the AD526 is maintained. This ground connection should not be corrupted by currents associated with other elements within the system. +15V –15V 0.1mF VOUT/VIN A2 A1 A0 1 2 4 8 16 32 64 128 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0.1mF AD574 12-BIT A/D CONVERTER VIN 0.1mF 0.1mF ANALOG ANALOG +VS GROUND 1 GROUND 2 –VS VOUT FORCE AMP AD526 VOUT SENSE GAIN NETWORK DIGITAL GROUND LATCHES AND LOGIC 1mF +5V Figure 37. Grounding and Bypassing CLK A2 A1 A0 +VS 0.1mF +5V 16 A1 15 14 13 12 A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 +VS 11 10 0.1mF +5V OUT 9 FORCE 16 B A1 1 15 14 13 12 A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 11 10 OUT 9 FORCE B 1 VOUT GAIN NETWORK GAIN NETWORK – AD526 1 2 – AD526 + 3 4 5 6 7 8 OUT SENSE 1 2 + 3 4 5 6 7 8 OUT SENSE 0.1mF VIN 0.1mF –VS –VS Figure 38. Cascaded Operation –10– REV. D AD526 OFFSET NULLING CASCADED OPERATION Input voltage offset nulling of the AD526 is best accomplished at a gain of 16, since the referred-to-input (RTI) offset is amplified the most at this gain and therefore is most easily trimmed. The resulting trimmed value of RTI voltage offset typically varies less than 3 µV across all gain ranges. A cascade of two AD526s can be used to achieve binarily weighted gains from 1 to 256. If gains from 1 to 128 are needed, no additional components are required. This is accomplished by using the B pin as shown in Figure 38. When the B pin is low, the AD526 is held in a unity gain stage independent of the other gain code values. Note that the low input current of the AD526 minimizes RTI voltage offsets due to source resistance. Figure 41 shows the AD526 with offset nulling accomplished with an 8-bit D/A converter (AD7524) circuit instead of the potentiometer shown in Figure 39. The calibration procedure is the same as before except that instead of adjusting the potentiometer, the D/A converter corrects for the offset error. This calibration circuit has a number of benefits in addition to eliminating the trimpot. The most significant benefit is that calibration can be under the control of a microprocessor and therefore can be implemented as part of an autocalibration scheme. Secondly, dip switches or RAM can be used to hold the 8-bit word after its value has been determined. In Figure 42 the offset null sensitivity, at a gain of 16, is 80 µV per LSB of adjustment, which guarantees dc accuracy to the 16-bit performance level. +VS 0.1mF 16 15 14 13 12 11 A0 CS CLK A2 LOGIC AND LATCHES A1 16 8 4 2 10 OUT 9 FORCE B 1 VOUT GAIN NETWORK – AD526 1 2 + 3 4 5 6 7 VIN OFFSET NULLING WITH A D/A CONVERTER 8 OUT SENSE +VS 0.1mF 20kV 0.1mF –VS Figure 39. Offset Voltage Null Circuit 16 15 The AD526 is rated for a full ± 10 V output voltage swing into 2 kΩ. In some applications, the need exists to drive more current into heavier loads. As shown in Figure 40, a high current booster may be connected “inside the loop” of the SPGA to provide the required current boost without significantly degrading overall performance. Nonlinearities, offset and gain inaccuracies of the buffer are minimized by the loop gain of the AD526 output amplifier. 13 12 A0 CS CLK A2 LOGIC AND LATCHES A1 OUTPUT CURRENT BOOSTER 14 16 8 4 2 11 10 OUT 9 FORCE B 1 VOUT GAIN NETWORK – AD526 1 +VS +VS 2 + 3 4 5 6 7 VIN 8 OUT SENSE 0.1mF AD581 OR AD587 +10V 3.3MV 7.5MV –VS VREF ALL BYPASS CAPACITORS ARE 0.1mF 0.1mF +VS 1kV MSB 16 A1 15 14 13 12 A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 11 10 LSB OUT 9 FORCE CS 0.01mF 1 HOS-100 GND VIN + 4 5 6 7 8 OUT SENSE 0.1mF RL –VS Figure 40. Current Output Boosting REV. D –VS Figure 41. Offset Nulling Using a DAC 0.01mF – 3 – AD548 + 0.01mF AD526 2 OUT 1 OUT 2 WR B GAIN NETWORK 1 AD7524 0.01mF 10mF –11– AD526 FLOATING-POINT CONVERSION High resolution converters are used in systems to obtain high accuracy, improve system resolution or increase dynamic range. There are a number of high resolution converters available with throughput rates of 66.6 kHz that can be purchased as a single component solution; however in order to achieve higher throughput rates, alternative conversion techniques must be employed. A floating point A/D converter can improve both throughput rate and dynamic range of a system. In a floating point A/D converter (Figure 42), the output data is presented as a 16-bit word, the lower 12 bits from the A/D converter form the mantissa and the upper 4 bits from the digital signal used to set the gain form the exponent. The AD526 programmable gain amplifier in conjunction with the comparator circuit scales the input signal to a range between half scale and full scale for the maximum usable resolution. The A/D converter diagrammed in Figure 42 consists of a pair of AD585 sample/hold amplifiers, a flash converter, a five-range programmable gain amplifier (the AD526) and a fast 12-bit A/D converter (the AD7572). The floating-point A/D converter achieves its high throughput rate of 125 kHz by overlapping the acquisition time of the first sample/hold amplifier and the settling time of the AD526 with the conversion time of the A/D converter. The first sample/hold amplifier holds the signal for the flash autoranger, which determines which binary quantum the input falls within, relative to full scale. Once the AD526 has settled to the appropriate level, then the second sample/hold amplifier can be put into hold which holds the amplified signal while the AD7572 perform its conversion routine. The acquisition time for the AD585 is 3 µs, and the conversion time for the AD7572 is 5 µs for a total of 8 µs, or 125 kHz. This performance relies on the fast settling characteristics of the AD526 after the flash autoranging (comparator) circuit quantizes the input signal. A 16-bit register holds the 3-bit output from the flash autoranger and the 12-bit output of the AD7572. The A/D converter in Figure 42 has a dynamic range of 96 dB. The dynamic range of a converter is the ratio of the full-scale input range to the LSB value. With a floating-point A/D converter the smallest value LSB corresponds to the LSB of the monolithic converter divided by the maximum gain of the PGA. The floating point A/D converter has a full-scale range of 5 V, a maximum gain of 16 V/V from the AD526 and a 12-bit A/D converter; this produces: LSB = ([FSR/2N]/Gain) = ([5 V/4096]/16) = 76 µV. The dynamic range in dBs is based on the log of the ratio of the full-scale input range to the LSB; dynamic range = 20 log (5 V/76 µV) = 96 dB. –15V +15V +5V –15V +15V +5V 10mF 30pF CLOCK 125MHz 1 1/6 3 2 50kV 10mF +5V 1/6 6 BUSY D12 MSB D11 1ms –15V +15V 4 S/H AD585 + 10mF AD526 68pF 2.5MHz 10kV F 74– LS174 VIN AD7572 +5V VIN D9 D7 68pF S D6 47mF VIN D5 B S/H AD585 D10 D8 + 10mF 10mF + –15V +15V 10mF + 5 +5V 74123 1/2 1/6 + + + 10mF 10mF + LSB A0 A1 A2 74– LS174 D4 D3 D2 D1 10kV –15V +15V +5V + + 10mF A0 10mF 10kV +5VREF 12 13 10kV 2.5kV 4 5 1/4 A2 11 9 10 1/4 6 E2 E3 NOTE: ALL BYPASS CAPACITORS ARE 0.1mF 10kV 1 2 8 1/4 3 10kV 1.25kV 11 1.25kV 1/4 74– LS174 10kV 5kV AD588 1mF E1 A1 74ALS86 1 3 2 1/4 1/6 10 LM339A Figure 42. Floating-Point A/D Converter –12– REV. D AD526 HIGH ACCURACY A/D CONVERTERS Very high accuracy and high resolution floating-point A/D converters can be achieved by the incorporation of offset and gain calibration routines. There are two techniques commonly used for calibration, a hardware circuit as shown in Figure 43 and/or a software routine. In this application the microprocessor is functioning as the autoranging circuit, requiring software overhead; therefore, a hardware calibration technique was applied which reduces the software burden. The software is used to set the gain of the AD526. In operation the signal is converted, and if the MSB of the AD574 is not equal to a Logical 1, the gain is increased by binary steps, up to the maximum gain. This maximizes the full-scale range of the conversion process and insures a wide dynamic range. The calibration technique uses two point correction, offset and gain. The hardware is simplified by the use of programmable magnitude comparators, the 74ALS528s, which can be “burned” for a particular code. In order to prevent under or over range hunting during the calibration process, the reference offset and gain codes should be different from the endpoint codes. A calibration cycle consists of selecting whether gain or offset is to be calibrated then selecting the appropriate multiplexer channel to apply the reference voltage to the signal channel. Once the operation has been initiated, the counter, a 74ALS869, drives the D/A converter in a linear fashion providing a small correction voltage to either the gain or offset trim point of the AD574. The output of the A/D converter is then compared to the value preset in the 74ALS528 to determine a match. Once a match is detected, the 74ALS528 produces a low going pulse which stops the counter. The code at the D/A converter is latched until the next calibration cycle. Calibration cycles are under the control of the microprocessor in this application and should be implemented only during periods of converter inactivity. +5V 200pF 10mF +15V –15V 10mF + + –15V +15V MSB NOISE REDUCTION AD585 7404 2 1mF 1 +15V +5V A3 R8 AD588 R4 A1 R1 R2 VIN1 A4 R5 –5V +15V +VS R3 R6 A2 0.1mF SYS GND –15V –VS 0.1mF AD7501 10kV AD526 –15V +15V VREF OP27 1kV VIN2 WR VIN3 LSB 50kV VIN4 WR DATA BUS AD574 F S –15V DECODED WR ADDRESS DECODED ADDRESS DECODED ADD +5V ADDRESS BUS 12 12 +5V CALIBRATION PRESET +5V VALUE MSB 74ALS 528 PIN 28 AD574 P=Q 7475 1/2 GAIN 74ALS 869 7475 7475 1/2 R21 C12 INPUT BUFFER LATCH DAC A OUT A R5 20kV R62 20kV R72 10kV R11 5kV A1 A2 GAIN AD712 AGND AD712 RFB B R41 C22 4 6 5 7400 LSB CONTROL LOGIC WR +5V LATCH DAC B OUT B A/B R102 20kV PIN 15 AD588 +5V A3 AD712 R92 AGND 10kV VREF P=Q OFFSET RFB A AD7628 WR MSB 74ALS 528 PIN 15 AD588 VREF MSB 1 3 2 7400 ADG221 LSB +5V 5kV R12 5kV R8 20kV A2 OFFSET AD712 AGND NOTE: ALL BYPASS CAPACITORS ARE 0.1mF LSB +5V Figure 43. High Accuracy A/D Converter REV. D –13– AD526 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP Package (N-16) 16-Lead Sided-Brazed Ceramic Package (D-16) 0.87 (22.1) MAX 1 8 PIN 1 0.18 (4.57) 0.018 (0.46) 0.100 (2.54) 0.033 (0.84) 0.040R 16 0.310 ⴞ0.01 (7.874 ⴞ0.254) 0.3 (7.62) 0.035 (0.89) 0.125 (3.18) MIN 0.430 (10.922) 0.25 0.31 (6.25) (7.87) 9 0.265 0.290 ⴞ0.010 (6.73) (7.37 ⴞ0.254) 1 0.18 (4.57) MAX 8 PIN 1 0.800 ⴞ0.010 (20.32 ⴞ0.254) 0.011 (0.28) 0.035 ⴞ0.01 (0.889 ⴞ0.254) SEATING PLANE 0.095 (2.41) 0.300 (7.62) REF 0.085 (2.159) 0.125 (3.175) MIN 0.180 ⴞ0.03 (4.57 ⴞ0.762) 0.047 ⴞ0.007 (1.19 ⴞ0.18) C1103d–0–8/99 9 0.017 +0.003 –0.002 (0.43 +0.076 –0.05 ) 0.100 (2.54) SEATING BSC PLANE 0.010 ⴞ0.002 (0.254 ⴞ0.05) 0.700 (17.78) BSC PRINTED IN U.S.A. 16 –14– REV. D