Data Sheet
AD5270/AD5271
1024-/256-Position, 1% Resistor Tolerance Error, SPI Interface and 50-TP Memory
Digital Rheostat
FEATURES
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FUNCTIONAL BLOCK DIAGRAM
Single-channel, 1024-/256-position resolution
20 kΩ, 50 kΩ, 100 kΩ nominal resistance
Maximum ±1% nominal resistor tolerance error
50-times programmable (50-TP) wiper memory
Rheostat mode temperature coefficient: 5 ppm/°C
2.7 V to 5.5 V single-supply operation
±2.5 V to ±2.75 V dual-supply operation for ac or bipolar operations
SPI-compatible interface
Wiper setting readback
Power on refreshed from 50-TP memory
Thin LFCSP, 10-lead, 3 mm × 3 mm × 0.8 mm package
Compact MSOP, 10-lead, 3 mm × 4.9 mm × 1.1 mm package
Figure 1.
APPLICATIONS
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Mechanical rheostat replacements
Op-amp: variable gain control
Instrumentation: gain, offset adjustment
Programmable voltage to current conversions
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration
GENERAL DESCRIPTION
The AD5270/AD52711 are single-channel, 1024-/256-position digital rheostats that combine industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package.
The AD5270/AD5271 ensure less than 1% end-to-end resistor
tolerance error and offer 50-times programmable (50-TP) memory.
The guaranteed industry leading low resistor tolerance error feature
simplifies open-loop applications as well as precision calibration
and tolerance matching applications.
1
The AD5270/AD5271 device wiper settings are controllable through
the SPI digital interface. Unlimited adjustments are allowed before
programming the resistance value into the 50-TP memory. The
AD5270/AD5271 do not require any external voltage supply to
facilitate fuse blow and there are 50 opportunities for permanent
programming. During 50-TP activation, a permanent blow fuse
command freezes the resistance position (analogous to placing
epoxy on a mechanical trimmer).
The AD5270/AD5271 are available in a 3 mm × 3 mm, 10-lead
LFCSP package and in a 10-lead MSOP package. The parts are
guaranteed to operate over the extended industrial temperature
range of −40°C to +125°C.
Protected by U.S. Patent Number 7,688,240.
Rev. G
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
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registered trademarks are the property of their respective owners.
Data Sheet
AD5270/AD5271
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Specifications........................................................ 3
Electrical Characteristics—AD5270................... 3
Electrical Characteristics—AD5271................... 5
Interface Timing Specifications.......................... 6
Absolute Maximum Ratings...................................8
Thermal Resistance........................................... 8
ESD Caution.......................................................8
Pin Configuration and Function Descriptions........ 9
Typical Performance Characteristics................... 10
Test Circuits......................................................... 16
Theory of Operation.............................................17
Serial Data Interface.........................................17
Shift Register....................................................17
RDAC Register ................................................18
50-TP Memory Block........................................19
Write Protection................................................20
RDAC and 50-TP Read Operation................... 20
Shut-Down Mode..............................................21
Resistor Performance Mode.............................21
Reset................................................................ 21
SDO Pin and Daisy-Chain Operation............... 21
RDAC Architecture........................................... 21
Programming the Variable Resistor..................21
EXT_CAP Capacitor.........................................22
Terminal Voltage Operating Range.................. 22
Power-Up Sequence........................................ 22
Outline Dimensions............................................. 23
Ordering Guide.................................................23
RAW (kΩ) and Resolution Options.................... 24
Evaluation Boards............................................ 24
REVISION HISTORY
1/2022—Rev. F to Rev. G
Changes to Table 1.......................................................................................................................................... 3
Changes to Table 4 and Table 6...................................................................................................................... 5
Changes to Figure 34 Caption and Figure 35 Caption.................................................................................. 14
Changes to Typical Performance Characteristics Section............................................................................. 10
Moved Table 11, Table 12, and Table 13........................................................................................................17
Moved Table 14..............................................................................................................................................19
Moved Table 15..............................................................................................................................................20
Changes to Table 15...................................................................................................................................... 20
Change to Rheostat Operation—1% Resistor Tolerance Section..................................................................21
Updated Outline Dimensions......................................................................................................................... 23
Changes to Ordering Guide........................................................................................................................... 23
Added RAW (kΩ) and Resolution Options Section......................................................................................... 24
analog.com
Rev. G | 2 of 24
Data Sheet
AD5270/AD5271
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5270
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
Resistor Integral Nonlinearity2, 3
R-INL
RAW = 20 kΩ, |VDD − VSS| = 3.0 V to 5.5 V
RAW = 20 kΩ, |VDD − VSS| = 2.7 V to 3.0 V
RAW = 50 kΩ, 100 kΩ
10
−1
−1
−1
−1
See Table 2 and Table 3
−1
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
R-Perf Mode4
Normal Mode
Resistance Temperature Coefficient5, 6
Wiper Resistance
RESISTOR TERMINALS
Terminal Voltage Range5, 7
Capacitance5 A
Capacitance5 W
Common-Mode Leakage Current5
DIGITAL INPUTS
Input Logic5
High
Low
Input Current
Input Capacitance5
DIGITAL OUTPUT
Output Voltage5
High
Low
Tristate Leakage Current
Output Capacitance5
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Supply Current
Positive
Negative
50-TP Store Current5, 8
Positive
Negative
OTP Read Current5, 9
Positive
Negative
Power Dissipation10
Power Supply Rejection Ratio5
analog.com
R-DNL
Code = full scale
Code = zero scale
Typ1
±0.5
±15
5
35
VSS
f = 1 MHz, measured to GND, code = half scale
f = 1 MHz, measured to GND, code = half scale
VA = VW
VINH
VINL
IIN
CIN
VOH
VOL
Max
Unit
+1
+1.5
+1
+1
Bits
LSB
LSB
LSB
LSB
+1
%
%
ppm/°C
Ω
70
VDD
V
pF
pF
nA
90
40
50
2.0
V
V
µA
pF
0.8
±1
5
RPULL_UP = 2.2 kΩ to VDD
RPULL_UP = 2.2 kΩ to VDD
VDD = 2.7 V to 5.5 V, VSS = 0 V
VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V
VDD − 0.1
V
−1
0.4
0.6
+1
V
V
µA
pF
5.5
±2.75
V
V
1
µA
µA
5
VDD
VDD/VSS
VSS = 0 V
IDD
ISS
2.7
±2.5
−1
IDD_OTP_STORE
ISS_OTP_STORE
4
−4
IDD_OTP_READ
ISS_OTP_READ
PSRR
mA
mA
500
−500
VIH = VDD or VIL = GND
ΔVDD/ΔVSS = ±5 V ± 10%
RAW = 20 kΩ
5.5
−66
µA
µA
µW
dB
−55
Rev. G | 3 of 24
Data Sheet
AD5270/AD5271
SPECIFICATIONS
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
RAW = 50 kΩ
RAW = 100 kΩ
DYNAMIC CHARACTERISTICS5, 11
Bandwidth
Typ1
Max
−75
−78
−67
−70
−3 dB, RAW = 10 kΩ, Terminal W, see Figure 42
Total Harmonic Distortion
Resistor Noise Density
Unit
kHz
RAW = 20 kΩ
RAW = 50 kΩ
RAW = 100 kΩ
VA = 1 V rms, f = 1 kHz, code = half scale
300
120
60
RAW = 20 kΩ
RAW = 50 kΩ
RAW= 100 kΩ
Code = half scale, TA = 25°C
RAW = 20 kΩ
RAW = 50 kΩ
RAW = 100 kΩ
−90
−88
−85
dB
nV/√Hz
13
25
32
1
Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions.
3
The maximum current in each code is defined by IAW = (VDD − 1)/RAW.
4
The terms resistor performance mode and R-Perf mode are used interchangeably. See the Resistor Performance Mode section.
5
Guaranteed by design and not subject to production test.
6
See Figure 25 for more details.
7
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal
adjustment.
8
Different from operating current, the supply current for the fuse program lasts approximately 55 ms.
9
Different from operating current, the supply current for the fuse read lasts approximately 500 ns.
10
PDISS is calculated from (IDD × VDD) + (ISS × VSS).
11
All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.
Table 2. AD5270—20 kΩ Resistor Performance Mode Code Range
Resistor Tolerance Per Code
|VDD − VSS| = 4.5 V to 5.5 V
|VDD − VSS| = 2.7 V to 4.5 V
R-TOLERANCE
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
From 0x078 to 0x3FF
From 0x037 to 0x3FF
From 0x028 to 0x3FF
From 0x0BE to 0x3FF
From 0x055 to 0x3FF
From 0x037 to 0x3FF
Table 3. AD5270—50 kΩ and 100 kΩ Resistor Performance Mode Code Range
Resistor Tolerance Per Code
RAW = 50 kΩ
RAW = 100 kΩ
R-TOLERANCE
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
From 0x078 to 0x3FF
From 0x055 to 0x3FF
From 0x032 to 0x3FF
From 0x04B to 0x3FF
From 0x032 to 0x3FF
From 0x019 to 0x3FF
analog.com
Rev. G | 4 of 24
Data Sheet
AD5270/AD5271
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5271
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 4.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
Resistor Integral Nonlinearity2, 3
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
R-Perf Mode4
Normal Mode
Resistance Temperature Coefficient5, 6
Wiper Resistance
RESISTOR TERMINALS
Terminal Voltage Range5, 7
Capacitance5 A
Capacitance5 W
Common-Mode Leakage Current5
DIGITAL INPUTS
Input Logic5
High
Low5
Input Current
Input Capacitance5
DIGITAL OUTPUT
Output Voltage5
High
Low
Tristate Leakage Current
Output Capacitance5
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Supply Current
Positive
Negative
50-TP Store Current5, 8
Positive
Negative
OTP Read Current5, 9
Positive
Negative
Power Dissipation10
Power Supply Rejection Ratio5
Symbol
Test Conditions/Comments
Min
Typ1
8
−1
−1
R-INL
R-DNL
See Table 5 and Table 6
−1
Code = full scale
Code = zero scale
±0.5
±15
5
35
VSS
f = 1 MHz, measured to GND, code = half scale
f = 1 MHz, measured to GND, code = half scale
VA = VW
VINH
VINL
IIN
CIN
VOH
VOL
Max
Unit
+1
+1
Bits
LSB
LSB
+1
70
VDD
90
40
50
2.0
0.8
±1
5
RPULL_UP = 2.2 kΩ to VDD
RPULL_UP = 2.2 kΩ to VDD
VDD = 2.7 V to 5.5 V, VSS = 0 V
VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V
VDD − 0.1
IDD
ISS
2.7
±2.5
V
V
µA
pF
5.5
±2.75
V
V
1
µA
µA
−1
IDD_OTP_STORE
ISS_OTP_STORE
4
−4
IDD_OTP_READ
ISS_OTP_READ
PSRR
V
V
µA
pF
0.4
0.6
+1
5
VSS = 0 V
V
pF
pF
nA
V
−1
VDD
VDD/VSS
%
%
ppm/°C
Ω
mA
mA
500
−500
VIH = VDD or VIL = GND
ΔVDD/ΔVSS = ±5 V ± 10%
RAW = 20 kΩ
5.5
−66
−55
RAW = 100 kΩ
−78
−70
µA
µA
µW
dB
DYNAMIC CHARACTERISTICS5, 11
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Rev. G | 5 of 24
Data Sheet
AD5270/AD5271
SPECIFICATIONS
Table 4.
Parameter
Symbol
Test Conditions/Comments
Bandwidth
Min
−3 dB, RAW = 10 kΩ, Terminal W, see Figure 42
RAW = 20 kΩ
Total Harmonic Distortion
Resistor Noise Density
Typ1
Max
Unit
kHz
300
RAW = 100 kΩ
VA = 1 V rms, f = 1 kHz, code = half scale
RAW = 20 kΩ
60
RAW = 100 kΩ
Code = half scale, TA = 25°C
RAW = 20 kΩ
−85
RAW = 100 kΩ
32
dB
−90
nV/√Hz
13
1
Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions.
3
The maximum current in each code is defined by IAW = (VDD − 1)/RAW.
4
The terms resistor performance mode and R-Perf mode are used interchangeably. See the Resistor Performance Mode section.
5
Guaranteed by design and not subject to production test.
6
See Figure 25 for more details.
7
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal
adjustment.
8
Different from operating current, the supply current for the fuse program lasts approximately 55 ms.
9
Different from operating current, the supply current for the fuse read lasts approximately 500 ns.
10
PDISS is calculated from (IDD × VDD) + (ISS × VSS).
11
All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.
Table 5. AD5271—20 kΩ Resistor Performance Mode Code Range
Resistor Tolerance per Code
|VDD − VSS| = 4.5 V to 5.5 V
|VDD − VSS| = 2.7 V to 4.5 V
R-TOLERANCE
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
From 0x1E to 0xFF
From 0x0F to 0xFF
From 0x06 to 0xFF
From 0x32 to 0xFF
From 0x19 to 0xFF
From 0x0E to 0xFF
Table 6. AD5271—100 kΩ Resistor Performance Mode Code Range
Resistor Tolerance per Code
RAW = 100 kΩ
R-TOLERANCE
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
From 0x14 to 0xFF
From 0x0F to 0xFF
From 0x0A to 0xFF
INTERFACE TIMING SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter
Limit1
Unit
Test Conditions/Comments
t 12
t2
t3
t4
20
10
10
15
ns min
ns min
ns min
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
analog.com
Rev. G | 6 of 24
Data Sheet
AD5270/AD5271
SPECIFICATIONS
Table 7.
Parameter
Limit1
Unit
Test Conditions/Comments
t5
t6
t7
t83, 4
t9
t105
tRDAC_R-PERF
tRDAC_NORMAL
tMEMORY_READ
tMEMORY_PROGRAM
tRESET
tPOWER-UP6
5
5
1
500
15
450
2
600
6
350
0.6
2
ns min
ns min
ns min
ns min
ns min
ns max
µs max
ns max
µs max
ms max
ms max
ms max
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignored
SCLK rising edge to SDO valid
RDAC register write command execute time
RDAC register write command execute time
Memory readback execute time
Memory program time
Reset 50-TP restore time
Power-on 50-TP restore time
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 50 MHz.
3
Refer to tRDAC_R-PER and tRDAC_NORMAL for RDAC register write operations.
4
Refer to tMEMORY_READ and tMEMORY_PROGRAM for memory commands operations.
5
RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF.
6
Maximum time after VDD − VSS is equal to 2.5 V.
Shift Register and Timing Diagrams
Figure 2. Shift Register Content
Figure 3. Write Timing Diagram (CPOL = 0, CPHA = 1)
Figure 4. Read Timing Diagram (CPOL = 0, CPHA = 1)
analog.com
Rev. G | 7 of 24
Data Sheet
AD5270/AD5271
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 8.
Parameter
Rating
VDD to GND
VSS to GND
VDD to VSS
VA, VW to GND
Digital Input and Output Voltage to GND
EXT_CAP to VSS
IA, IW
Continuous
RAW = 20 kΩ
RAW = 50 kΩ, 100 kΩ
Pulsed1
Frequency > 10 kHz
Frequency ≤ 10 kHz
Operating Temperature Range4
Maximum Junction Temperature
(TJ Maximum)
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Package Power Dissipation
–0.3 V to +7.0 V
+0.3 V to −7.0 V
7V
VSS − 0.3 V, VDD + 0.3 V
−0.3 V to VDD + 0.3 V
7V
±3 mA
±2 mA
±MCC2/d3
±MCC2/√d3
−40°C to +125°C
150°C
Maximum continuous current.
Pulse duty factor.
θJA1
θJC
Unit
10-Lead LFCSP
10-Lead MSOP
50
135
3
N/A
°C/W
°C/W
1
JEDEC 2S2P test board, still air (0 m/s air flow).
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
260°C
20 sec to 40 sec
(TJ max − TA)/θJA
2
Includes programming of 50-TP memory.
Package Type
−65°C to +150°C
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A and W terminals at a given resistance.
4
Table 9. Thermal Resistance
ESD CAUTION
1
3
θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
analog.com
Rev. G | 8 of 24
Data Sheet
AD5270/AD5271
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. MSOP Pin Configuration
Figure 6. LFCSP Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
VDD
A
W
VSS
EXT_CAP
GND
SDO
8
9
DIN
SCLK
10
SYNC
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
External Capacitor. Connect a 1 µF capacitor between EXT_CAP and VSS. This capacitor must have a voltage rating of ≥7 V.
Ground Pin, Logic Ground Reference.
Serial Data Output. This pin can be used to clock data from the shift register in daisy-chain mode or in readback mode. This open-drain
output requires an external pull-up resistor even if it is not use.
Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit input register.
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to
50 MHz.
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When goes low, it enables the shift
register and data is transferred in on the falling edges of the subsequent clocks. The selected register is updated on the rising edge of
following the 16th clock cycle. If is taken high before the 16th clock cycle, the rising edge of acts as an interrupt, and the write sequence is
ignored by the RDAC.
Exposed Pad. Leave floating or connected to VSS.
EPAD
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Rev. G | 9 of 24
Data Sheet
AD5270/AD5271
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5270)
Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5270)
Figure 8. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5270)
Figure 11. R-INL in Normal Mode vs. Code vs. Temperature (AD5270)
Figure 9. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5270)
Figure 12. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5270)
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Rev. G | 10 of 24
Data Sheet
AD5270/AD5271
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 13. R-DNL in Normal Mode vs. Code vs. Temperature (AD5270)
Figure 16. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5271)
Figure 14. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5270)
Figure 17. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5271)
Figure 15. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5271)
Figure 18. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5271)
analog.com
Rev. G | 11 of 24
Data Sheet
AD5270/AD5271
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 19. R-INL in Normal Mode vs. Code vs. Temperature (AD5271)
Figure 22. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5271)
Figure 20. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5271)
Figure 23. Supply Current (IDD, ISS) vs. Temperature
Figure 21. R-DNL in Normal Mode vs. Code vs. Temperature (AD5271)
Figure 24. Supply Current IDD vs. Digital Input Voltage
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Rev. G | 12 of 24
Data Sheet
AD5270/AD5271
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 25. Tempco ΔRWA/ΔT vs. Code
Figure 28. 50 kΩ Gain vs. Code vs. Frequency
Figure 26. Theoretical Maximum Current vs. Code
Figure 29. 100 kΩ Gain vs. Code vs. Frequency
Figure 27. 20 kΩ Gain vs. Code vs. Frequency
Figure 30. PSRR vs. Frequency
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Rev. G | 13 of 24
Data Sheet
AD5270/AD5271
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 34. Maximum Code Loss > 1% R-Tolerance Error vs. Voltage
Figure 31. THD + N vs. Frequency
Figure 35. Maximum Code Loss > 1% R-Tolerance Error vs. Temperature
Figure 32. THD + N vs. Amplitude
Figure 36. Digital Feedthrough
Figure 33. Maximum Glitch Energy
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Rev. G | 14 of 24
Data Sheet
AD5270/AD5271
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 37. VEXT_CAP Waveform While Writing Fuse
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Figure 38. Long-Term Drift Accelerated Average by Burn-In
Rev. G | 15 of 24
Data Sheet
AD5270/AD5271
TEST CIRCUITS
Figure 39 to Figure 43 define the test conditions used in the Specifications section.
Figure 39. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL,
R-DNL)
Figure 40. Wiper Resistance
Figure 42. Gain vs. Frequency
Figure 43. Common Leakage Current
Figure 41. Power Supply Sensitivity (PSS, PSRR)
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Rev. G | 16 of 24
Data Sheet
AD5270/AD5271
THEORY OF OPERATION
The AD5270/AD5271 are designed to operate as true variable
resistors for analog signals within the terminal voltage range of
VSS < VTERM < VDD. The RDAC register contents determine the
resistor wiper position. The RDAC register acts as a scratchpad
register, which allows unlimited changes of resistance settings. The
RDAC register can be programmed with any position setting using
the SPI interface. When a desirable wiper position is found, this
value can be stored in a 50-TP memory register. Thereafter, the
wiper position is always restored to that position for subsequent
power-up. The storing of 50-TP data takes approximately 350 ms;
during this time, the AD5270/AD5271 lock to prevent any changes
from taking place.
which should be set to zero, followed by four control bits and
10 RDAC data bits (note that for the AD5271 only, the lower two
RDAC data bits are don’t care if the RDAC register is read from or
written to). Data is loaded MSB first (Bit 15). The four control bits
determine the function of the software command as listed in Table
12. Figure 3 shows a timing diagram of a typical AD5270/AD5271
write sequence.
The write sequence begins by bringing the SYNC line low. The
SYNC pin must be held low until the complete data-word is loaded
from the DIN pin. When SYNC returns high, the serial data-word is
decoded according to the instructions in Table 12. The command
bits (Cx) control the operation of the digital potentiometer. The
data bits (Dx) are the values that are loaded into the decoded
register. The AD5270/AD5271 have an internal counter that counts
a multiple of 16 bits (a frame) for proper operation. For example,
AD5270/AD5271 each works with a 32-bit word but do not work
properly with a 31-bit or 33-bit word. The AD5270/AD5271 do not
require a continuous SCLK when SYNC is high. To minimize power
consumption in the digital input buffers, operate all serial interface
pins close to the VDD supply rails.
The AD5270/AD5271 also feature a patented 1% end-to-end resistor tolerance. This simplifies precision, rheostat mode, and openloop applications where knowledge of absolute resistance is critical.
SERIAL DATA INTERFACE
The AD5270/AD5271 contain a serial interface (SYNC, SCLK, DIN ,
and SDO), which is compatible with SPI interface standards, as
well as most DSPs. This device allows writing of data via the serial
interface to every register.
SHIFT REGISTER
For the AD5270/AD5271, the shift register is 16 bits wide, as
shown in Figure 2. The 16-bit word consists of two unused bits,
Table 11. Control Register Bit Description
Bit Name
Description
C0
50-TP program enable
0 = 50-TP program disabled (default)
1 = enable device for 50-TP program
RDAC register write protect
0 = wiper position frozen to value in 50-TP memory (default)1
1 = allow update of wiper position through digital interface
R-performance enable
0 = RDAC resistor tolerance calibration enabled (default)
1 = RDAC resistor tolerance calibration disabled
50-TP memory program success bit
0 = fuse program command unsuccessful (default)
1 = fuse program command successful
C1
C2
C3
1
Wiper position frozen to the last value programmed in the 50-TP memory. The wiper is frozen to midscale if the 50-TP memory has not been previously programmed.
Table 12. Command Operation Truth Table
Data[DB9:DB0]1
Command[DB13:DB10]
Command
Number
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
1
0
0
0
0
0
0
0
1
X
D9
X
D8
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D12
X
D02
2
3
0
0
0
0
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP: do nothing.
Write contents of serial register data to
RDAC.
Read contents of RDAC wiper register.
Store wiper setting: store RDAC setting to
50-TP.
analog.com
Rev. G | 17 of 24
Data Sheet
AD5270/AD5271
THEORY OF OPERATION
Table 12. Command Operation Truth Table
Data[DB9:DB0]1
Command[DB13:DB10]
Command
Number
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Operation
4
0
1
0
0
X
X
X
X
X
X
X
X
X
X
53
0
1
0
1
X
X
X
X
D5
D4
D3
D2
D1
D0
6
0
1
1
0
X
X
X
X
X
X
X
X
X
X
74
0
1
1
1
X
X
X
X
X
X
X
D2
D1
D0
8
9
1
1
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D0
Software reset: refresh RDAC with last 50TP memory stored value.
Read contents of 50-TP from SDO output
in the next frame.
Read address of last 50-TP programmed
memory location.
Write contents of serial register data to
control register.
Read contents of control register.
Software shutdown.
D0 = 0; normal mode.
D0 = 1; device placed in shutdown mode.
1
X is don’t care.
2
AD5271 = don’t care.
3
See Table 14 for 50-TP memory map.
4
See Table 11 for bit details.
Table 13. Control Register Bit Map
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
C3
C2
C1
C0
RDAC REGISTER
The RDAC register directly controls the position of the digital rheostat wiper. For example, when the RDAC register is loaded with all
zeros, the wiper is connected to Terminal A of the variable resistor.
The RDAC register is a standard logic register and there is no
restriction on the number of changes allowed. The basic mode of
setting the variable resistor wiper position (programming the RDAC
register) is accomplished by loading the serial data input register
with Command 1 (see Table 12) and with the desired wiper position
data.
analog.com
Rev. G | 18 of 24
Data Sheet
AD5270/AD5271
THEORY OF OPERATION
50-TP MEMORY BLOCK
The AD5270/AD5271 contain an array of 50-TP programmable
memory registers, which allow the wiper position to be programmed
up to 50 times. Table 13 shows the memory map. When the desired
wiper position is determined, the user can load the serial data
input register with Command 3 (see Table 12) which stores the
wiper position data in a 50-TP memory register. The first address
to be programmed is Location 0x01 (see Table 13); the AD5270/
AD5271 increment the 50-TP memory address for each subsequent
program until the memory is full. Programming data to 50-TP consumes approximately 4 mA for 55 ms, and takes approximately 350
ms to complete, during which time the shift register locks to prevent
any changes from occurring. Bit C3 of the control register can be
polled to verify that the fuse program command was completed
properly. No change in supply voltage is required to program the
50-TP memory; however, a 1 μF capacitor on the EXT_CAP pin
is required (see Figure 46). Prior to 50-TP activation, the AD5270/
AD5271 preset to midscale on power up.
Table 14. Memory Map
Data Byte[DB9:DB8]1
Command Number
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Register Contents
5
X
X
X
X
X
…
X
X
X
X
X
X
X
X
X
X
…
X
X
X
X
X
X
X
X
X
X
…
X
X
X
X
X
0
0
0
0
0
…
0
0
0
0
0
0
0
0
0
0
…
0
0
0
1
1
0
0
0
0
0
…
0
1
1
0
1
0
0
0
0
0
…
1
0
1
1
0
0
0
0
0
1
…
0
1
1
0
0
0
0
1
1
0
…
1
0
1
0
1
0
1
0
1
0
…
0
0
0
0
0
Reserved
1st programmed wiper location (0x01)
2nd programmed wiper location (0x02)
3rd programmed wiper location (0x03)
4th programmed wiper location (0x04)
…
10th programmed wiper location (0xA)
20th programmed wiper location (0x14)
30th programmed wiper location (0x1E)
40th programmed wiper location (0x28)
50th programmed wiper location (0x32)
1
X is don’t care.
analog.com
Rev. G | 19 of 24
Data Sheet
AD5270/AD5271
THEORY OF OPERATION
WRITE PROTECTION
At power-up, the serial data input register write commands for both
the RDAC register and the 50-TP memory registers are disabled.
The RDAC write protect bit, C1, of the control register (see Table
11 and Table 13) is set to 0 by default. This disables any change
of the RDAC register content regardless of the software commands,
except that the RDAC register can be refreshed from the 50-TP
memory using the software reset, Command 4. To enable programming of the RDAC register, the write protect bit (Bit C1), of the
control register must first be programmed by loading the serial
data input register with Command 7. To enable programming of
the 50-TP memory, the program enable bit (Bit C0) of the control
register, which is set to 0 by default, must first be set to 1.
RDAC AND 50-TP READ OPERATION
A serial data output SDO pin is available for readback of the internal RDAC register or 50-TP memory contents. The contents of the
RDAC register can be read back through SDO by using Command
2 (see Table 12). Data from the RDAC register is clocked out of the
SDO pin during the last 10 clocks of the next SPI operation.
It is possible to read back the contents of any of the 50-TP memory
registers through SDO by using Command 5. The lower six LSB
bits, D0 to D5 of the data byte, select which memory location is to
be read back, as shown in Table 13.
Data from the selected memory location is clocked out of the
SDO pin during the next SPI operation. A binary encoded version
address of the most recently programmed wiper memory location
can be read back using Command 6 (see Table 12). This can be
used to monitor the spare memory status of the 50-TP memory
block.
Table 15 provides a sample listing for the sequence of serial data
input (DIN) words with the serial data output appearing at the SDO
pin in hexadecimal format for a write and read to both the RDAC
register and the 50-TP memory (Memory Location 20).
Table 15. Write and Read to RDAC and 50-TP Memory
DIN
SDO1
Action
0x1C03
0x0500
0x0800
0x0C00
0xXXXX
0x1C03
0x0500
0x100
0x1800
0x0000
0x0C00
0xXX19
0x1419
0x2000
0x0000
0x0000
0x0100
0xXXXX
Enable update of the wiper position and the 50-TP memory contents through the digital interface.
Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position.
Prepares data read from RDAC register.
Stores RDAC register content into the 50-TP memory. A 16-bit word appears out of SDO, where the last 10 bits contain the contents of the RDAC
register (0x100).
Prepares data read of last programmed 50-TP memory monitor location.
NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs, Bits[DB5:DB0], contain the binary address of the last programmed 50-TP
memory location, for example, 0x19 (see Table 11).
Prepares data read from Memory Location 0x19.
Prepares data read from the control register. Sends a 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Location 0x19.
NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register. If Bit C3 = 1, the fuse
program command is successful.
1
X is don’t care.
analog.com
Rev. G | 20 of 24
Data Sheet
AD5270/AD5271
THEORY OF OPERATION
SHUT-DOWN MODE
The AD5270/AD5271 can be shut down by executing the software
shutdown command, Command 9 (see Table 12), and setting the
LSB to 1. This feature places the RDAC in a zero-power-consumption state where Terminal Ax is open circuited and the Wiper
Terminal Wx remains connected. It is possible to execute any command from Table 12 while the AD5270/AD5271 are in shutdown
mode. The parts can be taken out of shutdown mode by executing
Command 9 and setting the LSB to 0 or by a software reset,
Command 4 (see Table 12).
Table 16. Minimize Power Dissipation at the SDO Pin
DIN
1
SDO1
Action
X is don’t care
Keep the SYNC pin low until all 32 bits are clocked to their
respective serial registers. The SYNC pin is then pulled high to
complete the operation.
RESISTOR PERFORMANCE MODE
This mode activates a new, patented 1% end-to-end resistor tolerance that ensures a ±1% resistor tolerance error on each code,
that is, code = half scale, RWA = 10 kΩ ± 100 Ω. See Table 2,
Table 3, Table 5, and Table 6 to verify which codes achieve ±1%
resistor tolerance. The resistor performance mode is activated by
programming Bit C2 of the control register.
RESET
The AD5270/AD5271 can be reset through software by executing
Command 4 (see Table 12). The reset command loads the RDAC
register with the contents of the most recently programmed 50‑TP
memory location. The RDAC register loads with midscale if no
50-TP memory location has been previously programmed.
Figure 44. Daisy-Chain Configuration Using SDO
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented the
RDAC segmentation architecture for all the digital potentio-meters.
In particular, the AD5270/AD5271 employ a three-stage segmentation approach as shown in Figure 45.The AD5270/AD5271 wiper
switch is designed with the transmission gate CMOS topology.
SDO PIN AND DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting and 50-TP values
using Command 2 and Command 5, respectively (see Table 12),
or the SDO pin can be used in daisy-chain mode. Data is clocked
out of SDO on the rising edge of SCLK. The SDO pin contains an
open-drain N-channel FET that requires a pull-up resistor. To place
the pin in high impedance and minimize the power dissipation when
the pin is used, the 0x8001 data word followed by Command 0
should be sent to the part. Table 16 provides a sample listing for the
sequence of the serial data input (DIN). Daisy chaining minimizes
the number of port pins required from the controlling IC. As shown
in Figure 44, the user must tie the SDO pin of one package to
the DIN pin of the next package. The user may need to increase
the clock period because the pull-up resistor and the capacitive
loading at the SDO-to-DIN interface may require additional time
delay between subsequent devices. When two AD5270/AD5271
devices are daisy-chained, 32 bits of data are required. The first 16
bits go to U2, and the second 16 bits go to U1.
Figure 45. Simplified RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—1% Resistor Tolerance
DIN
SDO1
Action
The nominal resistance between Terminal A and Terminal W, RWA,
is 20 kΩ, 50 kΩ, or 100 kΩ and has 1024‑/256‑tap points accessed
by the wiper terminal. The 10-/8-bit data in the RDAC latch is
decoded to select one of the 1024 or 256 possible wiper settings.
The AD5270/AD5271 contain an internal ±1% resistor tolerance
calibration feature that can be disabled or enabled, enabled by
default, or by programming Bit C2 of the control register (see Table
11 and Table 13).
0xXXXX
0x8001
0xXXXX
0xXXXX
0x0000
High
Impedance
Last user command sent to the digipot.
Prepares the SDO pin to be placed in high
impedance mode.
The SDO pin is placed in high impedance.
The digitally programmed output resistance between the W terminal
and the A terminal, RWA, is calibrated to give a maximum of ±1%
absolute resistance error over both the full supply and temperature
ranges. As a result, the general equations for determining the
Table 16. Minimize Power Dissipation at the SDO Pin
analog.com
Rev. G | 21 of 24
Data Sheet
AD5270/AD5271
THEORY OF OPERATION
digitally programmed output resistance between the W terminal and
the A terminal are the following:
For the AD5270
RWA(D) =
D
1024
RWA(D) =
D
256
For the AD5271
× RWA
× RWA
(1)
(2)
where:
D is the decimal equivalent of the binary code loaded in the 10‑/
8‑bit RDAC register.
RWA is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of 35 Ω is
present. Regardless of which setting the part is operating in, take
care to limit the current between Terminal A to Terminal W to the
maximum continuous current of ±3 mA or a pulse current specified
in Table 8. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
EXT_CAP CAPACITOR
A 1 μF capacitor to VSS must be connected to the EXT_CAP pin, as
shown in Figure 46, on power-up and throughout the operation of
the AD5270/AD5271.
Figure 46. EXT_CAP Hardware Setup
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the AD5270/
AD5271 define the boundary conditions for proper 2-terminal digi-
analog.com
tal resistor operation. Supply signals present on Terminal A and
Terminal W that exceed VDD or VSS are clamped by the internal
forward-biased diodes, see Figure 47.
Figure 47. Maximum Terminal Voltages Set by VDD and VSS
The ground pins of the AD5270/AD5271 devices are primarily used
as digital ground references. To minimize the digital ground bounce,
join the AD5270/AD5271 ground terminal remotely to the common
ground. The digital input control signals to the AD5270/AD5271
must be referenced to the device ground pin (GND), and must
satisfy the logic level defined in the Specifications section. An
internal level shift circuit ensures that the common-mode voltage
range of the three terminals extends from VSS to VDD, regardless of
the digital input level.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at Terminal A and Terminal W (see Figure 47), it is important to power
VDD/VSS first before applying any voltage to Terminal A and Terminal W; otherwise, the diode is forward-biased such that VDD/VSS
are powered unintentionally. The ideal power-up sequence is VSS,
GND, VDD, digital inputs, VA, and VW. The order of powering VA,
VW, and the digital inputs is not important as long as they are
powered after VDD/VSS.
As soon as VDD is powered, the power-on preset activates which
first sets the RDAC to midscale and then restores the last programmed 50-TP value to the RDAC register.
Rev. G | 22 of 24
Data Sheet
AD5270/AD5271
OUTLINE DIMENSIONS
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Figure 49. 10-Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
Updated: November 08, 2021
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package
Option
Marking Code
AD5270BCPZ-100-RL7
AD5270BCPZ-20-RL7
AD5270BRMZ-100
AD5270BRMZ-100-RL7
AD5270BRMZ-20
AD5270BRMZ-20-RL7
AD5270BRMZ-50
AD5270BRMZ-50-RL7
AD5271BCPZ-20-RL7
AD5271BRMZ-100
AD5271BRMZ-100-RL7
AD5271BRMZ-20
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
10-Lead LFCSP (3mm x 3mm)
10-Lead LFCSP (3mm x 3mm)
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP (3mm x 3mm)
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Reel, 1500
Reel, 1500
Tube, 50
Reel, 1000
Tube, 50
Reel, 1000
Tube, 50
Reel, 1000
Reel, 1500
Tube, 50
Reel, 1000
Tube, 50
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
CP-10-9
RM-10
RM-10
RM-10
DEH
DEH
DDP
DDP
DDP
DDP
DDP
DDP
DEK
DEJ
DEJ
DEJ
analog.com
Rev. G | 23 of 24
Data Sheet
AD5270/AD5271
OUTLINE DIMENSIONS
Model1
Temperature Range
Package Description
Packing Quantity
Package
Option
Marking Code
AD5271BRMZ-20-RL7
-40°C to +125°C
10-Lead MSOP
Reel, 1000
RM-10
DEJ
1
Z = RoHS Compliant Part.
RAW (KΩ) AND RESOLUTION OPTIONS
Model1
RAW (kΩ)
Resolution
AD5270BCPZ-100-RL7
AD5270BCPZ-20-RL7
AD5270BRMZ-100, AD5270BRMZ-100-RL7
AD5270BRMZ-20, AD5270BRMZ-20-RL7
AD5270BRMZ-50, AD5270BRMZ-50-RL7
AD5271BCPZ-20-RL7
AD5271BRMZ-100, AD5271BRMZ-100-RL7
AD5271BRMZ-20, AD5271BRMZ-20-RL7
100
20
100
20
50
20
100
20
1,024
1,024
1,024
1,024
1,024
256
256
256
1
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model1
Description
EVAL-AD5270SDZ
Evaluation board
1
Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. G | 24 of 24
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