AD5291

256-/1024-Position, DigiPOT+ Potentiometers with Maximum ±1% R-Tolerance Error and 20-TP Memory AD5291/AD5292 FEATURES Single-channel, 256-/1024-position resolution 20 kΩ nominal resistance Calibrated ±1% nominal resistor tolerance (resistor performance mode) 20-time programmable (20-TP) set-and-forget resistance setting allows multiple time permanent programming Rheostat mode temperature coefficient: 35 ppm/°C Voltage divider temperature coefficient: 5 ppm/°C +9 V to +33 V single-supply operation ±9 V to ±16.5 V dual-supply operation SPI-compatible serial interface Wiper setting readback Power-on refreshed from 20-TP memory FUNCTIONAL BLOCK DIAGRAM VDD POWER-ON RESET VLOGIC SCLK SYNC DIN SDO RDY VSS EXT_CAP GND 07674-001 RESET AD5291/ AD5292 RDAC REGISTER SERIAL INTERFACE DATA OTP MEMORY BLOCK A W B APPLICATIONS Mechanical potentiometer replacement Instrumentation: gain and offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, and time constants Programmable power supply Low resolution DAC replacement Sensor calibration Figure 1. GENERAL DESCRIPTION The AD5291/AD5292, members of the Analog Devices, Inc., DigiPOT+ family of potentiometers, are single-channel, 256-/ 1024-position digital potentiometers1 that combine industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. These devices are capable of operating across a wide voltage range; supporting both dual supply operation at ±10.5 V to ±16.5 V and single supply operation at +21 V to +33 V, while ensuring less than 1% endto-end resistor tolerance (R-tolerance) error and offering 20-time programmable (20-TP) memory. The guaranteed industry-leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. 1 The AD5291/AD5292 device wiper settings are controllable through the SPI digital interface. Unlimited adjustments are allowed before programming the resistance value into the |20-TP memory. The AD5291/AD5292 do not require any external voltage supply to facilitate fuse blow and there are 20 opportunities for permanent programming. During 20-TP activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer). The AD5291/AD5292 are available in a compact 14-lead TSSOP package. The part is guaranteed to operate over the extended industrial temperature range of −40°C to +105°C. The terms digital potentiometer and RDAC are used interchangeably. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD5291/AD5292 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Electrical Characteristics—AD5291 .......................................... 3  Resistor Performance Mode Code Range—AD5291............... 4  Electrical Characteristics—AD5292 .......................................... 5  Resistor Performance Mode Code Range—AD5292............... 6  Interface Timing Specifications .................................................. 7  Timing Diagrams.......................................................................... 8  Absolute Maximum Ratings............................................................ 9  Thermal Resistance ...................................................................... 9  ESD Caution .................................................................................. 9  Pin Configuration and Function Descriptions ........................... 10  Typical Performance Characteristics ........................................... 11  Test Circuits ..................................................................................... 17  Theory of Operation ...................................................................... 18  Serial Data Interface ................................................................... 18  Shift Register ............................................................................... 18  RDAC Register ............................................................................ 18  20-TP Memory ........................................................................... 19  Write Protection ......................................................................... 19  Basic Operation .......................................................................... 20  20-TP Readback and Spare Memory Status ........................... 20  Shutdown Mode ......................................................................... 21  Resistor Performance Mode...................................................... 21  Reset ............................................................................................. 21  Daisy-Chain Operation ............................................................. 21  RDAC Architecture .................................................................... 21  Programming the Variable Resistor ......................................... 21  Programming the Potentiometer Divider ............................... 22  EXT_CAP Capacitor.................................................................. 22  Terminal Voltage Operating Range ......................................... 23  Applications Information .............................................................. 24  High Voltage DAC...................................................................... 24  Programmable Voltage Source with Boosted Output ........... 24  High Accuracy DAC .................................................................. 24  Variable Gain Instrumentation Amplifier .............................. 24  Audio Volume Control .............................................................. 25  Outline Dimensions ....................................................................... 26  Ordering Guide .......................................................................... 26  REVISION HISTORY 5/09—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD5291/AD5292 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5291 VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, −40°C < TA < +105°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance (R-Perf Mode3) Nominal Resistor Tolerance (Normal Mode) Resistance Temperature Coefficient4 Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient4 Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range6 Capacitance A, Capacitance B4 Capacitance W4 Common-Mode Leakage Current4 DIGITAL INPUTS Input Logic High4 Input Logic Low4 Input Current Input Capacitance4 DIGITAL OUTPUTS (SDO and RDY) Output High Voltage4 Output Low Voltage4 Tristate Leakage Current Output Capacitance4 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current Logic Supply Range Logic Supply Current OTP Store Current4, 7 OTP Read Current4, 8 Power Dissipation9 Power Supply Rejection Ratio4 Symbol N R-DNL R-INL ∆RAB/RAB ∆RAB/RAB (∆RAB/RAB)/∆T × 106 RW Conditions Min 8 −1 −1 −1 Typ1 Max Unit Bits LSB LSB % % ppm/°C Ω RWB, VA = NC See Table 2 0.5 ±20 35 60 +1 +1 +1 100 N DNL INL (∆VW/VW)/∆T × 106 VWFSE VWZSE VA, VB, VW CA, CB CW ICM VIH VIL IIL CIL VOH VOL COL VDD VDD/VSS IDD ISS VLOGIC ILOGIC ILOGIC_PROG ILOGIC_FUSE_READ PDISS PSSR 8 −1 −0.5 Code = half scale Code = full scale Code = zero scale −2 0 VSS f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VB = VW JEDEC compliant VLOGIC = 2.7 V to 5.5 V VLOGIC = 2.7 V to 5.5 V VIN = 0 V or VLOGIC 85 65 ±1 2.0 1.5 +1 +0.5 Bits LSB LSB ppm/°C LSB LSB V pF pF nA V V μA pF V V μA pF V V μA μA V μA mA mA μW %/% 0 2 VDD 0.8 ±1 5 RPULL_UP = 2.2 kΩ to VLOGIC RPULL_UP = 2.2 kΩ to VLOGIC VLOGIC − 0.4 −1 5 GND + 0.4 V +1 VSS = 0 V VDD/VSS = ±16.5 V VDD/VSS = ±16.5 V VLOGIC = 5 V; VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND ∆VDD/∆VSS = ±15 V ± 10% 9 ±9 −2 2.7 0.1 −0.1 1 25 25 8 0.025 33 ±16.5 2 5.5 10 110 0.08 Rev. 0 | Page 3 of 28 AD5291/AD5292 Parameter DYNAMIC CHARACTERISTICS4, 10 Bandwidth Total Harmonic Distortion VW Settling Time Symbol BW THDW tS Conditions −3 dB VA = 1 V rms, VB = 0 V, f = 1 kHz Min Typ1 520 −93 Max Unit kHz dB VA = 30 V, VB = 0 V, ±0.5 LSB error band, initial code = zero scale Code = full scale, normal mode Code = full scale, R-Perf mode Code = half scale, normal mode Code = half scale, R-Perf mode RWB = 10 kΩ, TA = 25°C, 0 kHz to 200 kHz 750 2.5 2.5 5 0.11 ns μs μs μs nV/√Hz Resistor Noise Density eN_WB 1 2 Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V. Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at Code 0x02 and the RWB at Code 0xFF or between RWA at Code 0xFD and RWA at Code 0x00. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V. 3 Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably. 4 Guaranteed by design and characterization, not subject to production test. 5 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables groundreferenced bipolar signal adjustment. 7 Different from operating current; supply current for fuse program lasts approximately 550 μs. 8 Different from operating current; supply current for fuse read lasts approximately 550 μs. 9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC). 10 All dynamic characteristics use VDD = +15 V, VSS = −15 V, and VLOGIC = 5 V. RESISTOR PERFORMANCE MODE CODE RANGE—AD5291 Table 2. Resistor Tolerance per Code 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance |VDD − VSS| = 30 V to 33 V RWB From 0x5A to 0xFF From 0x23 to 0xFF From 0x1E to 0xFF RWA From 0x00 to 0xA5 From 0x00 to 0xDC From 0x00 to 0xE1 |VDD − VSS| = 26 V to 30 V RWB From 0x7D to 0xFF From 0x2D to 0xFF From 0x19 to 0xFF RWA From 0x00 to 0x82 From 0x00 to 0xD2 From 0x00 to 0xE6 |VDD − VSS| = 22 V to 26 V RWB From 0x7D to 0xFF From 0x23 to 0xFF From 0x17 to 0xFF RWA From 0x00 to 0x82 From 0x00 to 0xDC From 0x00 to 0xE8 |VDD − VSS| = 21 V to 22 V RWB N/A From 0x23 to 0xFF From 0x17 to 0xFF RWA N/A From 0x00 to 0xDC From 0x00 to 0xE8 Rev. 0 | Page 4 of 28 AD5291/AD5292 ELECTRICAL CHARACTERISTICS—AD5292 VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, −40°C < TA < +105°C, unless otherwise noted. Table 3. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance (R-Perf Mode3) Nominal Resistor Tolerance (Normal Mode) Resistance Temperature Coefficient4 Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient4 Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range6 Capacitance A, Capacitance B4 Capacitance W4 Common-Mode Leakage Current4 DIGITAL INPUTS Input Logic High4 Input Logic Low4 Input Current Input Capacitance4 DIGITAL OUTPUTS (SDO and RDY) Output High Voltage4 Output Low Voltage4 Tristate Leakage Current Output Capacitance4 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current Logic Supply Range Logic Supply Current OTP Store Current4, 7 OTP Read Current4, 8 Power Dissipation9 Power Supply Rejection Ratio4 Symbol N R-DNL R-INL R-INL ∆RAB/RAB ∆RAB/RAB (∆RAB/RAB)/∆T × 106 RW Conditions Min 10 −1 −2 −3 −1 Typ1 Max Unit Bits LSB LSB LSB % % ppm/°C Ω RWB, VA = NC |VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V See Table 4 0.5 ±20 35 60 +1 +2 +3 +1 100 N DNL INL (∆VW/VW)/∆T × 106 VWFSE VWZSE VA, VB, VW CA, CB CW ICM VIH VIL IIL CIL VOH VOL COL VDD VDD/VSS IDD ISS VLOGIC ILOGIC ILOGIC_PROG ILOGIC_FUSE_READ PDISS PSSR 10 −1 −1.5 Code = half scale Code = full scale Code = zero scale −8 0 VSS f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VB = VW JEDEC compliant VLOGIC = 2.7 V to 5.5 V VLOGIC = 2.7 V to 5.5 V VIN = 0 V or VLOGIC 85 65 ±1 2.0 5 +1 +1.5 Bits LSB LSB ppm/°C LSB LSB V pF pF nA V V μA pF V V μA pF V V μA μA V μA mA mA μW %/% 0 8 VDD 0.8 ±1 5 RPULL_UP = 2.2 kΩ to VLOGIC RPULL_UP = 2.2 kΩ to VLOGIC VLOGIC − 0.4 −1 5 GND + 0.4 1 VSS = 0 V VDD/VSS = ±16.5 V VDD/VSS = ±16.5 V VLOGIC = 5 V; VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND ∆VDD/∆VSS = ±15 V ± 10% 9 ±9 −2 2.7 0.1 −0.1 1 25 25 8 0.025 33 ±16.5 2 5.5 10 110 0.08 Rev. 0 | Page 5 of 28 AD5291/AD5292 Parameter DYNAMIC CHARACTERISTICS4, 10 Bandwidth Total Harmonic Distortion VW Settling Time Symbol BW THDW tS Conditions −3 dB VA = 1 V rms, VB = 0 V, f = 1 kHz Min Typ1 520 −93 Max Unit kHz dB VA = 30 V, VB = 0 V, ±0.5 LSB error band, initial code = zero scale Code = full scale, normal mode Code = full scale, R-Perf mode Code = half scale, normal mode Code = half scale, R-Perf mode RWB = 10 kΩ, TA = 25°C, 0 kHz to 200 kHz 750 2.5 2.5 5 0.11 ns μs μs μs nV/√Hz Resistor Noise Density eN_WB 1 2 Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V. Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at Code 0x02 and the RWB at Code 0xFF or between RWA at Code 0xFD and RWA at Code 0x00. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V. 3 Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably. 4 Guaranteed by design and characterization, not subject to production test. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables groundreferenced bipolar signal adjustment. 7 Different from operating current; supply current for fuse program lasts approximately 550 μs. 8 Different from operating current; supply current for fuse read lasts approximately 550 μs. 9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC). 10 All dynamic characteristics use VDD = +15 V, VSS = −15 V, and VLOGIC = 5 V. RESISTOR PERFORMANCE MODE CODE RANGE—AD5292 Table 4. Resistor Tolerance per Code 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance |VDD − VSS| = 30 V to 33 V RWB From 0x15E to 0x3FF From 0x8C to 0x3FF From 0x5A to 0x3FF RWA From 0x00 to 0x2A1 From 0x00 to 0x373 From 0x00 to 0x3A5 |VDD − VSS| = 26 V to 30 V RWB From 0x1F4 to 0x3FF From 0xB4 to 0x3FF From 0x64 to 0x3FF RWA From 0x00 to 0x20B From 0x00 to 0x34B From 0x00 to 0x39B |VDD − VSS| = 22 V to 26 V RWB From 0x1F4 to 0x3FF From 0xFA to 0x3FF From 0x78 to 0x3FF RWA From 0x00 to 0x20B From 0x00 to 0x305 From 0x00 to 0x387 |VDD − VSS| = 21 V to 22 V RWB N/A From 0xFA to 0x3FF From 0x78 to 0x3FF RWA N/A From 0x00 to 0x305 From 0x00 to 0x387 Rev. 0 | Page 6 of 28 AD5291/AD5292 INTERFACE TIMING SPECIFICATIONS VDD/VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, −40°C < TA < + 105°C. All specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter t12 t2 t3 t4 t5 t6 t7 t8 t9 t104 t114 t124 t 124 Limit1 20 10 10 10 5 5 1 4003 14 1 40 2.4 410 8 1.5 450 1.3 450 20 2 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max μs max ns max ms max ms min ns max ms max ns max ns min ms max Description SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK fall ignore RDY rising edge to SYNC falling edge SYNC rising edge to RDY fall time RDY low time, RDAC register write command execute time (R-Perf mode) RDY low time, RDAC register write command execute time (normal mode) RDY low time, memory program execute time Software\hardware reset RDY low time, RDAC register readback execute time RDY low time, memory readback execute time SCLK rising edge to SDO valid Minimum RESET pulse width (asynchronous) Power-on OTP restore time t124 t124 t 134 t134 t144 tRESET tPOWER-UP5 1 2 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 50 MHz. 3 Refer to t12 and t13 for RDAC register and memory commands operations. 4 RPULL_UP = 2.2 kΩ to VLOGIC, with a capacitance load of 168 pF. 5 Typical power supply voltage slew rate of 2 ms/V. DB9 (MSB) 0 0 C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 DB0 (LSB) D1 D0 07674-003 CONTROL BITS DATA BITS Figure 2. AD5291/AD5292 Shift Register Content Rev. 0 | Page 7 of 28 AD5291/AD5292 TIMING DIAGRAMS t4 SCLK SYNC t2 t3 t1 t7 t9 t8 t5 t6 DIN X X C3 C2 D7 D6 D2 D1 D0 SDO t10 RDY RESET t11 t12 07674-004 tRESET Figure 3. Write Timing Diagram SCLK t9 SYNC DIN X X C3 D0 D0 X X C3 D1 D0 t14 SDO X X C3 D1 D0 07674-005 t11 RDY t13 Figure 4. Read Timing Diagram Rev. 0 | Page 8 of 28 AD5291/AD5292 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to GND VSS to GND VLOGIC to GND VDD to VSS VA, VB, VW to GND IA, IB, IW Pulsed1 Frequency > 10 kHz Frequency ≤ 10 kHz Continuous Digital Input and Output Voltage to GND EXT_CAP Voltage to GND Operating Temperature Range3 Maximum Junction Temperature (TJ max) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation 1 Rating −0.3 V to +35 V +0.3 V to − 16.5 V −0.3 V to + 7 V 35 V VSS − 0.3 V, VDD+ 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE ±3 mA/d2 ±3 mA/√d2 ±3 mA −0.3 V to VLOGIC + 0.3 V −0.3 V to +7 V −40°C to +105°C 150°C −65°C to +150°C 260°C 20 sec to 40 sec (TJ max − TA)/θJA θJA is defined by JEDEC specification JESD-51 and the value is dependent on the test board and test environment. Table 7. Thermal Resistance Package Type 14-Lead TSSOP 1 θJA 931 θJC 20 Unit °C/W JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec air flow). ESD CAUTION Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Pulse duty factor. 3 Includes programming of OTP memory. Rev. 0 | Page 9 of 28 AD5291/AD5292 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET 1 VSS 2 A3 W4 B5 VDD 6 EXT_CAP 7 14 RDY AD5291/ AD5292 TOP VIEW Not to Scale 13 SDO 12 SYNC 11 SCLK 10 DIN 07674-006 9 8 GND VLOGIC Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 Mnemonic RESET Description Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory default loads midscale until the first 20-TP wiper memory location is programmed. RESET is activated at the logic high transition. Tie RESET to VLOGIC if not used. Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. Terminal A of RDAC. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD. Terminal B of RDAC. VSS ≤ VB ≤ VDD. Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V. Logic Power Supply; 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. Ground Pin, Logic Ground Reference. Serial Data Input. The AD5291/AD5292 have a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the shift register in daisy-chain mode or in readback mode. Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from the RDAC register or memory. 2 3 4 5 6 7 8 9 10 11 12 VSS A W B VDD EXT_CAP VLOGIC GND DIN SCLK SYNC 13 14 SDO RDY Rev. 0 | Page 10 of 28 AD5291/AD5292 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) –40°C +25°C +105°C 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 07674-106 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 128 256 384 512 640 768 896 1024 CODE (Decimal) 0 32 64 96 128 160 192 224 256 CODE (Decimal) Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5292) 0.6 0.5 0.4 0.3 DNL (LSB) Figure 9. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5291) 1.0 0.8 0.6 0.4 INL (LSB) 0.2 0.1 0 –0.1 –0.2 07674-007 0.2 0 –0.2 –0.4 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 CODE (Decimal) CODE (Decimal) Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5292) 0.30 0.25 0.20 0.15 –40°C +25°C +105°C Figure 10. R-INL in Normal Mode vs. Code vs. Temperature (AD5292) 0.15 0.10 0.05 DNL (LSB) INL (LSB) 0.10 0.05 0 –0.05 –0.10 –0.15 07674-008 0 –0.05 –0.10 –0.15 –0.20 0 128 –40°C 256 384 +25°C 512 640 +105°C 768 896 1024 07674-011 –0.20 0 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 8. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5291) Figure 11. R-DNL in Normal Mode vs. Code vs. Temperature (AD5292) Rev. 0 | Page 11 of 28 07674-010 –0.3 –40°C +25°C +105°C –0.6 –40°C +25°C +105°C 07674-009 –0.06 –40°C +25°C +105°C AD5291/AD5292 0.25 0.20 0.15 0.10 0.05 0 –0.05 –0.10 0 32 64 96 128 160 192 224 256 CODE (Decimal) DNL (LSB) INL (LSB) –40°C +25°C +105°C 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 0 128 –40°C 256 384 +25°C 512 640 +105°C 768 896 1024 07674-015 07674-017 07674-016 07674-012 CODE (Decimal) Figure 12. R-INL in Normal Mode vs. Code vs. Temperature (AD5291) 0.03 0.02 0.01 –40°C +25°C +105°C Figure 15. DNL in R-Perf Mode vs. Code vs. Temperature (AD5292) 0.25 0.20 0.15 0.10 –40°C +25°C +105°C DNL (LSB) 0 –0.01 –0.02 –0.03 INL (LSB) 0.05 0 –0.05 –0.10 –0.15 –0.04 –0.05 0 32 64 96 128 160 192 224 256 CODE (Decimal) –0.20 07674-013 –0.25 0 32 64 96 128 160 192 224 256 CODE (Decimal) Figure 13. R-DNL in Normal Mode vs. Code vs. Temperature (AD5291) 1.5 Figure 16. INL in R-Perf Mode vs. Code vs. Temperature (AD5291) 0.14 0.12 –40°C +25°C +105°C 1.0 0.10 0.08 DNL (LSB) 0.5 INL (LSB) 0.06 0.04 0.02 0 –0.02 –0.04 0 –0.5 –1.0 –40°C 0 128 256 384 +25°C 512 640 +105°C 768 896 1024 07674-014 –1.5 –0.06 0 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 14. INL in R-Perf Mode vs. Code vs. Temperature (AD5292) Figure 17. DNL in R-Perf Mode vs. Code vs. Temperature (AD5291) Rev. 0 | Page 12 of 28 AD5291/AD5292 0.8 0.6 0.4 0.2 INL (LSB) –40°C +25°C +105°C 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.05 0 32 –40°C +25°C +105°C 0 –0.2 –0.4 –0.6 –0.8 0 128 256 384 512 640 768 896 1024 CODE (Decimal) 07674-018 DNL (LSB) 64 96 128 160 192 224 256 CODE (Decimal) Figure 18. INL in Normal Mode vs. Code vs. Temperature (AD5292) 0.10 –40°C +25°C +105°C Figure 21. DNL in Normal Mode vs. Code vs. Temperature (AD5291) 450 400 350 SUPPLY CURRENT (nA) VDD/VSS = ±15V VLOGIC = +5V ILOGIC 0.05 0 DNL (LSB) 300 250 200 150 100 50 0 ISS 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) 07674-022 07674-024 –0.05 –0.10 IDD –0.15 0 128 256 384 512 640 768 896 1024 CODE (Decimal) 07674-019 –0.20 –50 –40 –30 –20 –10 0 Figure 19. DNL in Normal Mode vs. Code vs. Temperature (AD5292) 0.20 0.15 0.10 0.05 INL (LSB) 700 Figure 22. Supply Current (IDD, ISS, ILOGIC) vs. Temperature VDD = 30V, VSS= 0V –40°C +25°C +105°C RHEOSTAT MODE TEMPCO (ppm/°C) 600 500 400 300 200 100 0 0 –0.05 –0.10 –0.15 –0.20 0 32 64 96 128 160 192 224 256 CODE (Decimal) Figure 20. INL in Normal Mode vs. Code vs. Temperature (AD5291) 07674-020 0 0 256 64 512 128 CODE (Decimal) 768 192 1024 AD5292 256 AD5291 Figure 23. Rheostat Mode Tempco ΔRWB/ΔT vs. Code (AD5292) Rev. 0 | Page 13 of 28 07674-021 AD5291/AD5292 700 POTENTIOMETER MODE TEMPCO (ppm/°C) 600 500 400 300 200 VDD = 30V, VSS= 0V –66 –68 –70 THD + N (dB) VDD/VSS = ±15V CODE = HALF SCALE VIN = 1V rms –72 –74 –76 –78 100 0 –80 07674-027 07674-028 07674-029 0 0 256 64 512 128 CODE (Decimal) 768 192 1024 AD5292 256 AD5291 07674-023 –82 100 1k 10k FREQUENCY (Hz) 100k Figure 24. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code 0 –4 –8 –12 –18 GAIN (dB) 0x100 (0x40) 0x200 (0x80) Figure 27. THD + Noise vs. Frequency 0 –10 –20 VDD/VSS = ±15V, CODE = HALF SCALE fIN = 1kHz AD5292 (AD5291) 0x080 (0x20) 0x040 (0x10) 0x020 ( 0x08) 0x010 (0x04) 0x008 (0x02) 0x004 (0x01) 0x002 0x001 07674-025 –30 THD + N (dB) –24 –28 –32 –36 –40 –44 –50 –54 1 –40 –50 –60 –70 –80 10 100 1k 10k 100k 1M FREQUENCY (Hz) –90 0.001 0.01 0.1 AMPLITUDE (V) 1 10 Figure 25. 20 kΩ Gain vs. Frequency vs. Code (AD5292) 68 64 60 56 52 48 PSRR (dB) THEORETICAL IWB_MAX (mA) Figure 28. THD + Noise vs. Amplitude 8 7 6 5 4 3 2 1 07674-026 VDD/VSS = 30V/0V VA = VDD VB = VSS 44 40 36 32 28 24 20 16 12 VDD/VSS = ±15V CODE = HALF SCALE VLOGIC = +5V 0.1 1 10 100 1k 10k 100k 1M 8 0.01 0 0 0 256 64 512 128 CODE (Decimal) 768 192 1024 AD5292 256 AD5291 FREQUENCY (Hz) Figure 26. Power Supply Rejection Ratio vs. Frequency Figure 29. Theoretical Maximum Current vs. Code Rev. 0 | Page 14 of 28 AD5291/AD5292 1.0 0.9 SUPPLY CURRENT I LOGIC (mA) 1.2 VDD = ±15V 1.0 0.8 0.6 0.8 0.7 VOLTAGE (V) VDD/VSS = ±15V VLOGIC = +5V VA = VDD VB = VSS 0.6 0.5 0.4 0.3 0.2 0.1 07674-031 0.4 0.2 0 –0.2 –0.4 –0.6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DIGITAL INPUT VOLTAGE (V) 4.0 4.5 5.0 TIME (µs) Figure 30. Supply Current ILOGIC vs. Digital Input Voltage 35 30 25 VOLTAGE (V) 20 15 10 5 0 –5 0.2 0.7 1.3 1.9 2.5 3.1 3.6 4.2 4.8 5.4 6.0 6.5 7.1 7.7 8.3 –1.0 –0.4 8.9 TIME (µs) VWB, CODE: FULL SCALE, NORMAL MODE VWB, CODE: FULL SCALE, R-PERF MODE 6 5 4 VWB, CODE: HALF-SCALE, NORMAL MODE Figure 33. Maximum Transition Glitch VDD/VSS = ±15V VLOGIC = +5V VOLTAGE (V) 3 2 1 0 –1 VWB, CODE: HALF-SCALE, R-PERF MODE SYNC VDD/VSS = 30V/0V VLOGIC = 5V VA = VDD VB = VSS 07674-033 TIME (ms) Figure 31. Large-Signal Settling Time, Code from Zero Scale to Full Scale 35 30 Figure 34. VEXT_CAP Waveform While Reading Fuse or Calibration 8 VDD/VSS = ±15V VLOGIC = +5V SUPPLY CURRENT I DD (mA) 6 25 VOLTAGE (V) 20 15 10 5 3 2 0 0 07674-034 07674-037 0.4 1.6 2.8 4.0 5.2 6.4 7.6 –2.0 –0.8 8.8 10.0 11.2 12.4 13.6 14.8 16.0 –0.2 0 0.2 0.4 0.6 TIME (ms) 0.8 1.0 1.2 TIME (ms) Figure 32. IDD Waveform While Blowing/Reading Fuse Figure 35. VEXT_CAP Waveform While Writing Fuse Rev. 0 | Page 15 of 28 17.2 –5 –0.4 –2 07674-036 0.2 0.8 1.4 2.0 2.6 3.2 3.8 4.4 5.0 5.6 6.2 6.8 7.4 8.0 –1.0 –0.4 8.6 07674-035 –0.4 –0.2 –0.1 0.1 0.2 0.4 0.5 0.7 0.8 1.0 1.1 1.3 1.4 1.6 1.7 1.9 2.0 2.2 2.3 2.5 2.6 2.8 2.9 3.1 3.2 3.4 3.6 0 –0.8 AD5291/AD5292 75.0 VDD/VSS = ±15V 300 62.5 NUMBER OF CODES (AD5291) 250 NUMBER OF CODES (AD5292) 50.0 200 37.5 150 25.0 100 12.5 50 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) Figure 36. Code Range > 1% R-Tolerance Error vs. Temperature Rev. 0 | Page 16 of 28 07674-056 0 –40 –30 –20 –10 0 0 AD5291/AD5292 TEST CIRCUITS Figure 37 to Figure 42 define the test conditions used in the Specifications section. NC DUT A W B VMS 07674-041 IW VDD V+ ~ VA A B V+ = VDD ± 10% ΔVMS PSRR (dB) = 20 log ΔV DD ΔVMS% PSS (%/%) = ΔVDD% W VMS NC = NO CONNECT Figure 37. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) DUT A V+ B W 07674-042 Figure 40. Power Supply Sensitivity (PSS, PSRR) +15V W DUT B 2.5V OP42 VOUT 07674-047 A V+ = VDD 1LSB = V+/2N VIN OFFSET GND VMS –15V Figure 38. Potentiometer Divider Nonlinearity Error (INL, DNL) +15V NC Figure 41. Gain vs. Frequency –15V GND GND VDD DUT VSS GND A W B GND 07674-048 DUT W B IWB VSS TO VDD CODE = 0x00 + – RWB= RW = 0.1V 0.1V IWB RWB 2 ICM +15V –15V 07674-043 A = NC NC +15V GND –15V NC = NO CONNECT Figure 39. Wiper Resistance Figure 42. Common-Mode Leakage Current Rev. 0 | Page 17 of 28 07674-044 AD5291/AD5292 THEORY OF OPERATION The AD5291/AD5292 , members of the Analog Devices, Inc., DigiPOT+ family of potentiometers are designed to operate as true variable resistors for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The patented ±1% resistor tolerance feature helps to minimize the total RDAC resistance error, which reduces the overall system error by offering better absolute matching and improved open-loop performance. The digital potentiometer wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The RDAC register can be programmed with any position setting using the standard SPI interface by loading the 16-bit data-word. Once a desirable position is found, this value can be stored in a 20-TP memory register. Thereafter, the wiper position is always restored to that position for subsequent power-up. The storing of 20-TP data takes approximately 6 ms; during this time, the shift register is locked, preventing any changes from taking place. The RDY pin identifies the completion of this 20-TP storage. AD5291, the lower two RDAC data bits are don’t cares if the RDAC register is read from or written to. Data is loaded MSB first (Bit DB15). The four control bits determine the function of the software command (see Table 9). Figure 3 shows a timing diagram of a typical AD5291/AD5292 write sequence. The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the DIN pin. When SYNC returns high, the serial data-word is decoded according to the commands in Table 9. The command bits (Cx) control the operation of the digital potentiometer. The data bits (Dx) are the values that are loaded into the decoded register. The AD5291/AD5292 have an internal counter that counts a multiple of 16 bits (a frame) for proper operation. For example, the AD5291/AD5292 work with a 32-bit word, but do not work properly with a 31-bit or 33-bit word. The AD5291/AD5292 do not require a continuous SCLK, when SYNC is high, and all serial interface pins should be operated at close to the VLOGIC supply rails to minimize power consumption in the digital input buffers. SERIAL DATA INTERFACE The AD5291/AD5292 contain a serial interface (SYNC, SCLK, DIN and SDO) that is compatible with SPI interface standards, as well as most DSPs. The parts allow writing of data via the serial interface to every register. RDAC REGISTER The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with all 0s, the wiper is connected to Terminal B of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. SHIFT REGISTER The AD5291/AD5292 shift register is 16 bits wide (see Figure 2). The 16-bit input word consists of two unused bits (set to 0), followed by four control bits, and 10 RDAC data bits. For the Table 9. Command Operation Truth Table Command 0 1 2 3 4 5 Command Bits [DB13:DB10] C3 C2 C1 C0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 1 D9 X D9 X X X X D8 X D8 X X X X D7 X D7 X X X X Data Bits [DB9:DB0]1 D6 D5 D4 D3 X X X X D6 D5 D4 D3 X X X X X X X X X X X X D4 X X D3 D2 X D2 X X X D2 D1 X D12 X X X D1 D0 X D02 X X X D0 6 7 8 0 0 1 1 1 0 1 1 0 0 1 0 X X X X X X X X X X X X X X X X X X D3 X X D2 X X D1 X X D0 X D0 Operation NOP command: do nothing. Write contents of serial data to RDAC. Read RDAC wiper setting from the SDO output in the next frame. Store wiper setting: store RDAC setting to 20-TP memory. Reset: refresh RDAC with 20-TP stored value. Read contents of 20-TP memory, or status of 20-TP memory, from the SDO output in the next frame. Write contents of serial data to control register. Read control register from the SDO output in the next frame. Software shutdown. D0 = 0 (normal mode). D0 = 1 (device placed in shutdown mode). 1 2 X = don’t care. In the AD5291, this bit is a don’t care. Rev. 0 | Page 18 of 28 AD5291/AD5292 20-TP MEMORY Once a desirable wiper position is found, the contents of the RDAC register can be saved into a 20-TP memory register (see Table 10). Thereafter, the wiper position is always set at that position for any future on-off-on power supply sequence. The AD5291/AD5292 have an array of 20 one-time programmable (OTP) memory registers. When the desired word is programmed to 20-TP memory, the device automatically verifies that the program command was successful. The verification process includes margin testing. Bit C3 of the control register can be polled to verify that the fuse program command was successful. Programming data to 20-TP memory consumes approximately 25 mA for 550 μs, and takes approximately 8 ms to complete. During this time, the shift register is locked, preventing any changes from taking place. The RDY pin can be used to monitor the completion of the 20-TP memory program and for verification. No change in supply voltage is required to program the 20-TP memory. However, a 1 μF capacitor on the EXT_CAP pin is required (see Figure 47). Prior to 20-TP activation, the AD5291/ AD5292 preset to midscale on power-up. Table 10. Write and Read to RDAC and 20-TP Memory DIN 0x1803 0x0500 0x0800 0x0C00 0x1C00 0x0000 SDO 0xXXXX 0x1803 0x0500 0x0100 0x0C00 0x000X Action Enable update of wiper position and 20-TP memory contents through digital interface. Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position. Prepare data read from the RDAC register. Stores RDAC register content into 20-TP memory. The 16-bit word appears out of SDO, where the last 10 bits contain the contents of the RDAC register (0x100). Prepare data read from the control register. NOP Instruction 0 sends 16-bit word out of SDO, where the last four bits contain the contents of the control register. If Bit C3 = 1, the fuse program command is successful. WRITE PROTECTION On power-up, the shift register write commands for both the RDAC register and the 20-TP memory register are disabled. The RDAC write protect bit, C1 of the control register (see Table 11 and Table 12), is set to 0 by default. This disables any change of the RDAC register content regardless of the software commands, except that the RDAC register can be refreshed from the 20-TP memory using the software reset command (Command 4) or through hardware by the RESET pin. To enable programming of the variable resistor wiper position (programming the RDAC register), the write protect bit, C1 of the control register, must first be programmed. This is accomplished by loading the shift register with Command 6 (see Table 9). To enable programming of the 20-TP memory block bit, C0 of the control register (set to 0 by default) must first be set to 1. Table 11. Control Register Bit Map1 DB9 X 1 DB8 X DB7 X DB6 X DB5 X DB4 X DB3 C3 DB2 C2 DB1 C1 DB0 C0 X = don’t care. Table 12. Control Register Description Bit Name C0 Description 20-TP program enable 0 = 20-TP program disabled (default) 1 = enable device for 20-TP program RDAC register write protect 0 = wiper position frozen to value in memory (default)1 1 = allow update of wiper position through digital Interface Calibration enable 0 = resistor performance mode enabled (default) 1 = normal mode enabled 20-TP memory program success 0 = fuse program command unsuccessful (default) 1 = fuse program command successful C1 C2 C3 1 Wiper position frozen to value last programmed in 20-TP memory. Wiper is frozen to midscale if 20-TP memory has not been previously programmed. Rev. 0 | Page 19 of 28 AD5291/AD5292 BASIC OPERATION The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the shift register with Command 1 (see Table 9) and the desired wiper position data. When the desired wiper position is determined, the user can load the shift register with Command 3 (see Table 9), which stores the wiper position data in the 20-TP memory register. After 6 ms, the wiper position is permanently stored in the 20-TP memory. The RDY pin can be used to monitor the completion of this 20-TP program. Table 10 provides a programming example, listing the sequence of serial data input (DIN) words with the serial data output appearing at the SDO pin in hexadecimal format. Data from the selected memory location are clocked out of the SDO pin during the next SPI operation, where the last 10 bits contain the contents of the specified memory location. It is also possible to calculate the address of the most recently programmed memory location by reading back the contents of read-only Memory Address 0x14 and Memory Address 0x15 using Command 5. The data bytes read back from Memory Address 0x014 and Memory Address 0x015 are thermometer encoded versions of the address of the last programmed memory location. For the example outlined in Table 13, the address of the last programmed location is calculated as (Number of Bits = 1 in Memory Address 0x14) + (Number of Bits = 1 in Memory Address 0x15) − 1 = 10 + 8 − 1 = 17 (0x10) If no memory location has been programmed, then the address generated is −1. 20-TP READBACK AND SPARE MEMORY STATUS It is possible to read back the contents of any of the 20-TP memory registers through SDO by using Command 5 (see Table 9). The lower five LSB bits (D0 to D4) of the data byte select which memory location is to be read back (see Table 14). Table 13. Example 20-TP Memory Readback DIN 0x1414 0x1415 0x0000 0x1410 0x0000 SDO 0xXXXX 0x03FF 0x00FF 0x0000 0xXXXX Action Prepares data read from Memory Address 0x14. Prepares data read from Memory Address 0x15. Sends 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Address 0x14. NOP Command 0 sends 16-bit word out of SDO, where last 10-bits contain the contents of Memory Address 0x15. Prepares data read from memory location 0x10. NOP Instruction 0 sends 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Address 0x10 (17). Table 14. Memory Map of Command 5 D9 X X X X X … X X X X X 1 2 D8 X X X X X … X X X X X Data Bits [DB9:DB0]1 D7 D6 D5 D4 D3 X X X 0 0 X X X 0 0 X X X 0 0 X X X 0 0 X X X 0 0 …………… X X X 0 1 X X X 0 1 X X X 1 0 X X X 1 0 X X X 1 0 D2 0 0 0 0 1 … 0 1 0 1 1 D1 0 0 1 1 0 … 0 1 1 0 0 D0 0 1 0 1 0 … 1 0 1 0 1 Register Contents 1st programmed wiper location (0x00) 2nd programmed wiper location (0x01) 3rd programmed wiper location (0x02) 4th programmed wiper location (0x03) 5th programmed wiper location (0x04) … 10th programmed wiper location (0x09) 15th programmed wiper location (0x0E) 20th programmed wiper location (0x13) Programmed memory status (thermometer encoded)2 (0x14) Programmed memory status (thermometer encoded)2 (0x15) X = don’t care. Allows the user to calculate the remaining spare memory locations. Rev. 0 | Page 20 of 28 AD5291/AD5292 SHUTDOWN MODE The AD5291/AD5292 can be placed in shutdown mode by executing the software shutdown command, Command 8 (see Table 9), and setting the LSB, D0, to 1. This feature places the RDAC in a special state in which Terminal A is open-circuited and Wiper W is connected to Terminal B. The contents of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 9 are supported while in shutdown mode. Execute Command 8 (see Table 9) and set the LSB, D0, to 0 to exit shutdown mode. AD5291/ AD5292 MOSI MICROCONTROLLER SCLK SS DIN U1 SDO VLOGIC RP 2.2kΩ AD5291/ AD5292 DIN U2 SDO SYNC SCLK SYNC SCLK 07674-050 Figure 43. Daisy-Chain Configuration Using SDO RDAC ARCHITECTURE To achieve optimum cost performance, Analog Devices has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5291/AD5292 employ a three-stage segmentation approach, as shown in Figure 44. The AD5291/AD5292 wiper switch is designed with the transmission gate CMOS topology and with the gate voltages derived from VDD and VSS. A RESISTOR PERFORMANCE MODE This mode activates a new, patented 1% end-to-end resistor tolerance that ensures a ±1% resistor tolerance on each code, that is, code = half scale, RWB = 10 kΩ ± 100 Ω. See Table 2 (AD5291) or Table 4 (AD5292) to check which codes achieve ±1% resistor tolerance. The resistor performance mode is activated by programming Bit C2 of the control register (see Table 11 and Table 12). The typical settling time is shown in Figure 31. RL RESET A low-to-high transition of the hardware RESET pin loads the RDAC register with the contents of the most recently programmed 20-TP memory location. The AD5291/AD5292 can also be reset through software by executing Command 4 (see Table 9). If no 20-TP memory location is programmed, then the RDAC register loads with midscale upon reset. The control register is restored with default bit settings; see Table 12. RL RM RM RW SW W 8-/10-BIT ADDRESS DECODER RL RM RL RW RM DAISY-CHAIN OPERATION The shift register serial data output pin (SDO) serves two purposes. It can be used to read the contents of the wiper setting or the internal memory values using Command 2 and Command 5, respectively (see Table 9) or it can be used to daisy-chain multiple devices. The remaining instructions are valid for daisy-chaining multiple devices in simultaneous operations. Daisy-chaining minimizes the number of port pins required from the controlling IC (see Figure 43). The SDO pin contains an open-drain N-Channel FET that requires a pull-up resistor, if this function is used. As shown in Figure 43, users must tie the SDO pin of one package to the DIN pin of the next package. Users may need to increase the clock period, because the pullup resistor and the capacitive loading at the SDO/DIN interface may require additional time delay between subsequent devices. When two AD5291/AD5292 devices are daisy-chained, 32 bits of data are required. The first 16 bits go to U2, and the second 16 bits go to U1. Hold the SYNC pin low until all 32 bits are clocked into their respective shift registers. The SYNC pin is then pulled high to complete the operation. B Figure 44. AD5291/AD5292 Simplified RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation—1% Resistor Tolerance The AD5291/AD5292 operate in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be left floating or tied to the W terminal, as shown in Figure 45. A W B B A W B A W 07674-052 Figure 45. Rheostat Mode Configuration The nominal resistance between Terminal A and Terminal B, RAB, is available in 20 kΩ and has 256 or 1024 tap points accessed by the wiper terminal. The 8-/10-bit data in the RDAC latch is decoded to select one of the 256/1024 possible wiper Rev. 0 | Page 21 of 28 07674-051 AD5291/AD5292 settings. The AD5291/AD5292 contain an internal ±1% resistor performance mode that can be disabled or enabled (this is enabled by default), by programming Bit C2 of the control register (see Table 11 and Table 12). The digitally programmed output resistance between the W terminal and the A terminal, RWA, and between the W terminal and B terminal, RWB, is internally calibrated to give a maximum of ±1% absolute resistance error across a wide code range. As a result, the general equations for determining the digitally programmed output resistance between the W terminal and B terminal are AD5291: of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity. VIN A W B VOUT 07674-053 Figure 46. Potentiometer Mode Configuration RWB (D)  AD5292: RWB (D )  D  R AB 256 D  R AB 1024 (1) (2) If ignoring the effect of the wiper resistance for simplicity, connecting the A terminal to 30 V and the B terminal to ground produces an output voltage at the Wiper W to Terminal B ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is equal to the voltage applied across Terminal A and Terminal B, divided by the 256/1024 positions of the potentiometer divider. The general equations defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B are AD5291: VW (D)  AD5292: VW (D)  1024  D D VA   VB 1024 1024 where: D is the decimal equivalent of the binary code loaded in the 8-/10-bit RDAC register. RAB is the end-to-end resistance. Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA is also calibrated to give a maximum of 1% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equations for this operation are AD5291: RWA (D )  AD5292: RWA (D)  1024  D  R AB 1024 (4) 256  D  R AB 256 (3) D 256  D  VA   VB 256 256 (5) (6) If using the AD5291/AD5292 in voltage divider mode as in Figure 46, then the ±1% resistor tolerance calibration feature reduces the error when matching with discrete resistors. However, it is recommended to disable the internal ±1% resistor tolerance calibration feature by programming Bit C2 of the control register (see Table 11 and Table 12) to optimize wiper position update rate. In this configuration, the RDAC is ratiometric and resistor tolerance error does not affect performance. Operation of the digital potentiometer in the voltage divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RWA and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. where: D is the decimal equivalent of the binary code loaded in the 8-/10-bit RDAC register. RAB is the end-to-end resistance. In the zero-scale condition, a finite total wiper resistance of 120 Ω is present. Regardless of which setting the part is operating in, take care to limit the current between Terminal A and Terminal B, between Terminal W and Terminal A, and between Terminal W and Terminal B, to the maximum continuous current of ±3 mA or to the pulse current specified in Table 6. Otherwise, degradation or possible destruction of the internal resistors may occur. EXT_CAP CAPACITOR A 1 μF capacitor to GND must be connected to the EXT_CAP pin (see Figure 47) on power-up and throughout the operation of the AD5291/AD5292. AD5291/ AD5292 EXT_CAP C1 1µF OTP MEMORY BLOCK PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at the wiper to B and at the wiper to A that is proportional to the input voltage at A to B, as shown in Figure 46. Unlike the polarity GND 07674-054 Figure 47. Hardware Setup for EXT_CAP Pin Rev. 0 | Page 22 of 28 AD5291/AD5292 TERMINAL VOLTAGE OPERATING RANGE The positive VDD and negative VSS power supplies of the AD5291/AD5292 define the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on Terminal A, Terminal B, and Terminal W that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 48). VDD control signals to the AD5291/AD5292 must be referenced to the device ground pin (GND), and satisfy the logic level defined in the Specifications section. Power-Up Sequence To ensure that the AD5291/AD5292 power up correctly, a 1 μF capacitor must be connected to the EXT_CAP pin. Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 48), it is important to power VDD and VSS first before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forwardbiased such that VDD and VSS are powered up unintentionally. The ideal power-up sequence is GND, VSS, VLOGIC and VDD, the digital inputs, and then VA, VB, and VW. The order of powering up VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD, VSS, and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, after VLOGIC is powered, the power-on preset activates, restoring the 20-TP memory value to the RDAC register. A W B VSS Figure 48. Maximum Terminal Voltages Set by VDD and V SS The ground pin of the AD5291/AD5292 device is primarily used as a digital ground reference. To minimize the digital ground bounce, the AD5291/AD5292 ground terminal should be joined remotely to the common ground. The digital input 07674-055 Rev. 0 | Page 23 of 28 AD5291/AD5292 APPLICATIONS INFORMATION HIGH VOLTAGE DAC The AD5292 can be configured as a high voltage DAC, with output voltage as high as 33 V. The circuit is shown in Figure 49. The output is VOUT (D)   D  1.2 V  1024    R2  1    R 1    HIGH ACCURACY DAC It is possible to configure the AD5292 as a high accuracy DAC by optimizing the resolution of the device over a specific reduced voltage range. This is achieved by placing external resistors on either side of the RDAC, as shown in Figure 51. The improved ±1% resistor tolerance specification greatly reduces error associated with matching to discrete resistors. VOUT (D )  R3  (D 1024  RAB ) V DD R1  ((1024  D )1024)  RAB  R3 VDD (7) where D is the decimal code from 0 to 1023. VDD RBIAS VDD U1A V+ D1 U2 (8) ADR512 AD8512 V– AD5292 20kΩ B U1B VOUT U1 R1 VDD U2 ±1% V+ AD5292 R2 20kΩ B 07674-153 AD8512 OP1177 V– VOUT 07674-154 R1 R2 R3 Figure 49. High Voltage DAC Figure 51. Optimizing Resolution PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT For applications that require high current adjustments such as a laser diode or a tunable laser, a boosted voltage source can be considered (see Figure 50). U3 2N7002 VIN VOUT CC W U2 RBIAS IL VARIABLE GAIN INSTRUMENTATION AMPLIFIER The AD8221 in conjunction with the AD5292 and the ADG1207, as shown in Figure 52, make an excellent instrumentation amplifier for use in data acquisition systems. The data acquisition system’s low distortion and low noise enable it to condition signals in front of a variety of ADCs. ADG1207 +VIN1 +VIN4 –VIN1 VDD AD5292 U1 A B OP184 SIGNAL LD AD5292 AD8221 VOUT 07674-155 Figure 50. Programmable Boosted Voltage Source VSS In this circuit, the inverting input of the op amp forces VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-channel FET (U3). The N-Channel FET power handling must be adequate to dissipate (VIN − VOUT) × IL power. This circuit can source a maximum of 100 mA with a 33 V supply. Figure 52. Data Acquisition System The gain can be calculated by using Equation 9. G(D)  1  D 1024  R 49.4 kΩ 07674-156 –VIN4 (9) AB Rev. 0 | Page 24 of 28 AD5291/AD5292 AUDIO VOLUME CONTROL The excellent THD performance and high voltage capability make the AD5291/AD5292 ideal for a digital volume control as an audio attenuator or gain amplifier. A typical problem in these systems is that a large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal causing an audible zipper noise. To prevent this, a zero-crossing window detector can be inserted to the SYNC line to delay the device update until the audio signal crosses the window. Because the input signal can operate on top of any dc level rather than absolute 0 V level, zero-crossing in this case means the signal is ac-coupled, and the dc offset level is the signal zero reference point. The configuration to reduce zipper noise is shown in Figure 53, and the results of using this configuration are shown in Figure 54. The input is ac-coupled by C1 and attenuated down before feeding into the window comparator formed by U2, U3, and U4B. U6 is used to establish the signal zero reference. The upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 V and 2.497 V (or 0.005 V window) in this example. This output is AND’ed with the SYNC signal such that the AD5293 updates whenever the signal crosses the window. To avoid a constant update of the device, the SYNC signal should be programmed as two pulses, rather than as one. In Figure 54, the lower trace shows that the volume level changes from a quarter-scale to full-scale when a signal change occurs near the zero-crossing window. C1 VIN 1µF 5V R1 100kΩ +5V U2 VCC ADCMP371 GND U4B +5V R5 10kΩ U3 VCC ADCMP371 GND R3 100kΩ 4 5 +15V C3 0.1µF C2 0.1µF –15V 61 U1 VDD AD5292 A R4 90kΩ R2 200Ω +15V VSS W 20kΩ SYNC SCLK DIN B GND 07674-157 7408 U4A U5 V+ V– VOUT 7408 2 SCLK DIN 5V U6 V+ AD8541 V– –15V SYNC Figure 53. Audio Volume Control with Zipper Noise Reduction 1 2 CHANNEL 1 FREQ = 20.25kHz 1.03V p-p 07674-158 Figure 54. Zipper Noise Detector Rev. 0 | Page 25 of 28 AD5291/AD5292 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 1 7 6.40 BSC PIN 1 0.65 BSC 1.05 1.00 0.80 0.15 0.05 COPLANARITY 0.10 1.20 MAX 0.20 0.09 8° 0° 0.30 0.19 SEATING PLANE 0.75 0.60 0.45 061908-A COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 55. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Model AD5291BRUZ-201 AD5291BRUZ-20-RL71 AD5292BRUZ-201 AD5292BRUZ-20-RL71 1 RAB (kΩ) 20 20 20 20 Resolution 256 256 1,024 1,024 Memory 20-TP 20-TP 20-TP 20-TP Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Package Option RU-14 RU-14 RU-14 RU-14 Z = RoHS Compliant Part. Rev. 0 | Page 26 of 28 AD5291/AD5292 NOTES Rev. 0 | Page 27 of 28 AD5291/AD5292 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07674-0-5/09(0) Rev. 0 | Page 28 of 28