AD5293BRUZ-100-RL7

Single-Channel, 1024-Position, 1% R-Tolerance Digital Potentiometer AD5293 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Single-channel, 1024-position resolution 20 kΩ, 50 kΩ, and 100 kΩ nominal resistance Calibrated 1% nominal resistor tolerance (resistor performance mode) Rheostat mode temperature coefficient: 35 ppm/°C Voltage divider temperature coefficient: 5 ppm/°C Single-supply operation: 9 V to 33 V Dual-supply operation: ±9 V to ±16.5 V SPI-compatible serial interface Wiper setting readback VDD RESET POWER-ON RESET AD5293 VLOGIC 10 SCLK SYNC RDAC REGISTER A SERIAL INTERFACE W DIN B SDO APPLICATIONS VSS EXT_CAP GND 07675-001 RDY Mechanical potentiometer replacement Instrumentation: gain and offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, and time constants Programmable power supply Low resolution DAC replacements Sensor calibration Figure 1. GENERAL DESCRIPTION The AD5293 is a single-channel, 1024-position digital potentiometer (in this data sheet, the terms digital potentiometer and RDAC are used interchangeably) with a 10 kHz Frequency ≤ 10 kHz Operating Temperature Range Maximum Junction Temperature (TJ max) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating −0.3 V to +35 V +0.3 V to −25 V −0.3 V to +7 V 35 V VSS − 0.3 V, VDD + 0.3 V −0.3 V to VLOGIC +0.3 V −0.3 V to +7 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type 14-Lead TSSOP ±3 mA ±2 mA 1 MCC2/d3 MCC2/√d3 −40°C to +105°C 150°C −65°C to +150°C θJA 931 θJC 20 Unit °C/W JEDEC 2S2P test board, still air (from 0 m/sec to 1 m/sec of air flow). ESD CAUTION 260°C 20 sec to 40 sec (TJ max − TA)/θJA Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Maximum continuous current. 3 Pulse duty factor. 1 Rev. E | Page 9 of 24 AD5293 Data Sheet RESET 1 14 RDY VSS 2 13 SDO AD5293 12 TOP VIEW Not to Scale 11 SYNC SCLK A 3 W 4 B 5 10 DIN VDD 6 9 GND EXT_CAP 7 8 VLOGIC 07675-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 Mnemonic RESET 2 VSS 3 4 5 6 7 8 9 10 A W B VDD EXT_CAP VLOGIC GND DIN 11 SCLK 12 SYNC 13 SDO 14 RDY Description Hardware Reset Pin. Sets the RDAC register to midscale. RESET is activated at the logic high transition. Tie RESET to VLOGIC if not used. Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC. VSS ≤ VA ≤ VDD. Wiper Terminal W of RDAC. VSS ≤ VW ≤ VDD. Terminal B of RDAC. VSS ≤ VB ≤ VDD. Positive Power Supply. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors. Connect a 1 µF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V. Logic Power Supply, 2.7 V to 5.5 V. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors. Ground Pin, Logic Ground Reference. Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register, and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC, following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the serial register in daisy-chain mode or in readback mode. Ready Pin. This active-high, open-drain output identifies the completion of a write or read operation to or from the RDAC register. Rev. E | Page 10 of 24 Data Sheet AD5293 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 0.6 0.4 0.4 0.2 0.2 INL (LSB) 0.6 0 –0.2 –0.6 –0.6 –0.8 RAB = 20kΩ 128 256 384 512 640 768 896 1023 CODE (Decimal) –1.0 0 0.4 0.4 0.3 0.3 DNL (LSB) 768 896 1023 0.2 0.1 0.2 0.1 0 0 –0.1 –0.1 –0.2 20kΩ 50kΩ 100kΩ –0.2 +105°C –0.3 256 384 512 640 768 896 1023 CODE (Decimal) –0.3 07675-007 +25°C –40°C 0 128 256 384 512 640 768 896 1023 CODE (Decimal) Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature 1.0 RAB = 20kΩ 0.8 0.6 0.6 0.4 0.4 INL (LSB) 0.8 0.2 20kΩ 50kΩ 100kΩ TEMPERATURE = 25°C 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 0 128 256 384 512 640 768 896 1023 CODE (Decimal) 07675-010 +105°C +25°C –40°C Figure 8. R-INL in Normal Mode vs. Code vs. Temperature –0.6 0 128 256 384 512 640 768 896 1023 CODE (Decimal) Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance Rev. E | Page 11 of 24 07675-216 DNL (LSB) 640 TEMPERATURE = 2 5°C 0.5 1.0 512 0.6 0.5 128 384 Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance RAB = 20kΩ 0 256 CODE (Decimal) Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature 0.6 128 07675-211 0 INL (LSB) –0.2 –0.4 –1.0 TEMPERATURE = 25°C 0 –0.4 –0.8 20kΩ 50kΩ 100kΩ 0.8 07675-106 INL (LSB) 1.0 –40°C +25°C +105°C 07675-215 1.0 AD5293 0.15 RAB = 20kΩ 0.10 0.10 0.05 0.05 DNL (LSB) 0 –0.05 –0.05 –0.10 –0.15 –0.15 128 256 384 512 640 768 896 1023 CODE (Decimal) –0.20 0 640 768 896 1023 TEMPERATURE = 25°C 0.5 0.2 INL (LSB) 0.6 0 0 –0.5 –0.2 –1.0 –0.6 384 512 640 768 896 1023 CODE (Decimal) –0.8 07675-014 –1.5 256 20kΩ 50kΩ 100kΩ +105°C +25°C –40°C 0 128 256 384 512 640 768 896 1023 CODE (Decimal) Figure 13. INL in R-Perf Mode vs. Code vs. Temperature 0.6 512 0.8 1.0 128 384 Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance RAB = 20kΩ 0 256 CODE (Decimal) Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature 1.5 128 07675-207 0 07675-011 –0.20 07675-213 +105°C +25°C –40°C INL (LSB) TEMPERATURE = 25°C 0 –0.10 Figure 16. INL in R-Perf Mode vs. Code vs. Nominal Resistance 0.6 RAB = 20kΩ TEMPERATURE = 2 5°C 0.5 0.4 0.4 0.3 0.3 DNL (LSB) 0.5 0.2 0.1 0.2 0.1 0 0 –0.1 –0.1 +105°C +25°C –40°C 0 128 256 384 512 640 768 20kΩ 50kΩ 100kΩ –0.2 –0.2 896 CODE (Decimal) 1023 07675-015 DNL (LSB) 20kΩ 50kΩ 100kΩ –0.3 0 128 256 384 512 640 768 896 CODE (Decimal) Figure 14. DNL in R-Perf Mode vs. Code vs. Temperature Figure 17. DNL in R-Perf Mode vs. Code vs. Nominal Resistance Rev. E | Page 12 of 24 1023 07675-203 DNL (LSB) 0.15 Data Sheet Data Sheet 0.6 0.4 0.4 0.2 0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 128 256 384 512 640 768 896 1023 CODE (Decimal) –0.8 07675-018 0 0 512 640 768 896 1023 20kΩ 50kΩ 100kΩ 0.04 0 DNL (LSB) –0.05 –0.04 –0.10 –0.08 –0.15 –0.12 RAB = 20kΩ 128 256 384 512 640 768 896 1023 CODE (Decimal) TEMPERATURE = 25°C –0.16 0 384 512 640 768 896 1023 Figure 22. DNL in Normal Mode vs. Code vs. Nominal Resistance 0.20 VDD/VSS = ±15V VLOGIC = +5V 400 256 CODE (Decimal) Figure 19. DNL in Normal Mode vs. Code vs. Temperature 450 128 07675-205 0 07675-019 –0.20 VDD = ±15V 0.18 SUPPLY CURRENT ILOGIC (mA) 350 ILOGIC 300 250 200 150 100 IDD 50 0 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) 07675-022 ISS Figure 20. Supply Current vs. Temperature 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DIGITAL INPUT VOLTAGE (V) 4.0 4.5 Figure 23. Supply Current, ILOGIC, vs. Digital Input Voltage. Rev. E | Page 13 of 24 5.0 07675-057 DNL (LSB) 384 0.08 0 SUPPLY CURRENT (nA) 256 Figure 21. INL in Normal Mode vs. Code vs. Nominal Resistance –40°C +25°C +105°C 0.05 128 CODE (Decimal) Figure 18. INL in Normal Mode vs. Code vs. Temperature 0.10 TEMPERATURE = 25°C 0 –0.2 –0.8 20kΩ 50kΩ 100kΩ 0.6 INL (LSB) INL (LSB) 0.8 –40°C +25°C +105°C RAB = 20kΩ 07675-209 0.8 AD5293 AD5293 Data Sheet 700 20kΩ 50kΩ 100kΩ 600 500 400 300 200 100 0 0 256 512 CODE (Decimal) 768 1023 VDD = 30V VSS= 0V 20kΩ 50kΩ 100kΩ 600 500 400 300 200 100 0 256 0 Figure 24. Rheostat Mode Tempco ΔRWB/ΔT vs. Code 512 CODE (Decimal) 768 1023 07675-024 POTENTIOMETER MODE TEMPCO (ppm/°C) VDD = 30V, VSS= 0V 07675-023 RHEOSTAT MODE TEMPCO (ppm/°C) 700 Figure 27. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code 0 0 0x200 –5 0x200 –10 0x100 –10 0x100 0x080 –20 0x040 0x080 –20 GAIN (dB) GAIN (dB) –15 0x040 –25 0x020 –30 –30 0x010 –40 0x008 0x010 –35 0x020 0x004 –50 0x008 0x002 –40 –60 0x001 0x004 –50 10 0x001 100 1k 10k 100k 1M FREQUENCY (Hz) –70 10 10k 100k 1M Figure 28. 100 kΩ Gain vs. Frequency vs. Code 0 0 0x200 –10 0x100 –10 0x080 –20 100kΩ 20kΩ 50kΩ PSRR (dB) 0x040 0x020 –30 0x010 –30 –40 0x008 –50 0x004 –50 –60 0x002 0x001 –60 10 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 26. 50 kΩ Gain vs. Frequency vs. Code –70 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 29. Power Supply Rejection Ratio (PSRR) vs. Frequency Rev. E | Page 14 of 24 07675-026 –40 07674-200 GAIN (dB) 1k FREQUENCY (Hz) Figure 25. 20 kΩ Gain vs. Frequency vs. Code –20 100 07675-201 0x002 07675-025 –45 Data Sheet 0 0 VDD/VSS = ±15V CODE = HALF SCALE VIN = 1V rms Noise BW = 22kHz 20kΩ 50kΩ 100kΩ –15 –30 VDD/VSS = ±15V, CODE = HALF SCALE fIN = 1kHz NOISE BW = 22kHz 20kΩ 50kΩ 100kΩ –20 –40 –45 THD + N (dB) THD + N (dB) AD5293 –60 –75 –60 –80 –100 –90 100k –140 0.001 FREQUENCY (Hz) 20k – 0pF 20k – 75pF 20k – 150pF 20k – 250pF 50k – 0pF 50k – 75pF Figure 33. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude 800,000 8 50k – 150pF 50k – 250pF 100k – 0pF 100k – 75pF 100k – 150pF 100k – 250pF BANDWIDTH (Hz) 700,000 600,000 500,000 400,000 300,000 200,000 6 5 4 8 16 32 64 CODE (Decimal) 128 07675-222 0 512 256 20kΩ 3 100,000 0 VDD/VSS = 30V/0V VA = VDD VB = VSS 7 THEORETICAL IWB_MAX (mA) 900,000 2 50kΩ 1 100kΩ 0 0 Figure 31. Maximum Bandwidth vs. Code vs. Net Capacitance 35 512 CODE (Decimal) VDD/VSS = 30V/0V VLOGIC = 5V VA = VDD VB = VSS 25 24 16 VOLTAGE (μV) VWB, CODE: FULL SCALE, R-PERF MODE 15 10 SYNC 5 20kΩ 50kΩ 100kΩ 20kΩ 50kΩ 100kΩ 15 14 12 13 11 9 10 8 7 6 5 4 3 2 1 0 –1 –2 –5 8 0 –8 –16 –24 07675-058 VWB, CODE: HALF-SCALE, NORMAL MODE VWB, CODE: HALF-SCALE, R-PERF MODE TIME (µs) 1023 VDD/VSS = ±15V VA = VDD VB = VSS CODE = HALF CODE 32 0 768 40 30 VOLTAGE (V) 256 Figure 34. Theoretical Maximum Current vs. Code VWB, CODE: FULL SCALE, NORMAL MODE 20 10 AMPLITUDE (V rms) Figure 30. Total Harmonic Distortion + Noise (THD + N) vs. Frequency 1,000,000 1 0.1 0.01 07675-029 10k Figure 32. Large Signal Settling Time, Code from Zero Scale to Full Scale Rev. E | Page 15 of 24 –32 –40 –0.5 0 5 10 15 20 25 TIME (µs) 30 Figure 35. Digital Feedthrough 35 40 45 07675-221 1k 07675-027 –120 100 07675-220 –120 –105 AD5293 Data Sheet 80 1.2 VDD/VSS = ±15V VLOGIC = +5V VA = VDD VB = VSS 0.8 20kΩ 50kΩ 100kΩ 0.6 VOLTAGE (V) 70 NUMBER OF CODES (AD5293) 1.0 0.4 0.2 0 –0.2 –0.4 20kΩ VA = VDD VB = VSS TEMPERATURE = 25°C 50kΩ 100kΩ 60 50 40 30 20 10 –2 0 2 4 6 8 10 12 14 16 TIME (µs) 0 21 07675-035 –0.8 VDD/VSS = ±15V 20kΩ 50kΩ 100kΩ 200 150 100 50 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) 07675-056 NUMBER OF CODES (AD5293) 250 30 VOLTAGE VDD/VSS 33 Figure 38. Code Range > 1% R-Tolerance Error vs. Voltage Figure 36. Maximum Transition Glitch 300 26 Figure 37. Code Range > 1% R-Tolerance Error vs. Temperature Rev. E | Page 16 of 24 07675-219 –0.6 Data Sheet AD5293 TEST CIRCUITS Figure 39 to Figure 44 define the test conditions used in the Specifications section. NC IW VA A V+ ~ VMS W B 07675-030 Figure 39. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL) PSS (%/%) = VMS Figure 42. Power Supply Sensitivity (PSS, PSRR) +15V A DUT A V+ = VDD 1LSB = V+/2N W VIN W DUT B VMS 2.5V Figure 40. Potentiometer Divider Nonlinearity Error (INL, DNL) +15V RWB = CODE = 0x00 RW = W + A = NC 2 0.1V IWB –15V GND VDD DUT A VSS GND B ICM +15V –15V W GND – VSS TO VDD –15V GND 0.1V IWB RWB 07675-032 B VOUT Figure 43. Gain vs. Frequency NC DUT OP42 B OFFSET GND 07675-031 V+ ΔVMS% ΔVDD% 07675-036 NC = NO CONNECT V+ = VDD ± 10% ΔVMS PSRR (dB) = 20 log ΔV DD 07675-033 VDD B NC GND NC = NO CONNECT +15V Figure 41. Wiper Resistance –15V Figure 44. Common-Mode Leakage Current Rev. E | Page 17 of 24 07675-037 DUT A W AD5293 Data Sheet THEORY OF OPERATION The AD5293 digital potentiometer is designed to operate as a true variable resistor for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The patented ±1% resistor tolerance feature helps to minimize the total RDAC resistance error, which reduces the overall system error by offering better absolute matching and improved open-loop performance. The digital potentiometer wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The RDAC register can be programmed with any position setting via the standard serial peripheral interface (SPI) by loading the 16-bit data-word. SERIAL DATA INTERFACE The AD5293 contains a serial interface (SYNC, SCLK, DIN, and SDO) that is compatible with SPI standards, as well as most DSPs. The device allows data to be written to every register via the SPI. SHIFT REGISTER The AD5293 shift register is 16 bits wide (see Figure 2). The 16-bit data-word consists of two unused bits, which are set to 0, followed by four control bits and 10 RDAC data bits. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command (see Table 11). Figure 3 shows a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the DIN pin. When SYNC returns high, the serial data-word is decoded according to the instructions in Table 11. The command bits (Cx) control the operation of the digital potentiometer. The data bits (Dx) are the values that are loaded into the decoded register. The AD5293 has an internal counter that counts a multiple of 16 bits (per frame) for proper operation. For example, the AD5293 works with a 32-bit word, but it cannot work properly with a 31- or 33-bit word. The AD5293 does not require a continuous SCLK, when SYNC is high, and all interface pins should be operated close to the supply rails to minimize power consumption in the digital input buffers. WRITE PROTECTION On power-up, the serial data input register write command for the RDAC register is disabled. The RDAC write protect bit, C1 of the control register (see Table 12 and Table 13), is set to 0 by default. This disables any change of the RDAC register content, regardless of the software commands, except that the RDAC register can be refreshed to midscale using the software reset command (Command 3, see Table 11) or through hardware, using the RESET pin. To enable programming of the variable resistor wiper position (programming the RDAC register), the write protect bit, C1 of the control register, must first be programmed. This is accomplished by loading the serial data input register with Command 4 (see Table 11). BASIC OPERATION The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the serial data input register with Command 1 (see Table 11) and the desired wiper position data. The RDY pin can be used to monitor the completion of this RDAC register write command. Command 2 can be used to read back the contents of the RDAC register (see Table 11). After issuing the readback command, the RDY pin can be monitored to indicate when the data is available to be read out on SDO in the next SPI operation. Instead of monitoring the RDY pin, a minimum delay can be implemented when executing a write or read command (see Table 5). Table 9 provides an example listing of a sequence of serial data input (DIN) words with the serial data output appearing at the SDO pin in hexadecimal format for an RDAC write and read. Table 9. RDAC Register Write and Read DIN 0x1802 0x0500 SDO 0xXXXX1 0x1802 0x0800 0x0000 0x0500 0x0100 1 RDAC REGISTER The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with all zeros, the wiper is connected to Terminal B of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. The RDY pin can be used to monitor the completion of a write to or read from the RDAC register. The AD5293 presets to midscale on power-up. Action Enable update of wiper position. Write 0x100 to the RDAC register. Wiper moves to ¼ full-scale position. Prepare data read from RDAC register. NOP (Instruction 0) sends a 16-bit word out of SDO, where the last 10 bits contain the contents of the RDAC register. X = unknown. SHUTDOWN MODE The AD5293 can be placed in shutdown mode by executing the software shutdown command (see Command 6 in Table 11), and setting the LSB to 1. This feature places the RDAC in a special state in which Terminal A is open-circuited and Wiper W is connected to Terminal B. The contents of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 11 are supported while in shutdown mode. Rev. E | Page 18 of 24 Data Sheet AD5293 sequence of the serial data input (DIN). Daisy chaining minimizes the number of port pins required from the controlling IC. As shown in Figure 45, users need to tie the SDO pin of one package to the DIN pin of the next package. Users may need to increase the clock period, because the pull-up resistor and the capacitive loading at the SDO-to-DIN interface may require additional time delay between subsequent devices. RESET A low-to-high transition of the hardware RESET pin loads the RDAC register with midscale. The AD5293 can also be reset through software by executing Command 3 (see Table 11). The control register is restored with default bits (see Table 13). RESISTOR PERFORMANCE MODE This mode activates a new, patented 1% end-to-end resistor tolerance that ensures a ±1% resistor tolerance on each code, that is, code = half scale, RWB =10 kΩ ± 100 Ω. See Table 2 and Table 4 to verify which codes achieve ±1% resistor tolerance. The resistor performance mode is activated by programming Bit C2 of the control register (see Table 12 and Table 13). The typical settling time is shown in Figure 32. When two AD5293s are daisy-chained, 32 bits of data are required. The first 16 bits go to U2, and the second 16 bits go to U1. The SYNC pin should be held low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. Keep the SYNC pin low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. SDO PIN AND DAISY-CHAIN OPERATION The serial data output pin (SDO) serves two purposes: it can be used to read the contents of the wiper setting and control register using Command 2, and Command 5, respectively (see Table 11) or the SDO pin can be used in daisy-chain mode. Data is clocked out of SDO on the rising edge of SCLK. The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor if this pin is used. To place the pin in high impedance and minimize the power dissipation when the pin is used, the 0x8001 data word followed by Command 0 should be sent to the part. Table 10 provides a sample listing for the VLOGIC AD5293 MOSI MICROCONTROLLER SCLK SS DIN AD5293 DIN SDO SCLK U2 SYNC SDO SCLK 07675-039 SYNC U1 RP 2.2kΩ Figure 45. Daisy-Chain Configuration Using SDO Table 10. Minimize Power Dissipation at the SDO Pin DIN 0xXXXX 0x8001 0x0000 1 SDO1 0xXXXX 0xXXXX High impedance Action Last user command sent to the digital potentiometer Prepares the SDO pin to be placed in high impedance mode The SDO pin is placed in high impedance X = don’t care. Table 11. Command Operation Truth Table Command 0 1 Command Bits[B13:B10] C3 C2 C1 C0 0 0 0 0 0 0 0 1 Data Bits[B9:B0]1 D9 D8 D7 D6 X X X X D9 D8 D7 D6 D5 X D5 D4 X D4 D3 X D3 D2 X D2 D1 X D1 D0 X D0 2 0 0 1 0 X X X X X X X X X X 3 4 0 0 1 1 0 1 0 0 X X X X X X X X X X X X X X X D2 X D1 X X 5 0 1 1 1 X X X X X X X X X X 6 1 0 0 0 X X X X X X X X X D0 1 Operation NOP command. Do nothing. Write contents of serial register data to RDAC. Read RDAC wiper setting from SDO output in the next frame. Reset. Refresh RDAC with midscale code. Write contents of serial register data to control register. Read control register from SDO output in the next frame. Software power-down. D0 = 0 (normal mode). D0 = 1 (device placed in shutdown mode). X = don’t care. Table 12. Control Register Bit Map D9 X1 1 D8 X1 D7 X1 D6 X1 D5 X1 D4 X1 X = don’t care. Rev. E | Page 19 of 24 D3 X1 D2 C2 D1 C1 D0 X1 AD5293 Data Sheet Table 13. Control Register Function Register Name Control Bit Name C2 Description Calibration enable. 0 = resistor performance mode (default). 1 = normal mode. RDAC register write protect. 0 = locks the wiper position through the digital interface (default). 1 = allows update of wiper position through digital interface. C1 The nominal resistance between Terminal A and Terminal B, RAB, is available in 20 kΩ, 50 kΩ, and 100 kΩ and has 1024 tap points that are accessed by the wiper terminal. The 10-bit data in the RDAC latch is decoded to select one of the 1024 possible wiper settings. The AD5293 contains an internal ±1% resistor tolerance calibration feature that can be enabled or disabled, enabled by default by programming Bit C2 of the control register (see Table 12 and Table 13). RDAC ARCHITECTURE To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5293 employs a 3-stage segmentation approach, as shown in Figure 46. The AD5293 wiper switch is designed with transmission gate CMOS topology and with the gate voltage derived from VDD. A The digitally programmed output resistance between the W terminal and the A terminal, RWA, and the W terminal and B terminal, RWB, is calibrated to give a maximum of ±1% absolute resistance error over both the full supply and temperature ranges. As a result, the general equation for determining the digitally programmed output resistance between the W terminal and B terminal is D (1) RWB (D)   R AB 1024 RL RM RL SW RM RW W where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RAB is the end-to-end resistance. RW 10-BIT ADDRESS DECODER RM RL RM RL 07675-040 B Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA is also calibrated to give a maximum of 1% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equation for this operation is Figure 46. Simplified RDAC Circuit RWA (D )  PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation—1% Resistor Tolerance The AD5293 operates in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be left floating or it can be tied to the W terminal, as shown in Figure 47. A W B A W B W B Figure 47. Rheostat Mode Configuration 07675-041 A 1024  D  R AB 1024 (2) where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RAB is the end-to-end resistance. In the zero-scale condition, a finite total wiper resistance of 120 Ω is present. Regardless of the setting in which the part is operating, care should be taken to limit the current between the A terminal to B terminal, the W terminal to the A terminal, and the W terminal to the B terminal to the maximum continuous current of ±3 mA or to the pulse current specified in Table 6. Otherwise, degradation, or possible destruction of the internal switch contact, can occur. Rev. E | Page 20 of 24 Data Sheet AD5293 PROGRAMMING THE POTENTIOMETER DIVIDER TERMINAL VOLTAGE OPERATING RANGE Voltage Output Operation The positive VDD and negative VSS power supplies of the AD5293 define the boundary conditions for proper 3-terminal, digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 50). The digital potentiometer easily generates a voltage divider at wiper-to-B terminal and wiper-to-A terminal that is proportional to the input voltage at A to B, as shown in Figure 48. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity. A A VOUT 07675-042 W B W B Figure 48. Potentiometer Mode Configuration If ignoring the effect of the wiper resistance for simplicity, connecting the A terminal to 30 V and the B terminal to ground produces an output voltage at the Wiper W to Terminal B that ranges from 0 V to 30 V − 1 LSB. Each LSB of voltage is equal to the voltage applied across the A terminal and B terminal, divided by the 1024 positions of the potentiometer divider. The general equation defining the output voltage at VW, with respect to ground for any valid input voltage applied to Terminal A and Terminal B, is VW (D)  D 1024  D VA   VB 1024 1024 (3) To optimize the wiper position update rate when in voltage divider mode, it is recommended that the internal ±1% resistor tolerance calibration feature be disabled by programming Bit C2 of the control register (see Table 11). Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RWA and RWB, and not on the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. EXT_CAP CAPACITOR A 1 μF capacitor to GND must be connected to the EXT_CAP pin (see Figure 49) on power-up and throughout the operation of the AD5293. This capacitor must have a voltage rating of ≥7 V. VSS Figure 50. Maximum Terminal Voltages Set by VDD and VSS The ground pin of the AD5293 is primarily used as a digital ground reference. To minimize the digital ground bounce, the AD5293 ground pin should be joined remotely to common ground. The digital input control signals to the AD5293 must be referenced to the device ground pin (GND) to satisfy the logic level defined in the Specifications section. Power-Up Sequence Because there are diodes to limit the voltage compliance at the A, B, and W terminals (see Figure 50), it is important to power VDD and VSS first, before applying any voltage to the A, B, and W terminals. Otherwise, the diode is forward-biased such that VDD and VSS are powered up unintentionally. The ideal power-up sequence is GND, VSS, VLOGIC, VDD, the digital inputs, and then VA, VB, and VW. The order of powering up VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD, VSS, and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, the power-on preset activates after VLOGIC is powered, restoring midscale to the RDAC register. AD5293 C1 1µF 07675-044 VIN VDD EXT_CAP 07675-043 GND Figure 49. Hardware Setup for the EXT_CAP Pin Rev. E | Page 21 of 24 AD5293 Data Sheet APPLICATIONS INFORMATION HIGH VOLTAGE DAC HIGH ACCURACY DAC The AD5293 can be configured as a high voltage DAC, with an output voltage as high as 33 V. The circuit is shown in Figure 51. The output is It is possible to configure the AD5293 as a high accuracy DAC by optimizing the resolution of the device over a specific reduced voltage range. This is achieved by placing external resistors on either side of the RDAC, as shown in Figure 53. The improved ±1% resistor tolerance specification greatly reduces error associated with matching to discrete resistors.  D × 1.2 V × 1024   R2  1 +   R   1   (4) where D is the decimal code from 0 to 1023. R3 + (D 1024 × RAB ) ×V DD VOUT (D) = VDD VDD VDD U2 U1A AD8512 D1 ADR512 U1 AD5293 V+ 20kΩ V– AD5293 U1B R2 20kΩ VOUT B R1 AD8512 VDD U2 V+ ±1% B V– R3 07675-153 R2 R1 Figure 53. Optimizing Resolution Figure 51. High Voltage DAC VARIABLE GAIN INSTRUMENTATION AMPLIFIER PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT For applications that require high current adjustments, such as a laser diode or tunable laser, a boosted voltage source can be considered (see Figure 52). U3 2N7002 U1 CC W U2 OP184 ADG1207 RBIAS VDD +VIN1 IL SIGNAL +VIN4 LD –VIN1 07675-155 AD5293 B The AD8221 in conjunction with the AD5293 and the ADG1207, as shown in Figure 54, make an excellent instrumentation amplifier for use in data acquisition systems. The data acquisition system is low distortion and low noise enable it to condition signals in front of a variety of ADCs. VOUT VIN A VOUT OP1177 AD5293 VOUT AD8221 –VIN4 Figure 52. Programmable Boosted Voltage Source VSS In this circuit, the inverting input of the op amp forces VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-channel FET (U3). The N-channel FET power handling must be adequate to dissipate (VIN − VOUT) × IL power. This circuit can source a maximum of 100 mA with a 33 V supply. 07675-156 RBIAS (5) R1 + ((1024 − D )1024) × RAB + R3 07675-154 VOUT (D) = Figure 54. Data Acquisition System The gain can be calculated by using Equation 6, as follows: Rev. E | Page 22 of 24 G( D ) = 1 + 49.4 kΩ (D 1024) × R AB (6) Data Sheet AD5293 AUDIO VOLUME CONTROL The input is ac-coupled by C1 and attenuated down before feeding into the window comparator formed by U2, U3, and U4B. U6 is used to establish the signal as zero reference. The upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 V and 2.497 V (or 0.005 V window) in this example. This output is AND’ed with the chip select signal such that the AD5293 updates whenever the signal crosses the window. To avoid a constant update of the device, program the chip select signal as two pulses instead of one. The excellent THD performance and high voltage capability of the AD5293 make it ideal for digital volume control. The AD5293 is used as an audio attenuator; it can be connected directly to a gain amplifier. A large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal, causing an audible zipper noise. To prevent this, a zero-crossing window detector can be inserted to the CS line to delay the device update until the audio signal crosses the window. Because the input signal can operate on top of any dc level, rather than absolute 0 V level, zero crossing in this case means the signal is ac-coupled, and the dc offset level is the signal zero reference point. In Figure 55, the lower trace shows that the volume level changes from a quarter-scale to full-scale when a signal change occurs near the zero-crossing window. The configuration to reduce zipper noise is shown in Figure 56, and the results of using this configuration are shown in Figure 55. 1 2 07675-158 CHANNEL 1 FREQ = 20.25kHz 1.03V p-p Figure 55. Zipper Noise Detector C1 VIN 1µF 5V U1 R1 100kΩ R2 200Ω R4 90kΩ +15V +5V C2 0.1µF –15V U4B +5V 4 7408 5 5V U6 V+ AD8541 V– U3 VCC ADCMP371 GND R3 100kΩ 6 1 +15V VSS U4A 7408 2 20kΩ SYNC SCLK SCLK SDIN SDIN SYNC W U5 V+ VOUT V– B –15V GND 07675-157 R5 10kΩ A C3 0.1µF U2 VCC ADCMP371 GND AD5293 VDD Figure 56. Audio Volume Control with Zipper Noise Reduction. Rev. E | Page 23 of 24 AD5293 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 0.75 0.60 0.45 8° 0° 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 57. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Model1 AD5293BRUZ-20 AD5293BRUZ-20-RL7 AD5293BRUZ-50 AD5293BRUZ-50-RL7 AD5293BRUZ-100 AD5293BRUZ-100-RL7 1 RAB (kΩ) 20 20 50 50 100 100 Resolution 1024 1024 1024 1024 1024 1024 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Z = RoHS Compliant Part. ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07675-0-3/16(E) Rev. E | Page 24 of 24 Package Description 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Package Option RU-14 RU-14 RU-14 RU-14 RU-14 RU-14