a
2.5 V to 5.5 V, 230 A, Parallel Interface
Dual Voltage-Output 8-/10-/12-Bit DACs
AD5332/AD5333/AD5342/AD5343*
FEATURES
AD5332: Dual 8-Bit DAC in 20-Lead TSSOP
AD5333: Dual 10-Bit DAC in 24-Lead TSSOP
AD5342: Dual 12-Bit DAC in 28-Lead TSSOP
AD5343: Dual 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 230 A @ 3 V, 300 A @ 5 V
via PD Pin
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–V REF or 0–2 V REF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40ⴗC to +105ⴗC
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 230 µA at 3 V, and feature a power-down pin, PD
that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can drive the output to
both supply rails, while the AD5333 and AD5342 allow a choice
of buffered or unbuffered reference input.
The AD5332/AD5333/AD5342/AD5343 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5333 and AD5342 allows the output
range to be set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5332/AD5333/AD5342/AD5343 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5332 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
VREFA
AD5332
POWER-ON
RESET
DB
7
..
.
DB0
CS
VDD
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
BUFFER
VOUTA
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
BUFFER
VOUTB
INTERFACE
LOGIC
WR
A0
CLR
RESET
POWER-DOWN
LOGIC
LDAC
VREFB
PD
GND
*Protected by U.S. Patent Number 5,969,657.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD5332/AD5333/AD5342/AD5343–SPECIFICATIONS
(V = 2.5 V to 5.5 V, V = 2 V. R = 2 k⍀ to GND; C =200 pF to GND; all specifications T to T unless otherwise noted.)
DD
REF
L
L
MIN
MAX
2
Parameter1
Min
B Version
Typ
Max
Unit
Conditions/Comments
3, 4
DC PERFORMANCE
AD5332
Resolution
Relative Accuracy
Differential Nonlinearity
AD5333
Resolution
Relative Accuracy
Differential Nonlinearity
AD5342/AD5343
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband5
Upper Deadband
Offset Error Drift6
Gain Error Drift6
DC Power Supply Rejection Ratio6
DC Crosstalk6
DAC REFERENCE INPUT6
VREF Input Range
OUTPUT CHARACTERISTICS6
Minimum Output Voltage4, 7
Maximum Output Voltage4, 7
DC Output Impedance
Short Circuit Current
Power-Up Time
LOGIC INPUTS6
Input Current
VIL, Input Low Voltage
Guaranteed Monotonic By Design Over All Codes
10
± 0.5
± 0.05
±4
± 0.5
Bits
LSB
LSB
Guaranteed Monotonic By Design Over All Codes
± 16
±1
±3
±1
60
60
VDD
VDD
Bits
LSB
LSB
% of FSR
% of FSR
mV
mV
ppm of FSR/°C
ppm of FSR/°C
dB
µV
Guaranteed Monotonic By Design Over All Codes
Lower Deadband Exists Only if Offset Error Is Negative
VDD = 5 V. Upper Deadband Exists Only if VREF = VDD
∆VDD = ± 10%
RL = 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND;
Gain = 0
>10
180
90
–90
–90
V
V
MΩ
kΩ
kΩ
dB
dB
Buffered Reference (AD5333 and AD5342)
Unbuffered Reference
Buffered Reference (AD5333 and AD5342)
Unbuffered Reference. Gain = 1, Input Impedance = RDAC
Unbuffered Reference. Gain = 2, Input Impedance = RDAC
Frequency = 10 kHz
Frequency = 10 kHz (AD5332, AD5333, and AD5342)
0.001
VDD – 0.001
0.5
25
16
2.5
5
V min
V max
Ω
mA
mA
µs
µs
Rail-to-Rail Operation
±1
µA
V
V
V
V
V
V
pF
0.8
0.6
0.5
2.4
2.1
2.0
Pin Capacitance
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
Bits
LSB
LSB
1
0.25
Reference Feedthrough
Channel-to-Channel Isolation
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
±1
± 0.25
12
±2
± 0.2
± 0.4
± 0.15
10
10
–12
–5
–60
200
VREF Input Impedance
VIH, Input High Voltage
8
± 0.15
± 0.02
3.5
2.5
5.5
V
300
230
450
350
µA
µA
0.2
0.08
1
1
µA
µA
VDD = 5 V
VDD = 3 V
Coming Out of Power-Down Mode. VDD = 5 V
Coming Out of Power-Down Mode. VDD = 3 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
All DACs active and excluding load currents
Unbuffered Reference. VIH = VDD, VIL = GND.
IDD increases by 50 µA at VREF > VDD – 100 mV.
In Buffered Mode extra current is (5 +VREF/RDAC) µA.
NOTES
1
See Terminology section.
2
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
3
Linearity is tested using a reduced code range: AD5332 (Code 8 to 255); AD5333 (Code 28 to 1023); AD5342/AD5343 (Code 115 to 4095).
4
DC specifications tested with outputs unloaded.
5
This corresponds to x codes. x = Deadband voltage/LSB size.
6
Guaranteed by design and characterization, not production tested.
7
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V REF = VDD and
“Offset plus Gain” Error must be positive.
Specifications subject to change without notice.
–2–
REV. 0
AD5332/AD5333/AD5342/AD5343
(VDD = 2.5 V to 5.5 V. RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless
AC CHARACTERISTICS1 otherwise noted.)
2
Parameter
B Version3
Min
Typ
Max
Unit
6
7
8
8
0.7
6
0.5
3
0.5
3.5
200
–70
µs
µs
µs
µs
V/µs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
Output Voltage Settling Time
AD5332
AD5333
AD5342
AD5343
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
8
9
10
10
Conditions/Comments
VREF = 2 V. See Figure 20
1/4 Scale to 3/4 Scale Change (40 H to C0 H)
1/4 Scale to 3/4 Scale Change (100 H to 300 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
1 LSB Change Around Major Carry
VREF = 2 V ± 0.1 V p-p. Unbuffered Mode
VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology section.
3
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3 (V
DD
= 2.5 V to 5.5 V, All specifications TMIN to TMAX unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Condition/Comments
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
0
0
20
5
4.5
5
5
4.5
5
4.5
20
20
50
20
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR Setup Time
CS to WR Hold Time
WR Pulsewidth
Data, GAIN, BUF, HBEN Setup Time
Data, GAIN, BUF, HBEN Hold Time
Synchronous Mode. WR Falling to LDAC Falling
Synchronous Mode. LDAC Falling to WR Rising
Synchronous Mode. WR Rising to LDAC Rising
Asynchronous Mode. LDAC Rising to WR Rising
Asynchronous Mode. WR Rising to LDAC Falling
LDAC Pulsewidth
CLR Pulsewidth
Time Between WR Cycles
A0 Setup Time
A0 Hold Time
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and
timed from a voltage level of (V IL + VIH)/2.
3
See Figure 1.
t1
t2
CS
t 13
t3
Specifications subject to change without notice.
WR
DATA,
GAIN,
BUF,
HBEN
t6
t4
t5
t7
t8
LDAC1
t9
t 10
t 11
LDAC2
CLR
t 14
t 15
t 12
A0
1SYNCHRONOUS LDAC UPDATE MODE
2ASYNCHRONOUS LDAC UPDATE MODE
Figure 1. Parallel Interface Timing Diagram
REV. 0
–3–
AD5332/AD5333/AD5342/AD5343
θJA Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
θJA Thermal Impedance (28-Lead TSSOP) . . . . 97.9°C/W
θJC Thermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W
θJC Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
θJC Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . (TJ max – TA)/θJA mW
θJA Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package
Option
AD5332BRU
AD5333BRU
AD5342BRU
AD5343BRU
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
RU-20
RU-24
RU-28
RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5332/AD5333/AD5342/AD5343 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD5332/AD5333/AD5342/AD5343
AD5332 FUNCTIONAL BLOCK DIAGRAM
VREFA
INPUT
REGISTER
CS
VDD
AD5332
POWER-ON
RESET
DB
7
...
DB0
AD5332 PIN CONFIGURATION
DAC
REGISTER
8-BIT
DAC
VOUTA
BUFFER
VREFB 1
20
DB7
VREFA 2
19
DB6
VOUTA 3
18
DB5
VOUTB 4
17
DB4
16
DB3
GND 5
8-BIT
AD5332
TOP VIEW 15 DB
2
(Not to Scale)
14 DB1
WR 7
CS 6
INTERFACE
LOGIC
INPUT
REGISTER
WR
DAC
REGISTER
8-BIT
DAC
BUFFER
VOUTB
DB0
A0 8
13
CLR 9
12
VDD
LDAC 10
11
PD
A0
RESET
CLR
POWER-DOWN
LOGIC
LDAC
PD
VREFB
GND
AD5332 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
2
3
4
5
6
7
8
9
10
VREFB
VREFA
VOUTA
VOUTB
GND
CS
WR
A0
CLR
LDAC
11
12
PD
VDD
13–20
DB0–DB7
Unbuffered reference input for DAC B.
Unbuffered reference input for DAC A.
Output of DAC A. Buffered output with rail-to-rail operation.
Output of DAC B. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Address pin for selecting which DAC A and DAC B.
Asynchronous active low control input that clears all input registers and DAC registers to zeros.
Active low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
REV. 0
–5–
AD5332/AD5333/AD5342/AD5343
AD5333 FUNCTIONAL BLOCK DIAGRAM
AD5333 PIN CONFIGURATION
VDD
VREFA
AD5333
POWER-ON
RESET
BUF
CS
24 DB9
BUF 2
23 DB8
VREFB 3
22 DB7
VREFA 4
VOUTA 5
GAIN
DB
.9
..
DB0
DAC
REGISTER
GAIN 1
INPUT
REGISTER
10-BIT
DAC
BUFFER
VOUTA
INTERFACE
LOGIC
INPUT
REGISTER
WR
10-BIT
DAC
BUFFER
VOUTB
A0
RESET
CLR
AD5333
21 DB6
20 DB5
TOP VIEW 19 DB4
GND 7 (Not to Scale) 18 DB3
VOUTB 6
CS 8
17 DB2
WR 9
16 DB1
A0 10
15 DB0
CLR 11
14 VDD
LDAC 12
DAC
REGISTER
10-BIT
13 PD
POWER-DOWN
LOGIC
LDAC
PD GND
VREFB
AD5333 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
2
3
4
5
6
7
8
9
10
11
12
GAIN
BUF
VREFB
VREFA
VOUTA
VOUTB
GND
CS
WR
A0
CLR
LDAC
13
14
PD
VDD
15–24
DB0–DB9
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
Reference input for DAC B.
Reference input for DAC A.
Output of DAC A. Buffered output with rail-to-rail operation.
Output of DAC B. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Address pin for selecting between DAC A and DAC B.
Asynchronous active-low control input that clears all input registers and DAC registers to zeros.
Active-low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
10 Parallel Data Inputs. DB9 is the MSB of these 10 bits.
–6–
REV. 0
AD5332/AD5333/AD5342/AD5343
AD5342 FUNCTIONAL BLOCK DIAGRAM
AD5342 PIN CONFIGURATION
VREFA
VDD
AD5342
POWER-ON
RESET
INPUT
REGISTER
DB.11
..
DB0
CS
DAC
REGISTER
12-BIT
DAC
BUFFER
VOUTA
28
DB11
BUF 2
27
DB10
VREFB 3
26
DB9
VREFA 4
25
DB8
VOUTA 5
24
DB7
23
DB6
VOUTB 6
NC 7
12-BIT
AD5342
TOP VIEW 22 DB5
NC 8 (Not to Scale) 21 DB4
INTERFACE
LOGIC
INPUT
REGISTER
WR
12-BIT
DAC
BUFFER
VOUTB
DAC
REGISTER
A0
RESET
CLR
GAIN 1
POWER-DOWN
LOGIC
GND 9
20
DB3
CS 10
19
DB2
WR 11
18
DB1
A0 12
17
DB0
CLR 13
16
VDD
LDAC 14
15
PD
NC = NO CONNECT
LDAC
VREFB
PD
GND
AD5342 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
2
3
4
5
6
7, 8
9
10
11
12
13
14
GAIN
BUF
VREFB
VREFA
VOUTA
VOUTB
NC
GND
CS
WR
A0
CLR
LDAC
15
16
PD
VDD
17–28
DB0–DB11
Gain Control Pin. This controls whether the output range from the DAC is 0-VREF or 0-2 VREF.
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
Reference Input for DAC B.
Reference Input for DAC A.
Output of DAC A. Buffered output with rail-to-rail operation.
Output of DAC B. Buffered output with rail-to-rail operation.
No Connect.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Address pin for selecting between DAC A and DAC B.
Asynchronous active low control input that clears all input registers and DAC registers to zeros.
Active low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
12 Parallel Data Inputs. DB11 is the MSB of these 12 bits.
REV. 0
–7–
AD5332/AD5333/AD5342/AD5343
AD5343 FUNCTIONAL BLOCK DIAGRAM
VREF
AD5343 PIN CONFIGURATION
VDD
20
DB7
2
19
DB6
VOUTA 3
18
DB5
VOUTB 4
17
DB4
16
DB3
VREF
POWER-ON
RESET
AD5343
HIGH BYTE
REGISTER
DB
7
...
..
.
HBEN 1
GND 5
12-BIT
AD5343
TOP VIEW 15 DB
2
(Not to Scale)
14 DB1
WR 7
CS 6
LOW BYTE
REGISTER
DB0
DAC
REGISTER
12-BIT
DAC
BUFFER
VOUTA
A0 8
13
HBEN
CS
INTERFACE
LOGIC
CLR
HIGH BYTE
REGISTER
LDAC
DB0
9
12
VDD
10
11
PD
WR
LOW BYTE
REGISTER
A0
DAC
REGISTER
12-BIT
DAC
BUFFER
VOUTB
RESET
CLR
LDAC
POWER-DOWN
LOGIC
PD
GND
AD5343 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
HBEN
2
3
4
5
6
7
8
9
10
VREF
VOUTA
VOUTB
GND
CS
WR
A0
CLR
LDAC
11
12
PD
VDD
13–20
DB0–DB7
This pin is used when writing to the device to determine if data is written to the high byte register or the
low byte register.
Unbuffered reference input for both DACs.
Output of DAC A. Buffered output with rail-to-rail operation.
Output of DAC B. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Address pin for selecting between DAC A and DAC B.
Asynchronous active low control input that clears all input registers and DAC registers to zeros.
Active low control input that updates the DAC registers with the contents of the input registers. This allows
all DAC outputs to be simultaneously updated.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
–8–
REV. 0
AD5332/AD5333/AD5342/AD5343
TERMINOLOGY
GAIN ERROR
AND
OFFSET
ERROR
RELATIVE ACCURACY
For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL versus Code plot can be seen in Figures
5, 6, and 7.
ACTUAL
OUTPUT
VOLTAGE
DIFFERENTIAL NONLINEARITY
IDEAL
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus Code plot can be seen in
Figures 8, 9, and 10.
POSITIVE
OFFSET
DAC CODE
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
Figure 3. Positive Offset Error and Gain Error
If the offset voltage is positive, the output voltage will still be
positive at zero input code. This is shown in Figure 3. Because
the DACs operate from a single supply, a negative offset cannot
appear at the output of the buffer amplifier. Instead, there will
be a code close to zero at which the amplifier output saturates
(amplifier footroom). Below this code there will be a deadband
over which the output voltage will not change. This is illustrated
in Figure 4.
GAIN ERROR
AND
OFFSET
ERROR
IDEAL
OUTPUT
VOLTAGE
GAIN ERROR
ACTUAL
This is a measure of the span error of the DAC (including any
error in the gain of the buffer amplifier). It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
expressed as a percentage of the full-scale range. This is illustrated in Figure 2.
NEGATIVE
OFFSET
DAC CODE
POSITIVE
GAIN ERROR
NEGATIVE
GAIN ERROR
ACTUAL
DEADBAND CODES
AMPLIFIER
FOOTROOM
(~ 1mV)
OUTPUT
VOLTAGE
IDEAL
NEGATIVE
OFFSET
DAC CODE
Figure 4. Negative Offset Error and Gain Error
Figure 2. Gain Error
REV. 0
–9–
AD5332/AD5333/AD5342/AD5343
OFFSET ERROR DRIFT
DIGITAL CROSSTALK
This is a measure of the change in Offset Error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
GAIN ERROR DRIFT
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of the other DAC. It is
expressed in nV-secs.
This is a measure of the change in Gain Error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.
ANALOG CROSSTALK
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by changes in
the supply voltage. PSRR is the ratio of the change in VOUT to a
change in VDD for full-scale output of the DAC. It is measured
in dBs. VREF is held at 2 V and VDD is varied ± 10%.
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-secs.
DC CROSSTALK
This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and
vice versa) and output change of the other DAC. It is expressed
in µV.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
the other DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC pin set
low and monitoring the output of the other DAC. The energy of
the glitch is expressed in nV-secs.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC output
to the reference input when the DAC output is not being updated
(i.e., LDAC is high). It is expressed in dBs.
MULTIPLYING BANDWIDTH
CHANNEL-TO-CHANNEL ISOLATION
This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of the other DAC. It
is measured by grounding one VREF pin and applying a 10 kHz,
4 V peak-to-peak sine wave to the other VREF pin. It is expressed
in dBs.
The amplifiers within the DAC have a finite bandwidth. The
Multiplying Bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The Multiplying Bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-Code Transition Glitch Energy is the energy of the
impulse injected into the analog output when the DAC changes
state. It is normally specified as the area of the glitch in nV secs
and is measured when the digital code is changed by 1 LSB at
the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00
to 011 . . . 11).
DIGITAL FEEDTHROUGH
Digital Feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device but is measured when the DAC is not being written to
(CS held high). It is specified in nV secs and is measured with a
full-scale change on the digital input pins, i.e. from all 0s to all
1s and vice versa.
–10–
REV. 0
Typical Performance Characteristics– AD5332/AD5333/AD5342/AD5343
1.0
12
3
TA = 25ⴗC
VDD = 5V
TA = 25ⴗC
VDD = 5V
TA = 25ⴗC
VDD = 5V
8
2
0
INL ERROR – LSBs
INL ERROR – LSBs
INL ERROR – LSBs
0.5
1
0
–1
4
0
–4
–0.5
–8
–2
0
50
100
150
CODE
200
–3
250
Figure 5. AD5332 Typical INL Plot
400
600
CODE
800
1000
0
–0.1
3000
4000
TA = 25ⴗC
VDD = 5V
0.4
0
2000
CODE
1.0
TA = 25ⴗC
VDD = 5V
0.1
1000
Figure 7. AD5342 Typical INL Plot
0.6
TA = 25ⴗC
VDD = 5V
DNL ERROR – LSBs
DNL ERROR – LSBs
200
Figure 6. AD5333 Typical INL Plot
0.3
0.2
–12
0
DNL ERROR – LSBs
–1.0
0.2
0
–0.2
0.5
0
–0.5
–0.2
0
50
100
150
CODE
200
–0.6
250
Figure 8. AD5332 Typical DNL Plot
0
400
600
CODE
–1
1000
0.75
0.50
ERROR – LSBs
MAX INL
MAX DNL
0.00
MIN DNL
–0.25
MIN INL
–0.25
MIN INL
–0.75
2
3
4
VREF – V
Figure 11. AD5332 INL and DNL
Error vs. VREF
REV. 0
5
–1.00
–40
4000
0.5
0
–0.75
3000
MAX INL
0.25
–0.50
2000
CODE
VDD = 5V
VREF = 2V
MAX DNL
–0.50
1000
1.0
VDD = 5V
VREF = 2V
0.50
0.25
0
Figure 10. AD5342 Typical DNL Plot
1.00
VDD = 5V
TA = 25ⴗC
0.75
–1.00
800
Figure 9. AD5333 Typical DNL Plot
1.00
ERROR – LSBs
200
ERROR – %
–0.3
–0.4
GAIN ERROR
0.0
OFFSET ERROR
MIN DNL
–0.5
0
40
80
TEMPERATURE – ⴗC
120
Figure 12. AD5332 INL Error and
DNL Error vs. Temperature
–11–
–1.0
–40
0
40
80
TEMPERATURE – ⴗC
120
Figure 13. AD5332 Offset Error
and Gain Error vs. Temperature
AD5332/AD5333/AD5342/AD5343
400
5
0.2
TA = 25ⴰC
VREF = 2V
0.1
300
GAIN ERROR
VOUT – Volts
–0.2
–0.3
–0.4
3
IDD – A
ERROR – %
3V SOURCE
–0.1
2
1
3V SINK
5V SINK
0
2
4
3
VDD – Volts
5
6
0
50
1
3
4
2
5
SINK/SOURCE CURRENT – mA
6
Figure 15. VOUT Source and Sink
Current Capability
400
0.5
Figure 16. Supply Current vs. DAC
Code
TA = 25ⴗC
1400
0.4
1200
300
1000
0.3
IDD – A
IDD – A
FULL-SCALE
1600
TA = 25ⴗC
200
0
ZERO-SCALE
DAC CODE
Figure 14. Offset Error and Gain
Error vs. VDD
TA = 25ⴗC
IDD – A
200
150
–0.5
1
VDD = 3.6V
250
100
OFFSET ERROR
0
0.2
800
600
VDD = 5V
400
100
0.1
200
0
2.5
3.0
3.5
4.0
VDD – V
4.5
5.0
0
2.5
5.5
Figure 17. Supply Current vs. Supply
Voltage
LDAC
0
3.0
3.5
4.0
VDD – V
4.5
5.0
5.5
Figure 18. Power-Down Current vs.
Supply Voltage
VDD = 5V
TA = 25ⴗC
CH2
VDD = 5.5V
4
0
–0.6
TA = 25ⴗC
VREF = 2V
350
5V SOURCE
CH1
VDD = 3V
0
1
2
3
VLOGIC – V
4
5
Figure 19. Supply Current vs. Logic
Input Voltage
TA = 25ⴰC
VDD = 5V
VREF = 2V
TA = 25ⴰC
VDD = 5V
VREF = 2V
VDD
CH1
VOUTA
VOUT
VOUTA
CH2
PD
CH2
CH1
CH1 2V, CH2 200mV, TIME BASE = 200s/DIV
CH1 500mV, CH2 5V, TIME BASE = 1s/DIV
Figure 21. Power-On Reset to 0 V
Figure 22. Exiting Power-Down to
Midscale
CH1 1V, CH2 5V, TIME BASE = 5s/DIV
Figure 20. Half-Scale Settling (1/4 to
3/4 Scale Code Change)
–12–
REV. 0
AD5332/AD5333/AD5342/AD5343
0.939
10
0.938
VDD = +5V
0
0.937
VDD = +3V
–10
0.935
–20
dB
VOUT – Volts
FREQUENCY
0.936
0.934
–30
0.933
0.932
–40
0.931
–50
0.930
0
100
150
200
250
300
IDD – A
350
0.929
400
Figure 23. IDD Histogram with VDD = 3
V and VDD = 5 V
–60
0.01
500 ns/DIV
Figure 24. AD5342 Major-Code Transition Glitch Energy
0.1
1
10
100
FREQUENCY – kHz
1k
10k
Figure 25. Multiplying Bandwidth
(Small-Signal Frequency Response)
TA = 25ⴗC
VREF = 2V
0
4mV/DIV
FULL-SCALE ERROR – %FSR
0.2
–0.2
–0.4
0
1
2
3
VREF – V
4
5
6
Figure 26. Full-Scale Error vs. VREF
750ns/DIV
Figure 27. DAC-DAC Crosstalk
FUNCTIONAL DESCRIPTION
where:
The AD5332/AD5333/AD5342/AD5343 are dual DACs fabricated on a CMOS process with resolutions of 8, 10, 12, and
12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to 5.5 V and
the output buffer amplifiers offer rail-to-rail output swing. The
AD5333 and AD5342 have reference inputs that may be buffered to draw virtually no current from the reference source.
Their output voltage range may be configured to be 0 to VREF
or 0 to 2 VREF. The reference inputs of the AD5332 and AD5343
are unbuffered and their output range is 0 to VREF. The devices
have a power-down feature that reduces current consumption to
only 80 nA @ 3 V.
D = decimal equivalent of the binary code which is loaded to
the DAC register:
0–255 for AD5332 (8 Bits)
0–1023 for AD5333 (10 Bits)
0–4095 for AD5342/AD5343 (12 Bits)
N = DAC resolution
Gain = Output Amplifier Gain (1 or 2)
VREF
REFERENCE
BUFFER
Digital-to-Analog Section
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 28 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by:
VOUT = VREF ×
REV. 0
D
× Gain
2N
BUF
GAIN
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
VOUT
OUTPUT
BUFFER AMPLIFIER
Figure 28. Single DAC Channel Architecture
–13–
AD5332/AD5333/AD5342/AD5343
Resistor String
PARALLEL INTERFACE
The resistor string section is shown in Figure 29. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it
is guaranteed monotonic.
The AD5332, AD5333, and AD5342 load their data as a single
8-, 10-, or 12-bit word, while the AD5343 loads data as a low
byte of 8 bits and a high byte containing 4 bits.
VREF
R
The AD5332/AD5333/AD5342/AD5343 DACs all have doublebuffered interfaces consisting of an input register and a DAC
register. DAC data, BUF, and GAIN inputs are written to the
input register under control of the Chip Select (CS) and Write
(WR).
Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it. The gain and buffer control signals
are also double-buffered and are only updated when LDAC is
taken low.
R
R
Double-Buffered Interface
TO OUTPUT
AMPLIFIER
R
This is useful if the user requires simultaneous updating of all
DACs and peripherals. The user may write to both input registers individually and then, by pulsing the LDAC input low, both
outputs will update simultaneously.
R
Figure 29. Resistor String
DAC Reference Input
The DACs operate with an external reference. The AD5332,
AD5333, and AD5342 have separate reference inputs for each
DAC, while the AD5343 has a single reference input for both
DACs. The reference inputs on the AD5333 and AD5342 may
be configured as buffered or unbuffered. The reference inputs
of the AD5332 and AD5343 are unbuffered. The buffered/
unbuffered option is controlled by the BUF pin.
In buffered mode (BUF = 1) the current drawn from an external reference voltage is virtually zero, as the impedance is at
least 10 MΩ. The reference input range is 1 V to VDD.
In unbuffered mode (BUF = 0) the user can have a reference
voltage as low as 0.25 V and as high as VDD since there is no
restriction due to headroom and footroom of the reference amplifier. The impedance is still large at typically 180 kΩ for 0–VREF
mode and 90 kΩ for 0–2 VREF mode.
Double-buffering is also useful where the DAC data is loaded in
two bytes, as in the AD5343, because it allows the whole data
word to be assembled in parallel before updating the DAC register.
This prevents spurious outputs that could occur if the DAC
register were updated with only the high byte or the low byte.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the input registers. In the case of the AD5332/
AD5333/AD5342/AD5343, the part will only update the DAC
register if the input register has been changed since the last
time the DAC register was updated. This removes unnecessary
crosstalk.
Clear Input (CLR)
CLR is an active low, asynchronous clear that resets the input and
DAC registers.
If using an external buffered reference (e.g., REF192) there is
no need to use the on-chip buffer.
Chip Select Input (CS)
Output Amplifier
Write Input (WR)
CS is an active low input that selects the device.
The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on
VREF, GAIN, the load on VOUT and offset error.
If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V
to VREF.
If a gain of 2 is selected (GAIN = 1), on the AD5333 and AD5342
the output range is 0.001 V to 2 VREF.
The output amplifier is capable of driving a load of 2 kΩ to
GND or VDD, in parallel with 500 pF to GND or VDD. The
source and sink capabilities of the output amplifier can be seen
in Figure 15.
WR is an active low input that controls writing of data to the
device. Data is latched into the input register on the rising edge
of WR.
Load DAC Input (LDAC)
LDAC transfers data from the input register to the DAC register
(and hence updates the outputs). Use of the LDAC function enables
double buffering of the DAC data, GAIN and BUF. There are
two LDAC modes:
Synchronous Mode: In this mode the DAC register is updated
after new data is read in on the rising edge of the WR input.
LDAC can be tied permanently low or pulsed as in Figure 1.
The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB
(at 8 bits) of 6 µs with the output unloaded. See Figure 20.
Asynchronous Mode: In this mode the outputs are not updated
at the same time that the input register is written to. When LDAC
goes low the DAC register is updated with the contents of the
input register.
–14–
REV. 0
AD5332/AD5333/AD5342/AD5343
High-Byte Enable Input (HBEN)
POWER-DOWN MODE
High-Byte Enable is a control input on the AD5343 only that
determines if data is written to the high-byte input register or
the low-byte input register.
The AD5332/AD5333/AD5342/AD5343 have low power consumption, dissipating typically 0.69 mW with a 3 V supply and
1.5 mW with a 5 V supply. Power consumption can be further
reduced when the DACs are not in use by putting them into
power-down mode, which is selected by taking pin PD low.
The low data byte of the AD5343 consists of data bits 0 to 7 at
data inputs DB0 to DB7, while the high byte consists of data
bits 8 to 11 at data inputs DB0 to DB3. DB4 to DB7 are ignored
during a high byte write, but they may be used for data to
set up the reference input as buffered/unbuffered, and buffer
amplifier gain. See Figure 32.
When the PD pin is high, the DACs work normally with a typical
power consumption of 300 µA at 5 V (230 µA at 3 V). In powerdown mode, however, the supply current falls to 200 nA at 5 V
(80 nA at 3 V) when both DACs are powered down. Not only
does the supply current drop, but the output stage is also internally
switched from the output of the amplifier, making it open-circuit.
This has the advantage that the outputs are three-state while
the part is in power-down mode, and provides a defined input
condition for whatever is connected to the outputs of the DAC
amplifiers. The output stage is illustrated in Figure 31.
HIGH BYTE
X
X
X
X
DB11 DB10 DB9 DB8
LOW BYTE
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X = UNUSED BIT
Figure 30. Data Format for AD5343
POWER-ON RESET
RESISTOR
STRING DAC
The AD5332/AD5333/AD5342/AD5343 are provided with a
power-on reset function, so that they power up in a defined state.
The power-on state is:
•
•
•
•
AMPLIFIER
VOUT
POWER-DOWN
CIRCUITRY
Normal operation
Reference input unbuffered
0 – VREF output range
Output voltage set to 0 V
Figure 31. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 µs for VDD = 5 V and 5 µs when
VDD = 3 V. This is the time from a rising edge on the PD pin to
when the output voltage deviates from its power-down voltage.
See Figure 22.
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
Table I. AD5332/AD5333/AD5342 Truth Table
CLR
LDAC
CS
WR
A0
Function
1
1
0
1
1
1
1
1
X
1
1
0
1
X
X
0
0
X
X
1
X
0➝1
0➝1
X
X
X
X
0
1
X
No Data Transfer
No Data Transfer
Clear All Registers
Load DAC A Input Register
Load DAC B Input Register
Update DAC Registers
X = don’t care.
Table II. AD5343 Truth Table
CLR
LDAC
CS
WR
A0
HBEN
Function
1
1
0
1
1
1
1
1
1
1
X
1
1
1
1
0
1
X
X
0
0
0
0
X
X
1
X
0➝1
0➝1
0➝1
0➝1
X
X
X
X
0
0
1
1
X
X
X
X
0
1
0
1
X
No Data Transfer
No Data Transfer
Clear All Registers
Load DAC A Low Byte Input Register
Load DAC A High Byte Input Register
Load DAC B Low Byte Input Register
Load DAC B High Byte Input Register
Update DAC Registers
X = don’t care.
REV. 0
–15–
AD5332/AD5333/AD5342/AD5343
SUGGESTED DATABUS FORMATS
Driving VDD from the Reference Voltage
In most applications GAIN and BUF are hard-wired. However,
if more flexibility is required, they can be included in a databus.
This enables you to software program GAIN, giving the option
of doubling the resolution in the lower half of the DAC range.
In a bused system GAIN and BUF may be treated as data inputs
since they are written to the device during a write operation and
take effect when LDAC is taken low. This means that the reference buffers and the output amplifier gain of multiple DAC
devices can be controlled using common GAIN and BUF lines.
If an output range of zero to VDD is required when the reference
inputs are configured as unbuffered, the simplest solution is to
connect the reference inputs to VDD. As this supply may not be
very accurate, and may be noisy, the devices may be powered
from the reference voltage, for example using a 5 V reference
such as the ADM663 or ADM666, as shown in Figure 34.
6V TO 16V
The AD5333 and AD5342 databuses must be at least 10, and
12 bits wide respectively, and are best suited to a 16-bit databus system.
VIN
Examples of data formats for putting GAIN and BUF on a 16bit databus are shown in Figure 32. Note that any unused bits
above the actual DAC data may be used for BUF and GAIN.
X
X
X
VDD
SENSE
VOUT(2)
VSET GND SHDN
VREF*
VOUT*
0.1F
GND
BUF GAIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AD5342
X
AD5332/AD5333/
AD5342/AD5343
ADM663/ADM666
AD5333
X
10F
0.1F
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
X BUF GAIN DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 34. Using an ADM663/ADM666 as Power and Reference to AD5332/AD5333/AD5342/AD5343
X = UNUSED BIT
Figure 32. GAIN and BUF Data on a 16-Bit Bus
Bipolar Operation Using the AD5332/AD5333/AD5342/AD5343
APPLICATIONS INFORMATION
Typical Application Circuits
The AD5332/AD5333/AD5342/AD5343 can be used with a
wide range of reference voltages, especially if the reference inputs
are configured to be unbuffered, in which case the devices offer
full, one-quadrant multiplying capability over a reference range
of 0.25 V to VDD. More typically, these devices may be used with a
fixed, precision reference voltage. Figure 33 shows a typical
setup for the devices when using an external reference connected to
the unbuffered reference inputs. If the reference inputs are unbuffered, the reference input range is from 0.25 V to VDD, but if the
on-chip reference buffers are used, the reference range is reduced.
Suitable references for 5 V operation are the AD780 and REF192.
For 2.5 V operation, a suitable external reference would be the
AD589, a 1.23 V bandgap reference.
The AD5332/AD5333/AD5342/AD5343 have been designed
for single supply operation, but bipolar operation is achievable
using the circuit shown in Figure 35. The circuit shown has been
configured to achieve an output voltage range of –5 V < VO <
+5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
VO = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2N)] – R4 × VREF/R3
where:
D is the decimal equivalent of the code loaded to the DAC, N is
DAC resolution and VREF is the reference voltage input.
With:
VREF = 2.5 V
R1 = R3 = 10 kΩ
R2 = R4 = 20 kΩ and VDD = 5 V.
VOUT = (10 × D/2N) – 5
VDD = 2.5V TO 5.5V
0.1F
10F
VDD = 5V
R4
20k⍀
VIN
EXT
REF
VDD
VOUT
GND
VREF*
0.1F
VOUT*
+5V
R3
10k⍀
AD5332/AD5333/
AD5342/AD5343
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 2.5V
10F
ⴞ5V
VIN
EXT
REF
GND
VDD
GND
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
VREF*
VOUT
0.1F
AD5332/AD5333/
AD5342/AD5343
VOUT*
AD780/REF192
Figure 33. AD5332/AD5333/AD5342/AD5343 Using
External Reference
WITH VDD = 5V
OR
AD589 WITH VDD = 2.5V
GND
–5V
R1
10k⍀
R2
20k⍀
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
Figure 35. Bipolar Operation using the AD5332/AD5333/
AD5342/AD5343
–16–
REV. 0
AD5332/AD5333/AD5342/AD5343
Decoding Multiple AD5332/AD5333/AD5342/AD5343
The CS pin on these devices can be used in applications to decode
a number of DACs. In this application, all DACs in the system
receive the same data and WR pulses, but only the CS to one of
the DACs will be active at any one time, so data will only be
written to the DAC whose CS is low. If multiple AD5343s are
being used, a common HBEN line will also be required to
determine if the data is written to the high-byte or low-byte
register of the selected DAC.
The 74HC139 is used as a 2- to 4-line decoder to address any
of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded address inputs are changing state. Figure 36
shows a diagram of a typical setup for decoding multiple devices
in a system. Once data has been written sequentially to all DACs in
a system, all the DACs can be updated simultaneously using a
common LDAC line. A common CLR line can also be used to
reset all DAC outputs to zero.
AD5332/AD5333/
AD5342/AD5343
A0
HBEN*
WR
LDAC
CLR
CS
A1
HBEN
WR
LDAC
CLR
DATA
INPUTS
AD5332/AD5333/
AD5342/AD5343
VDD
VCC
ENABLE
CODED
ADDRESS
1G
1A
74HC139
1B
1Y0
AD5332/AD5333/
AD5342/AD5343
1Y1
A0
HBEN*
WR
LDAC
CLR
CS
1Y2
1Y3
DGND
DATA
INPUTS
DATA BUS
A0
HBEN*
WR
LDAC
CLR
CS
Note that the AD5343 has only a single reference input. If using
the AD5332, AD5333, or AD5342, both reference inputs must
be connected.
5V
10F
0.1F
VIN
VREF
1k⍀
PASS
VDD
VREFA*
VOUT
VREFB*
PASS/
FAIL
1/2
CMP04
AD5332/AD5333/
AD5342
VOUTB
1/6 74HC05
GND
*NOT AD5343
Figure 37. Programmable Window Detector
Programmable Current Source
Figure 38 shows the AD5332/AD5333/AD5342/AD5343 used
as the control element of a programmable current source. In this
example, the full-scale current is set to 1 mA. The output voltage from the DAC is applied across the current setting resistor
of 4.7 kΩ in series with the 470 Ω adjustment potentiometer,
which gives an adjustment of about ± 5%. Suitable transistors to
place in the feedback loop of the amplifier include the BC107
and the 2N3904, which enable the current source to operate
from a minimum VSOURCE of 6 V. The operating range is determined by the operating characteristics of the transistor. Suitable
amplifiers include the AD820 and the OP295, both having railto-rail operation on their outputs. The current for any digital
input code and resistor value can be calculated as follows:
I = G × VREF ×
Where:
DATA
INPUTS
1k⍀
FAIL
D
mA
(2 × R)
N
G is the gain of the buffer amplifier (1 or 2)
D is the digital equivalent of the digital input code
N is the DAC resolution (8, 10, or 12 bits)
R is the sum of the resistor plus adjustment potentiometer in kΩ
AD5332/AD5333/
AD5342/AD5343
*AD5343 ONLY
A0
HBEN*
WR
LDAC
CLR
CS
VDD = 5V
DATA
INPUTS
0.1F
VSOURCE
VIN
Figure 36. Decoding Multiple DAC Devices
5V
VDD
EXT
REF
VREF*
VOUT
GND
AD5332/AD5333/AD5342/AD5343 as a Digitally Programmable Window Detector
0.1F
LOAD
VOUT*
AD5332/AD5333/
AD5342/AD5343
AD780/REF192
A digitally programmable upper/lower limit detector using the
two DACs in the AD5332/AD5333/AD5342 is shown in Figure
37. The upper and lower limits for the test are loaded to DACs
A and B which, in turn, set the limits on the CMP04. If a signal
at the VIN input is not within the programmed window, an LED
will indicate the fail condition.
REV. 0
10F
4.7k⍀
WITH VDD = 5V
GND
470⍀
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
Figure 38. Programmable Current Source
–17–
AD5332/AD5333/AD5342/AD5343
Coarse and Fine Adjustment Using the AD5332/AD5333/
AD5342/AD5343
Power Supply Bypassing and Grounding
The DACs in the AD5332/AD5333/AD5342/AD5343 can be
paired together to form a coarse and fine adjustment function,
as shown in Figure 39. DAC A is used to provide the coarse
adjustment while DAC B provides the fine adjustment. Varying
the ratio of R1 and R2 will change the relative effect of the coarse
and fine adjustments. With the resistor values shown the output
amplifier has unity gain for the DAC A output, so the output
range is 0 V to 2.5 V – 1 LSB. For DAC B the amplifier has a gain
of 7.6 × 10–3, giving DAC B a range equal to 2 LSBs of DAC A.
The circuit is shown with a 2.5 V reference, but reference voltages up to VDD may be used. The op amps indicated will allow a
rail-to-rail output swing.
Note that the AD5343 has only a single reference input. If using
the AD5332, AD5333, or AD5342, both reference inputs must
be connected.
VDD = 5V
0.1F
R3
51.2k⍀
10F
VIN
+5V
R1
390⍀
VDD
EXT V
OUT
REF
VREFA*
0.1F
GND
AD780/REF192
WITH VDD = 5V
R4
390⍀
VOUTA
AD5332/AD5333/
AD5342/AD5343
R2
51.2k⍀
VOUTB
VREFB*
GND
*NOT AD5343
VOUT
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5332/AD5333/AD5342/AD5343 is mounted should be
designed so that the analog and digital sections are separated,
and confined to certain areas of the board. If the device is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as closely as possible to the device. The AD5332/AD5333/AD5342/AD5343
should have ample supply bypassing of 10 µF in parallel with
0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors
are the tantalum bead type. The 0.1 µF capacitor should have
low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low
impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
The power supply lines of the device should use as large a trace
as possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run
near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run
at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far
the best, but not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground plane while signal traces are placed on the solder side.
Figure 39. Coarse and Fine Adjustment
–18–
REV. 0
AD5332/AD5333/AD5342/AD5343
Table III. Overview of AD53xx Parallel Devices
Part No.
Resolution DNL
VREF Pins
Settling Time
SINGLES
AD5330
AD5331
AD5340
AD5341
8
10
12
12
± 0.25
± 0.5
± 1.0
± 1.0
1
1
1
1
6 µs
7 µs
8 µs
8 µs
DUALS
AD5332
AD5333
AD5342
AD5343
8
10
12
12
± 0.25
± 0.5
± 1.0
± 1.0
2
2
2
1
6 µs
7 µs
8 µs
8 µs
QUADS
AD5334
AD5335
AD5336
AD5344
8
10
10
12
± 0.25
± 0.5
± 0.5
± 1.0
2
2
4
4
6 µs
7 µs
7 µs
8 µs
Additional Pin Functions
BUF
✓
✓
✓
GAIN
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
Package
Pins
✓
CLR
✓
✓
✓
✓
TSSOP
TSSOP
TSSOP
TSSOP
20
20
24
20
✓
✓
✓
✓
✓
TSSOP
TSSOP
TSSOP
TSSOP
20
24
28
20
✓
✓
✓
TSSOP
TSSOP
TSSOP
TSSOP
24
24
28
28
HBEN
✓
Table IV. Overview of AD53xx Serial Devices
Part No.
Resolution
No. of DACS
DNL
Interface
Settling Time
Package
Pins
SINGLES
AD5300
AD5310
AD5320
8
10
12
1
1
1
± 0.25
± 0.5
± 1.0
SPI
SPI
SPI
4 µs
6 µs
8 µs
SOT-23, MicroSOIC
SOT-23, MicroSOIC
SOT-23, MicroSOIC
6, 8
6, 8
6, 8
AD5301
AD5311
AD5321
8
10
12
1
1
1
± 0.25
± 0.5
± 1.0
2-Wire
2-Wire
2-Wire
6 µs
7 µs
8 µs
SOT-23, MicroSOIC
SOT-23, MicroSOIC
SOT-23, MicroSOIC
6, 8
6, 8
6, 8
DUALS
AD5302
AD5312
AD5322
8
10
12
2
2
2
± 0.25
± 0.5
± 1.0
SPI
SPI
SPI
6 µs
7 µs
8 µs
MicroSOIC
MicroSOIC
MicroSOIC
8
8
8
AD5303
AD5313
AD5323
8
10
12
2
2
2
± 0.25
± 0.5
± 1.0
SPI
SPI
SPI
6 µs
7 µs
8 µs
TSSOP
TSSOP
TSSOP
16
16
16
QUADS
AD5304
AD5314
AD5324
8
10
12
4
4
4
± 0.25
± 0.5
± 1.0
SPI
SPI
SPI
6 µs
7 µs
8 µs
MicroSOIC
MicroSOIC
MicroSOIC
10
10
10
AD5305
AD5315
AD5325
8
10
12
4
4
4
± 0.25
± 0.5
± 1.0
2-Wire
2-Wire
2-Wire
6 µs
7 µs
8 µs
MicroSOIC
MicroSOIC
MicroSOIC
10
10
10
AD5306
AD5316
AD5326
8
10
12
4
4
4
± 0.25
± 0.5
± 1.0
2-Wire
2-Wire
2-Wire
6 µs
7 µs
8 µs
TSSOP
TSSOP
TSSOP
16
16
16
AD5307
AD5317
AD5327
8
10
12
4
4
4
± 0.25
± 0.5
± 1.0
SPI
SPI
SPI
6 µs
7 µs
8 µs
TSSOP
TSSOP
TSSOP
16
16
16
Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html
REV. 0
–19–
AD5332/AD5333/AD5342/AD5343
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Thin Shrink Small Outline Package TSSOP
(RU-20)
20
C3829–2.5–4/00 (rev. 0)
0.260 (6.60)
0.252 (6.40)
11
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
10
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
24-Lead Thin Shrink Small Outline Package TSSOP
(RU-24)
0.311 (7.90)
0.303 (7.70)
24
13
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
12
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
28-Lead Thin Shrink Small Outline Package TSSOP
(RU-28)
0.386 (9.80)
0.378 (9.60)
28
15
PRINTED IN U.S.A.
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
14
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0433 (1.10)
MAX
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
–20–
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
REV. 0
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