2.5 V to 5.5 V, 250 μA, 2-Wire Interface
Dual-Voltage Output, 8-/10-/12-Bit DACs
AD5337/AD5338/AD5339
FEATURES
GENERAL DESCRIPTION
AD5337
2 buffered 8-bit DACs in 8-lead MSOP
AD5338, AD5338-1
2 buffered 10-bit DACs in 8-lead MSOP
AD5339
2 buffered 12-bit DACs in 8-lead MSOP
Low power operation: 250 mA @ 3 V, 300 mA @ 5 V
2-wire (I2C®compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
3 power-down modes
Double-buffered input logic
Output range: 0 V to VREF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit buffered
voltage output DACs, respectively. Each part is housed in an
8-lead MSOP package and operates from a single 2.5 V to 5.5 V
supply, consuming 250 μA at 3 V. On-chip output amplifiers
allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A
2-wire serial interface operates at clock rates up to 400 kHz.
This interface is SMBus compatible at VDD < 3.6 V. Multiple
devices can be placed on the same bus.
The references for the two DACs are derived from one reference
pin. The outputs of all DACs can be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit to ensure that the DAC outputs power up
to 0 V and remain there until a valid write to the device takes
place. A software clear function resets all input and DAC
registers to 0 V. A power-down feature reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated
equipment. The power consumption is typically 1.5 mW at 5 V
and 0.75 mW at 3 V, reducing to 1 μW in power-down mode.
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
FUNCTIONAL BLOCK DIAGRAM
VDD
REFIN
LDAC
SCL
SDA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
VOUTA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTB
INTERFACE
LOGIC
A0
POWER-DOWN
LOGIC
AD5337/AD5338/AD5339
GND
03756-001
POWER-ON
RESET
Figure 1.
Rev. B
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD5337/AD5338/AD5339
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier........................................................................ 15
Applications....................................................................................... 1
Power-on Reset ........................................................................... 15
General Description ......................................................................... 1
Serial Interface ............................................................................ 16
Functional Block Diagram .............................................................. 1
Write Operation.......................................................................... 17
Revision History ............................................................................... 2
Read Operation........................................................................... 18
Specifications..................................................................................... 3
Double-Buffered Interface ........................................................ 19
AC Characteristics........................................................................ 5
Power-Down Modes .................................................................. 19
Timing Characteristics ................................................................ 6
Applications..................................................................................... 20
Absolute Maximum Ratings............................................................ 7
Typical Application Circuit....................................................... 20
ESD Caution.................................................................................. 7
Bipolar Operation....................................................................... 20
Pin Configuration and Function Descriptions............................. 8
Multiple Devices on One Bus ................................................... 20
Terminology ...................................................................................... 9
Product as a Digitally Programmable Window Detector ..... 21
Typical Performance Characteristics ........................................... 11
Coarse and Fine Adjustment Capabilities............................... 21
Theory of Operation ...................................................................... 15
Power Supply Decoupling ......................................................... 21
Digital-to-Analog Converter Section ...................................... 15
Outline Dimensions ....................................................................... 24
Resistor String ............................................................................. 15
Ordering Guide .......................................................................... 25
DAC Reference Inputs ............................................................... 15
REVISION HISTORY
9/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Figure 31...................................................................... 16
Changes to Table 6.......................................................................... 16
Changes to Table 10........................................................................ 23
Changes to Ordering Guide .......................................................... 25
10/04—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Added AD5338-1................................................................Universal
Changes to Specifications.................................................................4
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
11/03—Rev. 0: Initial Version
Rev. B | Page 2 of 28
AD5337/AD5338/AD5339
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter 1
DC PERFORMANCE 3, 4
AD5337
Resolution
Relative Accuracy
Differential Nonlinearity
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
8
±0.15
±0.02
±1
±0.25
8
±0.15
±0.02
±0.5
±0.25
Bits
LSB
LSB
AD5338
Resolution
Relative Accuracy
Differential Nonlinearity
10
±0.5
±0.05
±4
±0.5
10
±0.5
±0.05
±2
±0.50
Bits
LSB
LSB
AD5339
Resolution
Relative Accuracy
Differential Nonlinearity
12
±2
±0.2
±16
±1
12
±2
±0.2
±8
±1
Bits
LSB
LSB
Offset Error
Gain Error
Lower Deadband
±0.4
±0.15
20
±3
±1
60
±0.4
±0.15
20
±3
±1
60
% of FSR
% of FSR
mV
Offset Error Drift 5
−12
−12
Gain Error Drift5
−5
−5
−60
200
Power Supply
Rejection Ratio5
DC Crosstalk5
DAC REFERENCE INPUTS5
VREF Input Range
VREF Input Impedance
Reference Feedthrough
OUTPUT CHARACTERISTICS5
Minimum Output Voltage 6
Maximum Output Voltage6
DC Output Impedance
Short Circuit Current
Power-Up Time
LOGIC INPUTS (A0)5
Input Current
Input Low Voltage (VIL)
0.25
37
B Version 2 Conditions/Comments
Guaranteed monotonic by design
over all codes
Guaranteed monotonic by design
over all codes
Guaranteed monotonic by design
over all codes
Lower deadband exists only if offset error
is negative
−60
ppm of
FSR/°C
ppm of
FSR/°C
dB
∆VDD = ±10%
200
μV
RL = 2 kΩ to GND or VDD
45
>10
−90
V
kΩ
MΩ
dB
Normal operation
Power-down mode
Frequency = 10 kHz
0.001
0.001
V
VDD −
0.001
0.5
25
16
2.5
5
VDD −
0.001
0.5
25
16
2.5
5
V
VDD
45
>10
−90
±1
0.8
0.6
0.5
0.25
37
VDD
±1
0.8
0.6
0.5
Rev. B | Page 3 of 28
Measure of the minimum drive
capabilities of the output amplifier
Measure of the maximum drive
capabilities of the output amplifier
Ω
mA
mA
μs
μs
VDD = 5 V
VDD = 3 V
Coming out of power-down mode, VDD = 5 V
Coming out of power-down mode, VDD = 3 V
μA
V
V
V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
AD5337/AD5338/AD5339
Parameter 1
Input High Voltage (VIH)
Pin Capacitance
LOGIC INPUTS (SCL, SDA)5
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Leakage Current (IIN)
Input Hysteresis (VHYST)
Min
2.4
2.1
2.0
A Grade
Typ
Max
3
B Grade
Typ
Max
3
VDD +
0.3
+0.3
VDD
±1
0.7
VDD
−0.3
0.05
VDD
Input Capacitance (CIN)
Glitch Rejection
0.7
VDD
–0.3
VDD +
0.3
+0.3
VDD
±1
0.05
VDD
8
LOGIC OUTPUT (SDA)5
Output Low Voltage (VOL)
Three-State Leakage
Current
Three-State Output
Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode) 7
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
Min
2.4
2.1
2.0
8
B Version 2 Conditions/Comments
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
V
SMBus compatible at VDD < 3.6 V
V
SMBus compatible at VDD < 3.6 V
μA
V
50
50
pF
ns
0.4
0.6
±1
0.4
0.6
±1
V
V
μA
8
2.5
Unit
V
V
V
pF
8
5.5
2.5
Input filtering suppresses noise spikes
of less than 50 ns
ISINK = 3 mA
ISINK = 6 mA
pF
5.5
V
VIH = VDD and VIL = GND
300
250
375
350
300
250
375
350
μA
μA
0.2
0.08
1.0
1.00
0.2
0.08
1.0
1.00
μA
μA
1
VIH = VDD and VIL = GND
IDD = 4 μA (max) during 0 readback on SDA
IDD = 1.5 μA (max) during 0 readback on SDA
See the Terminology section, for explanations of the specific parameters.
Temperature range for A Version and B Version: −40°C to +105°C; typical at 25°C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5337 (Code 8 to Code 248), AD5338, AD5338-1 (Code 28 to Code 995), AD5339 (Code 115 to Code 3981).
5
Guaranteed by design and characterization; not production tested.
6
For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive.
7
IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
2
Rev. B | Page 4 of 28
AD5337/AD5338/AD5339
AC CHARACTERISTICS
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
2, 3
Parameter
Output Voltage Settling Time
AD5337
AD5338
AD5339
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
A Version and B Version 1
Min
Typ
Max
6
7
8
0.7
12
1
1
3
200
−70
8
9
10
Unit
μs
μs
μs
V/μs
nV-s
nV-s
nV-s
nV-s
kHz
dB
1
Temperature range for A Version and B Version: −40°C to +105°C; typical at 25°C.
Guaranteed by design and characterization; not production tested.
3
See the Terminology section for explanations of the specific parameters.
2
Rev. B | Page 5 of 28
Conditions/Comments
VREF = VDD = 5 V
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 to 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
1 LSB change around major carry
VREF = 2 V ± 0.1 V p-p
VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz
AD5337/AD5338/AD5339
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
fSCL
t1
t2
t3
t4
t5
t6 1
t7
t8
t9
t10
t11
CB
2
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Conditions/Comments
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT, data hold time
tHD, DAT, data hold time
tSU, STA, setup time for repeated start
tSU, STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 VDD and 0.7 VDD.
SDA
t9
t3
t10
t11
t4
SCL
t4
START
CONDITION
t6
t2
t5
t7
REPEATED
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. B | Page 6 of 28
t1
t8
STOP
CONDITION
03756-002
1
Limit at TMIN, TMAX
A Version and B Version
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1 CB 2
400
AD5337/AD5338/AD5339
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
SCL, SDA to GND
A0 to GND
Reference Input Voltage to GND
VOUTA to VOUTB to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
MSOP Package
Power Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
(TJ max − TA) θJA
206°C/W
44°C/W
220 +5/−0°C
10 sec to 40 sec
Rev. B | Page 7 of 28
AD5337/AD5338/AD5339
VDD 1
VOUTA 2
VOUTB 3
REFIN 4
AD5337/
AD5338/
AD5339
TOP VIEW
(Not to Scale)
8
A0
7
SCL
6
SDA
5
GND
03756-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
VDD
VOUTA
VOUTB
REFIN
GND
SDA
7
SCL
8
A0
Description
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Reference Input Pin for the Two DACs. It has an input range from 0.25 V to VDD.
Ground Reference Point for All Circuitry on the Parts.
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift
register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift
register. Clock rates of up to 400 kbps can be accommodated in the 2-wire interface.
Address Input. Sets the least significant bit of the 7-bit slave address.
Rev. B | Page 8 of 28
AD5337/AD5338/AD5339
TERMINOLOGY
Relative Accuracy (Integral Nonlinearity, INL)
For the DAC, relative accuracy, or integral nonlinearity (INL),
is a measure, in LSBs, of the maximum deviation from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL vs. code plots can be seen in Figure 6, Figure 7, and
Figure 8.
Major-Code Transition Glitch Energy
The energy of the impulse injected into the analog output when
the code in the DAC register changes state. Normally specified
as the area of the glitch in nV-s, it is measured when the digital
code is changed by 1 LSB at the major carry transition (011...11
to 100...00 or 100...00 to 011...11).
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal 1
LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design.
Typical DNL vs. code plots can be seen in Figure 9, Figure 10,
and Figure 11.
Digital Feedthrough
A measure of the impulse injected into the analog output of the
DAC from the digital input pins of the device when the DAC
output is not being updated. Specified in nV-s and measured
with a worst-case change on the digital input pins, such as
changing from all 0s to all 1s or vice-versa.
Offset Error
A measure of the offset error of the DAC and the output
amplifier, expressed as a percentage of the full-scale range.
Gain Error
A measure of the span error of the DAC. It is the deviation in
slope of the actual DAC transfer characteristic from the ideal,
expressed as a percentage of the full-scale range.
Offset Error Drift
A measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift
A measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V and VDD is varied ±10%.
DC Crosstalk
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in μV.
Digital Crosstalk
The glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s, or
vice versa) in the input register of another DAC. It is expressed
in nV-s.
DAC-to-DAC Crosstalk
The glitch impulse transferred to the output of one DAC due to
a digital code change and subsequent output change of another
DAC. This includes both digital and analog crosstalk. It is
measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s, or vice versa) with the LDAC bit set low
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output.
Total Harmonic Distortion (THD)
The difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonic
distortion present in the DAC output. It is measured in dB.
Reference Feedthrough
The ratio of the amplitude of the signal at the DAC output to
the reference input when the DAC output is not being updated.
It is expressed in dB.
Rev. B | Page 9 of 28
AD5337/AD5338/AD5339
GAIN ERROR
PLUS
OFFSET ERROR
OUTPUT
VOLTAGE
ACTUAL
GAIN ERROR
PLUS
OFFSET ERROR
OUTPUT
VOLTAGE
IDEAL
ACTUAL
NEGATIVE
OFFSET
ERROR
POSITIVE
OFFSET
DAC CODE
DAC CODE
Figure 5. Transfer Function with Positive Offset
DEADBAND CODES
AMPLIFIER
FOOTROOM
(1mV)
03756-004
NEGATIVE
OFFSET
ERROR
Figure 4. Transfer Function with Negative Offset
Rev. B | Page 10 of 28
03756-005
IDEAL
AD5337/AD5338/AD5339
TYPICAL PERFORMANCE CHARACTERISTICS
0.3
1.0
TA = 25°C
VDD = 5V
TA = 25°C
VDD = 5V
0.2
DNL ERROR (LSB)
INL ERROR (LSB)
0.5
0
0.1
0
–0.1
–0.5
0
50
100
150
200
–0.3
250
03756-009
–1.0
03756-006
–0.2
0
50
100
Figure 6. AD5337 Typical INL Plot
250
800
1000
0.6
TA = 25°C
VDD = 5V
2
0.4
1
0.2
DNL ERROR (LSB)
0
–1
–2
TA = 25°C
VDD = 5V
0
–0.2
03756-007
–0.4
0
200
400
600
800
–0.6
1000
03756-010
INL ERROR (LSB)
200
Figure 9. AD5337 Typical DNL Plot
3
–3
150
CODE
CODE
0
200
400
CODE
600
CODE
Figure 7. AD5338 Typical INL Plot
Figure 10. AD5338 Typical DNL Plot
1.0
12
TA = 25°C
VDD = 5V
TA = 25°C
VDD = 5V
8
DNL ERROR (LSB)
0
–4
0
–0.5
–12
0
500
1000
1500
2000
2500
3000
3500
4000
–1.0
03756-011
–8
03756-008
INL ERROR (LSB)
0.5
4
0
500
1000
1500
2000
2500
3000
CODE
CODE
Figure 11. AD5339 Typical DNL Plot
Figure 8. AD5339 Typical INL Plot
Rev. B | Page 11 of 28
3500
4000
AD5337/AD5338/AD5339
0.2
0.50
TA = 25°C
VDD = 5V
TA = 25°C
VREF = 2V
0.1
GAIN ERROR
0
0.25
ERROR (%)
ERROR (LSB)
MAX DNL
MAX INL
0
MIN DNL
–0.1
–0.2
–0.3
–0.4
–0.25
MIN INL
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
03756-015
03756-012
–0.50
OFFSET ERROR
–0.5
–0.6
0
5.0
1
2
5
6
5
0.5
VDD = 5V
VREF = 3V
5V SOURCE
4
0.3
MAX INL
0.2
0.1
VOUT (V)
ERROR (LSB)
4
Figure 15. Offset Error and Gain Error vs. VDD
Figure 12. AD5337 INL and DNL Error vs. VREF
0.4
3
VDD (V)
VREF (V)
MAX DNL
0
MIN DNL
–0.1
3
3V SOURCE
2
–0.2
03756-013
–0.4
–0.5
–40
0
5V SINK
1
40
80
03756-016
MIN INL
–0.3
3V SINK
0
120
0
1
2
3
4
5
6
SINK/SOURCE CURRENT (mA)
TEMPERATURE (°C)
Figure 16. VOUT Source and Sink Current Capability
Figure 13. AD5337 INL and DNL Error vs. Temperature
1.0
300
VDD = 5V
VREF = 2V
250
0.5
IDD (µA)
200
0
150
GAIN ERROR
100
–0.5
–1.0
–40
0
40
80
0
120
TA = 25°C
VDD = 5V
VREF = 2V
03756-017
50
03756-014
ERROR (%)
OFFSET ERROR
ZERO SCALE
FULL SCALE
CODE
TEMPERATURE (°C)
Figure 17. Supply Current vs. Code
Figure 14. AD5337 Offset Error and Gain Error vs. Temperature
Rev. B | Page 12 of 28
AD5337/AD5338/AD5339
300
TA = 25°C
VDD = 5V
VREF = 5V
–40°C
250
CH1
+25°C
IDD (µA)
200
+105°C
VOUTA
150
100
SCL
CH2
03756-018
03756-021
50
0
2.5
3.0
3.5
4.0
4.5
5.0
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
5.5
VDD (V)
Figure 21. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
Figure 18. Supply Current vs. Supply Voltage
0.5
TA = 25°C
VDD = 5V
VREF = 2V
0.4
CH1
IDD (µA)
0.3
VDD
–40°C
0.2
+25°C
CH2
VOUTA
0
2.5
3.0
3.5
4.0
4.5
03756-019
+105°C
03756-022
0.1
5.0
CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV
5.5
VDD (V)
Figure 22. Power-On Reset to 0 V
Figure 19. Power-Down Current vs. Supply Voltage
400
TA = 25°C
350
300
CH1
DECREASING
250
IDD (µA)
TA = 25°C
VDD = 5V
VREF = 2V
VDD = 5V
INCREASING
VOUTA
VDD = 3V
200
SCL
150
100
CH2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
03756-023
0
03756-020
50
CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV
5.0
VLOGIC (V)
Figure 20. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage
Increasing and Decreasing
Rev. B | Page 13 of 28
Figure 23. Existing Power-Down to Midscale
AD5337/AD5338/AD5339
0.02
03756-024
FREQUENCY
150
200
250
0.01
0
–0.01
–0.02
300
IDD (µA)
03756-027
VDD = 5V
FULL-SCALE ERROR (V)
VDD = 3V
TA = 25°C
VDD = 5V
0
1
2
3
4
5
6
VREF (V)
Figure 24. IDD Histogram with VDD = 3 V and VDD = 5 V
Figure 27. Full-Scale Error vs. VREF
2.50
VOUT (V)
1mV/DIV
2.49
03756-025
2.47
50ns/DIV
1µs/DIV
Figure 28. DAC-to-DAC Crosstalk
Figure 25. AD5339 Major-Code Transition Glitch Energy
10
0
–10
dB
–20
–30
–40
03756-026
–50
–60
03756-028
2.48
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 26. Multiplying Bandwidth (Small-Signal Frequency Response)
Rev. B | Page 14 of 28
AD5337/AD5338/AD5339
THEORY OF OPERATION
The AD5337/AD5338/AD5339 are dual resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and
12 bits, respectively. Each part contains two output buffer
amplifiers and is written to via a 2-wire serial interface. The
DACs operate from single supplies of 2.5 V to 5.5 V, and the
output buffer amplifiers provide rail-to-rail output swing with a
slew rate of 0.7 V/μs. The two DACs share a single reference
input pin. Each DAC has three programmable power-down
modes that allow the output amplifier to be configured with
either a 1 kΩ load to ground, a 100 kΩ load to ground, or as a
high impedance three-state output.
R
R
R
03756-030
R
DIGITAL-TO-ANALOG CONVERTER SECTION
Figure 30. Resistor String
The architecture of one DAC channel consists of a resistorstring DAC followed by an output buffer amplifier. The voltage
at the REFIN pin provides the reference voltage for the DAC.
Figure 29 shows a block diagram of the DAC architecture.
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
VOUT =
TO OUTPUT
AMPLIFIER
R
VREF × D
2N
DAC REFERENCE INPUTS
There is a single reference input pin for the two DACs. The
reference input is unbuffered. The user can have a reference
voltage as low as 0.25 V and as high as VDD, because there is no
restriction due to headroom and foot room of any reference
amplifier.
It is recommended to use a buffered reference in the external
circuit, for example, REF192. The input impedance is typically
45 kΩ.
where:
D is the decimal equivalent of the binary code, which is loaded
to the DAC register
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, which gives an output range of 0 V to
VDD when the reference is VDD. The amplifier is capable of
driving a load of 2 kΩ to GND or VDD in parallel with 500 pF to
GND or VDD. The source and sink capabilities of the output
amplifier can be seen in the plot in Figure 16.
0 to 255 for AD5337 (8 bits)
0 to 1023 for AD5338 and AD5338-1 (10 bits)
0 to 4095 for AD5339 (12 bits)
N is the DAC resolution
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at 8 bits) of 6 μs.
REFIN
POWER-ON RESET
DAC
REGISTER
RESISTOR
STRING
VOUTA
03756-029
INPUT
REGISTER
OUTPUT BUFFER
AMPLIFIER
Figure 29. DAC Channel Architecture
RESISTOR STRING
The resistor string portion is shown in Figure 30. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines the node at which the voltage is
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches that connects the
string to the amplifier. Because the DAC comprises a string
of resistors, it is guaranteed to be monotonic.
The AD5337/AD5338/AD5339 power on in a defined state via a
power-on reset function. The power-on state is normal
operation, with output voltage set to 0 V.
Both input and DAC registers are filled with zeros until a valid
write sequence is made to the device. This is particularly useful
in applications where it is important to know the state of the
DAC outputs while the device is powering on.
Rev. B | Page 15 of 28
AD5337/AD5338/AD5339
Read/Write Sequence
2
The AD5337/AD5338/AD5339 are controlled via an I Ccompatible serial bus. The DACs are connected to this bus as
slave devices, that is, no clock is generated by the AD5337/
AD5338/AD5339 DACs. This interface is SMBus compatible at
VDD < 3.6 V.
The AD5337/AD5338/AD5339 have a 7-bit slave address. The
six MSBs are 000110, and the LSB is determined by the state of
the A0 pin. The facility of making hardwired changes to A0
allows the use of one or two of these devices on one bus. The
AD5338-1 has a unique 7-bit slave address. The six MSBs are
010001, and the LSB is again determined by the state of the A0
pin. Using a combination of AD5338 and AD5338-1 allows the
user to accommodate four of these dual 10-bit devices (eight
channels) on the same bus.
For the AD5337/AD5338/AD5339, all write access sequences
and most read sequences begin with the device address (with
R/W = 0), followed by the pointer byte. This pointer byte specifies
which DAC is being accessed in the subsequent read/write
operation (see Figure 31). In a write operation, the data follows
immediately. In a read operation, the address is resent with
R/W = 1, and then the data is read back. However, it is also
possible to perform a read operation by sending only the
address with R/W = 1. The previously loaded pointer settings
are then used for the read back operation. See Figure 32 for a
graphical explanation of the interface.
MSB
X
LSB
0
X
0
0
DACB DACA
Figure 31. Pointer Byte
The 2-wire serial bus protocol operates as follows:
1.
0
03756-031
SERIAL INTERFACE
The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address, followed by
an R/W bit. (This bit determines whether data is read from
or written to the slave device.)
The slave with the address corresponding to the transmitted
address responds by pulling SDA low during the ninth
clock pulse (this is termed the acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its shift register.
2.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits, followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high period
of SCL.
3.
When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a No
Acknowledge for the ninth clock pulse, that is, the SDA
line remains high. The master then brings the SDA line low
before the 10th clock pulse and high during the 10th clock
pulse to establish a stop condition.
Table 6 explains the individual bits that make up the pointer byte.
Table 6. Pointer Byte Bits
Pointer Byte Bit
X
0
DACB
DACA
Description
Don’t care bits.
This bit is reserved and must be set to 0
1: The following data bytes are for DAC B.
1: The following data bytes are for DAC A.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as two data bytes on the serial data line, SDA, under the
control of the serial clock input, SCL. The timing diagram for this
operation is shown in Figure 2. The two data bytes consist of four
control bits followed by 8, 10, or 12 bits of DAC data, depending
on the device type. The first two bits loaded are Bit PD1 and
Bit PD0, which control the mode of operation of the device.
See the Power-Down Modes section for a complete description.
Bit 13 is CLR, Bit 12 is LDAC, and the remaining bits are leftjustified DAC data bits, starting with the MSB (see Figure 32).
Table 7. Input Shift Register
Register
CLR
Setting
0
LDAC
1
0
1
Rev. B | Page 16 of 28
Result
All DAC registers and input registers are
filled with 0s on completion of the write
sequence.
Normal operation.
The two DAC registers and, therefore, all
DAC outputs, simultaneously updated on
completion of the write sequence.
Addressed input register only is updated.
There is no change in the contents of the
DAC registers.
AD5337/AD5338/AD5339
Default Read Back Condition
Multiple DAC Read Back Sequence
All pointer byte bits power-up to 0. Therefore, if the user
initiates a readback without writing to the pointer byte first, no
single DAC channel has been specified. In this case, the default
readback bits are all 0s, except for the CLR bit, which is 1.
If the user attempts to read back data from more than one DAC
at a time, the part reads back the default, power-on reset
conditions, that is, all 0s except for CLR, which is 1.
Multiple DAC Write Sequence
When writing to the AD5337/AD5338/AD5339 DACs, the user
must begin with an address byte (R/W = 0), after which the
DAC acknowledges that it is prepared to receive data by pulling
SDA low. This address byte is followed by the pointer byte,
which is also acknowledged by the DAC. Two bytes of data are
then written to the DAC, as shown in Figure 33. A stop
condition follows.
WRITE OPERATION
MOST SIGNIFICANT DATA BYTE
8-BIT AD5337
MSB
PD1
PD0
CLR
PD0
CLR
PD0
CLR
MSB
PD1
D7
D6
LDAC
D9
D8
D7
D10
D9
12-BIT AD5339
LDAC
D11
MSB
D4
D3
LSB
MSB
D6
D5
LSB
MSB
D8
D7
D5
10-BIT AD5338
MSB
PD1
LDAC
LSB
LEAST SIGNIFICANT DATA BYTE
8-BIT AD5337
D2
D1
D0
X
X
LSB
X
10-BIT AD5338
D4
D3
D6
D5
D2
D1
D0
X
D2
D1
D3
X
LSB
12-BIT AD5339
D4
X
LSB
D0
03756-032
Because there are individual bits in the pointer byte for each
DAC, it is possible to write the same data and control bits to two
DACs simultaneously by setting the relevant bits to 1.
Figure 32. Data Formats for Write and Read Back
SCL
SDA
0
0
START
CONDITION
BY
MASTER
0
1
1
ADDRESS BYTE
0
A0
R/W
X
ACK
BY
AD533x
LSB
X
MSB
POINTER BYTE
ACK
BY
AD533x
SCL
MSB
MOST SIGNIFICANT DATA BYTE
LSB
ACK
BY
AD533x
MSB
LEAST SIGNIFICANT DATA BYTE
Figure 33. Write Sequence
Rev. B | Page 17 of 28
LSB
ACK
BY
AD533x
STOP
CONDITION
BY
MASTER
03756-033
SDA
AD5337/AD5338/AD5339
READ OPERATION
Note that in a read sequence, data bytes are the same as those in
the write sequence, except that don’t cares are read back as 0s.
However, if the master sends an ACK and continues clocking
SCL (no stop is sent), the DAC retransmits the same two bytes
of data on SDA. This allows continuous read back of data from
the selected DAC register. Alternatively, the user can send a
start followed by the address with R/W = 1. In this case, the
previously loaded pointer settings are used and read back of
data can begin immediately.
When reading data back from the AD5337/AD5338/AD5339
DACs, the user begins with an address byte (R/W = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. This address byte is usually followed by the
pointer byte, which is also acknowledged by the DAC. Then, the
master initiates another start condition (repeated start) and the
address is resent with R/W = 1. This is acknowledged by the
DAC indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC as shown in Figure 34.
A stop condition follows.
SCL
0
SDA
0
0
1
START
CONDITION
BY
MASTER
0
1
A0
R/W
X
ADDRESS BYTE
LSB
X
ACK
MSB
BY
AD533x
POINTER BYTE
ACK
BY
AD533x
SCL
SDA
0
REPEATED
START
CONDITION
BY
MASTER
0
0
1
1
0
MSB
R/W
A0
ACK
BY
AD533x
ADDRESS BYTE
LSB
DATA BYTE
ACK
BY
MASTER
SCL
MSB
LSB
LEAST SIGNIFICANT DATA BYTE
NO
ACK
BY
MASTER
STOP
CONDITION
BY
MASTER
Figure 34. Read Sequence
Rev. B | Page 18 of 28
03756-034
SDA
AD5337/AD5338/AD5339
The AD5337/AD5338/AD5339 DACs have a double-buffered
interface consisting of two banks of registers—an input register
and a DAC register per channel. The input register is directly
connected to the input shift register, and the digital code is
transferred to the relevant input register upon completion of a
valid write sequence. The DAC register contains the digital code
used by the resistor string.
Access to the DAC register is controlled by the LDAC bit.
When the LDAC bit is set high, the DAC register is latched
and therefore, the input register can change state without
affecting the DAC register. This is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to three of the input registers individually; by setting the LDAC
bit low when writing to the remaining DAC input register, all
outputs update simultaneously.
When both bits are 0, the DAC works with its normal power
consumption of 300 μA at 5 V. However, for the three powerdown modes, the supply current falls to 200 nA at 5 V (80 nA at
3 V). Not only does the supply current drop, but the output
stage is also internally switched from the output of the amplifier
to a resistor network of known values. This is advantageous in
that the output impedance of the part is known while the part is
in power-down mode, which provides a defined input condition
for whatever is connected to the output of the DAC amplifier.
There are three options. The output can be connected internally
to GND through a 1 kΩ resistor, a 100 kΩ resistor, or can be left
open-circuited (three-state). Resistor tolerance = ±20%. The
output stage is illustrated in Figure 35.
RESISTOR
STRING DAC
These parts contain an extra feature whereby the DAC register
is only updated if its input register has been updated since the
last time that LDAC was brought low, thereby removing
unnecessary digital crosstalk.
POWER-DOWN MODES
The AD5337/AD5338/AD5339 have very low power consumption,
typically dissipating 0.75 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bit 15 and Bit 14
(PD1 and PD0) of the data byte. Table 8 shows how the state of
the bits corresponds to the mode of operation of the DAC.
POWER-DOWN
CIRCUITRY
PD0
0
1
0
1
VOUT
RESISTOR
NETWORK
Figure 35. Output Stage during Power-Down
The bias generator, output amplifiers, resistor string, and all
other associated linear circuitry are shut down when powerdown mode is activated. However, the contents of the DAC
registers remain unchanged when power-down mode is activated.
The time to exit power-down is typically 2.5 μs for VDD = 5 V
and 5 μs when VDD = 3 V. This is the time from the rising edge
of the eighth SCL pulse to the time when the output voltage
deviates from its power-down voltage (see Figure 23 for a plot).
Table 8. PD1/PD0 Operating Modes
PD1
0
0
1
1
AMPLIFIER
03756-035
DOUBLE-BUFFERED INTERFACE
Operating Mode
Normal Operation
Power-Down (1 kΩ load to GND)
Power-Down (100 kΩ load to GND)
Power-Down (three-state output)
Rev. B | Page 19 of 28
AD5337/AD5338/AD5339
APPLICATIONS
TYPICAL APPLICATION CIRCUIT
BIPOLAR OPERATION
The AD5337/AD5338/AD5339 can be used with a wide range of
reference voltages for full, one-quadrant multiplying capability
over a reference range of 0 V to VDD. More typically, these
devices are used with a fixed precision reference voltage.
Suitable references for 5 V operation are the AD780, the REF192,
and the ADR391 (2.5 V references). For 2.5 V operation, a
suitable external reference would be the AD589 or AD1580, a
1.23 V band gap reference. Figure 36 shows a typical setup for
the AD5337/AD5338/AD5339 when using an external reference.
Note that A0 can be high or low.
The AD5337/AD5338/AD5339 are designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 37. This circuit gives an output voltage range of
±5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
R2 = 10kΩ
+5V
6V TO 12V
VDD = 2.5V TO 5.5V
10µF
–5V
VOUTB
1µF
A0
GND SCL SDA
VOUTB
1µF
SDA
A0
03756-037
2-WIRE
SERIAL
INTERFACE
SCL
Figure 37. Bipolar Operation with the AD5339
GND
SERIAL
INTERFACE
The output voltage for any input code can be calculated as
follows:
R2 ⎤
D
R1 + R2
⎡
− REFIN × ⎥
VOUT = ⎢⎛⎜ REFIN × N ⎞⎟ ×
2 ⎠
R1 ⎦
R1
⎣⎝
Figure 36. AD5337/AD5338/AD5339 Using External Reference
If an output range of 0 V to VDD is required, the simplest
solution is to connect the reference input to VDD. Because this
supply can be inaccurate and noisy, the AD5337/AD5338/
AD5339 can be powered from a reference voltage, for example,
using a 5 V reference such as the REF195, which provides a
steady output supply voltage. With no load on the DACs, the
REF195 is required to supply 600 μA supply current to the DAC
and 112 μA to the reference input. When the DAC outputs are
loaded, the REF195 also needs to supply the current to the
loads; therefore, the total current required with a 10 kΩ load on
each output is
712 μA + 2 × (5 V/10 kΩ) = 1.7 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 3.4 ppm (17 μV) for the 1.7 mA
current drawn from it. This corresponds to a 0.0009 LSB error
at 8 bits and a 0.014 LSB error at 12 bits.
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
REFIN is the reference voltage input.
With REFIN = 5 V, R1 = R2 = 10 kΩ:
VOUT = (10 × D/2N) − 5
MULTIPLE DEVICES ON ONE BUS
Figure 38 shows two AD5339 devices on the same serial bus.
Each has a different slave address because the state of the A0 pin
is different. This allows each of four DACs to be written to or
read from independently.
VDD
PULL-UP
RESISTORS
A0
AD5339
SDA
SCL
MICROCONTROLLER
SDA
A0
SCL
AD5339
Figure 38. Multiple AD5339 Devices on One Bus
Rev. B | Page 20 of 28
03756-038
AD780/REF192/ADR391
WITH VDD = 5V OR
AD589/AD1580 WITH
VDD = 2.5V
±5V
VOUTA
AD5339
REFIN
VOUT
AD820/
OP295
VDD
REFIN
VOUTA
03756-036
EXT
REF
+5V
VOUT
GND
AD5337/
AD5338/
AD5339
VIN
0.1µF
AD1585
VIN
0.1µF
R1 = 10kΩ
10µF
AD5337/AD5338/AD5339
PRODUCT AS A DIGITALLY PROGRAMMABLE
WINDOW DETECTOR
POWER SUPPLY DECOUPLING
Figure 39 shows a digitally programmable upper/lower limit
detector using the two DACs in the AD5337/AD5338/AD5339.
The upper and lower limits for the test are loaded into DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the VIN input is not within the programmed window,
an LED indicates the fail condition.
5V
0.1µF
VREF
10µF
VIN
1kΩ
1kΩ
FAIL
PASS
VDD
REFIN
VOUTA
AD5337/
AD5338/
AD53391
DIN
SDA
SCL
SCL
1/2
CMP04
PASS/FAIL
VOUTB
1/6 74HC05
03756-039
GND
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. Window Detection
COARSE AND FINE ADJUSTMENT CAPABILITIES
The two DACs in the AD5337/AD5338/AD5339 can be paired
together to form a coarse and fine adjustment function, as
shown in Figure 40. DAC A is used to provide the coarse
adjustment while DAC B provides the fine adjustment. Varying
the ratio of R1 and R2 changes the relative effect of the coarse
and fine adjustments. With the resistor values and external
reference shown, the output amplifier has unity gain for the
DAC A output, thus, the output range is 0 V to 2.5 V − 1 LSB.
For DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B
a range equal to 19 mV.
The circuit is shown with a 2.5 V reference, but reference
voltages up to VDD can be used. The op amps indicated allow a
rail-to-rail output swing.
VDD = 5V
VIN
EXT
REF VOUT
GND
R4
390Ω
10µF
5V
REFIN
VOUT
VDD
VOUTA
1µF
AD780/REF192/ADR391
WITH VDD = 5V
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough on the board. Using a
microstrip technique is the best solution, but its use is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground plane,
while signal traces are placed on the solder side.
AD5337/
AD5338/
AD53391
GND
VOUTB
R1
390Ω
R2
51.2kΩ
1ADDITIONAL PINS OMITTED FOR CLARITY.
AD820/
OP295
03756-040
0.1µF
R3
51.2kΩ
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5337/AD5338/AD5339 are mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5337/AD5338/AD5339
are in a system where multiple devices require an AGND-toDGND connection, the connection should be made at one
point only. The star ground point should be established as close
as possible to the device. The AD5337/AD5338/AD5339 should
have ample supply bypassing of 10 μF in parallel with 0.1 μF on
the supply located as close to the package as possible, ideally
right up against the device. The 10 μF capacitors are the tantalum
bead type. The 0.1 μF capacitor should have low effective series
resistance (ESR) and low effective series inductance (ESI) to
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching. The
power supply lines of the AD5337/AD5338/AD5339 should use
as large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
they should never be run near the reference inputs. A ground
line routed between the SDA and SCL lines helps to reduce
crosstalk between them. This is not required on a multilayer
board because there is a separate ground plane, but separating
the lines does help.
Figure 40. Coarse/Fine Adjustment
Rev. B | Page 21 of 28
AD5337/AD5338/AD5339
Table 9. Overview of All AD53xx Serial Devices
Part No.
Singles
AD5300
AD5310
AD5320
AD5301
AD5311
AD5321
Duals
AD5302
AD5312
AD5322
AD5303
AD5313
AD5323
AD5337
AD5338
AD5338-1
AD5339
Quads
AD5304
AD5314
AD5324
AD5305
AD5315
AD5325
AD5306
AD5316
AD5326
AD5307
AD5317
AD5327
Octals
AD5308
AD5318
AD5328
Resolution (Bits)
No. of DACs
DNL (LSBs)
Interface
Settling Time (μs)
Package
Pins
8
10
12
8
10
12
1
1
1
1
1
1
±0.25
±0.50
±1.00
±0.25
±0.50
±1.00
SPI
SPI
SPI
2-Wire
2-Wire
2-Wire
4
6
8
6
7
8
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
6, 8
6, 8
6, 8
6, 8
6, 8
6, 8
8
10
12
8
10
12
8
10
10
12
2
2
2
2
2
2
2
2
2
2
±0.25
±0.50
±1.00
±0.25
±0.50
±1.00
±0.25
±0.50
±0.50
±1.00
SPI
SPI
SPI
SPI
SPI
SPI
2-Wire
2-Wire
2-Wire
2-Wire
6
7
8
6
7
8
6
7
7
8
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
MSOP
MSOP
MSOP
MSOP
8
8
8
16
16
16
8
8
8
8
8
10
12
8
10
12
8
10
12
8
10
12
4
4
4
4
4
4
4
4
4
4
4
4
±0.25
±0.50
±1.00
±0.25
±0.50
±1.00
±0.25
±0.50
±1.00
±0.25
±0.50
±1.00
SPI
SPI
SPI
2-Wire
2-Wire
2-Wire
2-Wire
2-Wire
2-Wire
SPI
SPI
SPI
6
7
8
6
7
8
6
7
8
6
7
8
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
10
10
10
10
10
10
16
16
16
16
16
16
8
10
12
8
8
8
±0.25
±0.50
±1.00
SPI
SPI
SPI
6
7
8
TSSOP
TSSOP
TSSOP
16
16
16
Rev. B | Page 22 of 28
AD5337/AD5338/AD5339
Table 10. Overview of AD53xx Parallel Devices
Part No.
Singles
AD5330
AD5331
AD5340
AD5341
Duals
AD5332
AD5333
AD5342
AD5343
Quads
AD5334
AD5335
AD5336
AD5344
Octals
AD5346
AD5347
AD5348
Resolution (Bits)
DNL (LSBs)
VREF Pins
Settling Time (μs)
8
10
12
12
±0.25
±0.50
±1.00
±1.00
1
1
1
1
6
7
8
8
8
10
12
12
±0.25
±0.50
±1.00
±1.00
2
2
2
1
6
7
8
8
8
10
10
12
±0.25
±0.50
±0.50
±1.00
2
2
4
4
6
7
7
8
8
10
12
±0.25
±0.50
±1.00
4
4
4
6
7
8
Rev. B | Page 23 of 28
Additional Pin Functions
BUF GAIN HBEN CLR
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Package
Pins
TSSOP
TSSOP
TSSOP
TSSOP
20
20
24
20
√
√
√
√
TSSOP
TSSOP
TSSOP
TSSOP
20
24
28
20
√
√
√
√
TSSOP
TSSOP
TSSOP
TSSOP
24
24
28
28
√
√
√
√
√
√
TSSOP, LFCSP
TSSOP, LFCSP
TSSOP, LFCSP
38, 40
38, 40
38, 40
√
√
√
√
√
√
√
√
AD5337/AD5338/AD5339
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5
5.15
4.90
4.65
4
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 41. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. B | Page 24 of 28
0.80
0.60
0.40
AD5337/AD5338/AD5339
ORDERING GUIDE
Model
AD5337ARM
AD5337ARM-REEL7
AD5337ARMZ 1
AD5337ARMZ-REEL71
AD5337BRM
AD5337BRM-REEL
AD5337BRM-REEL7
AD5337BRMZ1
AD5337BRMZ-REEL1
AD5337BRMZ-REEL71
AD5338ARM
AD5338ARM-REEL7
AD5338ARMZ1
AD5338ARMZ-REEL71
AD5338ARMZ-11
AD5338ARMZ-1REEL71
AD5338BRM
AD5338BRM-REEL
AD5338BRM-REEL7
AD5338BRMZ1
AD5338BRMZ-11
AD5338BRMZ-1REEL71
AD5339ARM
AD5339ARM-REEL7
AD5339ARMZ1
AD5339ARMZ-REEL71
AD5339BRM
AD5339BRM-REEL
AD5339BRM-REEL7
AD5339BRMZ1
AD5339BRMZ-REEL1
AD5339BRMZ-REEL71
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Z = Pb-free part, # denotes lead-free product, may be top or bottom marked.
Rev. B | Page 25 of 28
Package Option
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
D23
D23
D23#
D23#
D20
D20
D20
D20#
D20#
D20#
D24
D24
D5F
D5F
D57
D57
D21
D21
D21
D5H
D58
D58
D25
D25
D6P
D6P
D22
D22
D22
D6R
D6R
D6R
AD5337/AD5338/AD5339
NOTES
Rev. B | Page 26 of 28
AD5337/AD5338/AD5339
NOTES
Rev. B | Page 27 of 28
AD5337/AD5338/AD5339
NOTES
Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent
Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03756-0-9/06(B)
Rev. B | Page 28 of 28
