AD5343

a 2.5 V to 5.5 V, 500 A, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs AD5334/AD5335/AD5336/AD5344* GENERAL DESCRIPTION FEATURES AD5334: Quad 8-Bit DAC in 24-Lead TSSOP AD5335: Quad 10-Bit DAC in 24-Lead TSSOP AD5336: Quad 10-Bit DAC in 28-Lead TSSOP AD5344: Quad 12-Bit DAC in 28-Lead TSSOP Low Power Operation: 500 A @ 3 V, 600 A @ 5 V Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin 2.5 V to 5.5 V Power Supply Double-Buffered Input Logic Guaranteed Monotonic by Design Over All Codes Output Range: 0–VREF or 0–2 V REF Power-On Reset to Zero Volts Simultaneous Update of DAC Outputs via LDAC Pin Asynchronous CLR Facility Low Power Parallel Data Interface On-Chip Rail-to-Rail Output Buffer Amplifiers Temperature Range: –40 C to +105 C APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and 12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 500 µA at 3 V, and feature a power-down mode that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can drive the output to both supply rails. The AD5334/AD5335/AD5336/AD5344 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. The GAIN pin on the AD5334 and AD5336 allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF. Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin. On the AD5334, AD5335 and AD5336 an asynchronous CLR input is also provided. This resets the contents of the Input Register and the DAC Register to all zeros. These devices also incorporate a power-on-reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. The AD5334/AD5335/AD5336/AD5344 are available in Thin Shrink Small Outline Packages (TSSOP). AD5334 FUNCTIONAL BLOCK DIAGRAM (Other Diagrams Inside) VREFA/B VDD POWER-ON RESET GAIN DB7 . . . DB0 CS WR A0 A1 INPUT REGISTER DAC REGISTER 8-BIT DAC BUFFER AD5334 VOUTA INPUT REGISTER INTERFACE LOGIC INPUT REGISTER DAC REGISTER 8-BIT DAC BUFFER VOUTB DAC REGISTER 8-BIT 8-BIT DAC DAC BUFFER VOUTC INPUT REGISTER CLR LDAC DAC REGISTER 8-BIT DAC BUFFER TO ALL DACS AND BUFFERS POWER-DOWN LOGIC VOUTD *Protected by U.S. Patent Number 5,969,657; other patents pending. VREFC/D PD GND R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD5334/AD5335/AD5336/AD5344–SPECIFICATIONSotherwise noted.) (V = 2.5 V to 5.5 V, V = 2 V. R = 2 k to GND; C =200 pF to GND; all specifications T to T unless DD REF L L MIN MAX Parameter1 DC PERFORMANCE AD5334 Resolution Relative Accuracy Differential Nonlinearity AD5335/AD5336 Resolution Relative Accuracy Differential Nonlinearity AD5344 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Deadband5 Upper Deadband Offset Error Drift6 Gain Error Drift6 DC Power Supply Rejection Ratio6 DC Crosstalk6 DAC REFERENCE INPUT6 VREF Input Range VREF Input Impedance 3, 4 Min B Version Typ Max 2 Unit Conditions/Comments 8 ± 0.15 ± 0.02 10 ± 0.5 ± 0.05 12 ±2 ± 0.2 ± 0.4 ± 0.1 10 10 –12 –5 –60 200 ±1 ± 0.25 ±4 ± 0.5 ± 16 ±1 ±3 ±1 60 60 Bits LSB LSB Bits LSB LSB Bits LSB LSB % of FSR % of FSR mV mV ppm of FSR/°C ppm of FSR/°C dB µV Guaranteed Monotonic By Design Over All Codes Guaranteed Monotonic By Design Over All Codes Guaranteed Monotonic By Design Over All Codes Lower Deadband Exists Only if Offset Error Is Negative VDD = 5 V. Upper Deadband Exists Only if VREF = VDD ∆VDD = ± 10% RL = 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND; Gain = 0 0.25 180 90 90 45 –90 –90 VDD Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS6 Minimum Output Voltage4, 7 Maximum Output Voltage4, 7 DC Output Impedance Short Circuit Current Power-Up Time LOGIC INPUTS6 Input Current VIL, Input Low Voltage V kΩ kΩ kΩ kΩ dB dB V min V max Ω mA mA µs µs µA V V V V V V pF V µA µA µA µA Gain = 1. Input Impedance = RDAC (AD5336/AD5344) Gain = 2. Input Impedance = RDAC (AD5336) Gain = 1. Input Impedance = RDAC (AD5334/AD5335) Gain = 2. Input Impedance = RDAC (AD5334) Frequency = 10 kHz Frequency = 10 kHz Rail-to-Rail Operation 0.001 VDD – 0.001 0.5 50 20 2.5 5 ±1 0.8 0.6 0.5 2.4 2.1 2.0 3.5 2.5 600 500 0.2 0.08 5.5 900 700 1 1 VDD = 5 V VDD = 3 V Coming Out of Power-Down Mode. VDD = 5 V Coming Out of Power-Down Mode. VDD = 3 V VIH, Input High Voltage VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V All DACs active and excluding load currents. VIH = VDD, VIL = GND. IDD increases by 50 µA at VREF > VDD – 100 mV. NOTES 1 See Terminology section. 2 Temperature range: B Version: –40 °C to +105 °C; typical specifications are at 25°C. 3 Linearity is tested using a reduced code range: AD5334 (Code 8 to 255); AD5335/AD5336 (Code 28 to 1023); AD5344 (Code 115 to 4095). 4 DC specifications tested with outputs unloaded. 5 This corresponds to x codes. x = Deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V REF = VDD and “Offset plus Gain” Error must be positive. Specifications subject to change without notice. –2– REV. 0 AD5334/AD5335/AD5336/AD5344 AC CHARACTERISTICS1 wise noted.) Parameter 2 (VDD = 2.5 V to 5.5 V. RL = 2 k to GND; CL = 200 pF to GND. All specifications TMIN to TMAX unless other- B Version3 Min Typ Max 6 7 7 8 0.7 8 0.5 3 0.5 3.5 200 –70 8 9 9 10 Unit µs µs µs µs V/µs nV-s nV-s nV-s nV-s nV-s kHz dB Conditions/Comments VREF = 2 V. See Figure 20 1/4 Scale to 3/4 Scale Change (40 H to C0 H) 1/4 Scale to 3/4 Scale Change (100 H to 300 H) 1/4 Scale to 3/4 Scale Change (100 H to 300 H) 1/4 Scale to 3/4 Scale Change (400 H to C00 H) 1 LSB Change Around Major Carry Output Voltage Settling Time AD5334 AD5335 AD5336 AD5344 Slew Rate Major Code Transition Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion VREF = 2 V ± 0.1 V p-p. Unbuffered Mode VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz NOTES 1 Guaranteed by design and characterization, not production tested. 2 See Terminology section. 3 Temperature range: B Version: –40 °C to +105°C; typical specifications are at 25 °C. Specifications subject to change without notice. TIMING CHARACTERISTICS1, 2, 3 (V Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Limit at TMIN, TMAX 0 0 20 5 4.5 5 5 4.5 5 4.5 20 20 50 20 0 DD = 2.5 V to 5.5 V, All specifications TMIN to TMAX unless otherwise noted.) Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Condition/Comments CS to WR Setup Time CS to WR Hold Time WR Pulsewidth Data, GAIN, HBEN Setup Time Data, GAIN, HBEN Hold Time Synchronous Mode. WR Falling to LDAC Falling. Synchronous Mode. LDAC Falling to WR Rising. Synchronous Mode. WR Rising to LDAC Rising. Asynchronous Mode. LDAC Rising to WR Rising. Asynchronous Mode. WR Rising to LDAC Falling. LDAC Pulsewidth CLR Pulsewidth Time Between WR Cycles A0, A1 Setup Time A0, A1 Hold Time t1 CS NOTES 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. 3 See Figure 1. Specifications subject to change without notice. t2 t3 t 13 t4 t6 t5 WR DATA, GAIN, HBEN LDAC 1 t7 t9 t8 t 10 t 11 LDAC 2 CLR A0, A1 NOTES: t 14 t 15 t 12 1 SYNCHRONOUS LDAC UPDATE MODE 2 ASYNCHRONOUS LDAC UPDATE MODE Figure 1. Parallel Interface Timing Diagram REV. 0 –3– AD5334/AD5335/AD5336/AD5344 ABSOLUTE MAXIMUM RATINGS * (TA = 25°C unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Digital Input Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V Digital Output Voltage to GND . . . . . . –0.3 V to VDD + 0.3 V Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V VOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C TSSOP Package Power Dissipation . . . . . . . . . . . . . . . (TJ max – TA)/θJA mW θJA Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W θJA Thermal Impedance (28-Lead TSSOP) . . . . . 97.9°C/W θJC Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W θJC Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C Time at Peak Temperature . . . . . . . . . . . . .10 sec to 40 sec *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model AD5334BRU AD5335BRU AD5336BRU AD5344BRU Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) Package Option RU-24 RU-24 RU-28 RU-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5334/AD5335/AD5336/AD5344 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –4– REV. 0 AD5334/AD5335/AD5336/AD5344 AD5334 FUNCTIONAL BLOCK DIAGRAM VREFA/B VDD AD5334 PIN CONFIGURATION VREFC/D 1 POWER-ON RESET GAIN DB7 . . . DB0 CS WR A0 A1 INPUT REGISTER DAC REGISTER 8-BIT DAC BUFFER VOUTA 24 23 22 21 CLR GAIN DB7 DB6 DB5 AD5334 VREFA/B 2 VOUTA 3 VOUTB 4 VOUTC 5 VOUTD 6 8-BIT AD5334 20 TOP VIEW 19 DB4 GND 7 (Not to Scale) 18 DB3 CS 8 WR 9 A0 10 A1 11 17 16 15 14 13 INPUT REGISTER INTERFACE LOGIC INPUT REGISTER DAC REGISTER 8-BIT DAC BUFFER VOUTB DB2 DB1 DB0 VDD PD DAC REGISTER 8-BIT 8-BIT DAC DAC BUFFER VOUTC LDAC 12 INPUT REGISTER CLR LDAC DAC REGISTER 8-BIT DAC BUFFER TO ALL DACS AND BUFFERS POWER-DOWN LOGIC VOUTD VREFC/D PD GND AD5334 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15–22 23 24 Mnemonic VREFC/D VREFA/B VOUTA VOUTB VOUTC VOUTD GND CS WR A0 A1 LDAC PD VDD DB0–DB7 GAIN CLR Function Unbuffered Reference Input for DACs C and D. Unbuffered Reference Input for DACs A and B. Output of DAC A. Buffered Output with Rail-to-Rail Operation. Output of DAC B. Buffered Output with Rail-to-Rail Operation. Output of DAC C. Buffered Output with Rail-to-Rail Operation. Output of DAC D. Buffered Output with Rail-to-Rail Operation. Ground Reference Point for All Circuitry on the Part. Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. LSB Address Pin for Selecting which DAC Is to Be Written to. MSB Address Pin for Selecting which DAC Is to Be Written to. Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. Power-Down Pin. This active low control pin puts all DACs into power-down mode. Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Eight Parallel Data Inputs. DB7 is the MSB of these eight bits. Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. REV. 0 –5– AD5334/AD5335/AD5336/AD5344 AD5335 FUNCTIONAL BLOCK DIAGRAM VREFA/B POWER-ON RESET VDD AD5335 PIN CONFIGURATION VREFC/D 1 24 23 22 21 CLR HBEN DB7 DB6 DB5 AD5335 HIGH BYTE REGISTER DB7 . . . . . . DB0 CS WR A0 A1 HBEN INTERFACE LOGIC VREFA/B 2 VOUTA 3 VOUTB 4 VOUTC 5 VOUTD 6 10-BIT AD5335 20 LOW BYTE REGISTER DAC REGISTER 10-BIT DAC BUFFER VOUTA TOP VIEW 19 DB4 GND 7 (Not to Scale) 18 DB3 CS 8 17 16 15 14 13 DB2 DB1 DB0 VDD PD HIGH BYTE REGISTER WR 9 A0 10 A1 11 LOW BYTE REGISTER DAC REGISTER 10-BIT DAC LDAC 12 BUFFER VOUTB HIGH BYTE REGISTER LOW BYTE REGISTER DAC REGISTER 10-BIT DAC BUFFER VOUTC HIGH BYTE REGISTER LOW BYTE REGISTER DAC REGISTER 10-BIT DAC BUFFER VOUTD CLR LDAC RESET TO ALL DACS AND BUFFERS POWER-DOWN LOGIC VREFC/D PD GND AD5335 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15–22 23 24 Mnemonic VREFC/D VREFA/B VOUTA VOUTB VOUTC VOUTD GND CS WR A0 A1 LDAC PD VDD DB0–DB7 HBEN CLR Function Unbuffered Reference Input for DACs C and D. Unbuffered Reference Input for DACs A and B. Output of DAC A. Buffered output with rail-to-rail operation. Output of DAC B. Buffered output with rail-to-rail operation. Output of DAC C. Buffered output with rail-to-rail operation. Output of DAC D. Buffered output with rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. LSB Address Pin for Selecting which DAC Is to Be Written to. MSB Address Pin for Selecting which DAC Is to Be Written to. Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. Power-Down Pin. This active low control pin puts all DACs into power-down mode. Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Eight Parallel Data Inputs. DB7 is the MSB of these eight bits. This pin is used when writing to the device to determine if data is written to the high byte register or the low byte register. Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. –6– REV. 0 AD5334/AD5335/AD5336/AD5344 AD5336 FUNCTIONAL BLOCK DIAGRAM VREFA VREFB VDD VREFD 1 28 27 26 25 24 AD5336 PIN CONFIGURATION CLR GAIN DB9 DB8 DB7 DB6 POWER-ON RESET GAIN DB9 . . . DB0 CS WR A0 A1 INPUT REGISTER INTERFACE LOGIC INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER AD5336 VREFC 2 VREFB 3 VREFA 4 VOUTA VOUTA 5 VOUTB 6 VOUTC 7 GND 9 CS 10 WR 11 10-BIT AD5336 23 22 DAC REGISTER 10-BIT DAC BUFFER VOUTB DB5 TOP VIEW VOUTD 8 (Not to Scale) 21 DB4 20 19 18 17 16 15 DB3 DB2 DB1 DB0 VDD PD VOUTC A0 12 A1 13 LDAC 14 INPUT REGISTER CLR RESET LDAC DAC REGISTER 10-BIT DAC BUFFER TO ALL DACS AND BUFFERS POWER-DOWN LOGIC VOUTD VREFD VREFC PD GND AD5336 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17–26 27 28 Mnemonic VREFD VREFC VREFB VREFA VOUTA VOUTB VOUTC VOUTD GND CS WR A0 A1 LDAC PD VDD DB0–DB9 GAIN CLR Function Unbuffered Reference Input for DAC D. Unbuffered Reference Input for DAC C. Unbuffered Reference Input for DAC B. Unbuffered Reference Input for DAC A. Output of DAC A. Buffered output with rail-to-rail operation. Output of DAC B. Buffered output with rail-to-rail operation. Output of DAC C. Buffered output with rail-to-rail operation. Output of DAC D. Buffered output with rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. LSB Address Pin for Selecting which DAC Is to Be Written to. MSB Address Pin for Selecting which DAC is to Be Written to. Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. Power-Down Pin. This active low control pin puts all DACs into power-down mode. Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 10 Parallel Data Inputs. DB9 is the MSB of these 10 bits. Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF. Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. REV. 0 –7– AD5334/AD5335/AD5336/AD5344 AD5344 FUNCTIONAL BLOCK DIAGRAM VREFA VREFB VDD AD5344 PIN CONFIGURATION VREFD 1 VREFC 2 28 27 26 25 24 DB11 DB10 DB9 DB8 DB7 DB6 POWER-ON RESET DB11 . . . . . . DB0 CS WR A0 A1 AD5344 DAC REGISTER VREFB 3 VREFA 4 VOUTA 5 VOUTB 6 VOUTC 7 GND 9 CS 10 WR 11 INPUT REGISTER 12-BIT DAC BUFFER VOUTA 12-BIT AD5344 23 22 INPUT REGISTER INTERFACE LOGIC INPUT REGISTER DAC REGISTER 12-BIT DAC DB5 TOP VIEW VOUTD 8 (Not to Scale) 21 DB4 BUFFER VOUTB 20 19 18 17 16 15 DB3 DB2 DB1 DB0 VDD PD DAC REGISTER 12-BIT DAC A0 12 BUFFER VOUTC A1 13 LDAC 14 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER TO ALL DACS AND BUFFERS VOUTD LDAC POWER-DOWN LOGIC VREFD VREFC PD GND AD5344 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17–28 Mnemonic VREFD VREFC VREFB VREFA VOUTA VOUTB VOUTC VOUTD GND CS WR A0 A1 LDAC PD VDD DB0–DB11 Function Unbuffered Reference Input for DAC D. Unbuffered Reference Input for DAC C. Unbuffered Reference Input for DAC B. Unbuffered Reference Input for DAC A. Output of DAC A. Buffered output with rail-to-rail operation. Output of DAC B. Buffered output with rail-to-rail operation. Output of DAC C. Buffered output with rail-to-rail operation. Output of DAC D. Buffered output with rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. LSB Address Pin for Selecting which DAC Is to Be Written to. MSB Address Pin for Selecting which DAC Is to Be Written to. Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. Power-Down Pin. This active low control pin puts all DACs into power-down mode. Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 12 Parallel Data Inputs. DB11 is the MSB of these 12 bits. –8– REV. 0 AD5334/AD5335/AD5336/AD5344 TERMINOLOGY RELATIVE ACCURACY For the DAC, Relative Accuracy or Integral Nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL versus Code plot can be seen in Figures 5, 6, and 7. DIFFERENTIAL NONLINEARITY OUTPUT VOLTAGE GAIN ERROR AND OFFSET ERROR ACTUAL Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus Code plot can be seen in Figures 8, 9, and 10. OFFSET ERROR IDEAL POSITIVE OFFSET This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. If the offset voltage is positive, the output voltage will still be positive at zero input code. This is shown in Figure 3. Because the DACs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. Instead, there will be a code close to zero at which the amplifier output saturates (amplifier footroom). Below this code there will be a deadband over which the output voltage will not change. This is illustrated in Figure 4. GAIN ERROR DAC CODE Figure 3. Positive Offset Error and Gain Error GAIN ERROR AND OFFSET ERROR IDEAL OUTPUT VOLTAGE This is a measure of the span error of the DAC (including any error in the gain of the buffer amplifier). It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. This is illustrated in Figure 2. POSITIVE GAIN ERROR NEGATIVE GAIN ERROR ACTUAL NEGATIVE OFFSET DAC CODE ACTUAL DEADBAND CODES AMPLIFIER FOOTROOM (~1mV) OUTPUT VOLTAGE IDEAL NEGATIVE OFFSET DAC CODE Figure 4. Negative Offset Error and Gain Error Figure 2. Gain Error REV. 0 –9– AD5334/AD5335/AD5336/AD5344 OFFSET ERROR DRIFT DIGITAL FEEDTHROUGH This is a measure of the change in Offset Error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. GAIN ERROR DRIFT This is a measure of the change in Gain Error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. DC POWER-SUPPLY REJECTION RATIO (PSRR) Digital Feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device but is measured when the DAC is not being written to (CS held high). It is specified in nV-secs and is measured with a full-scale change on the digital input pins, i.e. from all 0s to all 1s and vice versa. DIGITAL CROSSTALK This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dBs. VREF is held at 2 V and VDD is varied ± 10%. DC CROSSTALK This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV secs. ANALOG CROSSTALK This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in µV. REFERENCE FEEDTHROUGH This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dBs. CHANNEL-TO-CHANNEL ISOLATION This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV secs. DAC-TO-DAC CROSSTALK This is a ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference inputs of the other DACs. It is measured by grounding one VREF pin and applying a 10 kHz, 4 V peak-to-peak sine wave to the other VREF pins. It is expressed in dBs. MAJOR-CODE TRANSITION GLITCH ENERGY This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with the LDAC pin set low and monitoring the output of another DAC. The energy of the glitch is expressed in nV secs. MULTIPLYING BANDWIDTH Major-Code Transition Glitch Energy is the energy of the impulse injected into the analog output when the DAC changes state. It is normally specified as the area of the glitch in nV secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). The amplifiers within the DAC have a finite bandwidth. The Multiplying Bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The Multiplying Bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. TOTAL HARMONIC DISTORTION This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs. – 10 – REV. 0 Typical Performance Characteristics– AD5334/AD5335/AD5336/AD5344 1.0 TA = 25 C VDD = 5V 0.5 INL ERROR – LSBs INL ERROR – LSBs 3 2 TA = 25 C VDD = 5V INL ERROR – LSBs 12 TA = 25 C VDD = 5V 8 1 4 0 0 0 –1 –4 –0.5 –2 –8 –12 –1.0 0 50 100 150 CODE 200 250 –3 0 200 400 600 CODE 800 1000 0 1000 2000 CODE 3000 4000 Figure 5. AD5334 Typical INL Plot Figure 6. AD5335 Typical INL Plot Figure 7. AD5336 Typical INL Plot 0.3 TA = 25 C VDD = 5V 0.6 TA = 25 C VDD = 5V 0.4 DNL ERROR – LSBs 1 TA = 25 C VDD = 5V DNL ERROR – LSBs 0.2 DNL ERROR – LSBs 0.5 0.1 0.2 0 0 0 –0.1 –0.2 –0.4 –0.6 0 200 400 600 CODE 800 1000 –0.5 –0.2 –0.3 0 50 100 150 CODE 200 250 –1 0 1000 2000 CODE 3000 4000 Figure 8. AD5334 Typical DNL Plot Figure 9. AD5335 Typical DNL Plot Figure 10. AD5336 Typical DNL Plot 0.5 VDD = 5V T A = 25 C MAX INL 0.5 0.4 0.3 ERROR – LSBs MAX DNL 1 VDD = 5V VREF = 2V VDD = 5V VREF = 2V MAX INL 0.25 0.5 ERROR – % MAX DNL ERROR – LSBs 0.2 0.1 0 –0.1 MIN DNL GAIN ERROR 0 MIN DNL 0 OFFSET ERROR –0.25 MIN INL –0.2 –0.3 MIN INL –0.5 –0.4 –0.5 0 1 2 3 VREF – V 4 5 –0.5 –1 40 0 40 80 120 TEMPERATURE – C 40 0 40 80 120 TEMPERATURE – C Figure 11. AD5334 INL and DNL Error vs. VREF Figure 12. AD5334 INL Error and DNL Error vs. Temperature Figure 13. AD5334 Offset Error and Gain Error vs. Temperature REV. 0 – 11 – AD5334/AD5335/AD5336/AD5344 0.2 0.1 0 T A = 25 C VREF = 2V GAIN ERROR 5 5V SOURCE 600 VDD = 5.5V 4 3V SOURCE 500 400 VDD = 3.6V ERROR – % 3 IDD – A –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 OFFSET ERROR VOUT – Volts 300 2 200 TA = 25 C VREF = 2V 1 5V SINK 3V SINK 100 0 0 1 2 4 3 VDD – Volts 5 6 0 1 3 4 2 5 SINK/SOURCE CURRENT – mA 6 0 ZERO-SCALE DAC CODE FULL SCALE Figure 14. Offset Error and Gain Error vs. VDD Figure 15. VOUT Source and Sink Current Capability Figure 16. Supply Current vs. DAC Code 600 TA = 25 C 500 0.5 TA = 25 C 0.4 1800 1600 1400 1200 400 IDD – A A A IDD – 0.3 1000 800 600 VDD = 5V VDD = 3V 300 IDD – 0.2 200 100 0.1 400 200 0 2.5 3.0 3.5 4.0 VDD – V 4.5 5.0 5.5 0 2.5 0 3.0 3.5 4.0 4.5 VDD – V 5.0 5.5 0 1 2 3 VLOGIC – V 4 5 Figure 17. Supply Current vs. Supply Voltage Figure 18. Power-Down Current vs. Supply Voltage Figure 19. Supply Current vs. Logic Input Voltage CH1 T A = 25 C 5µs VDD = 5V VREF = 5V VOUTA CH1 T A = 25 C VDD = 5V VREF = 2V VDD T A = 25 C VDD = 5V VREF = 2V CH1 VOUTA LDAC VOUTA PD CH2 CH2 CH2 CH1 1V, CH2 5V, TIME BASE= 1 s/DIV CH1 2V, CH2 200mV, TIME BASE = 200 s/DIV CH1 500mV, CH2 5V, TIME BASE = 1 s/DIV Figure 20. Half-Scale Settling (1/4 to 3/4 Scale Code Change) Figure 21. Power-On Reset to 0 V Figure 22. Exiting Power-Down to Midscale – 12 – REV. 0 AD5334/AD5335/AD5336/AD5344 0.929 0.928 0.927 10 0 –10 –20 FREQUENCY VOUT – Volts VDD = 3V VDD = 5V 0.926 0.925 0.924 0.923 0.922 0.921 0.920 0.919 dB –30 –40 –50 –60 0.01 500ns/DIV 300 350 400 450 500 IDD – A 550 600 0.1 1 10 100 FREQUENCY – kHz 1k 10k Figure 23. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 24. AD5344 Major-Code Transition Glitch Energy Figure 25. Multiplying Bandwidth (Small-Signal Frequency Response) 0.4 VDD = 5V TA = 25 C FULL-SCALE ERROR – %FSR 0.3 0.2 0.1 0 –0.1 –0.2 0 1 2 3 VREF – V 4 5 6 1mV/DIV 750ns/DIV Figure 26. Full-Scale Error vs. VREF Figure 27. DAC-DAC Crosstalk FUNCTIONAL DESCRIPTION The AD5334/AD5335/AD5336/AD5344 are quad resistorstring DACs fabricated on a CMOS process with resolutions of 8, 10, 10, and 12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers offer rail-to-rail output swing. The gain of the buffer amplifiers in the AD5334 and AD5336 can be set to 1 or 2 to give an output voltage range of 0 to VREF or 0 to 2 VREF. The AD5335 and AD5344 have output buffers with unity gain. The devices have a power-down feature that reduces current consumption to only 80 nA @ 3 V. Digital-to-Analog Section where: D = decimal equivalent of the binary code which is loaded to the DAC register: 0–255 for AD5334 (8 Bits) 0–1023 for AD5335/AD5336 (10 Bits) 0–4095 for AD5344 (12 Bits) N = DAC resolution Gain = Output Amplifier Gain (1 or 2) VREF GAIN INPUT REGISTER DAC REGISTER RESISTOR STRING OUTPUT BUFFER AMPLIFIER VOUT The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the DAC. Figure 28 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by: Figure 28. Single DAC Channel Architecture VOUT = VREF × D × Gain 2N REV. 0 – 13 – AD5334/AD5335/AD5336/AD5344 Resistor String The resistor string section is shown in Figure 29. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. VREF R Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC register becomes transparent and the contents of the input register are transferred to it. The gain control signal is also double-buffered and is only updated when LDAC is taken low. This is useful if the user requires simultaneous updating of all DACs and peripherals. The user may write to all input registers individually and then, by pulsing the LDAC input low, all outputs will update simultaneously. Double-buffering is also useful where the DAC data is loaded in two bytes, as in the AD5335, because it allows the whole data word to be assembled in parallel before updating the DAC register. This prevents spurious outputs that could occur if the DAC register were updated with only the high byte or the low byte. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5334/ AD5335/AD5336/AD5344, the part will only update the DAC register if the input register has been changed since the last time the DAC register was updated. This removes unnecessary crosstalk. Clear Input (CLR) R TO OUTPUT AMPLIFIER R R R Figure 29. Resistor String DAC Reference Input The DACs operate with an external reference. The reference inputs are unbuffered and have an input range of 0.25 V to VDD. The impedance per DAC is typically 180 kΩ for 0–VREF mode and 90 kΩ for 0–2 VREF mode. The AD5336 and AD5344 have separate reference inputs for each DAC, while the AD5334 and AD5335 have a reference inputs for each pair of DACS (A/B and C/D). Output Amplifier CLR is an active low, asynchronous clear that resets the input and DAC registers. Note that the AD5344 has no CLR function. Chip Select Input (CS) CS is an active low input that selects the device. Write Input (WR) The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on VREF, GAIN, the load on VOUT, and offset error. If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V to VREF. If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V to 2 VREF. However because of clamping the maximum output is limited to VDD – 0.001 V. The output amplifier is capable of driving a load of 2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in Figure 15. The slew rate is 0.7 V/µs with a half-scale settling time to ± 0.5 LSB (at 8 bits) of 6 µs with the output unloaded. See Figure 20. PARALLEL INTERFACE WR is an active low input that controls writing of data to the device. Data is latched into the input register on the rising edge of WR. Load DAC Input (LDAC) LDAC transfers data from the input register to the DAC register (and hence updates the outputs). Use of the LDAC function enables double buffering of the DAC and GAIN data. There are two LDAC modes: Synchronous Mode: In this mode the DAC register is updated after new data is read in on the rising edge of the WR input. LDAC can be tied permanently low or pulsed as in Figure 1. Asynchronous Mode: In this mode the outputs are not updated at the same time that the input register is written to. When LDAC goes low the DAC register is updated with the contents of the input register. High-Byte Enable Input (HBEN) The AD5334, AD5336, and AD5344 load their data as a single 8-, 10-, or 12-bit word, while the AD5335 loads data as a low byte of 8 bits and a high byte containing 2 bits. Double-Buffered Interface High-Byte Enable is a control input on the AD5335 only that determines if data is written to the high-byte input register or the low-byte input register. The low data byte of the AD5335 consists of data bits 0 to 7 at data inputs DB0 to DB7, while the high byte consists of Data Bits 8 and 9 at data inputs DB0 and DB1. DB2 to DB7 are ignored during a high byte write. See Figure 30. The AD5334/AD5335/AD5336/AD5344 DACs all have doublebuffered interfaces consisting of an input register and a DAC register. DAC data and GAIN inputs (when available) are written to the input register under control of the Chip Select (CS) and Write (WR). – 14 – REV. 0 AD5334/AD5335/AD5336/AD5344 HIGH BYTE X X X X X X DB9 DB8 LOW BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X = UNUSED BIT Figure 30. Data Format For AD5335 POWER-ON RESET The AD5334/AD5335/AD5336/AD5344 are provided with a power-on reset function, so that they power up in a defined state. The power-on state is: • Normal operation • 0 – VREF output range • Output voltage set to 0 V Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. POWER-DOWN MODE When the PD pin is high, the DACs work normally with a typical power consumption of 600 µA at 5 V (500 µA at 3 V). In powerdown mode, however, the supply current falls to 200 nA at 5 V (80 nA at 3 V) when the DACs are powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the outputs are three-state while the part is in power-down mode, and provides a defined input condition for whatever is connected to the outputs of the DAC amplifiers. The output stage is illustrated in Figure 31. RESISTOR STRING DAC AMPLIFIER VOUT POWER-DOWN CIRCUITRY Figure 31. Output Stage During Power-Down The AD5334/AD5335/AD5336/AD5344 have low power consumption, dissipating typically 1.5 mW with a 3 V supply and 3 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which is selected by taking pin PD low. The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs when VDD = 3 V. This is the time from a rising edge on the PD pin to when the output voltage deviates from its power-down voltage. See Figure 22. Table I. AD5334/AD5336/AD5344 Truth Table CLR 1 1 0 1 1 1 1 1 LDAC 1 1 X 1 1 1 1 0 CS 1 X X 0 0 0 0 X WR X 1 X 0➝ 1 0➝ 1 0➝ 1 0➝ 1 X A1 X X X 0 0 1 1 X A0 X X X 0 1 0 1 X Function No Data Transfer No Data Transfer Clear All Registers Load DAC A Input Register, GAIN A (AD5334/AD5336) Load DAC B Input Register, GAIN B (AD5334/AD5336) Load DAC C Input Register, GAIN C (AD5334/AD5336) Load DAC D Input Register, GAIN D (AD5334/AD5336) Update DAC Registers X = don’t care. Table II. AD5335 Truth Table CLR 1 1 0 1 1 1 1 1 1 1 1 1 LDAC 1 1 X 1 1 1 1 1 1 1 1 0 CS 1 X X 0 0 0 0 0 0 0 0 X WR X 1 X 0➝ 1 0➝ 1 0➝ 1 0➝ 1 0➝ 1 0➝ 1 0➝ 1 0➝ 1 X A1 X X X 0 0 0 0 1 1 1 1 X A0 X X X 0 0 1 1 0 0 1 1 X HBEN X X X 0 1 0 1 0 1 0 1 X Function No Data Transfer No Data Transfer Clear All Registers Load DAC A Low Byte Input Register Load DAC A High Byte Input Register Load DAC B Low Byte Input Register Load DAC B High Byte Input Register Load DAC C Low Byte Input Register Load DAC C High Byte Input Register Load DAC D Low Byte Input Register Load DAC D High Byte Input Register Update DAC Registers X = don’t care. REV. 0 – 15 – AD5334/AD5335/AD5336/AD5344 SUGGESTED DATABUS FORMATS 6V TO 16V In many applications the GAIN input of the AD5334 and AD5336 may be hard-wired. However, if more flexibility is required, it can be included in a data bus. This enables the user to software program GAIN, giving the option of doubling the resolution in the lower half of the DAC range. In a bused system GAIN may be treated as a data input since it is written to the device during a write operation and takes effect when LDAC is taken low. This means that the output amplifier gain of multiple DAC devices can be controlled using a common GAIN line. The AD5336 databus must be at least 10 bits wide and is best suited to a 16-bit databus system. Examples of data formats for putting GAIN on a 16-bit databus are shown in Figure 32. Note that any unused bits above the actual DAC data may be used for GAIN. AD5336 X X X X X GAIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X = UNUSED BIT 0.1 F 10 F VIN ADM663/ADM666 SENSE VOUT(2) VSET GND SHDN VDD VREF* 0.1 F VOUT* AD5334/AD5335/ AD5336/AD5344 GND *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN Figure 34. Using an ADM663/ADM666 as Power and Reference to AD5334/AD5335/AD5336/AD5344 Bipolar Operation Using the AD5334/AD5335/AD5336/AD5344 Figure 32. AD5336 Data Format for Byte Load with GAIN Data on 8-Bit Bus APPLICATIONS INFORMATION Typical Application Circuits The AD5334/AD5335/AD5336/AD5344 can be used with a wide range of reference voltages and offer full, one-quadrant multiplying capability over a reference range of 0.25 V to VDD. More typically, these devices may be used with a fixed, precision reference voltage. Figure 33 shows a typical setup for the devices when using an external reference connected to the reference inputs. Suitable references for 5 V operation are the AD780 and REF192. For 2.5 V operation, a suitable external reference would be the AD589, a 1.23 V bandgap reference. VDD = 2.5V TO 5.5V The AD5334/AD5335/AD5336/AD5344 have been designed for single supply operation, but bipolar operation is achievable using the circuit shown in Figure 35. The circuit shown has been configured to achieve an output voltage range of –5 V < VO < +5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or OP295 as the output amplifier. The output voltage for any input code can be calculated as follows: VO = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2N)] – R4 × VREF/R3 where: D is the decimal equivalent of the code loaded to the DAC, N is DAC resolution and VREF is the reference voltage input. With: VREF = 2.5 V R1 = R3 = 10 kΩ R2 = R4 = 20 kΩ and VDD = 5 V. VOUT = (10 × D/2N) – 5 VDD = 5V R4 20k 0.1 F 10 F R3 10k VIN VDD VOUT GND 0.1 F VREF* +5V 0.1 F VIN 10 F EXT REF GND VDD VOUT VREF* VOUT* AD5334/AD5335/ AD5336/AD5344 GND AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 2.5V *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN 5V EXT REF AD5334/AD5335/ AD5336/AD5344 VOUT* –5V R1 10k R2 20k Figure 33. AD5334/AD5335/AD5336/AD5344 Using External Reference Driving VDD from the Reference Voltage If an output range of zero to V DD is required, the simplest solution is to connect the reference inputs to VDD. As this supply may not be very accurate, and may be noisy, the devices may be powered from the reference voltage, for example using a 5 V reference such as the ADM663 or ADM666, as shown in Figure 34. AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 2.5V GND *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN Figure 35. Bipolar Operation using the AD5334/AD5335/ AD5336/AD5344 – 16 – REV. 0 AD5334/AD5335/AD5336/AD5344 Decoding Multiple AD5334/AD5335/AD5336/AD5344 The CS pin on these devices can be used in applications to decode a number of DACs. In this application, all DACs in the system receive the same data and WR pulses, but only the CS to one of the DACs will be active at any one time, so data will only be written to the DAC whose CS is low. If multiple AD5343s are being used, a common HBEN line will also be required to determine if the data is written to the high-byte or low-byte register of the selected DAC. The 74HC139 is used as a 2- to 4-line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 36 shows a diagram of a typical setup for decoding multiple devices in a system. Once data has been written sequentially to all DACs in a system, all the DACs can be updated simultaneously using a common LDAC line. A common CLR line can also be used to reset all DAC outputs to zero (except on the AD5344). AD5334/AD5335/ AD5336/AD5344 A1 A0 HBEN* WR DATA LDAC INPUTS CLR CS AD5334/AD5335/ AD5336/AD5344 A1 A0 HBEN* WR DATA INPUTS LDAC CLR CS 1Y0 1Y1 74HC139 1B 1Y2 1Y3 DGND AD5334/AD5335/ AD5336/AD5344 A1 A0 HBEN* WR DATA INPUTS LDAC CLR CS AD5334/AD5335/ AD5336/AD5344 used for some other purpose. The AD5336 and AD5344 have separate reference inputs for each DAC. The upper and lower limits for the test are loaded to DACs A and B which, in turn, set the limits on the CMP04. If a signal at the VIN input is not within the programmed window, an LED will indicate the fail condition. 5V 0.1 F 10 F VIN VREF VREFA VREFB VDD VOUTA 1/2 CMP04 PASS/ FAIL 1k FAIL 1k PASS AD5336/AD5344 VOUTB GND 1/6 74HC05 Figure 37. Programmable Window Detector Programmable Current Source A0 A1 HBEN WR LDAC CLR ENABLE CODED ADDRESS 1G 1A VCC DATA BUS VDD Figure 38 shows the AD5334/AD5335/AD5336/AD5344 used as the control element of a programmable current source. In this example, the full-scale current is set to 1 mA. The output voltage from the DAC is applied across the current setting resistor of 4.7 kΩ in series with the 470 Ω adjustment potentiometer, which gives an adjustment of about ± 5%. Suitable transistors to place in the feedback loop of the amplifier include the BC107 and the 2N3904, which enable the current source to operate from a minimum VSOURCE of 6 V. The operating range is determined by the operating characteristics of the transistor. Suitable amplifiers include the AD820 and the OP295, both having railto-rail operation on their outputs. The current for any digital input code and resistor value can be calculated as follows: D I = G × VREF × N mA (2 × R) Where: G is the gain of the buffer amplifier (1 or 2) D is the digital input code N is the DAC resolution (8, 10, or 12 bits) R is the sum of the resistor plus adjustment potentiometer in kΩ VDD = 5V A1 A0 HBEN* WR LDAC CLR CS DATA INPUTS *AD5335 ONLY 0.1 F 10 F VSOURCE Figure 36. Decoding Multiple DAC Devices VIN 5V VDD VOUT GND 0.1 F VREF* VOUT* AD820/ OP295 AD5334/AD5335/AD5336/AD5344 as a Digitally Programmable Window Detector LOAD EXT REF A digitally programmable upper/lower limit detector using two of the DACs in the AD5334/AD5335/AD5336/AD5344 is shown in Figure 37. Any pair of DACs in the device may be used, but for simplicity the description will refer to DACs A and B. Care must be taken to connect the correct reference inputs to the reference source. The AD5334 and AD5335 have only two reference inputs, VREFA/B for DACs A and B and VREFC/D for DACs C and D. If DACs A and B are used (for example) then only VREFA/B is needed. DACs C and D and VREFC/D may be REV. 0 – 17 – AD5334/AD5335/ AD5336/AD5344 AD780/REF192 WITH VDD = 5V GND 4.7k 470 *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN Figure 38. Programmable Current Source AD5334/AD5335/AD5336/AD5344 Coarse and Fine Adjustment Using the AD5334/AD5335/ AD5336/AD5344 Power Supply Bypassing and Grounding Two of the DACs in the AD5334/AD5335/AD5336/AD5344 can be paired together to form a coarse and fine adjustment function, as shown in Figure 39. As with the window comparator previously described, the description will refer to DACs A, and B and the reference connections will depend on the actual device used. DAC A is used to provide the coarse adjustment while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 will change the relative effect of the coarse and fine adjustments. With the resistor values shown the output amplifier has unity gain for the DAC A output, so the output range is zero to (VREF – 1 LSB). For DAC B the amplifier has a gain of 7.6 × 10–3, giving DAC B a range equal to 2 LSBs of DAC A. The circuit is shown with a 2.5 V reference, but reference voltages up to VDD may be used. The op amps indicated will allow a rail-to-rail output swing. VDD = 5V R3 51.2k R4 390 5V In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5334/AD5335/AD5336/AD5344 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the device is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as closely as possible to the device. The AD5334/AD5335/AD5336/AD5344 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. 0.1 F 10 F VIN EXT REF VOUT GND 0.1 F VREFA VDD VOUTA R1 390 R2 51.2k VOUT AD5336/AD5344 VOUTB AD780/REF192 WITH VDD = 5V VREFB GND Figure 39. Coarse and Fine Adjustment – 18 – REV. 0 AD5334/AD5335/AD5336/AD5344 Table III. Overview of AD53xx Parallel Devices Part No. SINGLES AD5330 AD5331 AD5340 AD5341 DUALS AD5332 AD5333 AD5342 AD5343 QUADS AD5334 AD5335 AD5336 AD5344 Resolution DNL 8 10 12 12 8 10 12 12 8 10 10 12 ± 0.25 ± 0.5 ± 1.0 ± 1.0 ± 0.25 ± 0.5 ± 1.0 ± 1.0 ± 0.25 ± 0.5 ± 0.5 ± 1.0 VREF Pins 1 1 1 1 2 2 2 1 2 2 4 4 Settling Time 6 µs 7 µs 8 µs 8 µs 6 µs 7 µs 8 µs 8 µs 6 µs 7 µs 7 µs 8 µs Additional Pin Functions BUF    GAIN     HBEN CLR            Package TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP Pins 20 20 24 20 20 24 28 20 24 24 28 28          Table IV. Overview of AD53xx Serial Devices Part No. SINGLES AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 Resolution 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 No. of DACS 1 1 1 1 1 1 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 DNL ± 0.25 ± 0.5 ± 1.0 ± 0.25 ± 0.5 ± 1.0 ± 0.25 ± 0.5 ± 1.0 ± 0.25 ± 0.5 ± 1.0 ± 0.25 ± 0.5 ± 1.0 ± 0.25 ± 0.5 ± 1.0 ± 0.25 ± 0.5 ± 1.0 ± 0.25 ± 0.5 ± 1.0 Interface SPI SPI SPI 2-Wire 2-Wire 2-Wire SPI SPI SPI SPI SPI SPI SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI Settling Time 4 µs 6 µs 8 µs 6 µs 7 µs 8 µs 6 µs 7 µs 8 µs 6 µs 7 µs 8 µs 6 µs 7 µs 8 µs 6 µs 7 µs 8 µs 6 µs 7 µs 8 µs 6 µs 7 µs 8 µs Package SOT-23, MicroSOIC SOT-23, MicroSOIC SOT-23, MicroSOIC SOT-23, MicroSOIC SOT-23, MicroSOIC SOT-23, MicroSOIC MicroSOIC MicroSOIC MicroSOIC TSSOP TSSOP TSSOP MicroSOIC MicroSOIC MicroSOIC MicroSOIC MicroSOIC MicroSOIC TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP Pins 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 8 8 8 16 16 16 10 10 10 10 10 10 16 16 16 16 16 16 Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html REV. 0 – 19 – AD5334/AD5335/AD5336/AD5344 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.311 (7.90) 0.303 (7.70) 24 13 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 12 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX SEATING PLANE 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8 0 0.028 (0.70) 0.020 (0.50) 28-Lead Thin Shrink Small Outline Package TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX SEATING PLANE 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8 0 0.028 (0.70) 0.020 (0.50) – 20 – REV. 0 PRINTED IN U.S.A. C3830–2.5–4/00 (rev. 0) 24-Lead Thin Shrink Small Outline Package TSSOP (RU-24)