AD538ACHIPS

a FEATURES V OUT = VY   Transfer Function  VX  Wide Dynamic Range (Denominator) –1000:1 Simultaneous Multiplication and Division Resistor-Programmable Powers and Roots No External Trims Required Low Input Offsets 100:1), the AD538 has a more detailed error specification that is the sum of three components: a percent of reading term, an output offset term and an input offset term for the VY/VX log ratio section. A sample application of this specification, taken from Table I, for the AD538AD with VY = 1 V, VZ = 100 mV and VX = 10 mV would yield a maximum error of ± 2.0% of reading ± 500 µV ± (1 V + 100 mV)/10 mV × 250 µV or ± 2.0% of reading ± 500 µV ± 27.5 mV. This example illustrates that with very low level inputs the AD538’s incremental gain (VY + VZ)/VX has increased to make the input offset contribution to error substantial. Table I. Sample Error Calculation Chart (Worst Case) VY Input (in V) 100:1 INPUT RANGE Total Error = ± % rdg ± Output VOS 10 VZ Input (in V) 10 VX Input (in V) 10 Ideal Output (in V) 10 Total Offset Error Term (in mV) 0.5 0.25 0.5 0.25 0.5 0.25 0.5 0.25 (AD) (BD) (AD) (BD) (AD) (BD) (AD) (BD) % of Reading Error Term (in mV) 100 (AD) 50 (BD) 100 (AD) 50 (BD) 10 (AD) 5 (BD) 1 (AD) 0.5 (BD) 200 (AD) 100 (BD) 5 (AD) 2.5 (BD) 100 (AD) 50 (BD) 20 (AD) 10 (BD) Total Error Summation (in mV) 100.5 (AD) 50.25 (BD) 100.5 (AD) 50.25 (BD) 10.5 5.25 1.5 0.75 (AD) (BD) (AD) (BD) Total Error Summation as a % of the Ideal Output 1.0 (AD) 0.5 (BD) 1.0 (AD) 0.5 (BD) 1.05 (AD) 0.5 (BD) 1.5 (AD) 0.75 (BD) 2.28 (AD) 1.17 (BD) 2.7 (AD) 1.4 (BD) 4.52 (AD) 2.51 (BD) 4.55 (AD) 2.53 (BD) 10 0.1 0.1 10 1 1 1 1 0.1 WIDE DYNAMIC RANGE Total Error = ± % rdg ± Output VOS ± Input VOS × (VY + VZ)/VX 1 0.1 0.10 0.1 0.01 0.1 10 28 (AD) 16.75 (BD) 1.76 1 (AD) (BD) 228 (AD) 116.75 (BD) 6.76 3.5 (AD) (BD) 10 0.05 2 0.25 5 0.01 0.01 5 125.75 (AD) 75.4 (BD) 25.53 (AD) 15.27 (BD) 225.75 (AD) 125.4 (BD) 45.53 (AD) 25.27 (BD) 10 0.01 0.1 1 REV. C –3– AD538 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250 mW Output Short Circuit-to-Ground . . . . . . . . . . . . . . . Indefinite Input Voltages VX , VY, V Z . . . . . . . . . . . . . (+VS – 1 V), –1 V Input Currents IX, IY, IZ, IO . . . . . . . . . . . . . . . . . . . . . . 1 mA Operating Temperature Range . . . . . . . . . . . –25°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65° C to +150°C Lead Temperature, Storage . . . . . . . . . . . . . . 60 sec, +300°C Thermal Resistance θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 IZ VZ B +10V +2V +VS –VS VO I 18 A 17 D 16 IX AD538 15 VX TOP VIEW 14 SIGNAL GND (Not to Scale) 13 PWR GND 12 C 11 IY 10 VY ORDERING GUIDE Model AD538AD AD538BD AD538ACHIPS AD538SD AD538SD/883B Temperature Range –25°C to +85° C –25°C to +85° C –25°C to +85° C –55°C to +125°C –55°C to +125°C Package Description Side-Brazed Ceramic DIP Side-Brazed Ceramic DIP Chips Side-Brazed Ceramic DIP Side-Brazed Ceramic DIP Package Option D-18 D-18 D-18 D-18 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD538 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –4– REV. C Typical Performance Characteristics– AD538 5.0 1000 SMALL SIGNAL BANDWITH – Hz 1M TOTAL % OF READING ERROR OUTPUT STAGE OFFSET – V 4.0 800 400k 3.0 600 VY = 10V dc VZ = VX +0.05 VX SIN 100k t 2.0 OFFSET 1.0 % OF READING 0 –55 –40 –20 0 20 40 60 TEMPERATURE – C 80 100 400 40k 200 0 125 10k 0.01 0.1 1 DENOMINATOR VOLTAGE, VX – V dc 10 Figure 1. Multiplier Error vs. Temperature (100 mV < VX, VY, V Z ≤ 10 V) Figure 4. Small Signal Bandwidth vs. Denominator Voltage (One-Quadrant Mult/Div) 5.0 1000 6.0 1200 TOTAL % OF READING ERROR TOTAL % OF READING ERROR OUTPUT STAGE OFFSET – V 4.0 800 4.0 800 3.0 600 3.0 600 % OF READING 2.0 400 2.0 400 200 OFFSET 1.0 OFFSET 200 % OF READING 1.0 0 –55 –40 –20 0 20 40 60 TEMPERATURE – C 80 100 0 125 0 –55 –40 –20 0 20 40 60 TEMPERATURE – C 80 100 0 125 Figure 2. Divider Error vs. Temperature (100 mV < VX, VY, V Z ≤ 10 V) Figure 5. Multiplier Error vs. Temperature (10 mV < VX, VY, V Z ≤ 100 mV) 1000 VX = 10V VY = 0V VZ = 5V +5V SIN 100 5.0 1000 TOTAL % OF READING ERROR t VOLTS VO IN mV PEAK-TO-PEAK 4.0 800 3.0 600 2.0 % OF READING 1.0 OFFSET 400 10 200 1 100 1k 10k 100k INPUT FREQUENCY – Hz 1M 0 –55 –40 –20 0 20 40 60 TEMPERATURE – C 80 100 0 125 Figure 3. V Z Feedthrough vs. Frequency Figure 6. Divider Error vs. Temperature (10 mV < VX, VY, V Z ≤ 100 mV) REV. C –5– OUTPUT STAGE OFFSET – V OUTPUT STAGE OFFSET – V 5.0 1000 AD538 150 100 VOLTAGE NOISE, en – V Hz 100 VO IN mV PEAK-TO-PEAK 10 FOR THE FREQUENCY RANGE OF 10Hz TO 100kHz THE TOTAL RMS OUTPUT NOISE, eo, FOR A GIVEN BANDWIDTH Bw, IS CALCULATED eo = en Bw VX = 0.01V 10 VX = 10V VY = 5V +5V SIN VZ = 0V t VOLTS 1 1.0 0.10 VX = 10V 0.1 100 1k 100k 10k INPUT FREQUENCY – Hz 1M 0.01 0.01 0.1 1 DC OUTPUT VOLTAGE – Volts 10 Figure 7. VY Feedthrough vs. Frequency Figure 8. 1 kHz Output Noise Spectral Density vs. DC Output Voltage IZ 1 VZ 2 B3 +10V 4 100 +2V 5 +VS 6 –VS 7 VO 8 I9 INTERNAL VOLTAGE REFERENCE OUTPUT 25k 100 25k 25k LOG RATIO 18 A D IX VX SIGNAL GND PWR GND C IY VY 17 Under normal operation, the log-ratio output will be directly connected to a second functional block at input C, the antilog subsection. This section performs the antilog according to the transfer function: VO = VY e   q  VC kT   16 15 14 AD538 13 As with the log-ratio circuit included in the AD538, the user may use the antilog subsection by itself. When both subsections are combined, the output at B is tied to C, the transfer function of the AD538 computational unit is:  VO = VY e    kT   q   VZ   ln   q   kT   VX      ;V 12 11 ANTILOG LOG 10 B = VC which reduces to: V  VO = VY  Z  VX  Finally, by increasing the gain, or attenuating the output of the log ratio subsection via resistor programming, it is possible to raise the quantity VZ /VX to the mth power. Without external programming, m is unity. Thus the overall AD538 transfer function equals: VO = VY where 0.2 < m < 5. When the AD538 is used as an analog divider, the VY input can be used to multiply the ratio VZ / VX by a convenient scale factor. The actual multiplication by the VY input signal is accomplished by adding the log of the VY input signal to the signal at C, which is already in the log domain.  VZ  V   X m 25k Figure 9. Functional Block Diagram FUNCTIONAL DESCRIPTION As shown in Figures 9 and 10, the VZ and VX inputs connect directly to the AD538’s input log ratio amplifiers. This subsection provides an output voltage proportional to the natural log of input voltage VZ , minus the natural log of input voltage VX. The output of the log ratio subsection at B can be expressed by the transfer function: VB V  kT = ln  Z  q VX  where k = 1.3806 × 10–23 J/K, q = 1.60219 × 10–19 C, T is in Kelvins. The log ratio configuration may be used alone, if correctly temperature compensated and scaled to the desired output level (see Applications section). –6– REV. C AD538 STABILITY PRECAUTIONS ONE-QUADRANT MULTIPLICATION/DIVISION At higher frequencies, the multistaged signal path of the AD538, as illustrated in Figure 10, can result in large phase shifts. If a condition of high incremental gain exists along that path (e.g., VO = VY × VZ / VX = 10 V × 10 mV/10 mV = 10 V so that ∆VO /∆VX = 1000), then small amounts of capacitive feedback from VO to the current inputs IZ or IX can result in instability. Appropriate care should be exercised in board layout to prevent capacitive feedback mechanisms under these conditions. IX LOGe VX – 0.2 M 5 + IZ LOGe VZ Ln Z IY LOGe VY Ln Y + ANTILOGe + VZ M VO = VY VX BUFFER Ln Z – Ln X Ln X M(Ln Z – Ln X) M(Ln Z – Ln X) +Ln Y Figure 12 shows how the AD538 may be easily configured as a precision one-quadrant multiplier/divider. The transfer function VOUT = VY (VZ /VX) allows “three” independent input variables, a calculation not available with a conventional multiplier. In addition, the 1000:1 (i.e., 10 mV to 10 V) input dynamic range of the AD538 greatly exceeds that of analog multipliers computing one-quadrant multiplication and division. VOUT = VY ( VZ ) VX 18 A IZ 1 VZ INPUT VZ 25k 2 LOG RATIO 17 D B 3 16 IX +10V 4 100 +2V 5 6 15 VX SIGNAL GND PWR GND C IY VY IN4148 100 25k 14 VX INPUT Figure 10. Model Circuit USING THE VOLTAGE REFERENCES +15V INTERNAL VOLTAGE REFERENCE OUTPUT 25k AD538 13 A stable bandgap voltage reference for scaling is included in the AD538. It is laser-trimmed to provide a selectable voltage output of +10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any voltages between +2 V and +10.2 V buffered as shown in Figure 11. The output impedance at Pin 5 is approximately 5 kΩ. Note that any loading of this pin will produce an error in the +10 V reference voltage. External loads on the +2 V output should be greater than 500 kΩ to maintain errors less than 1%. –15V VO OUTPUT I 7 12 8 11 ANTILOG 9 LOG 10 25k VY INPUT Figure 12. One-Quadrant Combination Multiplier/Divider IZ 1 +2V TO +10.2V BUFFERED VZ 2 B3 REF OUT +2V 25k LOG RATIO 18 A D IX VX SIGNAL GND PWR GND C IY VY 17 By simply connecting the input VX (Pin 15) to the +10 V reference (Pin 4), and tying the log-ratio output at B to the antilog input at C, the AD538 can be configured as a one-quadrant analog multiplier with 10-volt scaling. If 2-volt scaling is desired, VX can be tied to the +2 V reference. When the input VX is tied to the +10 V reference terminal, the multiplier transfer function becomes: V  VO = VY  Z   10 V  As a multiplier, this circuit provides a typical bandwidth of 400 kHz with values of VX , VY or VZ varying over a 100:1 range (i.e., 100 mV to 10 V). The maximum error with a 100 mV to 10 V range for the two input variables will typically be +0.5% of reading. Using the optional Z offset trim scheme, as shown in Figure 13, this error can be reduced to +0.25% of reading. By using the +10 V reference as the VY input, the circuit of Figure 12 is configured as a one-quadrant divider with a fixed scale factor. As with the one-quadrant multiplier, the inputs accept only single (positive) polarity signals. The output of the one-quadrant divider with a +10 V scale factor is: V  VO = 10 V  Z   VX  The typical bandwidth of this circuit is 370 kHz with 1 V to 10 V denominator input levels. At lower amplitudes, the bandwidth gradually decreases to approximately 200 kHz at the 2 mV input level. 16 4 15 100 50k 11.5k 5 100 25k 14 +VS 6 –VS 7 VO 8 I9 INTERNAL VOLTAGE REFERENCE OUTPUT 25k AD538 13 12 11 ANTILOG LOG 10 25k Figure 11. +2 V to +10.2 V Adjustable Reference In situations not requiring both reference levels, the +2 V output can be converted to a buffered output by tying Pins 4 and 5 together. If both references are required simultaneously, the +10 V output should be used directly and the +2 V output should be externally buffered. REV. C –7– AD538 TWO-QUADRANT DIVISION LOG RATIO OPERATION The two-quadrant linear divider circuit illustrated in Figure 13 uses the same basic connections as the one-quadrant version. However, in this circuit the numerator has been offset in the positive direction by adding the denominator input voltage to it. The offsetting scheme changes the divider’s transfer function from: V  VO = 10 V  Z   VX  to: Figure 14 shows the AD538 configured for computing the log of the ratio of two input voltages (or currents). The output signal from B is connected to the summing junction of the output amplifier via two series resistors. The 90.9 Ω metal film resistor effectively degrades the temperature coefficient of the ± 3500 ppm/° C resistor to produce a 1.09 kΩ +3300 ppm/° C equivalent value. In this configuration, the VY input must be tied to some voltage less than zero (–1.2 V in this case) removing this input from the transfer function. The 5 kΩ potentiometer controls the circuit’s scale factor adjustment providing a +1 V per decade adjustment. The output offset potentiometer should be set to provide a zero output with VX = VZ = 1 V. The input VZ adjustment should be set for an output of 3 V with VZ = l mV and VX = 1 V. –VS 68k 5% –1.2V 10M 1M OPTIONAL INPUT VOS ADJUSTMENT 90.9 1% 1k +3500 ppm/ C OUTPUT IZ VZ B +10V +2V VO = 1V LOG10 VO = 10 V (V Z + AVX VX )  VZ  = 10 V 1 A +   VX   VZ  = 10 A + 10 V    VX  AD589 ( VZ ) V X  35 kΩ  where A =    25 kΩ  As long as the magnitude of the denominator input is equal to or greater than the magnitude of the numerator input, the circuit will accept bipolar numerator voltages. However, under the conditions of a 0 V numerator input, the output would incorrectly equal +14 V. The offset can be removed by connecting the +10 V reference through resistors R1 and R2 to the output section’s summing node I at Pin 9 thus providing a gain of 1.4 at the center of the trimming potentiometer. The pot R2 adjusts out or corrects this offset, leaving the desired transfer function of 10 V (VZ / VX). OPTIONAL Z OFFSET TRIM –VS VOUT = 10 1 18 A D 25k 2 3 4 LOG RATIO 48.7 17 16 IX 15 14 VX VX INPUT 100 5 100 25k SIGNAL GND PWR GND C IY VY IN4148 +15V 6 INTERNAL VOLTAGE REFERENCE OUTPUT 25k AD538 13 12 11 10 5k SCALE FACTOR ADJUST 2k 1% –15V 7 VO I 8 9 ANTILOG LOG 25k NUMERATOR VZ DENOMINATOR VX +VS 10M 10k –VS OPTIONAL OUTPUT VOS ADJUSTMENT AD589 1M VOS ADJ 68k 5% –1.2V 10M 35k ( VZ ) VX VX FOR VZ Figure 14. Log Ratio Circuit 1 18 A IZ VZ B +10V 3.9M 25k 2 3 4 LOG RATIO 35k 17 D 16 IX 100 +2V 5 +15V –15V OUTPUT VO 6 7 8 9 100 25k INTERNAL VOLTAGE REFERENCE OUTPUT 25k AD538 15 VX SIGNAL GND 14 PWR GND 13 IN4148 C 12 11 10 The log ratio circuit shown achieves ± 0.5% accuracy in the log domain for input voltages within three decades of input range: 10 mV to 10 V. This error is not defined as a percent of fullscale output, but as a percent of input. For example, using a 1 V/decade scale factor, a 1% error in the positive direction at the INPUT of the log ratio amplifier translates into a 4.3 mV deviation from the ideal OUTPUT (i.e., 1 V × log10 (1.01) = 4.3214 mV). An input error 1% in the negative direction is slightly different, giving an output deviation of 4.3648 mV. IY VY R2 10k R1 12.4k ANTILOG LOG 25k I ZERO ADJUST Figure 13. Two-Quadrant Division with 10 V Scaling –8– REV. C AD538 ANALOG COMPUTATION OF POWERS AND ROOTS SQUARE ROOT OPERATION It is often necessary to raise the quotient of two input signals to a power or take a root. This could be squaring, cubing, squarerooting or exponentiation to some noninteger power. Examples include power series generation. With the AD538, only one or two external resistors are required to set ANY desired power, over the range of 0.2 to 5. Raising the basic quantity VZ /VX to a power greater than one requires that the gain of the AD538’s log ratio subtractor be increased, via an external resistor between pins A and D. Similarly, a voltage divider that attenuates the log ratio output between points B and C will program the power to a value less than one. RA B VZ VY 3 2 VY ( 10 VREF VZ m ) VREF 15 VX 8 VO C 12 A 18 D 17 The explicit square root circuit of Figure 16 illustrates a precise method for performing a real-time square root computation. For added flexibility and accuracy, this circuit has a scale factor adjustment. The actual square rooting operation is performed in this circuit by raising the quantity VZ / VX to the one-half power via the resistor divider network consisting of resistors RB and RC. For maximum linearity, the two resistors should be 1% (or better) ratio-matched metal film types. One volt scaling is achieved by dividing-down the 2 V reference and applying approximately 1 V to both the VY and VX inputs. In this circuit, the VX input is intentionally set low, to about 0.95 V, so that the VY input can be adjusted high, permitting a ± 5% scale factor trim. Using this trim scheme, the output voltage will be within ± 3 mV ± 0.2% of the ideal value over a 10 V to 1 mV input range (80 dB). For a decreased input dynamic range of 10 mV to 10 V (60 dB) the error is even less; here the output will be within ± 2 mV ± 0.2% of the ideal value. The bandwidth of the AD538 square root circuit is approximately 280 kHz with a 1 V p-p sine wave with a +2 V dc offset. This basic circuit may also be used to compute the cube, fourth or fifth roots of an input waveform. All that is required for a given root is that the correct ratio of resistors, RC and RB, be selected such that their sum is between 150 Ω and 200 Ω. The optional absolute value circuit shown preceding the AD538 allows the use of bipolar input voltages. Only one op amp is required for the absolute value function because the IZ input of the AD538 functions as a summing junction. If it is necessary to preserve the sign of the input voltage, the polarity of the op amp output may be sensed and used after the computation to switch the sign bit of a D.V.M. chip. VOUT = 1V VIN 1V POWERS m 2 3 4 5 RA 196 97.6 64.9 48.7 RA = 196 M –1 RB = RC 200 RB B VZ VY 3 2 VY ( 10 VREF VZ m ) VREF 15 VX 8 VO C 12 RC ROOTS m 1/2 1/3 1/4 1/5 RB 100 100 150 162 RC 100 49.9 49.9 40.2 RB = 1 –1 RC M Figure 15. Basic Configurations and Transfer Functions for the AD538 OPTIONAL ABSOLUTE VALUE SECTION 5k 10k 20k IN4148 +VS IN4148 IZ VZ B 1 18 A D IX VX SIGNAL GND PWR GND 25k 2 LOG RATIO RB * 100 17 7 VIN 20k 2 3 20k 1 8 6 VOS +10V +2V +2V 3 16 4 15 100 5 100 25k 14 AD OP-07 4 OR AD611 (VOS TAP –VS TO –VS) +15V 6 INTERNAL VOLTAGE REFERENCE OUTPUT 25k AD538 13 –15V 7 VOUT VO 8 12 C IY D1 VY IN4148 11 ANTILOG LOG 10 I9 1k 100 SCALE FACTOR TRIM 1k 25k * RATIO MATCH 1% METAL FILM RESISTORS FOR BEST ACCURACY RC * 100 Figure 16. Square Root Circuit REV. C –9– AD538 TRANSDUCER LINEARIZATION Many electronic transducers used in scientific, commercial or industrial equipment monitor the physical properties of a device and/or its environment. Sensing (and perhaps compensating for) changes in pressure, temperature, moisture or other physical phenomenon can be an expensive undertaking, particularly where high accuracy and very low nonlinearity are important. In conventional analog systems accuracy may be easily increased by offset and scale factor trims, however, nonlinearity is usually the absolute limitation of the sensing device. With the ability to easily program a complex analog function, the AD538 can effectively compensate for the nonlinearities of an inexpensive transducer. The AD538 can be connected between the transducer preamplifier output and the next stage of monitoring or transmitting circuitry. The recommended procedure for linearizing a particular transducer is first to find the closest function which best approximates the nonlinearity of the device and then, to select the appropriate exponent resistor value(s). ARC-TANGENT APPROXIMATION +15V –15V V V = [V REF –V ] (VZ ) VX 1.21 = TAN–1 (Z ) X 18 IZ 1 A D RA 931 , 1% VZ VZ B +10V 25k 2 3 4 LOG RATIO 17 16 IX 15 14 VX SIGNAL GND PWR GND C IY VY 100 +2V 5 +VS 6 7 8 100 25k VX 1F –VS INTERNAL VOLTAGE REFERENCE OUTPUT 25k AD538 13 12 11 10 1F VO IN4148 ANTILOG LOG 25k I9 0.1 F R1* 100k 10k FULL-SCALE ADJUST +15V R2* 100k The circuit of Figure 17 is typical of those AD538 applications where the quantity VZ /VX is raised to powers greater than one. In an approximate arc-tangent function, the AD538 will accurately compute the angle that is defined by X and Y displacements represented by input voltages VX and VZ. With accuracy to within one degree (for input voltages between 100 µV and 10 volts), the AD538 arc-tangent circuit is more precise than conventional analog circuits and is faster than most digital techniques. For a direct arc-tangent computation that requires fewer external components, refer to the AD639 data sheet. The circuit shown is set up for the transfer function:  VZ Vθ = Vθ REF − Vθ   VX  AD547JH 118k * RATIO MATCH 1% METAL 1F 100k –15V FILM RESISTORS FOR BEST ACCURACY Figure 17. The Arc-Tangent Function The VB /VA quantity is calculated in the same manner as in the one-quadrant divider circuit, except that the resulting quotient is raised to the 1.21 power. Resistor RA (nominally 931 Ω) sets the power or m factor. For the highest arc-tangent accuracy the external resistors R1 and R2 should be ratio matched; however, the offset trim scheme shown in other circuits is not required since nonlinearity effects are the predominant source of error. Also note that instability will occur as the output approaches 90° because, by definition, the arc-tangent function is infinite and therefore, the AD538’s gain will be extremely high. (  ) (( ))   1.21 where: θ = Tan −1  Z  X The (VθREF – Vθ) function is implemented in this circuit by adding together the output, Vθ, and an externally applied reference voltage, VθREF, via an external AD547 op amp. The 1 µF capacitor connected around the AD547’s 100 kΩ feedback resistor frequency compensates the loop (formed by the amplifier between Vθ and VY). –10– REV. C AD538 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Side-Brazed Ceramic DIP (D-18) 18 10 0.30 (7.62) 0.28 (7.12) 1 9 PIN 1 0.91 (23.12) 0.89 (22.61) 0.17 (4.32) MAX 0.175 (4.45) 0.125 (3.18) 0.306 (7.78) 0.294 (7.47) 0.12 (3.05) 0.06 (1.53) 0.02 (0.508) 0.105 (2.67) 0.06 (1.53) 0.015 (0.381) 0.095 (2.42) 0.04 (1.02) SEATING PLANE 0.012 (0.305) 0.008 (0.203) REV. C –11– PRINTED IN U.S.A. C959d–0–12/99 (rev. C)