AD5391BST-3-REEL

8-/16-Channel, 3 V/5 V, Serial Input, Single-Supply, 12-/14-Bit Voltage Output AD5390/AD5391/AD5392 FEATURES INTEGRATED FUNCTIONS AD5390: 16-channel, 14-bit voltage output DAC AD5391: 16-channel, 12-bit voltage output DAC AD5392: 8-channel, 14-bit voltage output DAC Guaranteed monotonic INL ±1 LSB max (AD5391) ±3 LSB max (AD5390-5/AD5392-5) ±4 LSB max (AD5390-3/AD5392-3) On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: −40°C to +85°C Rail-to-rail output amplifier Power-down mode Package types 64-lead LFCSP (9 mm × 9 mm) 52-lead LQFP (10 mm × 10 mm) User interfaces Channel monitor Simultaneous output update via LDAC Clear function to user-programmable code Amplifier boost mode to optimize slew rate User-programmable offset and gain adjust Toggle mode enables square wave generation Thermal monitor APPLICATIONS Instrumentation and industrial control Power amplifier control Level setting (ATE) Control systems Microelectromechanical systems (MEMs) Variable optical attenuators (VOAs) Optical transceivers (MSA 300, XFP) Serial SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible (featuring data readback) I2C®-compatible interface FUNCTIONAL BLOCK DIAGRAM DVDD (×3) DGND (×3/×4) AVDD (×2) AGND (×2) DAC_GND (×2) 14 DCEN/AD1 INPUT REG 0 DIN/SDA SYNC/AD0 STATE MACHINE AND CONTROL LOGIC INTERFACE CONTROL LOGIC SDO INPUT REG 1 DAC REG 0 14 DAC 0 VOUT 0 m REG0 14 14 14 14 14 SCLK/SCL REFOUT/REFIN SIGNAL_GND (×2) 1.25V/2.5V REFERENCE AD5390 SPI/I2C REF_GND c REG0 14 14 14 R DAC REG 1 14 DAC 1 VOUT 1 VOUT 2 m REG1 14 c REG1 R BUSY R VOUT 3 VOUT 4 PD 14 CLR RESET R VIN15 INPUT REG 7 14 MON_IN1 MUX MON_IN2 14 DAC REG 6 14 VOUT 5 DAC 6 VOUT 6 m REG6 14 14 14 14 14 POWER-ON RESET VIN0 INPUT REG 6 c REG6 R 14 14 DAC REG 7 14 R DAC 7 VOUT 7 m REG7 c REG7 VOUT 8 R ×2 R LDAC MON_OUT 03773-001 VOUT 15 Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD5390/AD5391/AD5392 TABLE OF CONTENTS Features .............................................................................................. 1 Integrated Functions ........................................................................ 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 AD5390-5/AD5391-5/AD5392-5 Specifications.......................... 4 AD5390-5/AD5391-5/AD5392-5 AC Characteristics................. 6 AD5390-3/AD5391-3/AD5392-3 Specifications.......................... 7 AD5390-3/AD5391-3/AD5392-3 AC Characteristics................. 9 Timing Characteristics................................................................... 10 Serial SPI-, QSPI-, MICROWIRE-, and DSPCompatible Interface.................................................................. 10 DSP-, SPI-, and MICROWIRECompatible Serial Interface ...................................................... 24 I2C Serial Interface ..................................................................... 26 I2C Write Operation ....................................................................... 27 4-Byte Mode................................................................................ 27 3-Byte Mode................................................................................ 28 2-Byte Mode................................................................................ 29 AD539x On-Chip Special Function Registers........................ 30 Control Register Write............................................................... 32 Hardware Functions....................................................................... 34 Reset Function ............................................................................ 34 Asynchronous Clear Function.................................................. 34 BUSY and LDAC Functions...................................................... 34 I2C Serial Interface...................................................................... 12 Power-On Reset.......................................................................... 34 Absolute Maximum Ratings.......................................................... 13 Power-Down ............................................................................... 34 ESD Caution................................................................................ 13 Microprocessor Interfacing....................................................... 34 Pin Configuraton and Function Descriptions ............................ 14 Application Information................................................................ 36 Terminology .................................................................................... 17 Power Supply Decoupling ......................................................... 36 Typical Performance Characteristics ........................................... 18 Typical Configuration Circuit .................................................. 36 Functional Description .................................................................. 22 AD539x Monitor Function ....................................................... 37 DAC Architecture....................................................................... 22 Toggle Mode Function............................................................... 37 Data Decoding ............................................................................ 23 Thermal Monitor Function....................................................... 37 Interfaces.......................................................................................... 24 Outline Dimensions ....................................................................... 39 Ordering Guide .......................................................................... 40 REVISION HISTORY 3/06—Rev. A to Rev. B Changes to Figure 1.......................................................................... 1 Changes to Table 9.......................................................................... 14 Changes to Table 12 and Table 15 ................................................ 23 Updated Outline Dimensions ....................................................... 39 Changes to Ordering Guide .......................................................... 40 10/04—Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Table 3.............................................................................6 Changes to Table 4.............................................................................7 Changes to Figure 36...................................................................... 35 Changes to Figure 37...................................................................... 36 Changes to Figure 38...................................................................... 36 Changes to Ordering Guide .......................................................... 41 4/04—Revision 0: Initial Version Rev. B | Page 2 of 44 AD5390/AD5391/AD5392 GENERAL DESCRIPTION The AD5390/AD5391 are complete single-supply, 16-channel, 14-bit and 12-bit DACs, respectively. The AD5392 is a complete single-supply, 8-channel, 14-bit DAC. The devices are available in either a 64-lead LFCSP or a 52-lead LQFP. All channels have an on-chip output amplifier with rail-to-rail operation. All devices include an internal 1.25/2.5 V, 10 ppm/°C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode that optimizes the output amplifier slew rate. The AD5390/AD5391/AD5392 contain a 3-wire serial interface with interface speeds in excess of 30 MHz that are compatible with SPI, QSPI, MICROWIRE, and DSP interface standards and an I2C-compatible interface supporting a 400 kHz data transfer rate. An input register followed by a DAC register provides doublebuffering, allowing DAC outputs to be updated independently or simultaneously using the LDAC input. Each channel has a programmable gain and offset adjust register, letting the user fully calibrate any DAC channel. Power consumption is typically 0.25 mA per channel. Table 1. Additional High Channel Count, Low Voltage, Single-Supply DACs in Portfolio Model AD5380BST-5 AD5380BST-3 AD5384BBC-5 AD5384BBC-3 AD5381BST-5 AD5381BST-3 AD5382BST-5 AD5382BST-3 AD5383BST-5 AD5383BST-3 Resolution 14 Bits 14 Bits 14 Bits 14 Bits 12 Bits 12 Bits 14 Bits 14 Bits 12 Bits 12 Bits AVDD Range 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V Output Channels 40 40 40 40 40 40 32 32 32 32 Linearity Error (LSB) ±4 ±4 ±4 ±4 ±1 ±1 ±4 ±4 ±1 ±1 Rev. B | Page 3 of 44 Package Description 100-Lead LQFP 100-Lead LQFP 100-Lead CSPBGA 100-Lead CSPBGA 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP Package Option ST-100 ST-100 BC-100 BC-100 ST-100 ST-100 ST-100 ST-100 ST-100 ST-100 AD5390/AD5391/AD5392 AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Offset Error Offset Error TC Gain Error Gain Temperature Coefficient 2 DC Crosstalk2 REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Input Current Reference Range AD5390-5 1 AD5392-51 AD5391-51 Unit 14 ±3 −1/+2 4 ±4 ±5 ±0.024 ±0.06 2 0.5 12 ±1 ±1 4 ±4 ±5 ±0.024 ±0.06 2 0.5 Bits LSB max LSB max mV max mV max μV/°C typ % FSR max % FSR max ppm FSR/°C typ LSB max 2.5 2.5 V 1 ±1 1 V to AVDD/2 1 ±1 1 V to AVDD/2 MΩ min μA max V min/max Reference Output 3 Output Voltage Reference TC Output Impedance OUTPUT CHARACTERISTICS2 Output Voltage Range 4 Short-Circuit Current Load Current Capacitive Load Stability RL = ∞ RL = 5 kΩ DC Output Impedance MONITOR OUTPUT PIN Output Impedance Three-State Leakage Current LOGIC INPUTS2 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance 2.495/2.505 1.22/1.28 ±10 ±15 2.2 2.495/2.505 1.22/1.28 ±10 ±15 2.2 V min/max V min/max ppm max ppm max kΩ typ 0/AVDD 40 ±1 0/AVDD 40 ±1 V min/max mA max mA max 200 1000 0.5 200 1000 0.5 pF max pF max Ω max 500 100 500 100 Ω typ nA typ 2 0.8 ±10 10 2 0.8 ±10 10 V min V max μA max pF max Test Conditions/Comments Guaranteed monotonic over temperature Measured at code 32 in the linear region At 25°C TMIN to TMAX ±1% for specified performance, AVDD = 2 × REFIN + 50 mV Typically 100 MΩ Typically ±30 nA Enabled via internal/external bit in control register; REF select bit in control register selects the reference voltage At ambient, optimized for 2.5 V operation At ambient when 1.25 V reference is selected Temperature range: 25°C to 85°C Temperature range: −40°C to +85°C DVDD = 2.7 V to 5.5 V Rev. B | Page 4 of 44 Total for all pins, TA = TMIN to TMAX AD5390/AD5391/AD5392 AD5390-5 1 AD5392-51 AD5391-51 Unit Test Conditions/Comments 0.7 DVDD 0.3 DVDD ±1 0.05 DVDD 8 50 0.7 DVDD 0.3 DVDD ±1 0.05 DVDD 8 50 V min V max μA max V min pF typ ns max SMBus-compatible at DVDD < 3.6 V SMBus-compatible at DVDD < 3.6 V 0.4 DVDD − 1 0.4 DVDD − 0.5 ±1 5 0.4 DVDD − 1 0.4 DVDD − 0.5 ±1 5 V max V min V max V min μA max pF typ DVDD = 5 V ± 10%, sinking 200 μA DVDD = 5 V ± 10%, SDO only, sourcing 200 μA DVDD = 2.7 V to 3.6 V, sinking 200 μA DVDD = 2.7 V to 3.6 V SDO only, sourcing 200 μA 0.4 0.6 ±1 8 0.4 0.6 ±1 8 V max V max μA max pF typ ISINK = 3 mA ISINK = 6 mA 4.5/5.5 2.7/5.5 4.5/5.5 2.7/5.5 V min/max V min/max −85 0.375 −85 0.375 AIDD 0.475 0.475 DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation 1 1 20 35 1 1 20 35 dB typ mA/channel max mA/channel max mA max μA max μA max mW max 20 20 mW max Parameter LOGIC INPUTS (SCL, SDA Only) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection LOGIC OUTPUTS (BUSY, SDO)2 Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)2 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity2 ∆Midscale/∆AVDD AIDD 1 Input filtering suppresses noise spikes of