Dual 12-Bit, High Bandwidth, Multiplying DAC with
4-Quadrant Resistors and Parallel Interface
AD5405
Data Sheet
FEATURES
GENERAL DESCRIPTION
10 MHz multiplying bandwidth
On-chip 4-quadrant resistors allow flexible output ranges
INL of ±1 LSB
40-lead LFCSP package
2.5 V to 5.5 V supply operation
±10 V reference input
21.3 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset
0.5 µA typical current consumption
Guaranteed monotonic
Readback function
The AD54051 is a CMOS, 12-bit, dual-channel, current output
digital-to-analog converter (DAC). This device operates from a
2.5 V to 5.5 V power supply, making it suited to battery-powered
and other applications.
Because of manufacturing with a CMOS submicron process, the
device offers excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor (RFB)
provides temperature tracking and full-scale voltage output when
combined with an external I to V precision amplifier. This device
also contains the 4-quadrant resistors necessary for bipolar
operation and other configuration modes.
APPLICATIONS
This DAC uses data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches fill with 0s, and the DAC outputs
are at zero scale.
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
The AD5405 has a 6 mm × 6 mm, 40-lead LFCSP package.
1
U.S. Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
R3A
R2_3A
R3
2R
AD5405
R2A
R2
2R
VREFA R1A
R1
2R
RFB
2R
RFBA
VDD
DATA
INPUTS
DB0
DB11
INPUT
BUFFER
LATCH
IOUT1A
12-BIT
R-2R DAC A
IOUT2A
DAC A/B
CONTROL
LOGIC
LATCH
IOUT1B
12-BIT
R-2R DAC B
IOUT2B
LDAC
GND
POWER-ON
RESET
R3
2R
CLR
R3B
R1
2R
R2
2R
R2_3B
R2B VREFB R1B
RFB
2R
RFBB
04463-001
CS
R/W
Figure 1.
Rev. D
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AD5405
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Operation ....................................................................... 14
Applications ....................................................................................... 1
Single-Supply Applications ....................................................... 15
General Description ......................................................................... 1
Adding Gain ................................................................................ 15
Functional Block Diagram .............................................................. 1
Divider or Programmable Gain Element ................................ 16
Revision History ............................................................................... 2
Reference Selection .................................................................... 16
Specifications..................................................................................... 3
Amplifier Selection .................................................................... 16
Timing Characteristics ................................................................ 5
Parallel Interface ......................................................................... 18
Absolute Maximum Ratings ............................................................ 6
Microprocessor Interfacing ....................................................... 18
ESD Caution .................................................................................. 6
PCB Layout and Power Supply Decoupling ........................... 19
Pin Configuration and Function Descriptions ............................. 7
Overview of the AD5424 to AD5547 Devices ............................ 22
Typical Performance Characteristics ............................................. 8
Outline Dimensions ....................................................................... 23
Terminology .................................................................................... 13
Ordering Guide .......................................................................... 23
General Description ....................................................................... 14
DAC Section ................................................................................ 14
REVISION HISTORY
7/2018—Rev. C to Rev. D
Changes to Pin 2 and Pin 3, Mnemonic Column, Table 4 .......... 7
1/2016—Rev. B to Rev. C
Deleted Positive Output Voltage Section and Figure 35............ 15
Changes to Adding Gain Section ................................................. 15
Changes to ADSP-21xx Processors to AD5405 Interface Section
Title, ADSP-BF504 to ADSP-BF592 Device Family to AD5405
Interface Section Title, and Figure 39 Caption ........................... 19
Deleted Evaluation Board for the DACs Section and Power
Supplies for the Evaluation Board Section .................................. 19
Changes to Table 10 ........................................................................ 22
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
12/2009—Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 1
Changes to Table 2 and Figure 2 ..................................................... 5
Changes to Table 4 and Figure 4 ..................................................... 7
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
7/2005—Rev. 0 to Rev. A
Changed Pin DAC A/B to DAC A/B ............................... Universal
Changes to Features List ...................................................................1
Changes to Specifications .................................................................3
Changes to Timing Characteristics .................................................5
Change to Absolute Maximum Ratings .........................................6
Change to Figure 7 and Figure 8 .....................................................8
Change to Figure 12 ..........................................................................9
Change to Figure 26 Through Figure 28 ..................................... 11
Changes to General Description Section .................................... 14
Change to Figure 31 ....................................................................... 14
Changes to Table 5 Through Table 10 ......................................... 14
Changes to Figure 34 and Figure 35 ............................................ 15
Changes to Figure 36 and Figure 37 ............................................ 16
Changes to Microprocessor Interfacing Section ........................ 18
Added Figure 38 Through Figure 40 ........................................... 18
Change to Power Supplies for the Evaluation Board Section ... 19
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
7/2004—Revision 0: Initial Version
Rev. D | Page 2 of 24
Data Sheet
AD5405
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted.
Table 1.1
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
Bipolar Zero-Code Error
Output Leakage Current
REFERENCE INPUT
Reference Input Range
VREFA, VREFB Input Resistance
VREFA to VREFB Input Resistance
Mismatch
R1, RFB Resistance
R2, R3 Resistance
R2 to R3 Resistance Mismatch
Input Capacitance
Code 0
Code 4095
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
Min
Typ
Max
Unit
12
±1
−1/+2
±25
±25
±1
±15
Bits
LSB
LSB
mV
ppm FSR/°C
mV
nA
nA
Data = 0x0000, TA = 25°C, IOUT1
Data = 0x0000, TA = −40°C to +125°C, IOUT1
±10
10
1.6
13
2.5
V
kΩ
%
Input resistance TC = −50 ppm/°C
Typ = 25°C, max = 125°C
20
20
0.06
25
25
0.18
kΩ
kΩ
%
Input resistance TC = −50 ppm/°C
Input resistance TC = −50 ppm/°C
Typ = 25°C, max = 125°C
±5
8
17
17
pF
pF
VDD = 3.6 V to 5.5 V
VDD = 2.5 V to 3.6 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5.5 V, ISOURCE = 200 µA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
VDD = 4.5 V to 5.5 V, ISINK = 200 µA
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
4
V
V
V
V
V
V
V
V
µA
pF
MHz
VREF = ±3.5 V p-p, DAC loaded all 1s
RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V
DAC latch alternately loaded with 0s and 1s
1.7
1.7
0.8
0.7
VDD − 1
VDD − 0.5
Output Low Voltage, VOL
Input Leakage Current, IIL
Input Capacitance
DYNAMIC PERFORMANCE
Reference Multiplying BW
Output Voltage Settling Time
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
Guaranteed monotonic
3.5
3.5
Input Low Voltage, VIL
Output High Voltage, VOH
Test Conditions/Comments
0.4
0.4
1
10
10
80
35
30
20
15
3
12
25
120
70
60
40
30
ns
ns
ns
ns
ns
nV-sec
70
48
17
30
dB
dB
pF
pF
Rev. D | Page 3 of 24
Interface time delay
Rise and fall times
1 LSB change around major carry, VREF = 0 V
DAC latch loaded with all 0s, VREF = ±3.5 V
1 MHz
10 MHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
AD5405
Parameter
Digital Feedthrough
Output Noise Spectral Density
Analog THD
Digital THD
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Wideband)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Intermodulation Distortion
f1 = 40 kHz, f2 = 50 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
IDD
Data Sheet
Min
Typ
1
1
Unit
nV-sec
25
81
nV/√Hz
dB
61
66
dB
dB
Test Conditions/Comments
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
At 1 kHz
VREF = 3. 5 V p-p, all 1s loaded, f = 1 kHz
Clock = 10 MHz, VREF = 3.5 V
VREF = 3.5 V
55
63
65
dB
dB
dB
50
60
62
dB
dB
dB
VREF = 3.5 V
73
80
87
dB
dB
dB
70
75
80
dB
dB
dB
72
65
dB
dB
VREF = 3.5 V
Clock = 10 MHz
Clock = 25 MHz
V
µA
µA
%/%
TA = 25°C, logic inputs = 0 V or VDD
TA = −40°C to +125°C, logic inputs = 0 V or VDD
∆VDD = ±5%
2.5
0.5
Power Supply Sensitivity
Max
5.5
0.7
10
0.001
Guaranteed by design and characterization, not subject to production test.
Rev. D | Page 4 of 24
Data Sheet
AD5405
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.1
Parameter
Write Mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
t14
t15
t16
t17
Data Readback Mode
t10
t11
t12
t13
Update Rate
Unit
Test Conditions/Comments
0
0
10
10
0
6
0
5
7
10
12
10
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
R/W to CS setup time
R/W to CS hold time
CS low time
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
CS rising to LDAC falling time
LDAC pulse width
CS rising to LDAC rising time
LDAC falling to CS rising time
0
0
5
35
5
10
21.3
ns typ
ns typ
ns typ
ns max
ns typ
ns max
MSPS
Address setup time
Address hold time
Data access time
Bus relinquish time
Consists of CS min high time, CS low time, and output voltage settling time
Guaranteed by design and characterization, not subject to production test.
t8
t2
t1
t2
R/W
t9
t3
CS
t4
t11
t10
t5
DACA/DACB
t6
DATA
t12
t7
DATA VALID
t13
DATA VALID
t14
LDAC 1
t15
t17
t16
04463-002
LDAC 2
1ASYNCHRONOUS
2SYNCHRONOUS
LDAC UPDATE MODE.
LDAC UPDATE MODE.
Figure 2. Timing Diagram
200µA
TO
OUTPUT
PIN
IOL
VOH (MIN) + VOL (MAX)
2
CL
50pF
200µA
IOH
Figure 3. Load Circuit for Data Timing Specifications
Rev. D | Page 5 of 24
04463-003
1
Limit at TMIN, TMAX
AD5405
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VREFA, VREFB, RFBA, RFBB to GND
IOUT1, IOUT2 to GND
Logic Inputs and Output1
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
40-lead LFCSP, θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
Infrared (IR) Reflow, Peak Temperature
(