AD5415YRUZ

Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface AD5415 Data Sheet FEATURES GENERAL DESCRIPTION 10 MHz multiplying bandwidth On-chip 4-quadrant resistors allow flexible output ranges INL of ±1 LSB 24-lead TSSOP package 2.5 V to 5.5 V supply operation ±10 V reference input 50 MHz serial interface 2.47 MSPS update rate Extended temperature range: −40°C to 125°C 4-quadrant multiplication Power-on reset 0.5 µA typical current consumption Guaranteed monotonic Daisy-chain mode Readback function The AD54151 is a CMOS, 12-bit, dual-channel, current output digital-to-analog converter (DAC). This device operates from a 2.5 V to 5.5 V power supply, making it suited to battery-powered applications and other applications. As a result of being manufactured on a CMOS submicron process, this device offers excellent 4-quadrant multiplication characteristics with large signal multiplying bandwidths of 10 MHz. The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external current to voltage precision amplifier. In addition, this device contains the 4-quadrant resistors necessary for bipolar operation and other configuration modes. This DAC uses a double-buffered, 3-wire serial interface that is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP interface standards. In addition, a serial data out pin (SDO) allows daisy-chaining when multiple packages are used. Data readback allows the user to read the contents of the DAC register via the SDO pin. On power-up, the internal shift register and latches are filled with 0s, and the DAC outputs are at zero scale. APPLICATIONS Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming The AD5415 DAC is available in a 24-lead TSSOP package. The EV-AD5415/49SDZ evaluation board is available for evaluating DAC performance. For more information, see UG-296, Evaluating the AD5415 Serial Input, Dual-Channel Current Output DAC. FUNCTIONAL BLOCK DIAGRAM R3A VDD R3 2R AD5415 R2A R2_3A R2 2R VREFA R1A R1 2R RFB 2R RFBA SYNC SCLK INPUT REGISTER SHIFT REGISTER DAC REGISTER IOUT1A 12-BIT R-2R DAC A IOUT2A SDIN SDO LDAC CLR R3 2R R3B IOUT2B R1 2R R2 2R R2_3B R2B VREFB R1B RFB 2R RFBB Figure 1. U.S. Patent Number 5,689,257. Rev. F IOUT1B 12-BIT R-2R DAC B POWER-ON RESET GND 1 DAC REGISTER 04461-001 INPUT REGISTER Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5415 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Circuit Operation ....................................................................... 15  Applications ....................................................................................... 1  Single-Supply Applications ....................................................... 16  General Description ......................................................................... 1  Adding Gain ................................................................................ 17  Functional Block Diagram .............................................................. 1  Divider or Programmable Gain Element ................................ 17  Revision History ............................................................................... 2  Reference Selection .................................................................... 18  Specifications..................................................................................... 3  Amplifier Selection .................................................................... 18  Timing Characteristics ................................................................ 5  Serial Interface ............................................................................ 20  Absolute Maximum Ratings............................................................ 7  Microprocessor Interfacing ....................................................... 22  ESD Caution .................................................................................. 7  PCB Layout and Power Supply Decoupling ........................... 24  Pin Configuration and Function Descriptions ............................. 8  Overview of the AD5424 to AD5547 Devices ............................ 25  Typical Performance Characteristics ............................................. 9  Outline Dimensions ....................................................................... 26  Terminology .................................................................................... 14  Ordering Guide .......................................................................... 26  General Description ....................................................................... 15  DAC Section ................................................................................ 15  REVISION HISTORY 12/15—Rev. E to Rev. F Deleted Positive Output Voltage Section..................................... 17 Changes to Adding Gain Section ................................................. 17 Changes to Reference Selection Section ...................................... 18 Changes to ADSP21xx to AD5415 Interface Section, ADSP-BF504 to ADSP-BF592 Device Family to AD5415 Interface Section, Figure 41, and Figure 42 .................................................. 22 Changes to MC68HC11 to AD5415 Interface Section and PIC16C6x/PIC16C7x to AD5415 Interface Section .................. 23 Changes to Overview of the AD5424 to AD5547 Devices Section Title ...................................................................................... 25 5/13—Rev. D to Rev. E Changes to General Description .................................................... 1 Change to Ordering Guide ............................................................ 26 5/12—Rev. C to Rev. D Changes SDO Control (SDO1 and SDO2) Section ................... 20 6/11—Rev. B to Rev. C Changes to General Description ................................................... 1 Deleted Evaluation Board for the DAC Section and Power Supplies for the Evaluation Board Section .................................. 24 Changes to Ordering Guide .......................................................... 26 7/05—Rev. 0 to Rev. A Changes to Features List ...................................................................1 Change to General Description .......................................................1 Changes to Specifications .................................................................3 Changes to Timing Characteristics .................................................5 Change to Figure 8 and Figure 9 .....................................................9 Change to Figure 13 ....................................................................... 10 Change to Figure 27 Through Figure 29 ..................................... 12 Change to Figure 32 ....................................................................... 15 Changes to Table 5 and Table 6 .................................................... 15 Change to Stability Section ........................................................... 16 Changes to Voltage-Switching Mode of Operation Section ..... 16 Change to Figure 35 ....................................................................... 16 Changes to Divider or Programmable Gain Element Section .... 17 Changes to Figure 36 Through Figure 38.................................... 17 Changes to Table 7 Through Table 10 ......................................... 19 Added ADSP-BF5xx-to-AD5415 Interface Section................... 22 Change to 80C51/80L51-to-AD5415 Interface Section ............ 23 Change to MC68HC11-to-AD5415 Interface Section .............. 23 Change to Power Supplies for the Evaluation Board Section ... 24 Changes to Table 13 ....................................................................... 28 Updated Outline Dimensions ....................................................... 29 Changes to Ordering Guide .......................................................... 29 7/04—Revision 0: Initial Version 4/10—Rev. A to Rev. B Added Figure 4 .................................................................................. 6 Rev. F | Page 2 of 27 Data Sheet AD5415 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted. Table 1.1 Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temperature Coefficient Bipolar Zero Code Error Output Leakage Current REFERENCE INPUT Reference Input Range VREFA, VREFB Input Resistance VREFA to VREFB Input Resistance Mismatch R1, RFB Resistance R2, R3 Resistance R2 to R3 Resistance Mismatch Input Capacitance Code 0 Code 4095 DIGITAL INPUTS/OUTPUT Input High Voltage, VIH Min Typ Max Unit 12 ±1 −1/+2 ±25 ±25 ±1 ±15 Bits LSB LSB mV ppm FSR/°C mV nA nA ±10 10 13 V kΩ 1.6 2.5 % Input resistance temperature coefficient (TC) = −50 ppm/°C Typ = 25°C, max = 125°C 20 20 0.06 25 25 0.18 kΩ kΩ % Input resistance TC = −50 ppm/°C Input resistance TC = −50 ppm/°C Typ = 25°C, max = 125°C ±5 8 17 17 Measured to ±1 mV of Full Scale (FS) Measured to ±4 mV of FS Measured to ±16 mV of FS Digital Delay 10% to 90% Settling Time Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Data = 0x0000, TA = 25°C, IOUT1 Data = 0x0000, TA = −40°C to +125°C, IOUT1 pF pF VDD = 3.6 V to 5.5 V VDD = 2.5 V to 3.6 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V VDD = 4.5 V to 5.5 V, ISOURCE = 200 μA VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA VDD = 4.5 V to 5.5 V, ISINK = 200 μA VDD = 2.5 V to 3.6 V, ISINK = 200 μA 4 V V V V V V V V μA pF MHz VREF = ±3.5 V p-p, DAC loaded all 1s RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V DAC latch alternately loaded with 0s and 1s 1.7 1.7 0.8 0.7 VDD − 1 VDD − 0.5 Output Low Voltage, VOL Input Leakage Current, IIL Input Capacitance DYNAMIC PERFORMANCE Reference Multiplying Bandwidth (BW) Output Voltage Settling Time Guaranteed monotonic 3.5 3.5 Input Low Voltage, VIL Output High Voltage, VOH Test Conditions/Comments 0.4 0.4 1 10 10 80 35 30 20 15 3 12 25 120 70 60 40 30 ns ns ns ns ns nV-sec 70 48 17 30 dB dB pF pF Rev. F | Page 3 of 27 Rise and fall times 1 LSB change around major carry, VREF = 0 V DAC latches loaded with all 0s, VREF = ±3.5 V 1 MHz 10 MHz DAC latches loaded with all 0s DAC latches loaded with all 1s AD5415 Parameter Digital Feedthrough Output Noise Spectral Density Analog THD Digital THD 100 kHz fOUT 50 kHz fOUT SFDR Performance (Wide Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT SFDR Performance (Narrow Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Intermodulation Distortion f1 = 40 kHz, f2 = 50 kHz f1 = 40 kHz, f2 = 50 kHz POWER REQUIREMENTS Power Supply Range IDD Data Sheet Min Typ 3 Max 5 25 81 nV/√Hz dB 61 66 dB dB Test Conditions/Comments Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s At 1 kHz VREF =3. 5 V p-p, all 1s loaded, f = 1 kHz Clock = 10 MHz, VREF = 3.5 V VREF = 3.5 V 55 63 65 dB dB dB 50 60 62 dB dB dB VREF = 3.5 V 73 80 87 dB dB dB 70 75 80 dB dB dB 72 65 dB dB VREF = 3.5 V Clock = 10 MHz Clock = 25 MHz V μA μA %/% TA = 25°C, logic inputs = 0 V or VDD TA = −40°C to +125°C, logic inputs = 0 V or VDD ∆VDD = ±5% 2.5 5.5 0.7 10 0.001 0.5 Power Supply Sensitivity 1 Unit nV-sec Guaranteed by design and characterization, not subject to production test. Rev. F | Page 4 of 27 Data Sheet AD5415 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 3 Update Rate Limit at TMIN, TMAX 50 20 8 8 13 5 4 5 30 0 12 10 25 60 2.47 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min MSPS Test Conditions/Comments 2 Maximum clock frequency SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time Data setup time Data hold time SYNC rising edge to SCLK falling edge Minimum SYNC high time SCLK falling edge to LDAC falling edge LDAC pulse width SCLK falling edge to LDAC rising edge SCLK active edge to SDO valid, strong SDO driver SCLK active edge to SDO valid, weak SDO driver Consists of cycle time, SYNC high time, data setup, and output voltage settling time Guaranteed by design and characterization, not subject to production test. Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register. 3 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in Figure 5. 1 2 t1 SCLK t8 t2 t4 t3 t7 SYNC t6 t5 DIN DB15 DB0 t9 t10 LDAC1 t11 LDAC2 NOTES ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED. Figure 2. Standalone Mode Timing Diagram Rev. F | Page 5 of 27 04461-002 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. AD5415 Data Sheet t1 SCLK t3 t2 t4 t7 SYNC t6 t8 t5 SDIN DB0 (N) DB15 (N) DB15 (N + 1) DB0 (N + 1) DB15 (N) DB0 (N) SDO 04461-003 t12 NOTES 1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS DETERMINED BY THE CONTROL BITS. IN THIS CASE, DATA IS CLOCKED OUT OF SDO ON THE FALLING EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain Timing Diagram SCLK 32 16 SYNC DB15 DB15 DB0 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION SELECTED REGISTER DATA CLOCKED OUT UNDEFINED Figure 4. Readback Mode Timing Diagram 200µA TO OUTPUT PIN IOL VOH (MIN) + VOL (MAX) 2 CL 50pF 200µA IOH Figure 5. Load Circuit for SDO Timing Specifications Rev. F | Page 6 of 27 04461-053 DB0 DB15 SDO 04461-004 SDIN Data Sheet AD5415 ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VREF, RFB to GND IOUT1, IOUT2 to GND Input Current to Any Pin Except Supplies Logic Inputs and Output1 Operating Temperature Range Extended (Y Version) Storage Temperature Range Junction Temperature 24-Lead TSSOP, θJA Thermal Impedance Lead Temperature, Soldering (10 sec) Infrared (IR) Reflow, Peak Temperature (