AD5433YCP

8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface AD5424/AD5433/AD5445 FEATURES GENERAL DESCRIPTION 2.5 V to 5.5 V supply operation Fast parallel interface (17 ns write cycle) Update rate of 20.4 MSPS INL of ±1 LSB for 12-bit DAC 10 MHz multiplying bandwidth ±10 V reference input Extended temperature range: –40°C to +125°C 20-lead TSSOP and chip scale (4 mm × 4 mm) packages 8-, 10-, and 12-bit current output DACs Upgrades to AD7524/AD7533/AD7545 Pin-compatible 8-, 10-, and 12-bit DACs in chip scale Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection Readback function 0.4 μA typical power consumption The AD5424/AD5433/AD5445 1 are CMOS 8-, 10-, and 12-bit current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suitable for battery-powered applications and many other applications. These DACs utilize data readback, allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with 0s and the DAC outputs are at zero scale. As a result of manufacturing with a CMOS submicron process, they offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 MHz. The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. While these devices are upgrades of the AD7524/AD7533/ AD7545 in multiplying bandwidth performance, they have a latched interface and cannot be used in transparent mode. APPLICATIONS Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming The AD5424 is available in small, 20-lead LFCSP and 16-lead TSSOP packages, while the AD5433/AD5445 DACs are available in small, 20-lead LFCSP and TSSOP packages. 1 U.S Patent No. 5,689,257. FUNCTIONAL BLOCK DIAGRAM VDD AD5424/ AD5433/ AD5445 POWER-ON RESET CS R/W VREF R RFB IOUT1 8-/10-/12-BIT R-2R DAC IOUT2 DAC REGISTER GND DB7/DB9/DB11 DB0 DATA INPUTS 03160-001 INPUT LATCH Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved. AD5424/AD5433/AD5445 TABLE OF CONTENTS Features .............................................................................................. 1 Bipolar Operation....................................................................... 18 Applications ....................................................................................... 1 Single-Supply Applications ....................................................... 19 General Description ......................................................................... 1 Positive Output Voltage ............................................................. 19 Functional Block Diagram .............................................................. 1 Adding Gain ................................................................................ 20 Revision History ............................................................................... 2 DACs Used as a Divider or Programmable Gain Element ... 20 Specifications..................................................................................... 3 Reference Selection .................................................................... 21 Timing Characteristics..................................................................... 5 Amplifier Selection .................................................................... 21 Absolute Maximum Ratings............................................................ 6 Parallel Interface ......................................................................... 22 ESD Caution .................................................................................. 6 Microprocessor Interfacing ....................................................... 22 Pin Configuration and Function Descriptions ............................. 7 PCB Layout and Power Supply Decoupling ................................ 23 Typical Performance Characteristics ............................................. 9 Evaluation Board for the AD5424/AD5433/AD5445 ........... 23 Terminology ................................................................................ 16 Power Supplies for Evaluation Board ...................................... 23 Theory of Operation ...................................................................... 17 Outline Dimensions ....................................................................... 28 Circuit Operation ....................................................................... 17 Ordering Guide .......................................................................... 29 REVISION HISTORY 8/09—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 29 3/05—Rev. 0 to Rev. A Updated Format ................................................................ Universal Changes to Specifications ............................................................... 4 Changes to Figure 49 .....................................................................17 Changes to Figure 50 .....................................................................18 Changes to Figure 51, Figure 52, and Figure 54 ........................19 Added Microprocessor Interfacing Section ...............................22 Added Figure 59.............................................................................24 Added Figure 60.............................................................................25 10/03—Initial Version: Revision 0 Rev. B | Page 2 of 32 AD5424/AD5433/AD5445 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE AD5424 Resolution Relative Accuracy Differential Nonlinearity AD5433 Resolution Relative Accuracy Differential Nonlinearity AD5445 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temperature Coefficient1 Output Leakage Current1 REFERENCE INPUT1 Reference Input Range VREF Input Resistance RFB Resistance Input Capacitance Code Zero Scale Code Full Scale DIGITAL INPUTS/OUTPUT1 Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Min Typ Max Unit Conditions 8 ±0.25 ±0.5 Bits LSB LSB Guaranteed monotonic 10 ±0.5 ±1 Bits LSB LSB Guaranteed monotonic 12 ±1 –1/+2 ±10 ±10 ±20 Bits LSB LSB mV ppm FSR/°C nA nA ±10 10 10 12 12 V kΩ kΩ 3 5 6 8 pF pF ±5 8 8 1.7 0.6 VDD − 1 VDD − 0.5 Output Low Voltage, VOL Input Leakage Current, IIL Input Capacitance DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth Output Voltage Settling Time Measured to ±16 mV of full scale Measured to ±4 mV of full scale Measured to ±1 mV of full scale Digital Delay 10% to 90% Settling Time Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error 4 0.4 0.4 1 10 10 30 35 80 20 15 2 70 48 V V V V V V μA pF MHz 60 70 120 40 30 ns ns ns ns ns nV-s dB dB Rev. B | Page 3 of 32 Guaranteed monotonic Data = 0×0000, TA = 25°C, IOUT1 Data = 0×0000, T = −40°C to +125°C, IOUT1 Input resistance TC = –50 ppm/°C Input resistance TC = –50 ppm/°C VDD = 4.5 V to 5 V, ISOURCE = 200 μA VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA VDD = 4.5 V to 5 V, ISINK = 200 μA VDD = 2.5 V to 3.6 V, ISINK = 200 μA VREF = ±3.5 V; DAC loaded all 1s VREF = ±3.5 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s Interface delay time Rise and fall time, VREF = 10 V, RLOAD = 100 Ω 1 LSB change around major carry, VREF = 0 V DAC latch loaded with all 0s, VREF = ±3.5 V Reference = 1 MHz Reference = 10 MHz AD5424/AD5433/AD5445 Parameter Output Capacitance IOUT1 Min IOUT2 Digital Feedthrough Analog THD Digital THD 50 kHz fOUT Output Noise Spectral Density SFDR Performance (Wide Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT SFDR Performance (Narrow Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Intermodulation Distortion Clock = 10 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz Clock = 25 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz POWER REQUIREMENTS Power Supply Range IDD Typ Max Unit Conditions 12 25 22 10 1 17 30 25 12 pF pF pF pF nV-s All 0s loaded All 1s loaded All 0s loaded All 1s loaded Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz Clock = 10 MHz, VREF = 3.5 V 81 dB 65 25 dB nV√Hz 55 63 65 dB dB dB 50 60 62 dB dB dB AD5445, VREF = 3.5 V 73 80 82 dB dB dB 70 75 80 dB dB dB AD5445, VREF = 3.5 V 65 72 dB dB 51 65 dB dB 2.5 0.4 Power Supply Sensitivity 1 @ 1 kHz AD5445, VREF = 3.5 V 5.5 0.6 5 0.001 V μA μA %/% Guaranteed by design, not subject to production test. Rev. B | Page 4 of 32 TA = 25°C, logic inputs = 0 V or VDD Logic inputs = 0 V or VDD, T= −40°C to +125°C ΔVDD = ±5% AD5424/AD5433/AD5445 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 t1 t2 t3 t4 t5 t6 t7 t8 t9 VDD = 4.5 V to 5.5 V 0 0 10 6 0 5 7 10 20 5 10 Unit ns min ns min ns min ns min ns min ns min ns min ns typ ns max ns typ ns max Conditions/Comments R/W to CS setup time R/W to CS hold time CS low time (write cycle) Data setup time Data hold time R/W high to CS low CS min high time Data access time Bus relinquish time Guaranteed by design, not subject to production test. R/W t2 t1 t2 t6 t7 CS t3 t4 DATA t5 DATA VALID t9 t8 DATA VALID Figure 2. Timing Diagram Rev. B | Page 5 of 32 03160-002 1 VDD = 2.5 V to 5.5 V 0 0 10 6 0 5 9 20 40 5 10 AD5424/AD5433/AD5445 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VREF, RFB to GND IOUT1, IOUT2 to GND Logic Inputs and Output 1 Operating Temperature Range Extended Industrial (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP θJA Thermal Impedance 20-Lead TSSOP θJA Thermal Impedance 20-Lead LFCSP θJA Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (