AD5443YRM-REEL

8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface AD5426/AD5432/AD5443 Data Sheet FEATURES GENERAL DESCRIPTION 2.5 V to 5.5 V supply operation 50 MHz serial interface 10 MHz multiplying bandwidth 2.5 MSPS update rate INL of ±1 LSB for 12-bit DAC ±10 V reference input Low glitch energy < 2 nV-s Extended temperature range −40°C to +125°C 10-lead MSOP Pin-compatible 8-, 10-, and 12-bit current output DACs Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection Daisy-chain mode Readback function 0.4 µA typical power consumption The AD5426/AD5432/AD54431 are CMOS 8-, 10-, and 12-bit current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suitable for battery-powered applications and many other applications. These DACs use a double buffered, 3-wire serial interface that is compatible with SPI, QSPI™, MICROWIRE, and most DSP interface standards. In addition, a serial data out pin (SDO) allows for daisy-chaining when multiple packages are used. Data readback allows the user to read the contents of the DAC register via the SDO pin. On power-up, the internal shift register and latches are filled with 0s and the DAC outputs are at zero scale. As a result of manufacturing on a CMOS submicron process, the parts offer excellent 4-quadrant multiplication characteristics with large signal multiplying bandwidths of 10 MHz. The applied external reference input voltage, VREF, determines the full-scale output current. An integrated feedback resistor, RFB, provides temperature tracking and full-scale voltage output when combined with an external current to voltage precision amplifier. APPLICATIONS Portable battery-powered applications Waveform generators Analog processing Instrumentation Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming The AD5426/AD5432/AD5443 DACs are available in small, 10-lead MSOPs. The EV-AD5443/46/53SDZ evaluation board is available for evaluating DAC performance. For more information, see the UG-327 evaluation board user guide. FUNCTIONAL BLOCK DIAGRAM VREF VDD AD5426/ AD5432/ AD5443 R 8-/10-/12-BIT R-2R DAC RFB IOUT1 IOUT2 DAC REGISTER POWER-ON RESET CONTROL LOGIC AND INPUT SHIFT REGISTER GND SDO 03162-001 SYNC SCLK SDIN INPUT LATCH Figure 1. 1 Protected by U.S. Patent No. 5,689,257. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5426/AD5432/AD5443 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Operation ....................................................................... 15 Applications ....................................................................................... 1 Single-Supply Applications ....................................................... 17 General Description ......................................................................... 1 Adding Gain ................................................................................ 17 Functional Block Diagram .............................................................. 1 DACs Used as a Divider or Programmable Gain Element ... 18 Revision History ............................................................................... 2 Reference Selection .................................................................... 18 Specifications..................................................................................... 3 Amplifier Selection .................................................................... 18 Timing Characteristics ................................................................ 5 Serial Interface ............................................................................ 20 Absolute Maximum Ratings ............................................................ 6 PCB Layout and Power Supply Decoupling................................ 22 ESD Caution .................................................................................. 6 Overview of the AD5426/AD5432/AD5443 and Related DACs .. 23 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 24 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 24 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 15 REVISION HISTORY 9/15—Rev. G to Rev. H Deleted Positive Output Voltage Section and Figure 45; Renumbered Sequentially.............................................................. 17 Changes to Adding Gain Section ................................................. 17 Changed Overview of AD54xx and AD55xx Devices Section to Overview of the AD5426/AD5432/AD5443 and Related DACs Section .................................................................................. 23 Changes to Ordering Guide .......................................................... 24 6/13—Rev. F to Rev. G Change to General Description Section ........................................ 1 Changes to Ordering Guide .......................................................... 24 7/12—Rev. E to Rev. F No Change to Content, Changed VDD Values in 7/12 Revision History Only ...................................................................................... 2 7/12—Rev. D to Rev. E Changed VDD = 3 V to VDD = 2.5 V ............................. Throughout Changes to Table 2 ............................................................................ 4 Changes to Table 4 ............................................................................ 7 Change to Daisy-Chain Mode Section ........................................ 20 Change to Ordering Guide ............................................................ 24 4/12—Rev. C to Rev. D Changed VDD = 2.5 V to VDD = 3 V ............................. Throughout Changes to General Description Section ...................................... 1 Deleted Microprocessor Interface Section, ADSP-21xx to AD5426/AD5432/AD5443 Interface Section, Figure 51, Figure 52, Table 11, ADSP-BF5x to AD5426/AD5432/AD5443 Interface Section, Figure 53 and Figure 54; Renumbered Sequentially ..................................................................................... 21 Deleted 80C51/80L51 to AD5426/AD5432/AD5443 Interface Section, Figure 55, MC68HC11 Interface to AD5426/AD5432/ AD5443 Interface Section, Figure 56, MICROWIRE to AD5426/AD5432/AD5443 Interface Section, Figure 57, PIC16C6x/7x to AD5426/AD5432/AD5443, and Figure 58 .... 22 Deleted Evaluation Board for the AD5426/AD5432/AD5443 Series of DACs Section, Operating the Evaluation Board Section, and Power Supplies Section ........................................... 23 Deleted Figure 59 and Figure 60................................................... 24 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 Deleted Figure 61............................................................................ 25 Deleted Figure 62............................................................................ 26 2/09—Rev. B to Rev. C Changes to Low Power Serial Interface Section and DaisyChain Mode Section....................................................................... 20 Updated Outline Dimensions ....................................................... 28 11/08—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 28 5/05—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Specifications .................................................................3 Changes to Figure 42...................................................................... 16 Change to Figure 45 ....................................................................... 17 Change to Figure 46 ....................................................................... 18 Changes to Table 7, Table 8, and Table 9 ..................................... 19 Additions to Microprocessor Interface Section.......................... 21 2/04—Revision 0: Initial Version Rev. H | Page 2 of 24 Data Sheet AD5426/AD5432/AD5443 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted; dc performance measured with OP177; ac performance with AD8038, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE AD5426 Resolution Relative Accuracy Differential Nonlinearity AD5432 Resolution Relative Accuracy Differential Nonlinearity AD5443 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temperature Coefficient1 Output Leakage Current REFERENCE INPUT1 Reference Input Range VREF Input Resistance RFB Resistance Input Capacitance Code Zero Scale Code Full Scale DIGITAL INPUT/OUTPUT1 Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Min Typ Max Unit Test Conditions/Comments 8 ±0.25 ±0.5 Bits LSB LSB Guaranteed monotonic 10 ±0.5 ±1 Bits LSB LSB Guaranteed monotonic 12 ±1 −1/+2 ±10 ±10 ±20 Bits LSB LSB mV ppm FSR/°C nA nA ±10 10 10 12 12 V kΩ kΩ 3 5 6 8 pF pF ±5 8 8 1.7 0.6 VDD − 1 VDD − 0.5 Output Low Voltage, VOL Input Leakage Current, IIL Input Capacitance DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth Output Voltage Settling Time Measured to ±16 mV of FS Measured to ±4 mV of FS Measured to ±1 mV of FS Digital Delay 10% to 90% Rise/Fall Time Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error 4 0.4 0.4 1 10 10 50 55 90 40 15 2 70 48 V V V V V V μA pF MHz 100 110 160 75 30 ns ns ns ns ns nV-s dB dB Rev. H | Page 3 of 24 Guaranteed monotonic Data = 0x0000, TA = 25°C, IOUT1 Data = 0x0000, T = −40°C to 125°C, IOUT1 Input resistance TC = −50 ppm/°C Input resistance TC = −50 ppm/°C VDD = 4.5 V to 5 V, ISOURCE = 200 μA VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA VDD = 4.5 V to 5 V, ISINK = 200 μA VDD = 2.5 V to 3.6 V, ISINK = 200 μA VREF = ±3.5 V; DAC loaded all 1s VREF = 10 V; RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s Interface delay time Rise and fall time, VREF = 10 V, RLOAD = 100 Ω 1 LSB change around major carry, VREF = 0 V DAC latch loaded with all 0s, VREF = ±3.5 1 MHz 10 MHz AD5426/AD5432/AD5443 Parameter Output Capacitance IOUT1 Data Sheet Min IOUT2 Digital Feedthrough Analog THD Digital THD 50 kHz fOUT 20 kHz fOUT Output Noise Spectral Density SFDR Performance (Wide Band) 50 kHz fOUT 20 kHz fOUT SFDR Performance (Narrow Band) 50 kHz fOUT 20 kHz fOUT Intermodulation Distortion POWER REQUIREMENTS Power Supply Range IDD Typ Max Unit Test Conditions/Comments 12 10 22 10 0.1 17 12 25 12 pF pF pF pF nV-s All 0s loaded All 1s loaded All 0s loaded All 1s loaded Feedthrough to DAC output with SYNC high and alternate loading of all 0s and all 1s VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz Clock = 1 MHz, VREF = 3.5 V, CCOMP = 1.8 pF 81 dB 73 74 25 dB dB nV/√Hz 75 76 dB dB 87 87 78 dB dB dB Clock = 1 MHz, f1 = 20 kHz, f2 = 25 kHz, VREF = 3.5 V V µA µA %/% TA = 25°C, logic inputs = 0 V or VDD T = −40°C to +125°C , logic inputs = 0 V or VDD ∆VDD = ±5% Clock = 1 MHz, VREF = 3.5 V 2.5 0.4 Power Supply Sensitivity1 1 @ 1 kHz Clock = 1 MHz, VREF = 3.5 V 5.5 0.6 5 0.001 Guaranteed by design and characterization, not subject to production testing. Rev. H | Page 4 of 24 Data Sheet AD5426/AD5432/AD5443 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter fSCLK t1 t2 t3 t4 1 t5 t6 t7 t8 t9 2, 3 2.5 V to 5.5 V 50 20 8 8 13 5 3 5 30 80 120 4.5 V to 5.5 V 50 20 8 8 13 5 3 5 30 45 65 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns typ ns max Test Conditions/Comments Max clock frequency SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK active edge setup time Data setup time Data hold time SYNC rising edge to SCLK active edge Minimum SYNC high time SCLK active edge to SDO valid Falling or rising edge as determined by control bits of serial word. Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with load circuit, as shown in Figure 4. 3 SDO operates with a VDD of 3.0 V to 5.5 V. 1 2 t1 SCLK t8 t2 t4 t3 t7 SYNC t6 t5 DB15 DB0 03162-002 DIN ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED. Figure 2. Standalone Mode Timing Diagram t1 SCLK t2 t4 t5 DB15 (N) t8 t6 SYNC SDIN t7 t3 t6 DB0 (N) DB15� (N + 1) DB0 (N + 1) DB15(N) DB0(N) SDO ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain and Readback Modes Timing Diagram Rev. H | Page 5 of 24 03162-003 t9 AD5426/AD5432/AD5443 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VDD to GND VREF, RFB to GND IOUT1, IOUT2 to GND Logic Inputs and Output 1 Operating Temperature Range Extended Industrial (Y Version) Storage Temperature Range Junction Temperature 10-lead MSOP θJA Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (