Data Sheet
AD5444/AD5446
12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface
FEATURES
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FUNCTIONAL BLOCK DIAGRAM
12 MHz multiplying bandwidth
INL of ±0.5 LSB at 12 bits
Pin-compatible 12-/14-bit current output DAC
2.5 V to 5.5 V supply operation
10-lead MSOP package
±10 V reference input
50 MHz serial interface
2.7 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset with brownout detection
0.4 µA typical current consumption
Guaranteed monotonic
Figure 1.
APPLICATIONS
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Portable, battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION
The AD5444/AD54461 are CMOS 12-bit and 14-bit, current output,
digital-to-analog converters (DACs). Operating from a single 2.5 V
to 5.5 V power supply, these devices are suited for battery-powered
and other applications.
As a result of the CMOS submicron manufacturing process, these
parts offer excellent 4-quadrant multiplication characteristics of up
to 12 MHz.
These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI, QSPI™, MICROWIRE™, and most DSP
interface standards. On power-up, the internal shift register and
latches are filled with 0s, and the DAC output is at zero scale.
1
The applied external reference input voltage (VREF) determines
the full-scale output current. These parts can handle ±10 V inputs
on the reference, despite operating from a single-supply power
supply of 2.5 V to 5.5 V. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external current-to-voltage precision amplifier. The
AD5444/AD5446 DACs are available in small 10-lead MSOP packages, which are pin-compatible with the AD5425/AD5426/AD5432/
AD5443 family of DACs.
The EVAL-AD5443/EVAL-AD5446/EVAL-AD5453 board is available
for evaluating DAC performance.
US Patent Number 5,689,257.
Rev. G
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
AD5444/AD5446
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Specifications........................................................ 3
Timing Characteristics........................................4
Absolute Maximum Ratings...................................6
ESD Caution.......................................................6
Pin Configuration and Function Descriptions........ 7
Typical Performance Characteristics..................... 8
Terminology......................................................... 14
Theory of Operation.............................................15
DAC Section.....................................................15
Circuit Operation.............................................. 15
Single-Supply Applications...............................17
Adding Gain......................................................17
Divider or Programmable Gain Element...........17
Amplifier Selection............................................18
Reference Selection......................................... 18
Serial Interface.................................................... 20
SYNC Function.................................................20
Microprocessor Interfacing............................... 21
PCB Layout and Power Supply Decoupling........ 23
Overview of Current Output Devices................... 24
Outline Dimensions............................................. 25
Ordering Guide ................................................25
Evaluation Boards............................................ 25
REVISION HISTORY
8/2022—Rev. F to Rev. G
Changes to General Description Section.........................................................................................................1
Changes to Input Leakage Current, IIL Parameter, Table 1............................................................................. 3
Moved Figure 4................................................................................................................................................ 5
Changes to Ordering Guide .......................................................................................................................... 25
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Rev. G | 2 of 25
Data Sheet
AD5444/AD5446
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX,
unless otherwise noted. DC performance measured with OP177, and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter
Min
STATIC PERFORMANCE
AD5444
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error (TUE)
Gain Error
AD5446
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error (TUE)
Gain Error
Gain Error Temperature Coefficient1
Output Leakage Current
REFERENCE INPUT1
Reference Input Range
VREF Input Resistance
RFB Feedback Resistance
Input Capacitance
Zero-Scale Code
Full-Scale Code
DIGITAL INPUTS/OUTPUTS1
Input High Voltage, VIH
Typ
Max
Unit
Test Conditions/Comments
12
±0.5
±1
±1
±0.5
Bits
LSB
LSB
LSB
LSB
Guaranteed monotonic
14
±2
−1/+2
±4
±2.5
±1
±10
Bits
LSB
LSB
LSB
LSB
ppm FSR/°C
nA
nA
±10
9
9
11
11
V
kΩ
kΩ
18
18
22
22
pF
pF
±2
7
7
2.0
1.7
Input Low Voltage, VIL
Output High Voltage, VOH
0.8
0.7
VDD − 1
VDD − 0.5
Output Low Voltage, VOL
0.4
0.4
±1
±10
10
Input Leakage Current, IIL
Input Capacitance
DYNAMIC PERFORMANCE1
Reference Multiplying Bandwidth
Multiplying Feedthrough Error
Output Voltage Settling Time
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
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12
100
24
16
20
Guaranteed monotonic
Data = 0x0000, TA = 25°C, IOUT1
Data = 0x0000, TA = −40°C to +125°C, IOUT1
Input resistance TC = −50 ppm/°C
Input resistance TC = −50 ppm/°C
V
V
V
V
V
V
V
V
µA
µA
pF
VDD = 3.6 V to 5 V
VDD = 2.5 V to 3.6 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5 V, ISOURCE = 200 µA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
VDD = 4.5 V to 5 V, ISINK = 200 µA
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
TA = 25°C
TA = −40°C to +125°C
MHz
VREF = ±3.5 V, DAC loaded with all 1s
VREF = ±3.5 V, DAC loaded with all 0s
100 kHz
1 MHz
10 MHz
VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s
72
64
44
dB
dB
dB
110
40
33
40
ns
ns
ns
ns
Interface delay time
Rev. G | 3 of 25
Data Sheet
AD5444/AD5446
SPECIFICATIONS
Table 1.
Parameter
Min
10%-to-90% Settling Time
Digital-to-Analog Glitch Impulse
Output Capacitance
IOUT1
IOUT2
Digital Feedthrough
Analog THD
Digital THD
50 kHz fOUT
20 kHz fOUT
Output Noise Spectral Density
SFDR Performance (Wide Band)
50 kHz fOUT
20 kHz fOUT
SFDR Performance (Narrow Band)
50 kHz fOUT
20 kHz fOUT
Intermodulation Distortion
POWER REQUIREMENTS
Power Supply Range, VDD
2.5
Supply Current, IDD
Power Supply Sensitivity1
1
Typ
Max
Unit
Test Conditions/Comments
10
2
30
ns
nV-s
Rise and fall time, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, VREF = 0 V
13
28
18
5
0.5
pF
pF
pF
pF
nV-s
83
dB
DAC latches loaded with all 0s
DAC latches loaded with all 1s
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and alternate loading of all 0s and
all 1s
VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz
Clock = 1 MHz, VREF = 3.5 V
71
77
25
dB
dB
nV/√Hz
78
74
dB
dB
@ 1 kHz
Clock = 10 MHz, VREF = 3.5 V
Clock = 1 MHz, VREF = 3.5 V
87
85
79
0.4
5.5
10
0.6
0.001
dB
dB
dB
f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V
V
µA
µA
%/%
TA = −40°C to +125°C, logic inputs = 0 V or VDD
TA = 25°C, logic inputs = 0 V or VDD
∆VDD = ±5%
Guaranteed by design and characterization and not subject to production test.
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF =
10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 5.5 V Unit
Test Conditions/Comments
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
Update Rate
50
20
8
8
8
5
4.5
5
30
23
2.7
50
20
8
8
8
5
4.5
5
30
30
2.7
Maximum clock frequency.
SCLK cycle time.
SCLK high time.
SCLK low time.
SYNC falling edge to SCLK active edge setup time.
Data setup time.
Data hold time.
SYNC rising edge to SCLK active edge setup time
Minimum SYNC high time.
SCLK active edge to SDO valid.
Consists of cycle time, SYNC high time, data setup time and output voltage settling time.
1
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Guaranteed by design and characterization and not subject to production test.
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Rev. G | 4 of 25
Data Sheet
AD5444/AD5446
SPECIFICATIONS
Figure 2. Standalone Timing Diagram
Figure 3. Daisy-Chain Timing Diagram
Figure 4. Load Circuit for SDO Timing Specifications
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Rev. G | 5 of 25
Data Sheet
AD5444/AD5446
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to 100
mA do not cause SCR latch-up.
Table 3.
Parameter
Rating
VDD to GND
VREF, RFB to GND
IOUT1, IOUT2 to GND
Logic Inputs and Outputs
Input Current (All Pins Except Supplies)
Operating Temperature Range Extended (Y Version)
Storage Temperature Range
Junction Temperature
10-lead MSOP θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (> R2||R3
and a gain error percentage of 100 × (R2||R3)/RFB must be taken
into consideration.
Figure 42. Current-Steering DAC Used as a Divider or Programmable Gain
Element
As D is reduced, the output voltage increases. For small values of
the digital fraction (D), it is important to ensure that the amplifier
does not saturate, and the required accuracy is met. For example,
an 8-bit DAC driven with the binary code 0x10 (0001 0000), that
is, 16 decimal, in the circuit of Figure 42, must cause the output
voltage to be 16 × VIN. However, if the DAC has a linearity specification of ±0.5 LSB, then D can, in fact, have a weight in the range
of 15.5/256 to 16.5/256, so the possible output voltage is in the
range 15.5 VIN to 16.5 VIN. This is an error of 3%, even though the
DAC itself has a maximum error of 0.2%.
DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite
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Rev. G | 17 of 25
Data Sheet
AD5444/AD5446
THEORY OF OPERATION
current supplied from the op amp through the DAC. Because only
a fraction (D) of the current into the VREF terminal is routed to the
IOUT1 terminal, the output voltage must change, as follows:
sequently, the slew rate and settling time of a voltage switching
DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to
minimize capacitance at the VREF node (voltage output node in
this application) of the DAC. This is done by using low input,
capacitance buffer amplifiers and careful board design.
Output Error Voltage due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREF terminal.
Most single-supply circuits include ground as part of the analog
signal range, which, in turn, requires an amplifier that can handle
rail-to-rail signals. A large range of single-supply amplifiers is available from Analog Devices, Inc. (see Table 8 and Table 9 for suitable
suggestions).
For a DAC leakage current of 10 nA, R equal to 10 kΩ, and a gain
(1/D) of 16, the error voltage is 1.6 mV.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The
input offset voltage of an op amp is multiplied by the variable gain
(due to the code-dependent output resistance of the DAC) of the
circuit. A change in this noise gain between two adjacent digital
fractions produces a step change in the output voltage due to
the amplifier’s input offset voltage. This output voltage change is
superimposed upon the desired change in output between the two
codes and gives rise to a differential linearity error, which, if large
enough, can cause the DAC to be nonmonotonic.
REFERENCE SELECTION
When selecting a reference for use with the AD5444/AD5446
current output DAC, pay attention to the output voltage temperature coefficient specification. This parameter affects not only the
full-scale error but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient must be consistent
with the system accuracy specifications. For example, an 8-bit
system required to hold its overall specification to within 1 LSB
over the temperature range 0°C to 50°C dictates that the maximum
system drift with temperature must be less than 78 ppm/°C.
The input bias current of an op amp also generates an offset at the
voltage output as a result of the bias current flowing in the feedback
resistor, RFB. Most op amps have input bias currents low enough to
prevent any significant errors in 12‑bit applications.
A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a maximum drift of 10 ppm/°C.
By choosing a precision reference with low output temperature
coefficient, this error source can be minimized. Table 7 suggests
some of the dc references available from Analog Devices that are
suitable for use with this range of current output DACs.
Common-mode rejection of the op amp is important in voltage
switching circuits because it produces a code-dependent error at
the voltage output of the circuit. Most op amps have adequate common-mode rejection for use at 8-bit, 10-bit, and 12‑bit resolutions.
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly. ConTable 7. Suitable Analog Devices Precision References
Part No.
Output Voltage (V)
Initial Tolerance
Accuracy (%)
Temperature Drift
Coefficient (ppm/°C)
ISS (mA)
Output Noise (µV p-p)
Package
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
10
10
5
5
2.5
2.5
3
3
2.5
5
2.5
5
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
3
9
3
9
3
9
3
9
3
3
9
9
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
20
20
10
10
6
6
10
10
3.5
8
5
8
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
Table 8. Suitable Analog Devices Precision Op Amps
Part No.
Supply Voltage (V)
VOS (Max) (µV)
IB (Max) (nA)
0.1 Hz to 10 Hz Noise (µV p-p)
Supply Current (µA)
Package
OP97
OP1177
±2 to ±20
±2.5 to ±15
25
60
0.1
2
0.5
0.4
600
500
SOIC-8
MSOP, SOIC-8
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Rev. G | 18 of 25
Data Sheet
AD5444/AD5446
THEORY OF OPERATION
Table 8. Suitable Analog Devices Precision Op Amps
Part No.
Supply Voltage (V)
VOS (Max) (µV)
IB (Max) (nA)
0.1 Hz to 10 Hz Noise (µV p-p)
Supply Current (µA)
Package
AD8551
AD8603
AD8628
2.7 to 5
1.8 to 6
2.7 to 6
5
50
5
0.05
0.001
0.1
1
2.3
0.5
975
50
850
MSOP, SOIC-8
TSOT
TSOT, SOIC-8
Table 9. Suitable Analog Devices High Speed Op Amps
Part No.
Supply Voltage (V)
BW @ ACL (Typ)
(MHz)
Slew Rate (Typ) (V/µs) VOS (Max) (µV)
IB (Max) (nA)
Package
AD8065
AD8021
AD8038
AD9631
5 to 24
±2.25 to ±12
3 to 12
±3 to ±6
145
490
350
320
180
120
425
1300
0.006
10500
750
7000
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
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1500
1000
3000
10,000
Rev. G | 19 of 25
Data Sheet
AD5444/AD5446
SERIAL INTERFACE
The AD5444/AD5446 have an easy-to-use, 3-wire interface that is
compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. Data is written to the device in 16-bit words. This 16‑bit word
consists of two control bits, 12 data bits or 14 data bits, as shown in
Figure 43 and Figure 44. The AD5446 uses all 14 bits of DAC data
while AD5444 uses 12 bits and ignores the 2 LSBs.
Control Bit C1 and Control Bit C0 allow the user to load and
update the new DAC code and to change the active clock edge.
By default, the shift register clocks data on the falling edge, but this
can be changed via the control bits. If changed, the DAC core is
inoperative until the next data frame. A power cycle resets this back
to the default condition. On-chip, power-on reset circuitry ensures
the device powers on with zero scale loaded to the DAC register
and the IOUT line.
Table 10. DAC Control Bits
C1
C0
Function Implemented
0
0
1
1
0
1
0
1
Load and update (power-on default)
Disable SDO
No operation
Clock data to shift register on rising edge
SYNC FUNCTION
SYNC is an edge-triggered input that acts as a frame synchronization signal. Data can be transferred into the device only while SYNC
is low. To start the serial data transfer, SYNC should be taken
low, observing the minimum SYNC falling to the SCLK falling edge
setup time, t4. To minimize the power consumption of the device,
the interface powers up fully only when the device is being written
to, that is, on the falling edge of SYNC.
After the falling edge of the 16th SCLK pulse, bring SYNC high to
transfer data from the input shift register to the DAC register.
Daisy-Chain Mode
Daisy-chain mode is the default power-on mode. To disable the daisy-chain function, write 01 to the control word. In daisy-chain
mode, the internal gating on the SCLK is disabled. The SCLK is
continuously applied to the input shift register when SYNC is low.
If more than 16 clock pulses are applied, the data ripples out of
the shift register and appears on the SDO line. This data is clocked
out on the rising edge of the SCLK (this is the default; use the
control word to change the active edge) and is valid for the next
device on the falling edge (default). By connecting this line to the
SDIN input on the next device in the chain, a multidevice interface
is constructed. Sixteen clock pulses are required for each device in
the system. Therefore, the total number of clock cycles must equal
16 N, where N is the number of devices in the chain.
When the serial transfer to all devices is complete, SYNC should be
taken high. This prevents any further data from being clocked into
the shift register. A burst clock containing the exact number of clock
cycles can be used, and SYNC can be taken high sometime later.
After the rising edge of SYNC, data is automatically transferred
from each device’s input register to the addressed DAC.
When the control bits = 10, the device is in no operation mode. This
can be useful in daisy-chain applications where the user does not
want to change the settings of a particular DAC in the chain. Simply
write 10 to the control bits for that DAC and the following data bits
are ignored.
The SCLK and DIN input buffers are powered down on the rising
edge of SYNC.
Figure 43. AD5444 12-Bit Input Shift Register Contents
Figure 44. AD5446 14-Bit Input Shift Register Contents
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Rev. G | 20 of 25
Data Sheet
AD5444/AD5446
SERIAL INTERFACE
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5444/AD5446 DAC is through
a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a
3‑wire interface consisting of a clock signal, a data signal, and
a synchronization signal. The AD5444/AD5446 requires a 16-bit
word, with the default being data valid on the falling edge of SCLK,
but this can be changed using the control bits in the data-word.
Table 11. SPORT Control Register Setup
Name
Setting
Description
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
1
1
00
1
1
1
1111
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
ADSP-2191M to AD5444/AD5446 Interface
The ADSP-2191M DSP is easily interfaced to the AD5444/AD5446
DAC without the need for extra glue logic. Figure 45 is an example
of an SPI interface between the DAC and the ADSP-2191M. SCK
of the DSP drives the serial clock line, SCLK. SYNC is driven from
one of the port lines, in this case SPIxSEL.
Blackfin to AD5444/AD5446 Interface
The ADSP-BF504 to ADSP-BF592 family of processors has an
SPI-compatible port that enables the processor to communicate
with SPI-compatible devices. Figure 47 shows a serial interface between the ADSP-BF504 to ADSP-BF592 family (the ADSP-BF534
shown as an example) and the AD5444/AD5446 DAC. In this
configuration, data is transferred through the MOSI (master output/slave input) pin. SYNC is driven by the SPI chip select pin,
which is a reconfigured programmable flag pin.
Figure 45. ADSP-2191M SPI to AD5444/AD5446 Interface
A serial interface between the DAC and DSP SPORT is shown in
Figure 46. In this interface example, SPORT0 is used to transfer
data to the DAC shift register. Transmission is initiated by writing
a word to the Tx register after the SPORT has been enabled. In
a write sequence, data is clocked out on each rising edge of the
DSP serial clock and clocked into the DAC input shift register on
the falling edge of its SCLK. The update of the DAC output takes
place on the rising edge of the SYNC signal.
Figure 47. ADSP-BF534 to AD5444/AD5446 Interface
The ADSP-BF534 processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and the
DSP SPORT is shown in Figure 48. When the SPORT is enabled,
initiate transmission by writing a word to the Tx register. The data
is clocked out on each rising edge of the DSPs serial clock and
clocked into the DAC input shift register on the falling edge of its
SCLK. The DAC output is updated by using the transmit frame
synchronization (TFS) line to provide a SYNC signal.
Figure 46. ADSP-2191M to AD5444/AD5446 Interface
Communication between two devices at a given clock speed is
possible when the following specifications are compatible: frame
sync delay and frame sync setup-and-hold, data delay and data
setup-and-hold, and SCLK width. The DAC interface expects a
t4 (SYNC falling edge to SCLK falling edge setup time) of 13
ns minimum. See the user manuals at www.analog.com/adsp-21xxprocessor-manuals for information on clock and frame sync frequencies for the SPORT register.
Table 11 shows the setup for the SPORT control register.
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Figure 48. ADSP-BF534 to AD5444/AD5446 Interface
80C51/80L51 to AD5444/AD5446 Interface
A serial interface between the DAC and the 80C51/80L51 is shown
in Figure 49. TxD of the 80C51/80L51 drives SCLK of the DAC
serial interface, while RxD drives the serial data line, SDIN. P1.1
is a bit-programmable pin on the serial port and is used to drive
Rev. G | 21 of 25
Data Sheet
AD5444/AD5446
SERIAL INTERFACE
SYNC. When data is to be transmitted to the switch, P1.1 is taken
low. The 80C51/80L51 transmits data only in 8-bit bytes; therefore,
only eight falling clock edges occur in the transmit cycle. To load
data correctly to the DAC, P1.1 is left low after the first eight bits
are transmitted, and a second write cycle is initiated to transmit the
second byte of data.
If the user wants to verify the data previously written to the input
shift register, the SDO line can be connected to MISO of the
MC68HC11, and, with SYNC low, the shift register clocks data out
on the rising edges of SCLK.
Data on RxD is clocked out of the microcontroller on the rising edge
of TxD and is valid on the falling edge. As a result, no glue logic
is required between the DAC and microcontroller interface. P1.1 is
taken high following the completion of this cycle. The 80C51/80L51
provides the LSB of its SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this into
account.
Figure 51 shows an interface between the DAC and any MICROWIRE-compatible device. Serial data is shifted out on the falling
edge of the serial clock, SK, and is clocked into the DAC input shift
register on the rising edge of SK, which corresponds to the falling
edge of the DAC SCLK.
MICROWIRE to AD5444/AD5446 Interface
Figure 51. MICROWIRE to AD5444/AD5446 Interface
Figure 49. 80C51/80L51 to AD5444/AD5446 Interface
MC68HC11 Interface to AD5444/AD5446
Interface
Figure 50 is an example of a serial interface between the DAC and
the MC68HC11 microcontroller. The serial peripheral interface (SPI)
on the MC68HC11 is configured for master mode (MSTR) = 1, clock
polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The
SPI is configured by writing to the SPI control register (SPCR); see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the DAC interface, the MOSI output drives the serial data line
(SDIN) of the AD5444/AD5446.
The SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5444/AD5446, the SYNC line is taken
low (PC7). Data appearing on the MOSI output is valid on the falling
edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit
bytes with only eight falling clock edges occurring in the transmit
cycle. Data is transmitted MSB first. To load data to the DAC, PC7
is left low after the first eight bits are transferred, and a second
serial write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
PIC16C6x/7x to AD5444/AD5446 Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured as
an SPI master with the clock polarity bit (CKP) = 0. This is done
by writing to the synchronous serial port control register (SSPCON);
see the PIC16/17 Microcontroller User Manual.
In this example, I/O port RA1 is used to provide a SYNC signal and
enable the serial port of the DAC. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore,
two consecutive write operations are required. Figure 52 shows the
connection diagram.
Figure 52. PIC16C6x/7x to AD5444/AD5446 Interface
Figure 50. MC68HC11 to AD5444/AD5446 Interface
analog.com
Rev. G | 22 of 25
Data Sheet
AD5444/AD5446
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit boards on which the
AD5444/AD5446 are mounted must be designed so the analog and
digital sections are separated and confined to certain areas of the
board. If the DACs are in systems in which multiple devices require
an AGND to DGND connection, make the connection at one point
only. Establish the star ground point as close as possible to the
devices.
The DAC must have ample supply bypassing of 10 µF in parallel
with 0.1 µF on the supply located as close to the package as
possible, ideally right up against the device. The 0.1 µF capacitor
must have low effective series resistance (ESR) and effective series
inductance (ESI), like the common ceramic types that provide
a low impedance path to ground at high frequencies, to handle
transient currents due to internal logic switching. Low ESR, 1 µF
to 10 µF tantalum or electrolytic capacitors must also be applied
at the supplies to minimize transient disturbance and filter out low
frequency ripple.
analog.com
Fast switching signals, such as clocks, must be shielded with digital
ground to avoid radiating noise to other parts of the board and must
never run near the reference inputs.
Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other to reduce the
effects of feedthrough throughout the board.
A microstrip technique, by far the best, is not always possible with
a double-sided board. In this technique, the component side of the
board is dedicated to the ground plane, while signal traces are
placed on the solder side.
It is good practice to employ compact, minimum lead length PCB
layout design. Ensure that the leads to the input are as short as
possible to minimize IR drops and stray inductance.
Match the PCB metal traces between VREF and RFB to minimize
gain error. To maximize high frequency performance, locate the
current to voltage (I to V) amplifier as close to the device as
possible.
Rev. G | 23 of 25
Data Sheet
AD5444/AD5446
OVERVIEW OF CURRENT OUTPUT DEVICES
Table 12.
Part Number
Resolution (Bits)
Number of DACs
INL (LSB)
Interface
Package1
Features
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
±0.25
±0.25
±0.25
±0.25
±0.25
±0.5
±0.5
±0.5
±0.5
±0.25
±1
±0.5
±1
±1
±1
±1
±1
±0.5
±1
±2
±1
±1
±1
±1
±2
±2
±2
±2
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
RU-16, CP-20
RM-10
RU-20
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
RU-24
UJ-8
RM-10
RM-10
RU-24
CP-40
RU-20, CP-20
RU-24
RU-16
UJ-8, RM-8
RM-10
UJ-8, RM-8
RM-8
RU-28
RM-8
RU-38
RM-8
RU-28
RU-16
RU-38
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
12 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial interface
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
1
RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
analog.com
Rev. G | 24 of 25
Data Sheet
AD5444/AD5446
OUTLINE DIMENSIONS
Figure 53. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Updated: August 15, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
AD5444YRMZ
AD5444YRMZ-REEL7
AD5446YRMZ
AD5446YRMZ-RL7
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
1
Packing Quantity
Reel, 1000
Reel, 1000
Package
Option
Marking Code
RM-10
RM-10
RM-10
RM-10
D6X
D6X
D7Z
D7Z
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model1
Description
EV-AD5443/46/53SDZ
Evaluation Board
1
Z = RoHS Compliant Part.
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Rev. G | 25 of 25
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