Dual 8-/10-/12-Bit, High Bandwidth,
Multiplying DACs with Serial Interface
AD5429/AD5439/AD5449
Data Sheet
FEATURES
GENERAL DESCRIPTION
10 MHz multiplying bandwidth
INL of ±0.25 LSB at 8 bits
16-lead TSSOP package
2.5 V to 5.5 V supply operation
±10 V reference input
50 MHz serial interface
2.47 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset
0.5 μA typical current consumption
Guaranteed monotonic
Daisy-chain mode
Readback function
The AD5429/AD5439/AD54491 are CMOS, 8-, 10-, and 12-bit,
dual-channel, current output digital-to-analog converters (DAC),
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
As a result of being manufactured on a CMOS submicron process,
these parts offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of 10 MHz.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
APPLICATIONS
These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI, QSPI™, MICROWIRE™, and most DSP
interface standards. In addition, a serial data out (SDO) pin allows
daisy-chaining when multiple packages are used. Data readback
allows the user to read the contents of the DAC register via the
SDO pin. On power-up, the internal shift register and latches
are filled with 0s, and the DAC outputs are at zero scale.
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
The AD5429/AD5439/AD5449 DACs are available in 16-lead
TSSOP packages. The EV-AD5415/49SDZ evaluation board is
available for evaluating DAC performance. For more
information, see the UG-297 evaluation board user guide.
FUNCTIONAL BLOCK DIAGRAM
VREFA
AD5429/AD5439/AD5449
RFB
R
VDD
SYNC
SCLK
SHIFT
REGISTER
INPUT
REGISTER
DAC
REGISTER
RFBA
IOUT1A
8-/10-/12-BIT
R-2R DAC A
IOUT2A
SDIN
SDO
LDAC
POWER-ON
RESET
INPUT
REGISTER
DAC
REGISTER
IOUT1B
8-/10-/12-BIT
R-2R DAC B
IOUT2B
RFB
R
LDAC
VREFB
RFBB
04464-001
CLR
Figure 1.
1
U.S. Patent Number 5,689,257.
Rev. F
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Technical Support
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AD5429/AD5439/AD5449
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital-to-Analog Converter .................................................... 15
Applications ....................................................................................... 1
Circuit Operation ....................................................................... 15
General Description ......................................................................... 1
Single-Supply Applications ....................................................... 17
Functional Block Diagram .............................................................. 1
Adding Gain ................................................................................ 18
Revision History ............................................................................... 2
Divider or Programmable Gain Element ................................ 18
Specifications..................................................................................... 3
Reference Selection .................................................................... 19
Timing Characteristics ................................................................ 5
Amplifier Selection .................................................................... 19
Timing Diagrams.......................................................................... 5
Serial Interface ............................................................................ 20
Absolute Maximum Ratings............................................................ 7
Microprocessor Interfacing ....................................................... 22
ESD Caution .................................................................................. 7
PCB Layout and Power Supply Decoupling ........................... 24
Pin Configuration and Function Descriptions ............................. 8
Overview of Multiplying DAC Devices ....................................... 25
Typical Performance Characteristics ............................................. 9
Outline Dimensions ....................................................................... 26
Terminology .................................................................................... 14
Ordering Guide .......................................................................... 26
Theory of Operation ...................................................................... 15
REVISION HISTORY
1/16—Rev. E to Rev. F
Changed AD54xx to AD5429/AD5439/AD5449 ........... Throughout
Changed ADSP-21xx to ADSP-2191M and Family........ Throughout
Changed ADSP-2101/ADSP-2103/ADSP-2191 to
ADSP-2191M ................................................................. Throughout
Changed ADSP-BF5xx to ADSP-BF534 ........................... Throughout
Deleted Positive Output Voltage Section and Figure 41;
Renumbered Sequentially.............................................................. 17
Changes to Adding Gain Section ................................................. 18
Changed Overview of AD54xx Devices Section to Overview
of Multiplying DAC Devices Section ........................................... 26
5/13—Rev. D to Rev. E
Changes to General Description .................................................... 1
Changes to Ordering Guide .......................................................... 26
6/11—Rev. C to Rev. D
Changes to General Description .................................................... 1
Deleted Evaluation Board for the DAC Section ......................... 24
Changes to Ordering Guide .......................................................... 30
7/05—Rev. 0 to Rev. A
Changes to Features List ...................................................................1
Changes to Specifications .................................................................3
Changes to Timing Characteristics .................................................5
Changes to Absolute Maximum Ratings Section ..........................7
Changes to General Description Section .................................... 15
Changes to Table 5.......................................................................... 15
Changes to Table 6.......................................................................... 16
Changes to Single-Supply Applications Section ......................... 17
Changes to Divider or Programmable Gain Element Section .... 18
Changes to Table 7 Through Table 10 ......................................... 20
Added ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface
Section.............................................................................................. 23
Change to PCB Layout and Power Supply Decoupling Section ..... 25
Changes to Power Supplies for the Evaluation Board Section .... 25
Changes to Table 13 ....................................................................... 29
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 30
7/04—Revision 0: Initial Version
4/10—Rev. B to Rev. C
Added to Figure 4 ............................................................................. 6
3/08—Rev. A to Rev. B
Added t13 and t14 Parameters to Table 2 ......................................... 5
Changes to Figure 2 .......................................................................... 5
Changes to Figure 3 .......................................................................... 6
Changes to Figure 38 ...................................................................... 16
Changes to Ordering Guide .......................................................... 30
Rev. F | Page 2 of 28
Data Sheet
AD5429/AD5439/AD5449
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance is measured with the OP177, and ac performance is measured with the AD8038, unless otherwise noted.
Table 1.
Parameter 1
STATIC PERFORMANCE
AD5429
Resolution
Relative Accuracy
Differential Nonlinearity
AD5439
Resolution
Relative Accuracy
Differential Nonlinearity
AD5449
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature
Coefficient
Output Leakage Current
REFERENCE INPUT
Reference Input Range
VREFA, VREFB Input Resistance
VREFA-to-VREFB Input Resistance
Mismatch
Input Capacitance
Code 0
Code 4095
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
Min
Typ
9
±10
11
1.6
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
Digital-to-Analog Glitch Impulse
Conditions
8
±0.5
±1
Bits
LSB
LSB
Guaranteed monotonic
10
±0.5
±1
Bits
LSB
LSB
Guaranteed monotonic
12
±1
−1/+2
±25
Bits
LSB
LSB
mV
ppm FSR/°C
Guaranteed monotonic
±5
±15
nA
nA
Data = 0x0000, TA = 25°C, IOUT1
Data = 0x0000, IOUT1
13
2.5
V
kΩ
%
Input resistance temperature coefficient = −50 ppm/°C
Typical = 25°C, maximum = 125°C
3.5
3.5
pF
pF
VDD = 3.6 V to 5.5 V
VDD = 2.5 V to 3.6 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5.5 V, ISOURCE = 200 µA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
VDD = 4.5 V to 5.5 V, ISINK = 200 µA
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
4
V
V
V
V
V
V
V
V
µA
pF
MHz
VREF = ±3.5 V p-p, DAC loaded all 1s
RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V,
DAC latch alternately loaded with 0s and 1s
1.7
1.7
0.8
0.7
VDD − 1
VDD − 0.5
Output Low Voltage, VOL
Input Leakage Current, IIL
Input Capacitance
DYNAMIC PERFORMANCE
Reference-Multiplying Bandwidth
Output Voltage Settling Time
Unit
±5
Input Low Voltage, VIL
Output High Voltage, VOH
Max
0.4
0.4
1
10
10
80
35
30
20
3
120
70
60
40
ns
ns
ns
ns
nV-sec
Rev. F | Page 3 of 28
1 LSB change around major carry, VREF = 0 V
AD5429/AD5439/AD5449
Parameter 1
Multiplying Feedthrough Error
Data Sheet
Min
Output Capacitance
Digital Feedthrough
Output Noise Spectral Density
Analog THD
Digital THD
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Wide Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Intermodulation Distortion
f1 = 40 kHz, f2 = 50 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
IDD
Typ
Max
Unit
12
25
3
70
48
17
30
5
dB
dB
pF
pF
nV-sec
25
81
nV/√Hz
dB
61
66
dB
dB
AD5449, 65k codes, VREF = 3.5 V
55
63
65
dB
dB
dB
50
60
62
dB
dB
dB
AD5449, 65k codes, VREF = 3.5 V
73
80
87
dB
dB
dB
70
75
80
dB
dB
dB
72
65
dB
dB
AD5449, 65k codes, VREF = 3.5 V
Clock = 10 MHz
Clock = 25 MHz
V
µA
µA
%/%
TA = 25°C, logic inputs = 0 V or VDD
TA = −40°C to +125°C, logic inputs = 0 V or VDD
∆VDD = ±5%
2.5
0.5
Power Supply Sensitivity
1
Conditions
DAC latches loaded with all 0s, VREF = ±3.5 V
1 MHz
10 MHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
@ 1 kHz
VREF = 3. 5 V p-p, all 1s loaded, f = 1 kHz
Clock = 10 MHz, VREF = 3.5 V
5.5
0.7
10
0.001
Guaranteed by design and characterization, not subject to production test.
Rev. F | Page 4 of 28
Data Sheet
AD5429/AD5439/AD5449
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t123
t13
t14
Update Rate
Limit at TMIN, TMAX
50
20
8
8
13
5
4
5
30
0
12
10
25
60
12
4.5
2.47
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Conditions/Comments2
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
CLR pulse width
SYNC rising edge to LDAC falling edge
Consists of cycle time, SYNC high time, data setup, and output voltage settling time
1
Guaranteed by design and characterization, not subject to production test.
Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
3
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5.
2
TIMING DIAGRAMS
t1
SCLK
t8
t2
t4
t3
t7
SYNC
t6
t5
SDIN
DB15
DB0
t9
t10
LDAC1
t11
LDAC2
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED.
Figure 2. Standalone Mode Timing Diagram
Rev. F | Page 5 of 28
04464-002
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
AD5429/AD5439/AD5449
Data Sheet
t1
SCLK
t2
t4
t3
t7
SYNC
t5
SDIN
t6
t8
DB0
(N)
DB15
(N)
DB15
(N + 1)
DB0
(N + 1)
DB15
(N)
DB0
(N)
t12
SDO
04464-003
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON THE FALLING
EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain Timing Diagram
SCLK
16
32
SYNC
DB15
DB0
DB15
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB0
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
Figure 4. Readback Mode Timing Diagram
200A
TO OUTPUT
PIN
IOL
VOH (MIN) + VOL (MAX)
2
CL
50pF
200A
IOH
Figure 5. Load Circuit for SDO Timing Specifications
Rev. F | Page 6 of 28
04464-059
DB15
SDO
04464-004
SDIN
Data Sheet
AD5429/AD5439/AD5449
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VREFx, RFBx to GND
IOUT1, IOUT2 to GND
Input Current to Any Pin Except Supplies
Logic Inputs and Output 1
Operating Temperature Range
Extended (Y Version)
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (> R2||R3
and a gain error percentage of 100 × (R2||R3)/RFB must be taken
into consideration.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current into the VREFx terminal
is routed to the IOUT1 terminal, the output voltage changes as
follows:
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
Current-steering DACs are very flexible and lend themselves
to many applications. If this type of DAC is connected as the
feedback element of an op amp and RFBA is used as the input
resistor, as shown in Figure 42, the output voltage is inversely
proportional to the digital input fraction, D.
where R is the DAC resistance at the VREFx terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
For D = 1 − 2−n, the output voltage is
VOUT = − VIN / D = − VIN / (1 − 2 − n )
VDD
R1
IOUT1A
VREFA 8-/10-/12-BIT
DAC
IOUT2A
VOUT
R3
GND
R2
GAIN =
R2 + R3
R2
R2R3
R1 =
R2 + R3
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
04464-011
VIN
C1
RFBA
VDD
Figure 41. Increasing Gain of Current Output DAC
VDD
VIN
RFBA
IOUT1A
IOUT2A
VDD
8-/10-/12-BIT V
REF A
DAC
GND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
04464-012
VOUT
Figure 42. Current-Steering DAC Used as a Divider or Programmable Gain Element
Rev. F | Page 18 of 28
Data Sheet
AD5429/AD5439/AD5449
REFERENCE SELECTION
the amplifier input offset voltage. This output voltage change is
superimposed on the desired change in output between the two
codes and gives rise to a differential linearity error, which, if
large enough, could cause the DAC to be nonmonotonic. The
input bias current of an op amp also generates an offset at the
voltage output as a result of the bias current flowing in the feedback
resistor, RFB. Most op amps have input bias currents low enough
to prevent significant errors in 12-bit applications.
When selecting a reference for use with the AD5429/AD5439/
AD5449 series of current output DACs, pay attention to the
reference output voltage temperature coefficient specification. This
parameter affects not only the full-scale error, but it can also affect
the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy
specifications. For example, an 8-bit system required to hold its
overall specification to within 1 LSB over the temperature range of
0°C to 50°C dictates that the maximum system drift with temperature should be less than 78 ppm/°C. A 12-bit system with the same
temperature range to overall specification within 2 LSBs requires a
maximum drift of 10 ppm/°C. By choosing a precision reference
with a low output temperature coefficient, this error source can be
minimized. Table 7 lists some references available from Analog
Devices, Inc., that are suitable for use with this range of current
output DACs.
Common-mode rejection of the op amp is important in voltageswitching circuits because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.
If the DAC switches are driven from true wideband low impedance
sources (VIN and AGND), they settle quickly. Consequently, the
slew rate and settling time of a voltage-switching DAC circuit
is determined largely by the output op amp. To obtain minimum
settling time in this configuration, minimize capacitance at the VREF
node (the voltage output node in this application) of the DAC by
using low input capacitance buffer amplifiers and careful board
design.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC, the
input offset voltage of an op amp is multiplied by the variable gain
of the circuit. A change in this noise gain between two adjacent
digital fractions produces a step change in the output voltage due to
Most single-supply circuits include ground as part of the analog
signal range, which, in turn, requires an amplifier that can handle
rail-to-rail signals. Analog Devices offers a wide range of singlesupply amplifiers (see Table 8 and Table 9).
Table 7. Suitable Analog Devices Precision References
Part No.
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
Output Voltage (V)
10
10
5
5
2.5
2.5
3
3
2.5
5
2.5
5
Initial Tolerance (%)
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
Temp Drift (ppm/°C)
3
9
3
9
3
9
3
9
3
3
9
9
ISS (mA)
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
Output Noise (µV p-p)
20
20
10
10
6
6
10
10
3.5
8
5
8
Package
SOIC
TSOT, SC70
SOIC
TSOT, SC70
SOIC
TSOT, SC70
SOIC
TSOT, SC70
SOIC
SOIC
TSOT
TSOT
Table 8. Suitable Analog Devices Precision Op Amps
Part No.
OP97
OP1177
AD8551
AD8603
AD8628
Supply Voltage (V)
±2 to ±20
±2.5 to ±15
2.7 to 5
1.8 to 6
2.7 to 6
VOS (Max) (µV)
25
60
5
50
5
IB (Max) (nA)
0.1
2
0.05
0.001
0.1
0.1 Hz to 10 Hz Noise (µV p-p)
0.5
0.4
1
2.3
0.5
Supply Current (µA)
600
500
975
50
850
Package
SOIC
MSOP, SOIC
MSOP, SOIC
TSOT
TSOT, SOIC
Table 9. Suitable Analog Devices High Speed Op Amps
Part No.
AD8065
AD8021
AD8038
AD9631
Supply Voltage (V)
5 to 24
±2.5 to ±12
3 to 12
±3 to ±6
BW @ ACL (MHz)
145
490
350
320
Slew Rate (V/µs)
180
120
425
1300
Rev. F | Page 19 of 28
VOS (Max) (µV)
1500
1000
3000
10,000
IB (Max) (nA)
6000
10,500
750
7000
Package
SOIC, SOT-23, MSOP
SOIC, MSOP
SOIC, SC70
SOIC
AD5429/AD5439/AD5449
Data Sheet
SERIAL INTERFACE
SDO Control (SDO1 and SDO2)
The AD5429/AD5439/AD5449 have an easy-to-use, 3-wire
interface that is compatible with SPI, QSPI, MICROWIRE, and
most DSP interface standards. Data is written to the device in
16-bit words. Each 16-bit word consists of four control bits and
eight, 10, or 12 data bits, as shown in Figure 43 through Figure 45.
The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an open-drain
driver. The strength of the SDO driver affects the timing of t12,
and, when stronger, allows a faster clock cycle.
Low Power Serial Interface
SDO2
0
SDO1
0
Function Implemented
Full SDO driver
0
1
1
1
0
1
Weak SDO driver
SDO configured as open drain
Disable SDO output
Table 10. SDO Control Bits
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC. The SCLK and SDIN input buffers
are powered down on the rising edge of SYNC.
DAC Control Bit C3 to Control Bit C0
Daisy-Chain Control (DSY)
Control Bit C3 to Control Bit C0 allow control of various functions
of the DAC, as shown in Table 11. The default settings of the DAC
at power-on are such that data is clocked into the shift register
on falling clock edges and daisy-chain mode is enabled. The device
powers on with a zero-scale load to the DAC register and IOUT lines.
The DAC control bits allow the user to adjust certain features at
power-on. For example, daisy-chaining can be disabled if not in
use, an active clock edge can be changed to a rising edge, and DAC
output can be cleared to either zero scale or midscale. The user
can also initiate a readback of the DAC register contents for verification.
DSY allows the enabling or disabling of daisy-chain mode.
A 1 enables daisy-chain mode; a 0 disables daisy-chain mode.
When disabled, a readback request is accepted; SDO is automatically enabled; the DAC register contents of the relevant
DAC are clocked out on SDO; and, when complete, SDO is
disabled again.
Hardware CLR Bit (HCLR)
The default setting for the hardware CLR bit is to clear the registers
and DAC output to zero code. A 1 in the HCLR bit allows the
CLR pin to clear the DAC outputs to midscale, and a 0 clears to
zero scale.
Control Register (Control Bits = 1101)
Active Clock Edge (SCLK)
While maintaining software compatibility with single-channel
current output DACs (AD5426/AD5432/AD5443), these DACs
also feature additional interface functionality. Set the control bits
to 1101 to enter control register mode. Figure 46 shows the
contents of the control register, the functions of which are
described in the following sections.
The default active clock edge is a falling edge. Write a 1 to this
bit to clock data in on the rising edge, or a 0 to clock it in on the
falling edge.
C3
DB0 (LSB)
C2
C1
C0
DB7
DB6
DB5
DB4
DB3
CONTROL BITS
DB2
DB1
DB0
0
0
0
0
DATA BITS
04464-013
DB15 (MSB)
Figure 43. AD5429 8-Bit Input Shift Register Contents
C3
DB0 (LSB)
C2
C1
C0
DB9
DB8
DB7
DB6
DB5
CONTROL BITS
DB4
DB3
DB2
DB1
DB0
0
0
DB2
DB1
DATA BITS
04464-014
DB15 (MSB)
Figure 44. AD5439 10-Bit Input Shift Register Contents
C3
DB0 (LSB)
C2
C1
C0
DB11
DB10
DB9
DB8
DB7
CONTROL BITS
DB6
DB5
DB4
DB3
DB0
DATA BITS
04464-015
DB15 (MSB)
Figure 45. AD5449 12-Bit Input Shift Register Contents
1
DB0 (LSB)
1
0
1
SDO2
SDO1
DSY
HCLR
SCLK
X
X
X
CONTROL BITS
Figure 46. Control Register Loading Sequence
Rev. F | Page 20 of 28
X
X
X
X
04464-016
DB15 (MSB)
Data Sheet
AD5429/AD5439/AD5449
SYNC Function
SYNC is an edge-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the
device only while SYNC is low. To start the serial data transfer,
SYNC should be taken low, observing the minimum SYNC
falling edge to SCLK falling edge setup time, t4.
Daisy-Chain Mode
Daisy-chain mode is the default power-on mode. To disable the
daisy-chain function, write 1001 to the control word. In daisychain mode, the internal gating on SCLK is disabled. SCLK is
continuously applied to the input shift register when SYNC is
low. If more than 16 clock pulses are applied, the data ripples
out of the shift register and appears on the SDO line. This data
is clocked out on the rising edge of SCLK (this is the default; use
the control word to change the active edge) and is valid for the
next device on the falling edge of SCLK (default). By connecting
this line to the SDIN input on the next device in the chain,
a multidevice interface is constructed. For each device in the
system, 16 clock pulses are required. Therefore, the total number
of clock cycles must equal 16n, where n is the total number of
devices in the chain. See Figure 4.
When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents additional data from being clocked
into the input shift register. A burst clock containing the exact
number of clock cycles can be used, after which SYNC can be
taken high. After the rising edge of SYNC, data is automatically
transferred from the input shift register of each device to the
addressed DAC.
When control bits = 0000, the device is in no operation mode.
This may be useful in daisy-chain applications in which the user
does not want to change the settings of a particular DAC in the
chain. Write 0000 to the control bits for that DAC; subsequent
data bits are ignored.
Standalone Mode
After power-on, write 1001 to the control word to disable daisychain mode. The first falling edge of SYNC resets the serial
clock counter to ensure that the correct number of bits are
shifted in and out of the serial shift registers. A SYNC edge
during the 16-bit write cycle causes the device to abort the
current write cycle.
After the falling edge of the 16th SCLK pulse, data is automatically transferred from the input shift register to the DAC. For
another serial transfer to take place, the counter must be reset
by the falling edge of SYNC.
LDAC Function
The LDAC function allows asynchronous and synchronous
updates to the DAC output. The DAC is asynchronously updated
when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected,
whereby the DAC is updated on the 16th clock falling edge when
the device is in standalone mode, or on the rising edge of SYNC
when the device is in daisy-chain mode.
Software LDAC Function
Load-and-update mode can also serve as a software update function, irrespective of the voltage level on the LDAC pin.
Table 11. DAC Control Bits
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC
A and B
A
A
A
B
B
B
A and B
A and B
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Function Implemented
No operation (power-on default)
Load and update
Initiate readback
Load input register
Load and update
Initiate readback
Load input register
Update DAC outputs
Load input registers
Disable daisy-chain
Clock data to shift register on rising edge
Clear DAC output to zero scale
Clear DAC output to midscale
Control word
Reserved
No operation
Rev. F | Page 21 of 28
AD5429/AD5439/AD5449
Data Sheet
See the ADSP-2191M user manual at www.analog.com for
details on clock and frame SYNC frequencies for the SPORT
register. Table 12 shows the setup for the SPORT control register.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5429/AD5439/AD5449
DACs is through a serial bus that uses standard protocol and is
compatible with microcontrollers and DSP processors. The
communication channel is a 3-wire interface consisting of a
clock signal, a data signal, and a synchronization signal. The
AD5429/AD5439/AD5449 require a 16-bit word, with the
default being data valid on the falling edge of SCLK; however,
this is changeable using the control bits in the data-word.
Table 12. SPORT Control Register Setup
ADSP-2191M*
SPIxSEL
AD5429/AD5439/
AD5449*
SYNC
SDIN
SCK
SCLK
ADSP-BF534-to-AD5429/AD5439/AD5449 Interface
The ADSP-BF534 family of processors has an SPI-compatible port
that enables the processor to communicate with SPI-compatible
devices. A serial interface between the BlackFin® processor and
the AD5429/AD5439/AD5449 DAC is shown in Figure 49. In
this configuration, data is transferred through the MOSI pin.
SYNC is driven by the SPIxSEL pin, which is a reconfigured
programmable flag pin.
*ADDITIONAL PINS OMITTED FOR CLARITY.
SPIxSEL
Figure 47. ADSP-2191M SPI-to-AD5429/AD5439/AD5449 Interface
The ADSP-2191M processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
DSP SPORT is shown in Figure 48. In this interface example,
SPORT0 is used to transfer data to the DAC shift register.
Transmission is initiated by writing a word to the Tx register after
SPORT has been enabled. In a write sequence, data is clocked
out on each rising edge of the DSP serial clock and clocked into
the DAC input shift register on the falling edge of its SCLK.
Updating of the DAC output takes place on the rising edge of
the SYNC signal.
AD5429/AD5439/
AD5449*
ADSP-2191M*
AD5429/AD5439/
AD5449*
ADSP-BF534*
04464-027
MOSI
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
SYNC
MOSI
SDIN
SCK
SCLK
04464-033
The ADSP-2191M family of DSPs is easily interfaced to an
AD5429/AD5439/AD5449 DAC without the need for extra glue
logic. Figure 47 is an example of a serial peripheral interface (SPI)
between the DAC and the ADSP-2191M. The MOSI (master
output, slave input) pin of the DSP drives the serial data line,
SDIN. SYNC is driven from a port line, in this case SPIxSEL.
Setting
1
1
00
1
1
1
1111
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 49. ADSP-BF534-to-AD5429/AD5439/AD5449 Interface
A serial interface between the DAC and the DSP SPORT is shown
in Figure 50. When SPORT is enabled, initiate transmission by
writing a word to the Tx register. The data is clocked out on each
rising edge of the DSP serial clock and clocked into the DAC
input shift register on the falling edge of its SCLK. The DAC
output is updated by using the transmit frame synchronization
(TFS) line to provide a SYNC signal.
AD5429/AD5439/
AD5449*
ADSP-BF534*
TFS
SYNC
DT
SDIN
TFS
SYNC
SCLK
DT
SDIN
SCLK
04464-028
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 48. ADSP-2191M SPORT-to-AD5429/AD5439/AD5449 Interface
Communication between two devices at a given clock speed is
possible when the following specifications are compatible: frame
SYNC delay and frame SYNC setup-and-hold, data delay and
data setup-and-hold, and SCLK width. The DAC interface expects
a t4 (SYNC falling edge to SCLK falling edge setup time) of 13 ns
minimum.
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 50. ADSP-BF534 SPORT-to-AD5429/AD5439/AD5449 Interface
Rev. F | Page 22 of 28
04464-034
ADSP-2191M and Family-to-AD5429/AD5439/AD5449
Interface
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
Data Sheet
AD5429/AD5439/AD5449
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and then a second write cycle is initiated
to transmit the second byte of data. Data on RxD is clocked out
of the microcontroller on the rising edge of TxD and is valid on
the falling edge of TxD. As a result, no glue logic is required
between the DAC and microcontroller interface. P1.1 is taken
high following the completion of this cycle. The 80C51/80L51
provide the LSB of the SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this
requirement into account.
To load data to the DAC, leave PC7 low after the first eight bits
are transferred and perform a second serial write operation to
the DAC. PC7 is taken high at the end of this procedure.
If the user wants to verify the data previously written to the input
shift register, the SDO line can be connected to MISO of the
MC68HC11, and, with SYNC low, the shift register clocks data
out on the rising edges of SCLK.
MICROWIRE-to-AD5429/AD5439/AD5449 Interface
Figure 53 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC SCLK.
MICROWIRE*
AD5429/AD5439/
AD5449*
80C51*
SCLK
RxD
SDIN
P1.1
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 51. 80C51/80L51-to-AD5429/AD5439/AD5449 Interface
MC68HC11-to-AD5429/AD5439/AD5449 Interface
Figure 52 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The SPI on the MC68HC11
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured
by writing to the SPI control register (SPCR); see the MC68HC11
user manual. The SCK of the MC68HC11 drives the SCLK of
the DAC interface; the MOSI output drives the serial data line
(SDIN) of the AD5429/AD5439/AD5449.
MC68HC11*
MOSI
SDIN
SYNC
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 microcontroller user manual for
more information. In this example, the I/O port, RA1, is used to
provide a SYNC signal and enable the serial port of the DAC. This
microcontroller transfers only eight bits of data during each serial
transfer operation; therefore, two consecutive write operations
are required. Figure 54 shows the connection diagram.
PIC16C6x/7x*
AD5429/AD5439/
AD5449*
SCK/RC3
SCLK
SDI/RC4
SDIN
RA1
04464-030
SCLK
SDIN
CS
PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface
SYNC
SCK
SCLK
Figure 53. MICROWIRE-to-AD5429/AD5439/AD5449 Interface
AD5429/AD5439/
AD5449*
PC7
SK
SO
*ADDITIONAL PINS OMITTED FOR CLARITY.
04464-029
TxD
AD5429/AD5439/
AD5449*
04464-031
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 51. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line, SDIN.
P1.1 is a bit-programmable pin on the serial port and is used to
drive SYNC. When data is to be transmitted to the switch, P1.1
is taken low. The 80C51/80L51 transmit data in 8-bit bytes only;
therefore, only eight falling clock edges occur in the transmit cycle.
valid on the falling edge of SCK. Serial data from the 68HC11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 52. MCH68HC11/68L11-to-AD5429/AD5439/AD5449 Interface
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5429/AD5439/AD5449, the SYNC
line is taken low (PC7). Data appearing on the MOSI output is
Rev. F | Page 23 of 28
Figure 54. PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface
04464-032
80C51/80L51-to-AD5429/AD5439/AD5449 Interface
AD5429/AD5439/AD5449
Data Sheet
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5429/AD5439/AD5449 is mounted should be
designed so that the analog and digital sections are separate
and confined to certain areas of the board. If the DAC is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
The DAC should have ample supply bypassing of 10 µF in parallel
with 0.1 µF on the supply, located as close as possible to the
package, ideally right up against the device. The 0.1 µF capacitor
should have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types of
capacitors that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Components, such as clocks, that produce fast-switching signals,
should be shielded with digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
layout reduces the effects of feedthrough on the board. A microstrip technique is by far the best method, but its use is not always
possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, and
signal traces are placed on the soldered side.
It is good practice to use compact, minimum lead-length PCB
layout design. Leads to the input should be as short as possible
to minimize IR drops and stray inductance.
The PCB metal traces between VREFx and RFBx should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close as
possible to the device.
Rev. F | Page 24 of 28
Data Sheet
AD5429/AD5439/AD5449
OVERVIEW OF MULTIPLYING DAC DEVICES
Table 13.
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
1
Resolution
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
No. DACs
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
INL (LSB)
±0.25
±0.25
±0.25
±0.25
±0.25
±0.5
±0.5
±0.5
±0.5
±0.25
±1
±0.5
±1
±1
±1
±1
±1
±0.5
±1
±2
±1
±1
±1
±1
±2
±2
±2
±2
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package 1
RU-16, CP-20
RM-10
RU-20
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
RU-24
UJ-8
RM-10
RM-8
RU-24
CP-40
RU-20, CP-20
RU-24
RU-16
UJ-8, RM-8
RM-8
UJ-8, RM-8
RM-8
RU-28
RM-8
RU-38
RM-8
RU-28
RU-16
RU-38
RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. F | Page 25 of 28
Features
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
AD5429/AD5439/AD5449
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 55. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5429YRU-REEL7
AD5429YRUZ
AD5429YRUZ-REEL7
AD5439YRU-REEL
AD5439YRU-REEL7
AD5439YRUZ
AD5439YRUZ-REEL7
AD5449YRU
AD5449YRU-REEL
AD5449YRU-REEL7
AD5449YRUZ
AD5449YRUZ-REEL
AD5449YRUZ-REEL7
EV-AD5415/49SDZ
1
Resolution
8
8
8
10
10
10
10
12
12
12
12
12
12
INL (LSB)
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±1
±1
±1
±1
±1
±1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Z = RoHS Compliant Part.
Rev. F | Page 26 of 28
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation Board
Package Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
Data Sheet
AD5429/AD5439/AD5449
NOTES
Rev. F | Page 27 of 28
AD5429/AD5439/AD5449
Data Sheet
NOTES
©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04464-0-1/16(F)
Rev. F | Page 28 of 28
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