Serial Input, Voltage Output
12-/14-Bit Digital-to-Analog Converters
AD5530/AD5531
FUNCTIONAL BLOCK DIAGRAM
Pin-compatible 12-, 14-bit digital-to-analog converters
Serial input, voltage output
Maximum output voltage range of ±10 V
Data readback
3-wire serial interface
Clear function to a user-defined voltage
Power-down function
Serial data output for daisy-chaining
16-lead TSSOP
APPLICATIONS
Industrial automation
Automatic test equipment
Process control
General-purpose instrumentation
VSS
VDD
AD5530/AD5531
REFIN
R
12-/14-BIT
DAC
R
VOUT
R
REFAGND
R
LDAC
DUTGND
DAC REGISTER
RBEN
CLR
SDIN
POWER-DOWN
CONTROL LOGIC
SHIFT REGISTER
GND
SCLK
SYNC
PD
SDO
00938-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The AD5530/AD5531 are single 12- and 14-bit (respectively)
serial input, voltage output digital-to-analog converters (DAC).
They utilize a versatile 3-wire interface that is compatible with
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Data
is presented to the part in a 16-bit serial word format. Serial
data is available on the SDO pin for daisy-chaining purposes.
Data readback allows the user to read the contents of the DAC
register via the SDO pin.
The DAC output is buffered by a gain of two amplifier and
referenced to the potential at DUTGND. LDAC can be used to
update the output of the DAC asynchronously. A power-down
pin (PD) allows the DAC to be put into a low power state, and
a CLR pin allows the output to be cleared to a user-defined
voltage, the potential at DUTGND.
The AD5530/AD5531 are available in 16-lead TSSOP.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
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Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD5530/AD5531
TABLE OF CONTENTS
Features .............................................................................................. 1
PD Function................................................................................ 13
Applications....................................................................................... 1
Readback Function .................................................................... 13
Functional Block Diagram .............................................................. 1
CLR Function.............................................................................. 13
General Description ......................................................................... 1
Output Voltage............................................................................ 14
Revision History ............................................................................... 2
Bipolar Configuration................................................................ 14
Specifications..................................................................................... 3
Microprocessor Interfacing........................................................... 15
AC Performance Characteristics ................................................ 5
AD5530/AD5531 to ADSP-21xx.............................................. 15
Standalone Timing Characteristics............................................ 5
AD5530/AD5531 to 8051 Interface ......................................... 15
Daisy-Chaining and Readback Timing Characteristics.......... 6
AD5530/AD5531 to MC68HC11 Interface ............................ 15
Absolute Maximum Ratings............................................................ 7
Applications Information .............................................................. 17
ESD Caution.................................................................................. 7
Optocoupler Interface................................................................ 17
Pin Configuration and Function Descriptions............................. 8
Serial Interface to Multiple AD5530s or AD5531s ................ 17
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Daisy-Chaining Interface with Multiple AD5530s or
AD5531s ...................................................................................... 17
Theory of Operation ...................................................................... 13
Outline Dimensions ....................................................................... 18
DAC Architecture....................................................................... 13
Ordering Guide .......................................................................... 18
Serial Interface ............................................................................ 13
REVISION HISTORY
1/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Figure 28...................................................................... 17
3/06—Rev. 0 to Rev. A
Change to Table 3 ............................................................................. 5
Change to Figure 4 ........................................................................... 8
Change to Output Voltage Section............................................... 14
Change to Ordering Guide............................................................ 18
5/02—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD5530/AD5531
SPECIFICATIONS
VDD = 15 V ± 10%; VSS = −15 V ± 10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter 1
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Gain Temperature Coefficient 2
REFERENCE INPUTS2
Reference Input Range
DC Input Resistance
Input Current
DUTGND INPUT2
DC Input Impedance
Max Input Current
Input Range
O/P CHARACTERISTICS2
Output Voltage Swing
Short-Circuit Current
Resistive Load
Capacitive Load
DC Output Impedance
DIGITAL I/O
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance2
SDO VOL, Output Low Voltage
POWER REQUIREMENTS
VDD/VSS
Power Supply Sensitivity
ΔFull Scale/ΔVDD
ΔFull Scale/ΔVSS
IDD
ISS
IDD in Power-Down
1
2
AD5530
AD5531
Unit
12
±1
±1
±2
±2
±1
0.5
10
14
±2
±1
±8
±8
±4
0.5
10
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
ppm FSR/°C typ
ppm FSR/°C max
0 to 5
100
±1
0 to 5
100
±1
V min to V max
MΩ typ
μA max
Per input, typically ±20 nA
60
±0.3
−4 to +4
60
±0.3
−4 to +4
kΩ typ
mA typ
V min to V max
Max output range ±10 V
±10
15
5
1200
0.5
±10
15
5
1200
0.5
V max
mA max
kΩ min
pF max
Ω max
2.4
0.8
±10
10
0.4
2.4
0.8
±10
10
0.4
V min
V max
μA max
pF max
V max
Total for all pins
3 pF typical
ISINK = 1 mA
+15/−15
+15/−15
V nom
±10% for specified performance
110
100
2
2
150
110
100
2
2
150
dB typ
dB typ
mA max
mA max
μA max
Outputs unloaded
Outputs unloaded
Typically 50 μA
Temperature range for B Version: −40°C to +85°C.
Guaranteed by design, not subject to production test.
Rev. B | Page 3 of 20
Test Conditions/Comments
Guaranteed monotonic over temperature
Typically within ±1 LSB
Typically within ±1 LSB
Max output range ±10 V
To 0 V
To 0 V
AD5530/AD5531
VDD = 12 V ± 10%; VSS = −12 V ± 10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Gain Temperature Coefficient 2
REFERENCE INPUTS2
Reference Input Range
DC Input Resistance
Input Current
DUTGND INPUT2
DC Input Impedance
Max Input Current
Input Range
O/P CHARACTERISTICS2
Output Voltage Swing
Short-Circuit Current
Resistive Load
Capacitive Load
DC Output Impedance
DIGITAL I/O
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance2
SDO VOL, Output Low Voltage
POWER REQUIREMENTS
VDD/VSS
Power Supply Sensitivity
ΔFull Scale/ΔVDD
ΔFull Scale/ΔVSS
IDD
ISS
IDD in Power-Down
1
2
AD5530
AD5531
Unit
12
±1
±1
±2
±2
±1
0.5
10
14
±2
±1
±8
±8
±4
0.5
10
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
ppm FSR/°C typ
ppm FSR/°C max
0 to 4.096
100
±1
0 to 4.096
100
±1
V min to V max
MΩ typ
μA max
Per input, typically ±20 nA
60
±0.3
−3 to +3
60
±0.3
−3 to +3
kΩ typ
mA typ
V min to V max
Max output range ±8.192 V
±8.192
15
5
1200
0.5
±8.192
15
5
1200
0.5
V max
mA max
kΩ min
pF max
Ω max
2.4
0.8
±10
10
0.4
2.4
0.8
±10
10
0.4
V min
V max
μA max
pF max
V max
Total for all pins
3 pF typical
ISINK = 1 mA
+12/−12
+12/−12
V nom
±10% for specified performance
110
100
2
2
150
110
100
2
2
150
dB typ
dB typ
mA max
mA max
μA max
Outputs unloaded
Outputs unloaded
Typically 50 μA
Temperature range for B Version: −40°C to +85°C.
Guaranteed by design, not subject to production test.
Rev. B | Page 4 of 20
Test Conditions/Comments
Guaranteed monotonic over temperature
Typically within ±1 LSB
Typically within ±1 LSB
Max output range ±8.192 V
To 0 V
To 0 V
AD5530/AD5531
AC PERFORMANCE CHARACTERISTICS
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
B Version
Unit
Test Conditions/Comments
20
μs typ
Full-scale change to ±½ LSB. DAC latch contents alternately
loaded with all 0s and all 1s.
Slew Rate
Digital-to-Analog Glitch Impulse
1.3
120
V/μs typ
nV-s typ
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
0.5
100
nV-s typ
nV/√Hz typ
DAC latch alternately loaded with 0x0FFF and 0x1000. Not
dependent on load conditions.
Effect of input bus activity on DAC output under test.
All 1s loaded to DAC.
STANDALONE TIMING CHARACTERISTICS
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless
otherwise noted.
Table 4.
Parameter 1, 2
fMAX
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
2
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SCLK frequency
SCLK cycle time
SCLK low time
SCLK high time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Min SYNC high time
Data setup time
Data hold time
SYNC high to LDAC low
LDAC pulse width
LDAC high to SYNC low
CLR pulse width
Guaranteed by design, not subject to production test.
Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to
90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
t1
t3
SCLK
t4
SYNC
t2
t5
t6
t7
MSB
SDIN
DB15
DB14
t8
LSB
DB11
DB0
t9
LDAC1
t11
t10
t12
CLR
1LDAC
00938-002
1
Limit at TMIN, TMAX
7
140
60
60
50
40
50
40
15
5
50
5
50
CAN BE TIED PERMANENTLY LOW, IF REQUIRED.
Figure 2. Timing Diagram for Standalone Mode
Rev. B | Page 5 of 20
AD5530/AD5531
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless
otherwise noted.
Table 5.
Parameter 1, 2, 3
fMAX
t1
t2
t3
t4
t5
t6
t7
t8
t12
t13
t14
t15
t16
t17
Limit at TMIN, TMAX
2
500
200
200
50
40
50
40
15
50
130
50
50
50
100
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
Description
SCLK frequency
SCLK cycle time
SCLK low time
SCLK high time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Min SYNC high time
Data setup time
Data hold time
CLR pulse width
SCLK falling edge to SDO valid
SCLK falling edge to SDO invalid
RBEN to SCLK falling edge setup time
RBEN hold time
RBEN falling edge to SDO valid
1
Guaranteed by design, not subject to production test.
Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to
90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3
SDO; RPULLUP = 5 kΩ, CL = 15 pF
2
t1
t3
SCLK
t4
t6
t7
MSB
SDIN
DB15
DB14
t8
DB11
LSB
DB0
t13
SDO
(DAISYCHAINING)
t14
MSB
DB15
LSB
DB11
DB0
t15
t16
RBEN
t13
t17
SDO
(READBACK)
0
MSB
Figure 3. Timing Diagram for Daisy-Chaining and Readback Mode
Rev. B | Page 6 of 20
t14
0
RB13
RB0
LSB
00938-003
SYNC
t2
t5
AD5530/AD5531
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to GND
VSS to GND
Digital Inputs to GND
SDO to GND
REFIN to REFAGND
REFIN to GND
REFAGND to GND
DUTGND to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature (TJ MAX)
Package Power Dissipation
Thermal Impedance θJA
TSSOP (RU-16)
Lead Temperature (Soldering 10 sec)
IR Reflow, Peak Temperature (
