32-Channel, 14-Bit
Voltage-Output DAC
AD5532
FEATURES
GENERAL DESCRIPTION
High integration:
32-channel DAC in 12 mm × 12 mm CSPBGA
Adjustable voltage output range
Guaranteed monotonic
Readback capability
DSP/microcontroller compatible serial interface
Output impedance:
0.5 Ω (AD5532-1, AD5532-2)
500 Ω (AD5532-3)
1 kΩ (AD5532-5)
Output voltage span:
10 V (AD5532-1, AD5532-3, AD5532-5)
20 V (AD5532-2)
Infinite sample-and-hold capability to ±0.018% accuracy
Temperature range −40°C to +85°C
The AD55321 is a 32-channel, 14-bit voltage-output DAC with
an additional infinite sample-and-hold mode. The selected
DAC register is written to via the 3-wire serial interface; VOUT
for this DAC is then updated to reflect the new contents of the
DAC register. DAC selection is accomplished via Address Bits
A0–A4. The output voltage range is determined by the offset
voltage at the OFFS_IN pin and the gain of the output amplifier.
It is restricted to a range from VSS + 2 V to VDD – 2 V because of
the headroom of the output amplifier.
The device is operated with AVCC = 5 V ± 5%; DVCC = 2.7 V to
5.25 V; VSS = −4.75 V to −16.5 V; and VDD = 8 V to 16.5 V. The
AD5532 requires a stable 3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
APPLICATIONS
1.
Automatic test equipment
Optical networks
Level setting
Instrumentation
Industrial control systems
Data acquisition
Low cost I/O
2.
3.
DVCC AVCC
REF_IN REF_OUT
32-channel, 14-bit DAC in one package, guaranteed
monotonic.
Available in a 74-lead CSPBGA package with a body size of
12 mm ×12 mm.
Droopless/infinite sample-and-hold mode.
OFFS_IN
VDD
VSS
AD5532
VOUT0
ADC
BUSY
DGND
SER/PAR
DAC
OFFS_OUT
MODE
AGND
MUX
VOUT31
DAC
INTERFACE
CONTROL
LOGIC
ADDRESS INPUT REGISTER
SCLK DIN DOUT
SYNC/CS
A4–A0
CAL
OFFSET_SEL
WR
00939-C-001
TRACK/RESET
DAC_GND
DAC
14-BIT BUS
VIN
Figure 1. Functional Block Diagram
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2010 Analog Devices, Inc. All rights reserved.
AD5532
TABLE OF CONTENTS
Specifications..................................................................................... 3
Output Buffer Stage—Gain and Offset.................................... 14
ISHA Mode.................................................................................... 5
Offset Voltage Channel .............................................................. 14
Timing Characteristics..................................................................... 6
Reset Function ............................................................................ 14
Parallel Interface ........................................................................... 6
ISHA Mode ................................................................................. 14
Parallel Interface Timing Diagrams ........................................... 6
Analog Input (ISHA Mode) ...................................................... 14
Serial Interface .............................................................................. 7
TRACK Function (ISHA Mode) .............................................. 15
Absolute Maximum Ratings............................................................ 8
Modes of Operation ................................................................... 15
ESD Caution .................................................................................. 8
Serial Interface ............................................................................ 16
Pin Configuration and Function Descriptions ............................. 9
Parallel Interface (ISHA Mode Only) ...................................... 17
Terminology .................................................................................... 11
Microprocessor Interfacing ....................................................... 17
Dac Mode .................................................................................... 11
Application Circuits ................................................................... 18
ISHA Mode.................................................................................. 11
Power Supply Decoupling ......................................................... 19
Typical Performance Characteristics ........................................... 12
Outline Dimensions ....................................................................... 20
Functional Description .................................................................. 14
Ordering Guide .......................................................................... 20
REVISION HISTORY
6/10—Data Sheet Changed from Rev. C to Rev. D
Changes to Table 5 ...................................................................... 8
Changes to Ordering Guide ....................................................20
6/04—Data Sheet Changed from Rev. B to Rev. C
Updated Format ........................................................... Universal
Changed LFBGA to CSPBGA .................................... Universal
Changes to Outline Dimensions.............................................24
Changes to Ordering Guide ....................................................24
6/02—Data Sheet Changed from Rev. A to Rev. B
Term SHA changed to ISHA ........................................... Global
Changes to Absolute Maximum Ratings ................................. 6
Changes to Ordering Guide ...................................................... 6
Changes to Functional Description .......................................11
Changes to Table 8 ....................................................................11
Changes to ISHA Mode ...........................................................11
Added Figure 27 and accompanying text ..............................15
Changes to Power Supply Decoupling Section .....................15
Rev. D | Page 2 of 20
AD5532
SPECIFICATIONS
VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V;
REF_IN = 3 V; output range from VSS + 2 V to VDD − 2 V. All outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter 2
DAC DC PERFORMANCE
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset
Gain
Full Scale Error
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage
Input Voltage Range 3
Input Current
REF_OUT
Output Voltage
Output Impedance3
Reference Temperature Coefficient3
ANALOG OUTPUTS (VOUT 0–31)
Output Temperature Coefficient3, 4
DC Output Impedance3
AD5532-1
AD5532-3
AD5532-5
Output Range
Resistive Load3, 5
Capacitive Load3, 5
AD5532-1
AD5532-3
AD5532-5
Short-Circuit Current3
DC Power-Supply Rejection Ratio3
DC Crosstalk3
ANALOG OUTPUT (OFFS_OUT)
Output Temperature Coefficient3, 4
DC Output Impedance3
Output Range
Output Current
Capacitive Load
DIGITAL INPUTS3
Input Current
Input Low Voltage
Input High Voltage
Input Hysteresis (SCLK and CS Only)
A Version 1
AD5532-1/-3/-5
AD5532-2 Only
Unit
14
±0.39
±1
90/170/250
3.52
±2
14
±0.39
±1
180/350/500
7
±2
Bits
% of FSR max
LSB max
mV min/typ/max
typ
% of FSR max
3.0
2.85/3.15
1
3.0
2.85/3.15
1
V typ
V min/max
μA max
3
280
60
3
280
60
V typ
kΩ typ
ppm/°C typ
10
10
ppm/°C typ
0.5
500
1
VSS + 2/VDD − 2
5
0.5
Ω typ
Ω typ
kΩ typ
V min/max
kΩ min
VSS + 2 /VDD − 2
5
500
15
40
7
−70
−70
250
500
7
−70
−70
1800
pF max
nF max
nF max
mA typ
dB typ
dB typ
μV max
10
1.3
50 to REF_IN−12
10
100
10
1.3
50 to REF_IN−12
10
100
ppm/°C typ
kΩ typ
mV typ
μA max
pF max
±10
0.8
0.4
2.4
2.0
200
±10
0.8
0.4
2.4
2.0
200
μA max
V max
V max
V min
V min
mV typ
Rev. D | Page 3 of 20
Conditions/Comments
±0.15% typ
±0.5 LSB typ, monotonic
See Figure 8
< 1 nA typ
VDD = +15 V ±5%
VSS = −15 V ±5%
Source current
±5 μA typ
DVCC = 5 V ±5%
DVCC = 3 V ±10%
DVCC = 5 V ±5%
DVCC = 3 V ±10%
AD5532
A Version 1
AD5532-1/-3/-5
AD5532-2 Only
10
10
Unit
pF max
Conditions/Comments
0.4
4.0
0.4
2.4
±1
15
0.4
4.0
0.4
2.4
±1
15
V max
V min
V max
V min
μA max
pF typ
Sinking 200 μA.
Sourcing 200 μA.
Sinking 200 μA.
Sourcing 200 μA.
DOUT only.
DOUT only.
8/16.5
−4.75/−16.5
4.75/5.25
2.7/5.25
8/16.5
−4.75/−16.5
4.75/5.25
2.7/5.25
V min/max
V min/max
V min/max
V min/max
15
15
mA max
15
15
mA max
33
1.5
280
33
1.5
280
mA max
mA max
mW typ
Output Voltage Settling Time
22
30
μs max
OFFS_IN Settling Time
10
25
Digital-to-Analog Glitch Impulse
1
1
nV-s typ
Digital Crosstalk
Analog Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
5
1
0.2
400
5
1
0.2
400
nV-s typ
nV-s typ
nV-s typ
nV/(√Hz) typ
2
Parameter
Input Capacitance
DIGITAL OUTPUTS (BUSY, DOUT)3
Output Low Voltage, DVCC = 5 V
Output High Voltage, DVCC = 5 V
Output Low Voltage, DVCC = 3 V
Output High Voltage, DVCC = 3 V
High Impedance Leakage Current
High Impedance Output Capacitance
POWER REQUIREMENTS
Power-Supply Voltages
VDD
VSS
AVCC
DVCC
Power-Supply Currents 6
IDD
ISS
AICC
DICC
Power Dissipation6
AC CHARACTERISTICS3
1
A version: Industrial temperature range -40°C to +85°C; typical at +25°C.
See Terminology section.
3
Guaranteed by design and characterization, not production tested.
4
AD780 as reference for the AD5532.
5
Ensure that you do not exceed TJ (max). See Absolute Maximum Ratings section.
6
Output unloaded.
2
Rev. D | Page 4 of 20
μs max
10 mA typ. All channels
full scale.
10 mA typ. All channels
full scale.
26 mA typ.
1 mA typ.
VDD = 10 V, VSS = −5 V.
500 pF, 5 kΩ load. Full-scale
change.
500 pF, 5 kΩ load; 0 V to 3 V
step.
1 LSB change around. Major
carry.
AD5532
ISHA MODE
Table 2.
2
Parameter
ANALOG CHANNEL
VIN to VOUT Nonlinearity 3
Offset Error
Gain
ANALOG INPUT (VIN)
Input Voltage Range
Input Lower Dead Band
Input Upper Dead Band
Input Current
Input Capacitance 4
ANALOG INPUT (OFFS_IN)
Input Current
Input Voltage Range
AC CHARACTERISTICS
Output Settling Time4
Acquisition Time
AC Crosstalk4
A Version 1
AD5532-1/-3/-5
AD5532-2 Only
Unit
Conditions/Comments
±0.018
±50
3.46/3.52/3.6
±0.018
±75
6.96/7/7.02
% max
mV max
min/typ/max
±0.006% typ after offset and gain adjustment.
±10 mV typ. See Figure 9.
See Figure 9
0 to 3
70
40
1
0 to 3
70
40
1
V
mV max
mV max
μA max
Nominal input range.
50 mV typ. Referred to VIN. See Figure 9.
12 mV typ. Referred to VIN. See Figure 9.
100 nA typ.
VIN acquired on 1 channel.
20
20
pF typ
1
0/4
1
0/4
μA max
Vmin/max
100 nA typ.
Output range restricted from VSS + 2 V to VDD − 2 V.
3
16
5
3
16
5
μs max
μs max
nV-s typ
Output unloaded.
1
A version: Industrial temperature range -40°C to +85°C; typical at +25°C.
See Terminology section.
Input range 100 mV to 2.96 V.
4
Guaranteed by design and characterization, not production tested.
2
3
Rev. D | Page 5 of 20
AD5532
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Table 3.
Parameter 1, 2
t1
t2
t3
t4
t5
t6
1
2
Limit at TMIN, TMAX (A Version)
0
0
50
50
20
7
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
CS to WR setup time
CS to WR hold time
CS pulse width low
WR pulse width low
A4–A0, CAL, OFFS_SEL to WR setup time
A4–A0, CAL, OFFS_SEL to WR hold time
See Figure 2 and Figure 3, the parallel interface timing diagrams.
Guaranteed by design and characterization, not production tested.
PARALLEL INTERFACE TIMING DIAGRAMS
t2
t1
CS
t3
200μA
IOL
t4
WR
A4–A0, CAL,
OFFS_SEL
1.6V
CL
50pF
200μA
IOH
00939-C-003
TO OUTPUT
PIN
t6
00939-C-002
t5
Figure 3. Load Circuit for DOUT Timing Specifications
Figure 2. Parallel Write (ISHA Mode Only)
Rev. D | Page 6 of 20
AD5532
SERIAL INTERFACE
Table 4.
Parameter 1 , 2
fCLKIN 3
t1
t2
t3
t4
t5
t6
t7
t8 4
t94
t10
t11
t12 5
Limit at TMIN, TMAX (A Version)
14
28
28
15
50
10
5
5
20
60
400
400
7
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
Conditions/Comments
SCLK frequency
SCLK high pulse width
SCLK low pulse width
SYNC falling edge to SCLK falling edge setup time
SYNC low time
DIN setup time
DIN hold time
SYNC falling edge to SCLK rising edge setup time for read back
SCLK rising edge to DOUT valid
SCLK falling edge to DOUT high impedance
10th SCLK falling edge to SYNC falling edge for read back
24th SCLK falling edge to SYNC falling edge for DAC mode write
SCLK falling edge to SYNC falling edge setup time for read back
t1
1
SCLK
2
3
t3
4
5
6
7
8
9
10
t2
SYNC
t5
t4
00939-C-004
t6
DIN
MSB
LSB
Figure 4. 10-Bit Write (ISHA Mode and Both Readback Modes)
t1
SCLK
1
2
t3
3
4
5
21
22
23
24
1
t2
SYNC
t4
t11
t5
00939-C-005
t6
DIN
MSB
LSB
Figure 5. 24-Bit Write (DAC Mode)
t7
SCLK
10
t1
1
2
t12
3
4
5
6
7
8
9
10
11
12
13
14
t2
SYNC
t10
t9
t8
DOUT
MSB
LSB
Figure 6. 14-Bit Read (Both Readback Modes)
1
See Figure 4, Figure 5, and Figure 6.
Guaranteed by design and characterization, not production tested.
3
In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulse width is 20 ns.
4
These numbers are measured with the load circuit of Figure 3.
5 SYNC
should be taken low while SCLK is low for read back.
2
Rev. D | Page 7 of 20
00939-C-006
t4
AD5532
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 5.
Parameter 1
VDD to AGND
VSS to AGND
AVCC to AGND, DAC_GND
DVCC to DGND
Digital Inputs to DGND
Digital Outputs to DGND
REF_IN to AGND, DAC_ GND
VIN to AGND, DAC_GND
VOUT 0–31 to AGND
OFFS_IN to AGND
OFFS_OUT to AGND
AGND to DGND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
74-Lead CSPBGA Package,
θJA Thermal Impedance
Reflow Soldering
Peak Temperature
AD5532ABC-x
AD5532ABCZ-x
Time at Peak Temperature
Max Power Dissipation
Max Continuous Load Current at
TJ = 70°C, per Channel Group
Rating
−0.3 V to +17 V
+0.3 V to −17 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V
−0.3 V to DVCC + 0.3 V
−0.3 V to AVCC + 0.3 V
−0.3 V to AVCC + 0.3 V
VSS − 0.3 V to VDD + 0.3 V
VSS − 0.3 V to VDD + 0.3 V
AGND - 0.3 V to AVCC + 0.3 V
−0.3 V to +0.3 V
−40°C to +85°C
−65°C to +150°C
150°C
41°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
For higher junction temperatures derate as follows:
TJ (°C)
70
90
100
110
125
135
150
Max Continuous Load Current per Group (mA)
15.5
9.025
6.925
5.175
3.425
2.55
1.5
ESD CAUTION
220°C
260°C
10 sec to 40 sec
(150°C − TA)/θJA mW 2
15 mA 3
1
Transient currents of up to 100 mA do not cause SCR latch-up.
This limit includes load power.
3
This maximum allowed continuous load current is spread over 8 channels
and channels are grouped as follows:
Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10
Group 2: Channels 14, 16, 18, 20. 21, 24, 25, 26
Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29
Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31
2
Rev. D | Page 8 of 20
AD5532
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10 11
A
A
B
B
C
C
D
D
E
E
F
F
TOP VIEW
G
H
H
J
J
K
K
L
L
1
2
3
4
5
6
7
8
9
10 11
00939-C-028
G
Figure 7. 74-Lead CSPBGA Ball Configuration
Table 6. 74-Lead CSPBGA Ball Configuration
CSPBGA Number
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C6
Ball Name
Not connected
A4
A2
A0
CS/SYNC
DVCC
SCLK
OFFSET_SEL
BUSY
TRACK/RESET
Not connected
VO16
Not connected
A3
A1
WR
DGND
DIN
CAL
SER/PAR
DOUT
REF_IN
VO18
DAC_GND1
Not connected
CSPBGA Number
C10
C11
D1
D2
D10
D11
E1
E2
E10
E11
F1
F2
F10
F11
G1
G2
G10
G11
H1
H2
H10
H11
J1
J2
J6
Ball Name
AVCC1
REF_OUT
VO20
DAC_GND2
AVCC2
OFFS_OUT
VO26
VO14
AGND1
OFFS_IN
VO25
VO21
AGND2
VO6
VO24
VO8
VO5
VO3
VO23
VIN
VO4
VO7
VO22
VO19
VSS2
Rev. D | Page 9 of 20
CSPBGA Number
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
Ball Name
VO9
VO11
VO17
VO15
VO27
VSS3
VSS1
VSS4
VDD2
VO2
VO10
VO13
VO12
Not connected
VO28
VO29
VO30
VDD3
VDD1
VDD4
VO31
VO0
VO1
Not connected
AD5532
Table 7. Pin Function Descriptions
Pin
AGND (1–2)
AVCC (1–2)
VDD (1–4)
VSS (1–4)
DGND
DVCC
DAC_GND (1–2)
REF_IN
REF_OUT
VOUT (0–31)
VIN
A4–A1, A0
CAL
CS/SYNC
WR
OFFSET_SEL
SCLK
DIN
DOUT
SER/PAR
OFFS_IN
OFFS_OUT
BUSY
TRACK/RESET
Function
Analog GND pins.
Analog Supply pins. Voltage range from 4.75 V to 5.25 V.
VDD Supply pins. Voltage range from 8 V to 16.5 V.
VSS Supply pins. Voltage range from –4.75 V to –16.5 V.
Digital GND pins.
Digital Supply pins. Voltage range from 2.7 V to 5.25 V.
Reference GND supply for all DACs.
Reference voltage for Channels 0–31.
Reference Output Voltage.
Analog Output Voltages from the 32 channels.
Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
Parallel Interface: 5 address pins for 32 channels. A4 = MSB of channel address. A0 = LSB. Internal pull-up devices on these
logic inputs. Therefore, they can be left floating and default to a logic high condition.
Parallel Interface: Control input that allows all 32 channels to acquire VIN simultaneously. Internal pull-down devices on
these logic inputs. Therefore, they can be left floating and default to a logic low condition
This is the active low Chip Select pin for the parallel interface and the Frame Synchronization pin for the serial interface.
Parallel interface: Write pin; active low. This is used in conjunction with the CS pin to address the device using the parallel
interface. Internal pull-down devices on these logic inputs. Therefore, they can be left floating and default to a logic low
condition.
Parallel interface: Offset Select pin; active high. This is used to select the offset channel. Internal pull-down devices on
these logic inputs. Therefore, they can be left floating and default to a logic low condition
Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode).
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK. Internal pull-up devices on these logic
inputs. Therefore, they can be left floating and default to a logic high condition.
Output from the DAC registers for read back. Data is clocked out on the rising edge of SCLK and is valid on the falling
edge of SCLK.
This pin allows the user to select whether the serial or parallel interface is used. If the pin is tied low, the parallel interface
is used. If it is tied high, the serial interface is used. Internal pull-down devices on these logic inputs. Therefore, they can
be left floating and default to a logic low condition.
Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the
user wants to drive this pin with the offset channel.
Offset Output. This is the acquired/programmed offset voltage which can be tied to OFFS_IN to offset the span.
This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when
the acquisition operation is complete.
If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the gain/offset
stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge of TRACK. See TRACK
Input section for further information. This input can also be used as a means of resetting the complete device to its
power-on-reset conditions. This is achieved by applying a low-going pulse of between 90 ns and 200 ns to this pin. See
section on RESET Function for further details. Internal pull-up devices on these logic inputs. Therefore, they can be left
floating and default to a logic high condition.
VOUT
OUTPUT
VOLTAGE
GAIN ERROR +
OFFSET ERROR
IDEAL
TRANSFER
FUNCTION
FULL-SCALE
ERROR RANGE
IDEAL GAIN × REFIN
IDEAL GAIN × 50mV
0
16k
DAC CODE
00939-C-007
OFFSET
RANGE
ACTUAL
TRANSFER
FUNCTION
OFFSET
ERROR
0V
70mV
LOWER
DEAD BAND
Figure 8. DAC Transfer Function (OFFS_IN=0)
2.96 3V
UPPER
DEAD BAND
Figure 9. ISHA Transfer Function
Rev. D | Page 10 of 20
VIN
00939-C-008
IDEAL TRANSFER
FUNCTION
AD5532
TERMINOLOGY
Output Noise Spectral Density
DAC MODE
This is a measure of the maximum deviation from a straight
line passing through the endpoints of the DAC transfer
function. It is expressed as a percentage of full-scale span.
This is a measure of internally generated random noise.
Random noise is characterized as a spectral density (voltage per
root Hertz). It is measured by loading all DACs to midscale and
measuring noise at the output. It is measured in nV/(√Hz).
Differential Nonlinearity (DNL)
Output Temperature Coefficient
This is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
DNL of ±1 LSB maximum ensures monotonicity.
This is a measure of the change in analog output with changes
in temperature. It is expressed in ppm/°C.
Offset
DC power-supply rejection ratio is a measure of the change in
analog output for a change in supply voltage (VDD and VSS). It is
expressed in dBs. VDD and VSS are varied ±5%.
Integral Nonlinearity (INL)
Offset is a measure of the output with all zeros loaded to the
DAC and OFFS_IN = 0. Because the DAC is lifted off the
ground by approximately 50 mV, this output is typically
DC Power-Supply Rejection Ratio (PSRR)
DC Crosstalk
VOUT = Gain × 50 mV
Full-Scale Error
This is a measure of the output error with all 1s loaded to the
DAC. It is expressed as a percentage of full-scale range. See
Figure 8. It is calculated as
Full − Scale Error = VOUT ( Full −Scale) − (Ideal Gain × REFIN )
This is the DC change in the output level of one DAC at
midscale in response to a full-scale code change (all 0s to all 1s
and vice versa) and an output change of all other DACs. It is
expressed in μV.
ISHA MODE
VIN to VOUT Nonlinearity
The measure of the maximum deviation from a straight line
passing through the endpoints of the VIN versus VOUT transfer
function. It is expressed as a percentage of the full-scale span.
where
Ideal Gain = 3.52 for AD5532 − 1/ − 3 /− 5
Ideal Gain = 7 for AD5532 − 2
Offset Error
Output Settling Time
This is the time taken from when the last data bit is clocked into
the DAC until the output has settled to within ±0.39%.
OFFS_IN Settling Time
This is a measure of the output error when VIN = 70 mV. Ideally,
with VIN = 70 mV:
VOUT = (Gain × 70 ) − ((Gain − 1) × VOFFS _ IN ) mV
The time taken from a 0 V to 3 V step change in input voltage
on OFFS_IN until the output has settled to within ±0.39%.
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal). It is expressed in mV and can be positive or
negative. See Figure 9.
Digital-to-Analog Glitch Impulse
Gain Error
This is the area of the glitch injected into the analog output
when the code in the DAC register changes state. It is specified
as the area of the glitch in nV-secs when the digital code is
changed by 1 LSB at the major carry transition (011 . . . 11 to
100 . . . 00 or 100 . . . 00 to 011 . . . 11).
This is a measure of the span error of the analog channel. It is
the deviation in slope of the transfer function expressed in mV.
See Figure 9. It is calculated as
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale while a full-scale code change (all 1s to all 0s and
vice versa) is written to another DAC. It is expressed in nV-secs.
Analog Crosstalk
This is the area of the glitch transferred to the output (VOUT) of
one DAC due to a full-scale change in the output (VOUT) of
another DAC. The area of the glitch is expressed in nV-secs.
Digital Feedthrough
This is a measure of the impulse injected into the analog
outputs from the digital control inputs when the part is not
being written to, i.e., CS/SYNC is high. It is specified in nV-secs
and is measured with a worst-case change on the digital input
pins, for example, from all 0s to all 1s and vice versa.
Gain Error =
Actual Full-Scale Output − Ideal Full-Scale Output − Offset Error
where:
Ideal Full−Scale Output = Gain × 2.96 − ((Gain − 1) × VOFFS _ IN )
AC Crosstalk
This is the area of the glitch that occurs on the output of one
channel while another channel is acquiring. It is expressed in
nV-secs.
Output Settling Time
This is the time taken from when BUSY goes high to when the
output has settled to ±0.018%.
Acquisition Time
This is the time taken for the VIN input to be acquired. It is the
length of time that BUSY stays low.
Rev. D | Page 11 of 20
AD5532
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
3.535
VREFIN = 3V
0.8 VOFFS_IN = 0V
TA = 25°C
0.6
TA = 25°C
VREFIN = 3V
3.530
0.2
VOUT (V)
DNL ERROR (LSB)
0.4
0
–0.2
3.525
–0.4
–0.8
–1.0
0
2k
4k
6k
8k
10k
DAC CODE
12k
14k
00939-C-012
00939-C-009
–0.6
3.520
16k
6
10
0.2
1.0
8
DNL MAX
0
0
INL MIN
DNL MIN
TA = 25°C
VREFIN = 3V
VOFFS_IN = 0.5V
4
2
–0.1
–0.2
0
40
TEMPERATURE (°C)
00939-C-013
00939-C-010
0
–1.0
–40
–6
6
VOUT (V)
INL ERROR (% FSR)
DNL ERROR (LSB)
–4
0.1
INL MAX
–0.5
2
0
–2
SINK/SOURCE CURRENT (mA)
Figure 13. VOUT Source and Sink Capability
Figure 10. Typical DNL Plot
0.5
4
–2
80
TIME BASE (2μs/DIV)
Figure 14. Full-Scale Settling Time
Figure 11. INL Error an DNL Error vs. Temperature
5.309
5.325
DAC LOADED TO MIDSCALE
VREFIN = 3V
VOFFS_IN = 0V
5.308
5.315
5.307
5.306
VOUT (V)
5.295
5.305
5.304
5.303
5.275
–40
0
40
TEMPERATURE (°C)
80
5.302
TA = 25°C
VREFIN = 3V
VOFFS_IN = 0V
00939-C-014
5.285
00939-C-011
VOUT (V)
5.305
5.301
TIME BASE (50ns/DIV)
Figure 15. Major Code Transition Glitch Impulse
Figure 12. VOUT vs. Temperature
Rev. D | Page 12 of 20
AD5532
0.024
70k
TA = 25°C
0.020 VREFIN = 3V
V
= 0V
0.016 OFFS_IN
63791
60k
50k
0.008
FREQUENCY
0.004
0
–0.004
40k
30k
–0.008
20k
–0.012
00939-C-015
–0.016
–0.020
–0.024
0.10
2.96
VIN (V)
Figure 16. VIN to VOUT Accuracy after Offset and Gain Adjustment (ISHA
Mode)
5V
100
BUSY
90
VOUT
TA = 25°C
VREFIN = 3V
VIN = 0 → 1.5V
10
1V
2μs
00939-C-016
0%
Figure 17. Acquisition Time and Output Settling Time (ISHA Mode)
Rev. D | Page 13 of 20
10k
1545
200
0
5.2670
5.2676
VOUT (V)
5.2682
Figure 18. ISHA-Mode Repeatability (64 k Acquisitions)
00939-C-017
VOUT ERROR (%)
0.012
TA = 25°C
VREFIN = 3V
VIN = 1.5V
VOFFS_IN = 0V
AD5532
FUNCTIONAL DESCRIPTION
The AD5532 consists of 32 DACs and an ADC (for ISHA
mode) in a single package. In DAC mode, a 14-bit digital word
is loaded into one of the 32 DAC Registers via the serial
interface. This is then converted (with gain and offset) into an
analog output voltage (VOUT0–VOUT31).
To update a DAC’s output voltage, the required DAC is
addressed via the serial port. When the DAC address and code
have been loaded, the selected DAC converts the code.
At power-on, all the DACs, including the offset channel, are
loaded with zeros. Each of the 33 DACs is offset internally by
50 mV (typ) from GND, so the outputs VOUT 0 to VOUT 31 are
50 mV (typ) at power-on if the OFFS_IN pin is driven directly
by the on-board offset channel (OFFS_OUT), i.e. if OFFS_IN is
50 mV, VOUT = (Gain × VDAC) – (Gain – 1) ×VOFFS_IN = 50 mV.
OUTPUT BUFFER STAGE—GAIN AND OFFSET
The function of the output buffer stage is to translate the 50
mV–3 V output of the DAC to a wider range. This is done by
gaining up the DAC output by 3.52/7 and offsetting the voltage
by the voltage on OFFS_IN pin.
AD5532-1/AD5532-3/AD5532-5:
VOUT = 3.52 × VDAC − 2.52 × VOFFS _ IN
AD5532-2:
VOUT = 7 × VDAC − 6 × VOFFS _ IN
VDAC is the output of the DAC.
VOFFS_IN is the voltage at the OFFS_IN pin.
The following table shows how the output range on VOUT relates
to the offset voltage supplied by the user.
OFFS_IN this offset voltage can be used as the offset voltage for
the 32 output amplifiers. It is important to choose the offset so
that VOUT is within maximum ratings.
RESET FUNCTION
The reset function on the AD5532 can be used to reset all
nodes on this device to their power-on reset condition. This is
implemented by applying a low-going pulse of between 90 ns
and 200 ns to the TRACK/RESETpin on the device. If the
applied pulse is less than 90 ns, it is assumed to be a glitch
and no operation takes place. If the applied pulse is wider
than 200 ns, this pin adopts its track function on the selected
channel, VIN is switched to the output buffer, and an acquisition
on the channel does not occur until a rising edge of TRACK.
ISHA MODE
In ISHA mode, the input voltage VIN is sampled and converted
into a digital word. The noninverting input to the output buffer
(gain and offset stage) is tied to VIN during the acquisition
period to avoid spurious outputs, while the DAC acquires the
correct code. This is completed in 16 μs max. The updated DAC
output then assumes control of the output voltage. The output
voltage of the DAC is connected to the noninverting input of
the output buffer. Because the channel output voltage is
effectively the output of a DAC, there is no droop associated
with it. As long as power is maintained to the device, the output
voltage is constant until this channel is addressed again.
Because the internal DACs are offset by 70 mV (max) from
GND, the minimum VIN in ISHA mode is 70 mV. The
maximum VIN is 2.96 V due to the upper dead band of 40 mV
(max).
ANALOG INPUT (ISHA MODE)
VOFFS_IN
(V)
0.5
1
VDAC
(V)
0.05 to 3
0.05 to 3
VOUT
(AD5532-1/-3/-5)
−1.26 to +9.3
−2.52 to +8.04
VOUT
(AD5532-2)
Headroom limited
−6 to +15
VOUT is limited only by the headroom of the output amplifiers.
VOUT must be within maximum ratings.
OFFSET VOLTAGE CHANNEL
The offset voltage can be externally supplied by the user at
OFFS_IN or it can be supplied by an additional offset voltage
channel on the device itself. The offset can be set up in two
ways. In ISHA mode, the required offset voltage is set up on VIN
and acquired by the offset channel. In DAC mode, the code
corresponding to the offset value is loaded directly into the
offset DAC. This offset channel’s DAC output is directly
connected to OFFS_OUT. By connecting OFFS_OUT to
Figure 19 shows the equivalent analog input circuit. The
Capacitor C1 is typically 20 pF and can be attributed to pin
capacitance and 32 off-channels. When a channel is selected, an
extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged
to the previously acquired voltage on that particular channel so
it must charge/discharge to the new level. The external source
must be able to charge/discharge this additional capacitance
within 1 μs–2 μs of channel selection so that VIN can be
acquired accurately. Thus, a low impedance source is suggested.
ADDRESSED CHANNEL
VIN
C1
20pF
C2
7.5pF
00939-C-018
Table 8. Sample Output Voltage Ranges
Figure 19. Analog Input Circuit
Large source impedances significantly affect the performance
of the ADC. An input buffer amplifier may be required.
Rev. D | Page 14 of 20
AD5532
1. ISHA Mode
TRACK FUNCTION (ISHA MODE)
Typically in ISHA mode of operation TRACK is held high and
the channel begins to acquire when it is addressed. However, if
TRACK is low when the channel is addressed, VIN is switched to
the output buffer and an acquisition on the channel does not
occur until a rising edge of TRACK. At this stage, the BUSY pin
goes low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and VIN
is free to change again without affecting this output value.
This is useful in an application where the user wants to ramp up
VIN until VOUT reaches a particular level (see Figure 20). VIN
does not need to be acquired continuously while it is ramping
up. TRACK can be kept low and only when VOUT has reached its
desired voltage is TRACK brought high. At this stage, the
acquisition of VIN begins.
In the example shown, a desired voltage is required on the
output of the pin driver. This voltage is represented by one input
to a comparator. The microcontroller/microprocessor ramps up
the input voltage on VIN through a DAC. TRACK is kept low
while the voltage on VIN ramps up so that VIN is not continually
acquired. When the desired voltage is reached on the output of
the pin driver, the comparator output switches. The μC/μP then
knows what code is required to be input to obtain the desired
voltage at the DUT. The TRACK input is now brought high and
the part begins to acquire VIN. At this stage BUSY goes low until
VIN has been acquired. The output buffer is then switched from
VIN to the output of the DAC.
MODES OF OPERATION
The AD5532 can be used in four different modes of operation.
These modes are set by two mode bits, the first two bits in the
serial word.
Table 9. Modes of Operation
Mode Bit 2
0
1
0
1
Operating Mode
ISHA mode
DAC mode
Acquire and Read Back
Read Back
2. DAC Mode
In this standard mode, a selected DAC register is loaded serially.
This requires a 24-bit write (10 bits to address the relevant DAC
plus an extra 14 bits of DAC data). MSB is written first. The
user must allow 400 ns (min) between successive writes in DAC
mode.
3. Acquire and Readback Mode
This mode allows the user to acquire VIN and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and VIN is acquired in 16 μs (max).
Following the acquisition, after the next falling edge of SYNC,
the data in the relevant DAC register is clocked out onto the
DOUT line in a 14-bit serial format. The full acquisition time
must elapse before the DAC register data can be clocked out.
4. Readback Mode
Again, this is a Readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of SYNC, the data in the relevant DAC
register is clocked out onto the DOUT line in a 14-bit serial
format. The user must allow 400 ns (min) between the last
SCLK falling edge in the 10-bit write and the falling edge of
SYNC in the 14-bit read back. The serial write and read words
can be seen in Figure 21.
This feature allows the user to read back the DAC register code
of any of the channels. In DAC mode, this is useful in
verification of write cycles. In ISHA mode, readback is useful if
the system has been calibrated and the user wants to know what
code in the DAC corresponds to a desired voltage on VOUT. If
this voltage is required again, the user can input the code
directly to the DAC register without going through the
acquisition sequence.
PIN
DRIVER
VIN
CONTROLLER
DAC
ACQUISITION
CIRCUIT
OUTPUT
STAGE
VOUT1
DEVICE
UNDER
TEST
BUSY
TRACK
AD5532
THRESHOLD
VOLTAGE
ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
Figure 20. Typical ATE Circuit Using TRACK Input
Rev. D | Page 15 of 20
00939-C-019
Mode Bit 1
0
0
1
1
In this mode, a channel is addressed and that channel acquires
the voltage on VIN. This mode requires a 10-bit write (see Figure
21a) to address the relevant channel (VOUT0–VOUT31, offset
channel or all channels). MSB is written first.
AD5532
not shift data in or out until it receives the falling edge of the
SYNC signal.
SERIAL INTERFACE
The serial interface allows easy interfacing to most microcontrollers and DSPs, such as the PIC16C, PIC17C, QSPI, SPI,
DSP56000, TMS320, and ADSP-21xx, without the need for any
glue logic. When interfacing to the 8051, the SCLK must be
inverted. The Microprocessor Interfacing section explains how
to interface to some popular DSPs and microcontrollers. Figure
4, Figure 5, and Figure 6 show the timing diagram for a serial
read and write to the AD5532. The serial interface works with
both a continuous and a noncontinuous serial clock. The first
falling edge of SYNC resets a counter that counts the number of
serial clocks to ensure the correct number of bits are shifted in
and out of the serial shift registers. Any further edges on SYNC
are ignored until the correct number of bits are shifted in or
out. Once the correct number of bits for the selected mode has
been shifted in or out, the SCLK is ignored. In order for another
serial transfer to take place the counter must be reset by the
falling edge of SYNC.
Table 10
Pin
SER/PAR
Description
This pin is tied high to enable the serial interface
and to disable the parallel interface. The serial
interface is controlled by the four pins that follow.
Standard 3-wire interface pins. The SYNC pin is
shared with the CS function of the parallel interface.
Data Out pin for reading back the contents of the
DAC registers. The data is clocked out on the rising
edge of SCLK and is valid on the falling edge of
SCLK.
The four different modes of operation are described
in the Modes of Operation section.
In DAC mode, this is a test bit. When high, it loads all
0s or all 1s to the 32 DACs simultaneously. In ISHA
mode, all 32 channels acquire VIN at the same time
when this bit is high. In ISHA mode, the acquisition
time is then 45 μs (typ) and accuracy may be
reduced. This bit is set low for normal use.
If this is set high, the offset channel is selected and
Bits A4–A0 are ignored.
Must be set low for correct operation of the part.
Used to address any one of the 32 channels
(A4 = MSB of address, A0 = LSB).
Used to write a 14-bit word into the addressed DAC
register. Only valid when in DAC mode.
SYNC,
DIN, SCLK
DOUT
Mode
Bits
Cal Bit
In readback, the first rising SCLK edge after the falling edge of
SYNC causes DOUT to leave its high impedance state and data is
clocked out onto the DOUT line and also on subsequent SCLK
rising edges. The DOUT pin goes back into a high impedance
state on the falling edge of the 14th SCLK. Data on the DIN line
is latched in on the first SCLK falling edge after the falling edge
of the SYNC signal and on subsequent SCLK falling edges.
During read-back DIN is ignored. The serial interface does
Offset Sel
Bit
Test Bit
A4–A0
DB13–
DB0
MSB
LSB
0
0
MODE BIT 1
CAL
0
OFFSET_SEL
MODE BIT 2
A4–A0
TEST BIT
MODE BITS
a. 10-BIT SERIAL WRITE WORD (ISHA MODE)
MSB
LSB
0
1
CAL
0
OFFSET_SEL
A4–A0
DB13–DB0
TEST BIT
MODE BITS
b. 24-BIT INPUT SERIAL WRITE WORD (DAC MODE)
MSB
LSB
1
0
CAL
OFFSET_SEL
0
LSB
MSB
DB13–DB0
A4–A0
TEST BIT
MODE BITS
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
10-BIT
SERIAL WORD
WRITTEN TO PART
c. INPUT SERIAL INTERFACE (ACQUIRE AND READ-BACK MODE)
MSB
LSB
1
CAL
OFFSET_SEL
0
A4–A0
DB13–DB0
TEST BIT
MODE BITS
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
d. INPUT SERIAL INTERFACE (READ-BACK MODE)
Figure 21. Serial Interface Formats
Rev. D | Page 16 of 20
00939-C-020
1
LSB
MSB
AD5532
PARALLEL INTERFACE (ISHA MODE ONLY)
Figure 22 shows the connection diagram.
AD5532*
Table 11.
WR
A4–A0
OFFSET_SEL
CAL
Description
Active low package select pin. This pin is shared
with the SYNC function for the serial interface.
Active low write pin. The values on the address
pins are latched on a rising edge of WR.
Five address pins (A4 = MSB of address,
A0 = LSB). These are used to address the
relevant channel (out of a possible 32).
Offset select pin. This has the same function as
the Offset_Sel bit in the serial interface. When it
is high, the offset channel is addressed. The
address on A4–A0 is ignored in this case.
When this pin is high, all 32 channels acquire
VIN simultaneously. The acquisition time is then
45 μs (typ) and accuracy may be reduced.
MICROPROCESSOR INTERFACING
AD5532 to ADSP-21xx Interface
ADSP-21xx DSPs are easily interfaced to the AD5532 without
the need for extra logic.
A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP serial clock and
clocked into the AD5532 on the falling edge of its SCLK. In
readback, 16 bits of data are clocked out of the AD5532 on each
rising edge of SCLK and clocked into the DSP on the rising
edge of SCLK. DIN is ignored. The valid 14 bits of data is
centered in the 16-bit RX register in this configuration. The
SPORT Control register should be set up as in Table 12.
DR
TFS
RFS
DIN
SCLK
DT
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. AD5532 to ADSP-2101/ADSP-2103 Interface
AD5532 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5532, the MOSI output drives the serial data line (DIN)
of the AD5532, and the MISO input is driven from DOUT. The
SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5532, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. To transmit
10 data bits in ISHA mode, it is important to left-justify the data
in the SPDR register. PC7 must be pulled low to start a transfer.
It is taken high and pulled low again before other read/write
cycles can take place. Figure 23 shows a connection diagram.
Table 12.
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
SLEN = 1001
SLEN = 0111
SLEN = 1111
DOUT
SYNC
00939-C-021
Pin
CS
ADSP-2101/
ADSP-2103*
AD5532*
DOUT
Rev. D | Page 17 of 20
MISO
SYNC
PC7
SCLK
SCK
DIN
Alternate framing
Active low frame signal
Right justify data
Internal serial clock
Frame every word
External framing signal
Internal framing signal
10-bit data-words (ISHA mode write)
3 × 8-bit data-words (DAC mode write)
16-bit data-words (Readback mode)
MC68HC11*
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. AD5532 to MC68HC11 Interface
00939-C-022
The SER/PAR bit must be tied low to enable the parallel
interface and disable the serial interface. The parallel interface is
controlled by nine pins, as described in Table 11.
AD5532
AD5532 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity Bit = 0. This is done by
writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
this example, the I/O port RA1 is being used to pulse SYNC
and enable the serial port of the AD5532. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two or three consecutive read/write
operations are needed depending on the mode. Figure 24
shows the connection diagram.
DOUT
DIN
SYNC
PARAMETRIC
MEASUREMENT SYSTEM BUS
UNIT
DAC
ACTIVE
LOAD
DAC
DAC
STORED
DATA
AND INHIBIT
PATTERN
SCK/RC3
DRIVER
DAC
FORMATTER
SDO/RC5
DUT
DAC
SDI/RC4
RA1
PERIOD
GENERATION
AND
DELAY
TIMING
*ADDITIONAL PINS OMITTED FOR CLARITY
DAC
COMPARE
REGISTER
DAC
Figure 24. AD5532 to PIC16C6x/7x Interface
00939-C-025
SCLK
PIC16C6x/7x*
00939-C-023
AD5532*
The AD5532 has several advantages: no refreshing is required,
there is no droop, pedestal error is eliminated, and there is no
need for extra filtering to remove glitches. Overall a higher level
of integration is achieved in a smaller area (see Figure 26).
COMPARATOR
AD5532 to 8051
DACs
The AD5532 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode 0.
In this mode, serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 25 shows how the 8051 is
connected to the AD5532. Because the AD5532 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5532
requires its data with the MSB first. Because the 8051 outputs
the LSB first, the transmit routine must take this into account.
AD5532*
8051*
SCLK
TxD
DOUT
RxD
00939-C-024
P1.1
Figure 26. AD5532 in an ATE System
Typical Application Circuit (DAC Mode)
The AD5532 can be used in many optical networking
applications that require a large number of DACs to perform
control and measurement functions. In the example shown in
Figure 27, the outputs of the AD5532 are amplified and used to
control actuators that determine the position of MEMS mirrors
in an optical switch. The exact position of each mirror is
measured using sensors. The sensor readings are muxed using
four dual, 4-channel matrix switches (ADG739) and fed back to
an 8-channel, 14-bit ADC (AD7856).
The control loop is driven by an ADSP-2191M, a 16-bit fixedpoint DSP with 3 SPORT interfaces and 2 SPI ports. The DSP
uses some of these serial ports to write data to the DAC, control
the multiplexer, and read back data from the ADC.
DIN
SYNC
SYSTEM BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. AD5532 to 8051 Interface
APPLICATION CIRCUITS
1
AD5532
AD5532 in a Typical ATE System
The AD5532 is ideally suited for use in automatic test
equipment. Several DACs are required to control pin drivers,
comparators, active loads, and signal timing. Traditionally,
sample-and-hold devices were used in this application.
32
MEMS
MIRROR
ARRAY
S
E
N
S
32 O
R
1
1
ADG739
×4
AD7856
8
ADSP-2191M
00939-C-026
AD8544
×2
Figure 27. Typical Optical Control and Measurement Application Circuit
Rev. D | Page 18 of 20
AD5532
Typical Application Circuit (ISHA Mode)
The AD5532 can be used to set up voltage levels on 32 channels
as shown in the circuit that follows. An AD780 provides the 3 V
reference for the AD5532 and for the AD5541 16-bit DAC. A
simple 3-wire interface is used to write to the AD5541. Because
the AD5541 has an output resistance of 6.25 kΩ(typ), the time
taken to charge/discharge the capacitance at the VIN pin is
significant. Hence an AD820 is used to buffer the DAC output.
Note that it is important to minimize noise on VIN and REFIN
when laying out the circuit.
AVCC DVCC
AVCC
VSS
VDD
CS
DIN
SCLK
AD5541*
AD820
VIN
AD5532*
REF
VOUT0–VOUT31
OFFS_IN
OFFS_OUT
REFIN
AD780*
SCLK DIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
00939-C-027
VOUT
Figure 28. Typical Application Circuit (ISHA Mode)
The power supply lines of the AD5532 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals, such as clocks, should be shielded with digital ground
to avoid radiating noise to other parts of the board and should
never be run near the reference inputs. A ground line routed
between the DIN and SCLK lines helps reduce crosstalk between
them (not required on a multilayer board as there is a separate
ground plane, but separating the lines helps).
Note it is essential to minimize noise on VIN and REFIN lines.
Particularly for optimum ISHA performance, the VIN line must
be kept noise free. Depending on the noise performance of the
board, a noise filtering capacitor may be required on the VIN
line. If this capacitor is necessary, then for optimum throughput
it may be necessary to buffer the source which is driving VIN.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A micro-strip technique is by far the best, but not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground plane while
signal traces are placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
the package during the assembly process.
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD5532 is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5532 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
For supplies with multiple pins (VSS, VDD, AVCC) it is recommended to tie those pins together. The AD5532 should have
ample supply bypassing of 10 μF in parallel with 0.1 μF on each
supply located as close to the package as possible, ideally right
up against the device. The 10 μF capacitors are the tantalum
bead type. The 0.1 μF capacitor should have low effective series
resistance (ESR) and effective series inductance (ESI), such as
the common ceramic types that provide a low impedance path
to ground at high frequencies, to handle transient currents due
to internal logic switching.
Rev. D | Page 19 of 20
AD5532
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
12.00
BSC SQ
11 10 9 8 7 6 5 4 3 2 1
BALL A1
INDICATOR
10.00
BSC SQ
BOTTOM
VIEW
TOP VIEW
1.00
BSC
A
B
C
D
E
F
G
H
J
K
L
DETAIL A
1.70
MAX
DETAIL A
1.10
0.25
0.30 MIN
0.20
COPLANARITY
SEATING
PLANE
061306-A
0.70
0.60
0.50
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-192-ABD-1
Figure 29. 74-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-74)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5532ABC-1
AD5532ABC-1REEL
AD5532ABC-2
AD5532ABC-3
AD5532ABC-3REEL
AD5532ABC-5
AD5532ABC-5REEL
AD5532ABCZ-1
AD5532ABCZ-1REEL
AD5532ABCZ-2
AD5532ABCZ-3
AD5532ABC-5
EVAL-AD5532EBZ
1
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Function
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
32 DACs, 32-Channel ISHA
Evaluation Board
Output
Impedance
0.5 Ω typ
0.5 Ω typ
0.5 Ω typ
500 Ω typ
500 Ω typ
1 kΩ typ
1 kΩ typ
0.5 Ω typ
0.5 Ω typ
0.5 Ω typ
500 Ω typ
1 kΩ typ
Z = RoHS Compliant Part.
© 2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00939-0-6/10(D)
Rev. D | Page 20 of 20
Output
Voltage Span
10 V
10 V
20 V
10 V
10 V
10 V
10 V
10 V
10 V
20 V
10 V
10 V
Package
Description
74-Ball CSP_BGA
74-Ball CSP_BGA
74-Ball CSP_BGA
74-Ball CSP_BGA
74-Ball CSP_BGA
74-Ball CSP_BGA
74-Ball CSP_BGA
74-Ball CSP_BGA
74-Ball CSP_BGA
74-Ball CSP_BGA
74-Ball CSP_BGA
74-Ball CSP_BGA
Package
Option
BC-74
BC-74
BC-74
BC-74
BC-74
BC-74
BC-74
BC-74
BC-74
BC-74
BC-74
BC-74
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