AD5542CRZ

2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DACs AD5541/AD5542 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS VDD Full 16-bit performance 3 V and 5 V single-supply operation Low 0.625 mW power dissipation 1 µs settling time Unbuffered voltage output capable of driving 60 kΩ loads directly SPI-/QSPI-/MICROWIRE-compatible interface standards Power-on reset clears DAC output to 0 V (unipolar mode) 5 kV HBM ESD classification Low glitch: 1.1 nV-sec 8 AD5541 16-BIT DAC REF 3 VOUT 2 AGND 16-BIT DAC LATCH CS 4 CONTROL LOGIC SCLK 5 SERIAL INPUT REGISITER 07557-001 DIN 6 1 7 DGND Figure 1. AD5541 APPLICATIONS VDD 14 Digital gain and offset adjustment Automatic test equipment Data acquisition systems Industrial process control The AD5541/AD5542 utilize a versatile 3-wire interface that is compatible with SPI, QSPI™, MICROWIRE™ and DSP interface standards. The AD5541/AD5542 are available in 8-lead and 14-lead SOIC packages. RFB INV 2 VOUT 3 AGNDF 4 AGNDS REFF 6 16-BIT DAC REFS 5 16-BIT DAC LATCH CS 7 LDAC 11 SCLK 8 CONTROL LOGIC DIN 10 SERIAL INPUT REGISITER 12 DGND 07557-002 The AD5541/AD5542 are single, 16-bit, serial input, voltage output digital-to-analog converters (DACs) that operate from a single 2.7 V to 5.5 V supply. The DAC output range extends from 0 V to VREF. The AD5542 can be operated in bipolar mode, which generates a ±VREF output swing. The AD5542 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. 1 13 RINV GENERAL DESCRIPTION The DAC output range extends from 0 V to VREF and is guaranteed monotonic, providing 1 LSB INL accuracy at 16 bits without adjustment over the full specified temperature range of −40°C to +85°C. Offering unbuffered outputs, the AD5541/AD5542 achieve a 1 µs settling time with low power consumption and low offset errors. Providing a low noise performance of 11.8 nV/√Hz and low glitch, the AD5541/AD5542 is suitable for deployment across multiple end systems. RFB AD5542 Figure 2. AD5542 Table 1. Part No. AD5541A/AD5542A AD5024/AD5044/AD5064 AD5062 AD5063 Description Single, 16-bit unbuffered nanoDAC™, ±1 LSB INL, LFCSP Quad 12-/14-/16-bit nanoDAC, ±1 LSB INL, TSSOP Single, 16-bit nanoDAC, ±1 LSB INL, SOT-23 Single, 16-bit nanoDAC, ±1 LSB INL, SOT-23 PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Single-Supply Operation. The AD5541 and AD5542 are fully specified and guaranteed for a single 2.7 V to 5.5 V supply. Low Power Consumption. These parts consume typically 0.625 mW with a 5 V supply and 0.375 mV at 3 V. 3-Wire Serial Interface. Unbuffered Output Capable of Driving 60 kΩ Loads. This reduces power consumption because there is no internal buffer to drive. Power-On Reset Circuitry. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1999–2012 Analog Devices, Inc. All rights reserved. AD5541/AD5542 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Bipolar Output Operation ......................................................... 12 Applications ....................................................................................... 1 Output Amplifier Selection ....................................................... 12 General Description ......................................................................... 1 Force Sense Amplifier Selection ............................................... 12 Functional Block Diagrams ............................................................. 1 Reference and Ground ............................................................... 12 Product Highlights ........................................................................... 1 Power-On Reset .......................................................................... 13 Revision History ............................................................................... 2 Power Supply and Reference Bypassing .................................. 13 Specifications..................................................................................... 3 Microprocessor Interfacing ........................................................... 14 Timing Characteristics ................................................................ 4 AD5541/AD5542 to ADSP-21xx Interface ............................. 14 Absolute Maximum Ratings ............................................................ 5 AD5541/AD5542 to 68HC11/68L11 Interface....................... 14 ESD Caution .................................................................................. 5 AD5541/AD5542 to MICROWIRE Interface ........................ 14 Pin Configurations and Function Descriptions ........................... 6 AD5541/AD5542 to 80C51/80L51 Interface .......................... 14 Typical Performance Characteristics ............................................. 7 Applications Information .............................................................. 15 Terminology .................................................................................... 10 Optocoupler Interface ................................................................ 15 Theory of Operation ...................................................................... 11 Decoding Multiple AD5541/AD5542s .................................... 15 Digital-to-Analog Section ......................................................... 11 Outline Dimensions ....................................................................... 16 Serial Interface ............................................................................ 11 Ordering Guide .......................................................................... 17 Unipolar Output Operation ...................................................... 11 REVISION HISTORY 3/12—Rev. E to Rev. F Change to Figure 19 ......................................................................... 9 Changes to Ordering Guide .......................................................... 17 3/11—Rev. D to Rev. E Changed +105°C to +85°C, General Description Section .......... 1 2/11—Rev. C to Rev. D Changes to Features Section, General Description Section, Product Highlights Section ............................................................. 1 Added Table 1; Renumbered Sequentially .................................... 1 Added Output Noise Spectral Density Parameter and Output Noise Parameter, Table 2.................................................................. 3 Changes to Ordering Guide .......................................................... 17 4/10—Rev. B to Rev. C Changes to General Description Section ...................................... 1 Changes to Features List .................................................................. 1 Changes to Product Highlights .......................................................1 Changes to Table 1.............................................................................3 Changes to Table 3.............................................................................5 Changes to Figure 16, Figure 17, and Figure 19 ....................... 8, 9 Changes to Theory of Operations Section .................................. 11 Changes to Microprocessor Interfacing Section ........................ 14 Changes to Outline Dimensions .................................................. 16 Changes to Ordering Guide .......................................................... 17 8/08—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Timing Characteristics Section ...................................4 Changes to Table 3.............................................................................5 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 17 10/99—Rev. 0 to Rev. A Rev. F | Page 2 of 20 Data Sheet AD5541/AD5542 SPECIFICATIONS VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 STATIC PERFORMANCE Resolution Relative Accuracy (INL) Min Typ Max Differential Nonlinearity (DNL) ±0.5 ±0.5 ±0.5 ±0.5 Gain Error +0.5 ±1.0 ±2.0 ±4.0 ±1.0 ±1.5 ±2 ±3 Gain Error Temperature Coefficient Unipolar Zero Code Error ±0.1 ±0.3 Unipolar Zero Code Temperature Coefficient AD5542 Bipolar Resistor Matching ±0.05 16 ±0.7 ±1.5 Bipolar Zero Offset Error 1.000 ±0.0015 ±1 Bipolar Zero Temperature Coefficient Bipolar Zero Code Offset Error ±0.2 ±1 ±0.0076 ±5 ±6 ±5 ±6 Bipolar Gain Error +1 ±5 ±6 Bipolar Gain Temperature Coefficient OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough DAC Output Impedance Output Noise Spectral Density Output Noise Power Supply Rejection Ratio DAC REFERENCE INPUT Reference Input Range Reference Input Resistance 2 LOGIC INPUTS Input Current Input Low Voltage, VINL Input High Voltage, VINH Input Capacitance 3 Hysteresis Voltage3 REFERENCE 3 Reference −3 dB Bandwidth Reference Feedthrough Signal-to-Noise Ratio Reference Input Capacitance ±0.1 0 −VREF VREF − 1 LSB VREF − 1 LSB 1 17 1.1 0.2 6.25 11.8 0.134 ±1.0 2.0 9 7.5 VDD ±1 0.8 Unit Bits LSB LSB LSB LSB LSB LSB LSB ppm/°C LSB LSB ppm/°C V V μs V/μs nV-sec nV-sec kΩ nV/√Hz µV p-p LSB Unipolar operation AD5542 bipolar operation To 1/2 LSB of FS, CL = 10 pF CL = 10 pF, measured from 0% to 63% 1 LSB change around the major carry All 1s loaded to DAC, VREF = 2.5 V Tolerance typically 20% DAC code = 0x8400, frequency = 1 kHz 0.1 Hz to 10 Hz ΔVDD ± 10% V kΩ kΩ Unipolar operation AD5542, bipolar operation 2.2 1 92 26 26 MHz mV p-p dB pF pF Rev. F | Page 3 of 20 TA = 25°C RFB/RINV, typically RFB = RINV = 28 kΩ Ratio error TA = 25°C 0.15 10 L, C grades B, J grades A grade Guaranteed monotonic J grade TA = 25°C Ω/Ω % LSB LSB ppm/°C LSB LSB LSB LSB ppm/°C μA V V pF V 2.4 Test Conditions TA = 25°C TA = 25°C All 1s loaded All 0s loaded, VREF = 1 V p-p at 100 kHz Code 0x0000 Code 0xFFFF AD5541/AD5542 Data Sheet Parameter 1 POWER REQUIREMENTS VDD IDD Power Dissipation 1 2 3 Min Typ Max Unit 125 0.625 5.5 150 0.825 V μA mW 2.7 Test Conditions Digital inputs at rails Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C. Reference input resistance is code-dependent, minimum at 0x8555. Guaranteed by design, not subject to production test. TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V ±10%, VREF = 2.5 V, VINH = 3 V and 90% of VDD, VINL = 0 V and 10% of VDD, AGND = DGND = 0 V; −40°C < TA < +85°C, unless otherwise noted. Table 3. Parameter 1, 2 fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t9 t10 t11 t12 2 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Description SCLK cycle frequency SCLK cycle time SCLK high time SCLK low time CS low to SCLK high setup CS high to SCLK high setup SCLK high to CS low hold time SCLK high to CS high hold time Data setup time Data hold time (VINH = 90% of VDD, VINL = 10% of VDD) Data hold time (VINH = 3V, VINL = 0 V) LDAC pulse width CS high to LDAC low setup CS high time between active periods Guaranteed by design and characterization. Not production tested All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2. t1 SCLK t3 t2 t6 CS t5 t7 t4 t12 t8 t5 DIN DB15 t11 t10 LDAC* *AD5542 ONLY. CAN BE TIED PERMANENTLY LOW IF REQUIRED. Figure 3. Timing Diagram Rev. F | Page 4 of 20 07557-003 1 Limit 25 40 20 20 10 15 30 20 15 4 7.5 30 30 30 Data Sheet AD5541/AD5542 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to AGND Digital Input Voltage to DGND VOUT to AGND AGND, AGNDF, AGNDS to DGND Input Current to Any Pin Except Supplies Operating Temperature Range Industrial (A, B, C Versions) Commercial (J, L Versions) Storage Temperature Range Maximum Junction Temperature (TJ max) Package Power Dissipation Thermal Impedance, θJA SOIC (R-8) SOIC (R-14) Lead Temperature, Soldering Peak Temperature1 ESD2 1 2 Rating −0.3 V to +6 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to +0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +85°C 0°C to 70°C −65°C to +150°C 150°C (TJ max – TA)/θJA 149.5°C/W 104.5°C/W 260°C 5 kV As per JEDEC Standard 20. HBM Classification. Rev. F | Page 5 of 20 AD5541/AD5542 Data Sheet VOUT 1 AGND 2 AD5541 REF 3 TOP VIEW CS 4 (Not to Scale) 8 VDD 7 DGND 6 DIN 5 SCLK 07557-004 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. AD5541 Pin Configuration Table 5. AD5541 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VOUT AGND REF CS SCLK DIN DGND VDD Description Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry. Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD. Logic Input Signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. Digital Ground. Ground reference for digital circuitry. Analog Supply Voltage, 5 V ± 10%. RFB 1 14 VDD VOUT 2 13 INV 12 DGND AGNDF 3 AD5542 TOP VIEW 11 LDAC (Not to Scale) 10 DIN REFS 5 REFF 6 9 NC CS 7 8 SCLK NC = NO CONNECT 07557-005 AGNDS 4 Figure 5. AD5542 Pin Configuration Table 6. AD5542 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 Mnemonic RFB VOUT AGNDF AGNDS REFS REFF CS SCLK NC DIN LDAC 12 13 DGND INV 14 VDD Description Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output. Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry (Force). Ground Reference Point for Analog Circuitry (Sense). Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD. Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD. Logic Input Signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. No Connect. Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. Digital Ground. Ground reference for digital circuitry. Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to external op amps inverting input in bipolar mode. Analog Supply Voltage, 5 V ± 10%. Rev. F | Page 6 of 20 Data Sheet AD5541/AD5542 TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0.50 0 –0.25 –0.50 –0.75 0 8192 16384 24576 32768 40960 49152 CODE 57344 65536 VDD = 5V VREF = 2.5V 0.25 0 –0.25 –0.50 0 8192 Figure 6. Integral Nonlinearity vs. Code 0.75 0 –0.25 –0.50 –0.75 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 0.50 0.25 0 –0.25 –0.50 –60 07557-007 –1.00 –60 VDD = 5V VREF = 2.5V Figure 7. Integral Nonlinearity vs. Temperature –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 07557-010 DIFFERENTIAL NONLINEARITY (LSB) VDD = 5V VREF = 2.5V Figure 10. Differential Nonlinearity vs. Temperature 0.50 0.75 VDD = 5V TA = 25°C VREF = 2.5V TA = 25°C 0.25 0.50 LINEARITY ERROR (LSB) DNL 0 –0.25 –0.50 DNL 0.25 0 INL –0.25 INL 2 3 4 5 SUPPLY VOLTAGE (V) 6 7 –0.50 07557-008 –0.75 0 Figure 8. Linearity Error vs. Supply Voltage 1 2 3 4 REFERENCE VOLTAGE (V) 5 Figure 11. Linearity Error vs. Reference Voltage Rev. F | Page 7 of 20 6 07557-011 INTEGRAL NONLINEARITY (LSB) 57344 65536 Figure 9. Differential Nonlinearity vs. Code 0.25 LINEARITY ERROR (LSB) 16384 24576 32768 40960 49152 CODE 07557-009 DIFFERENTIAL NONLINEARITY (LSB) 0.25 07557-006 INTEGRAL NONLINEARITY (LSB) VDD = 5V VREF = 2.5V AD5541/AD5542 Data Sheet 0 0.15 VDD = 5V VREF = 2.5V TA = 25°C –0.1 0.10 ZERO-CODE ERROR (LSB) GAIN ERROR (LSB) –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 VDD = 5V VREF = 2.5V TA = 25°C 0.05 0 –0.05 –0.10 –40 25 TEMPERATURE (°C) 85 –0.15 08898-012 –0.9 Figure 12. Gain Error vs. Temperature 25 TEMPERATURE (°C) 85 Figure 15. Zero-Code Error vs. Temperature 2.0 132 TA = 25°C VDD = 5V VREF = 2.5V 130 TA = 25°C 128 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) –40 08898-015 –0.8 126 124 122 120 1.5 REFERENCE VOLTAGE VDD = 5V 1.0 SUPPLY VOLTAGE VREF = 2.5V 0.5 –40 25 TEMPERATURE (°C) 85 0 08898-013 116 0 1 2 3 4 6 Figure 16. Supply Current vs. Reference Voltage or Supply Voltage Figure 13. Supply Current vs. Temperature 200 200 VDD = 5V VREF = 2.5V TA = 25°C 180 REFERENCE CURRENT (µA) 160 140 120 100 80 60 150 100 50 40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DIGITAL INPUT VOLTAGE (V) 0 0 10,000 20,000 30,000 40,000 CODE (Decimal) 50,000 60,000 Figure 17. Reference Current vs. Code Figure 14. Supply Current vs. Digital Input Voltage Rev. F | Page 8 of 20 70,000 08898-017 20 08898-014 SUPPLY CURRENT (µV) 5 VOLTAGE (V) 08898-016 118 Data Sheet AD5541/AD5542 VREF = 2.5V VDD = 5V TA = 25°C VREF = 2.5V VDD = 5V TA = 25°C 2µs/DIV 100 100 DIN (5V/DIV) CS (5V/DIV) 10pF 50pF 100pF 200pF VOUT (50mV/DIV) 10 VOUT (0.5V/DIV) 08898-018 2µs/DIV Figure 18. Digital Feedthrough 08898-020 10 Figure 20. Large Signal Settling Time 1.236 5 CS 0 1.234 VREF = 2.5V VDD = 5V TA = 25°C –5 100 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • VOUT (1V/DIV) 90 –10 1.230 –15 1.228 VOUT –20 VOUT (50mV/DIV) GAIN = –216 1LSB = 8.2mV –25 10 0% • • • • 1.224 –0.5 0 0.5 1.0 1.5 TIME (µs) –30 2.0 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0.5µs/DIV Figure 21. Small Signal Settling Time Figure 19. Digital-to-Analog Glitch Impulse Rev. F | Page 9 of 20 07557-021 1.226 07557-032 VOLTAGE (V) 1.232 AD5541/AD5542 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Figure 9 illustrates a typical DNL vs. code plot. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with changes in temperature. It is expressed in ppm/°C. Zero Code Error Zero code error is a measure of the output error when zero code is loaded to the DAC register. Zero Code Temperature Coefficient This is a measure of the change in zero code error with a change in temperature. It is expressed in mV/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition. A plot of the digital-toanalog glitch impulse is shown in Figure 19. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. CS is held high while the CLK and DIN signals are toggled. It is specified in nV-sec and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in Figure 18. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Power-supply rejection ratio is quoted in terms of percent change in output per percent change in VDD for full-scale output of the DAC. VDD is varied by ±10%. Reference Feedthrough Reference feedthrough is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p. Rev. F | Page 10 of 20 Data Sheet AD5541/AD5542 THEORY OF OPERATION The AD5541/AD5542 are single, 16-bit, serial input, voltage output DACs. They operate from a single supply ranging from 2.7 V to 5.5 V and consume typically 125 µA with a supply of 5 V. Data is written to these devices in a 16-bit word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, these parts are designed with a power-on reset function. In unipolar mode, the output is reset to 0 V; in bipolar mode, the AD5542 output is set to −VREF. Kelvin sense connections for the reference and analog ground are included on the AD5542. DIGITAL-TO-ANALOG SECTION The DAC architecture consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 22. The DAC architecture of the AD5541/AD5542 is segmented. The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each switch connects one of 15 matched resistors to either AGND or VREF. The remaining 12 bits of the data-word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network. VOUT 2R 2R . . . . . 2R 2R 2R . . . . . 2R S0 S1 . . . . . S11 E1 E2 . . . . . E15 UNIPOLAR OUTPUT OPERATION FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS 07557-022 VREF 12-BIT R-2R LADDER Figure 22. DAC Architecture With this type of DAC configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage, as shown in the following equation: VOUT = These DACs are capable of driving unbuffered loads of 60 kΩ. Unbuffered operation results in low supply current, typically 300 μA, and a low offset error. The AD5541 provides a unipolar output swing ranging from 0 V to VREF. The AD5542 can be configured to output both unipolar and bipolar voltages. Figure 23 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table 7. 5V 10µF 0.1µF SERIAL INTERFACE VREF × D 2 0.1µF VDD REF(REFF*) REFS* DIN N AD5541/AD5542 AD820/ OP196 OUT SCLK LDAC* DGND AGND UNIPOLAR OUTPUT EXTERNAL OP AMP *AD5542 ONLY. For a reference of 2.5 V, the equation simplifies to the following: 2. 5 × D 65,536 This gives a VOUT of 1.25 V with midscale loaded and 2.5 V with full-scale loaded to the DAC. The LSB size is VREF/65,536. 2.5V CS where: D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC. VOUT = The AD5542 has an LDAC function that allows the DAC latch to be updated asynchronously by bringing LDAC low after CS goes high. LDAC should be maintained high while data is written to the shift register. Alternatively, LDAC can be tied permanently low to update the DAC synchronously. With LDAC tied permanently low, the rising edge of CS loads the data to the DAC. Figure 23. Unipolar Output Table 7. Unipolar Code Table DAC Latch Contents MSB LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 Rev. F | Page 11 of 20 Analog Output VREF × (65,535/65,536) VREF × (32,768/65,536) = ½ VREF VREF × (1/65,536) 0V 07557-023 2R R The AD5541/AD5542 are controlled by a versatile 3- or 4-wire serial interface that operates at clock rates up to 25 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram is shown in Figure 3. Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the input register on the rising edge of the serial clock, SCLK. Data is loaded MSB first in 16-bit words. After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC. Data can be loaded to the part only while CS is low. + R SERIAL INTERFACE AD5541/AD5542 Data Sheet Assuming a perfect reference, the unipolar worst-case output voltage can be calculated from the following equation: VOUT-UNI = Assuming a perfect reference, the worst-case bipolar output voltage can be calculated from the following equation: D × (VREF + VGE ) + V ZSE + INL 216 VOUT-BIP = [(V OUT − UNI ] ) + VOS (2 + RD ) − VREF (1 + RD ) 1 + (2 + RD ) A where: VOUT−UNI is unipolar mode worst-case output. D is code loaded to DAC. VREF is reference voltage applied to the part. VGE is gain error in volts. VZSE is zero scale error in volts. INL is integral nonlinearity in volts. where: VOUT-BIP is the bipolar mode worst-case output. VOUT−UNI is the unipolar mode worst-case output. VOS is the external op amp input offset voltage. RD is the RFB and RINV resistor matching error. A is the op amp open-loop gain. BIPOLAR OUTPUT OPERATION OUTPUT AMPLIFIER SELECTION With the aid of an external op amp, the AD5542 can be configured to provide a bipolar voltage output. A typical circuit of such operation is shown in Figure 24. The matched bipolar offset resistors, RFB and RINV, are connected to an external op amp to achieve this bipolar output swing, typically RFB = RINV = 28 kΩ. Table 8 shows the transfer function for this output operating mode. Also provided on the AD5542 are a set of Kelvin connections to the analog ground inputs. For bipolar mode, a precision amplifier should be used and supplied from a dual power supply. This provides the ±VREF output. In a single-supply application, selection of a suitable op amp may be more difficult as the output swing of the amplifier does not usually include the negative rail, in this case, AGND. This can result in some degradation of the specified performance unless the application does not use codes near zero. +5V +2.5V + 10µF 0.1µF +5V RFB SERIAL INTERFACE VDD REFF REFS CS DIN SCLK RFB RINV INV UNIPOLAR OUTPUT OUT AD5541/AD5542 LDAC DGND AGNDF AGNDS –5V EXTERNAL OP AMP Figure 24. Bipolar Output (AD5542 Only) Table 8. Bipolar Code Table DAC Latch Contents MSB LSB 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 Analog Output +VREF × (32,767/32,768) +VREF × (1/32,768) 0V −VREF × (1/32,768) −VREF × (32,768/32,768) = −VREF 07557-024 0.1µF The selected op amp needs to have a very low-offset voltage (the DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need for output offset trims. Input bias current should also be very low because the bias current, multiplied by the DAC output impedance (approximately 6 kΩ), adds to the zero code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code-independent, but to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds another time constant to the system, hence increasing the settling time of the output. A higher 3 dB amplifier bandwidth results in a shorter effective settling time of the combined DAC and amplifier. FORCE SENSE AMPLIFIER SELECTION Use single-supply, low-noise amplifiers. A low-output impedance at high frequencies is preferred because the amplifiers need to be able to handle dynamic currents of up to ±20 mA. REFERENCE AND GROUND Because the input impedance is code-dependent, the reference pin should be driven from a low impedance source. The AD5541/ AD5542 operate with a voltage reference ranging from 2 V to VDD. References below 2 V result in reduced accuracy. The fullscale output voltage of the DAC is determined by the reference. Table 7 and Table 8 outline the analog output voltage or particular digital codes. For optimum performance, Kelvin sense connections are provided on the AD5542. If the application does not require separate force and sense lines, tie the lines close to the package to minimize voltage drops between the package leads and the internal die. Rev. F | Page 12 of 20 Data Sheet AD5541/AD5542 POWER-ON RESET POWER SUPPLY AND REFERENCE BYPASSING The AD5541/AD5542 have a power-on reset function to ensure that the output is at a known state on power-up. On power-up, the DAC register contains all 0s until the data is loaded from the serial register. However, the serial register is not cleared on power-up, so its contents are undefined. When loading data initially to the DAC, 16 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 16 bits are loaded, the last 16 are kept, and if less than 16 bits are loaded, bits remain from the previous word. If the AD5541/AD5542 need to be interfaced with data shorter than 16 bits, the data should be padded with 0s at the LSBs. For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor. Rev. F | Page 13 of 20 AD5541/AD5542 Data Sheet MICROPROCESSOR INTERFACING AD5541/AD5542 TO MICROWIRE INTERFACE Figure 27 shows an interface between the AD5541/AD5542 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5541/ AD5542 on the rising edge of the serial clock. No glue logic is required because the DAC clocks data into the input shift register on the rising edge. AD5541/AD5542 TO ADSP-21XX INTERFACE ADSP-21xx LDAC** CS DT DIN SCLK AD5541/ AD5542* SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. **AD5542 ONLY. 07557-025 FO Figure 25. AD5541/AD5542 to ADSP-21xx Interface AD5541/AD5542 TO 68HC11/68L11 INTERFACE Figure 26 shows a serial interface between the AD5541/AD5542 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/ 68L11 drives the SCLK of the DAC, and the MOSI output drives the serial data line serial DIN. The CS signal is driven from one of the port lines. The 68HC11/68L11 is configured for master mode: MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is valid on the rising edge of SCK. PC6 LDAC** PC7 CS MOSI DIN SCK AD5541/ AD5542* SCLK Figure 27. AD5541/AD5542 to MICROWIRE Interface AD5541/AD5542 TO 80C51/80L51 INTERFACE A serial interface between the AD5541/AD5542 and the 80C51/ 80L51 microcontroller is shown in Figure 28. TxD of the microcontroller drives the SCLK of the AD5541/AD5542, and RxD drives the serial data line of the DAC. P3.3 is a bit programmable pin on the serial port that is used to drive CS. The 80C51/80L51 provide the LSB first, whereas the AD5541/ AD5542 expects the MSB of the 16-bit word first. Care should be taken to ensure the transmit routine takes this into account. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmit data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the DAC requires a 16-bit word, P3.3 must be left low after the first eight bits are transferred, and brought high after the second byte is transferred. LDAC on the AD5542 can also be controlled by the 80C51/ 80L51 serial port output by using another bit programmable pin, P3.4. 80C51/ 80L51* P3.4 LDAC** P3.3 CS RxD DIN TxD SCLK AD5541/ AD5542* *ADDITIONAL PINS OMITTED FOR CLARITY. **AD5542 ONLY. AD5541/ AD5542* Figure 28. AD5541/AD5542 to 80C51/80L51 Interface SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. **AD5542 ONLY. DIN *ADDITIONAL PINS OMITTED FOR CLARITY. 07557-026 68HC11/ 68L11* CS SCLK Figure 25 shows a serial interface between the AD5541/AD5542 and the ADSP-21xx. The ADSP-21xx should be set to operate in the SPORT transmit alternate framing mode. The ADSP-21xx are programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out on each rising edge of the serial clock, an inverter is required between the DSP and the DAC, because the AD5541/AD5542 clock data in on the falling edge of the SCLK. TFS CS SO 07557-027 MICROWIRE* 07557-028 Microprocessor interfacing to the AD5541/AD5542 is via a serial bus that uses standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 3- or 4-wire interface consisting of a clock signal, a data signal and a synchronization signal. The AD5541/AD5542 require a 16-bit data-word with data valid on the rising edge of SCLK. The DAC update can be done automatically when all the data is clocked in or it can be done under control of the LDAC (AD5542 only). Figure 26. AD5541/AD5542 to 68HC11/68L11 Interface Rev. F | Page 14 of 20 Data Sheet AD5541/AD5542 APPLICATIONS INFORMATION OPTOCOUPLER INTERFACE DECODING MULTIPLE AD5541/AD5542s The digital inputs of the AD5541/AD5542 are Schmitt-triggered so that they can accept slow transitions on the digital input lines. This makes these parts ideal for industrial applications where it may be necessary to isolate the DAC from the controller via optocouplers. Figure 29 illustrates such an interface. The CS pin of the AD5541/AD5542 can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device receives the CS signal at any one time. The DAC addressed is determined by the decoder. There is some digital feedthrough from the digital input lines. Using a burst clock minimizes the effects of digital feedthrough on the analog signal channels. Figure 30 shows a typical circuit. 5V REGULATOR POWER 10µF 0.1µF AD5541/AD5542 SCLK CS VDD DIN 10kΩ SCLK DIN VDD VDD VOUT SCLK SCLK ENABLE VDD CODED ADDRESS AD5541/AD5542 10kΩ CS AD5541/AD5542 EN CS DECODER DIN VOUT SCLK CS VOUT DGND AD5541/AD5542 VDD CS DIN 10kΩ SCLK GND Figure 29. AD5541/AD5542 in an Optocoupler Interface AD5541/AD5542 CS DIN VOUT SCLK Figure 30. Addressing Multiple AD5541/AD5542s Rev. F | Page 15 of 20 07557-030 DIN 07557-029 DIN VOUT AD5541/AD5542 Data Sheet OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 5 1 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 31. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 8 14 1 7 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 32. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. F | Page 16 of 20 060606-A 4.00 (0.1575) 3.80 (0.1496) Data Sheet AD5541/AD5542 ORDERING GUIDE Model 1 AD5541CR AD5541CRZ AD5541CRZ-REEL7 AD5541LR AD5541LR-REEL7 AD5541LRZ AD5541LRZ-REEL7 AD5541BR AD5541BRZ AD5541BRZ-REEL AD5541JR AD5541JR-REEL7 AD5541JRZ AD5541JRZ-REEL7 AD5541AR AD5541AR-REEL7 AD5541ARZ AD5541ARZ-REEL7 AD5542CR AD5542CR-REEL7 AD5542CRZ AD5542CRZ-REEL7 AD5542LR AD5542LRZ AD5542BR AD5542BRZ AD5542BRZ-REEL7 AD5542JR AD5542JR-REEL7 AD5542JRZ AD5542JRZ-REEL7 AD5542AR AD5542AR-REEL7 AD5542ARZ AD5542ARZ-REEL7 EVAL-AD5541/42EBZ 1 INL ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±4 LSB ±4 LSB ±4 LSB ±4 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±4 LSB ±4 LSB ±4 LSB ±4 LSB DNL ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1.5 LSB ±1.5 LSB ±1.5 LSB ±1.5 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1.5 LSB ±1.5 LSB ±1.5 LSB ±1.5 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 0°C to 70°C 0°C to 70°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Z = RoHS Compliant Part. Rev. F | Page 17 of 20 Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N Evaluation Board Package Option R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 R-14 AD5541/AD5542 Data Sheet NOTES Rev. F | Page 18 of 20 Data Sheet AD5541/AD5542 NOTES Rev. F | Page 19 of 20 AD5541/AD5542 Data Sheet NOTES ©1999–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07557-0-3/12(F) Rev. F | Page 20 of 20