True Accuracy, 16-Bit ±12 V/±15 V,
Serial Input Voltage Output DAC
AD5570
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VSS
VDD
DGND
AD5570
POWER-ON
RESET
REFGND
2R
16-BIT
DAC
VOUT
AGND
R
AGNDS
R
DAC REGISTER
REFIN
POWER-DOWN
CONTROL LOGIC
SHIFT REGISTER
LDAC
SDIN
SCLK
SYNC
SDO
CLR
PD
03760-001
Full 16-bit performance
1 LSB maximum INL and DNL
Output voltage range up to ±14 V
On-board reference buffers, eliminating the need for a
negative reference
Controlled output during power-on
Temperature ranges of −40°C to +85°C for A/B version/−40°C
to +125°C for W/Y version
Settling time of 10 μs to 0.003%
Clear function to 0 V
Asynchronous update of outputs (LDAC pin)
Power-on reset
Serial data output for daisy chaining
Data readback facility
5 kV HBM ESD classification
Figure 1.
APPLICATIONS
Industrial automation
Automatic test equipment
Process control
Data acquisition systems
General-purpose instrumentation
GENERAL DESCRIPTION
The AD5570 is a single 16-bit serial input, voltage output DAC
that operates from supply voltages of ±11.4 V up to ±16.5 V.
Integral linearity (INL) and differential nonlinearity (DNL) are
accurate to 1 LSB. During power-up, when the supply voltages
are changing, VOUT is clamped to 0 V via a low impedance path.
The AD5570 DAC comes complete with a set of reference
buffers. The reference buffers allow a single, positive reference
to be used. The voltage on REFIN is gained up and inverted
internally to give the positive and negative reference for the
DAC core. Having the reference buffers on-chip eliminates the
need for external components such as inverters, precision
amplifiers, and resistors, thereby reducing the overall solution
size and cost.
The AD5570 uses a versatile 3-wire interface that is compatible
with SPI®, QSPI™, MICROWIRE™, and DSP® interface standards.
Data is presented to the part as a 16-bit serial word. Serial data
is available on the SDO pin for daisy-chaining purposes. Data
readback allows the user to read the contents of the DAC
register via the SDO pin.
Features on the AD5570 include LDAC which is used to update
the output of the DAC. The device also has a power-down pin
(PD), allowing the DAC to be put into a low power state, and a
CLR pin that allows the output to be cleared to 0 V.
The AD5570 is available in a 16-lead SSOP.
PRODUCT HIGHLIGHTS
1.
1 LSB maximum INL and DNL.
2.
Buffered voltage output up to ±14 V.
3.
Output controlled during power-up.
4.
On-board reference buffers.
5.
Wide temperature range of −40°C to +125°C.
6.
5 kV HBM ESD classification.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD5570
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Architecture....................................................................... 16
Applications....................................................................................... 1
Reference Buffers........................................................................ 16
Functional Block Diagram .............................................................. 1
Serial Interface ............................................................................ 16
General Description ......................................................................... 1
Transfer Function....................................................................... 17
Product Highlights ........................................................................... 1
Clear (CLR) ................................................................................. 17
Revision History ............................................................................... 2
Power-Down (PD) ..................................................................... 17
Specifications..................................................................................... 3
Power-On Reset.......................................................................... 17
Timing Characteristics..................................................................... 5
Serial Data Output (SDO)......................................................... 17
Standalone ..................................................................................... 5
Applications Information .............................................................. 19
Timing Characteristics..................................................................... 6
Typical Operating Circuit ......................................................... 19
Daisy-Chaining and Readback ................................................... 6
Layout Guidelines....................................................................... 20
Absolute Maximum Ratings............................................................ 8
Opto-Isolators............................................................................. 20
ESD Caution.................................................................................. 8
Microprocessor Interfacing....................................................... 21
Pin Configuration and Function Descriptions............................. 9
Evaluation Board ........................................................................ 22
Terminology .................................................................................... 10
Outline Dimensions ....................................................................... 24
Typical Performance Characteristics ........................................... 11
Ordering Guide .......................................................................... 24
General Description ....................................................................... 16
REVISION HISTORY
11/10—Rev. B to Rev. C
Added HBM ESD Classification to Features and Product
Highlights Section ............................................................................ 1
Added ESD Parameter to Table 4 ................................................... 8
Changes to Ordering Guide .......................................................... 24
9/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 3............................................................................ 6
Changes to Figure 43...................................................................... 21
Changes to AD5570 to 8xC51 Interface Section ........................ 21
Changes to Ordering Guide .......................................................... 24
4/05—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 3
Changes to Table 4............................................................................ 8
Added Figure 16.............................................................................. 12
Revision 0: Initial Version
Rev. C | Page 2 of 24
AD5570
SPECIFICATIONS
VDD = +11.4 V to +16.5 V, VSS = −11.4 V to −16.5 V, VREF = 5 V, REFGND = AGND = DGND = 0 V, RL = 5 kΩ, CL = 200 pF to AGND;
all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter 1
ACCURACY
Resolution
Monotonicity
Differential Nonlinearity (DNL)
Relative Accuracy (INL)
B/Y Grade
A/W Grade
Positive INL Drift Over Time 3
A/B Grades
W/Y Grades
Negative Full-Scale Error
Full-Scale Error
Bipolar Zero Error
Gain Error
Gain Temperature Coefficient 4
REFERENCE INPUT
Reference Input Range4
Input Current
OUTPUT CHARACTERISTICS4
Output Voltage Range
Min
Max
Unit
Test Conditions/Comments
16
16
−1
±0.3
+1
Bits
Bits
LSB
−1
−2
±0.4
±0.6
+1
+2
LSB
LSB
±7.5
±6
±7.5
±7.5
±1.5
ppm
ppm
mV
mV
mV
mV
ppm FSR/°C
5
7
±0.1
V
V
μA
With ±11.4 V supplies
With ±16.5 V supplies
VDD − 1.4
VDD − 2.5
16
13
7
V
V
μs
μs
μs
V/μs
nV-s
With ±11.4 V supplies
With ±16.5 V supplies
At 16 bits to ±0.5 LSB
To 0.0003%
512 LSB code change
Measured from 10% to 90%
±12 V supplies; 1 LSB change around
the major carry
See Figure 16
2.5
6.5
±0.9
±1.8
±0.9
±1.8
+0.25
4
4
5
5
VSS + 1.4
VSS + 2.5
Output Voltage Settling Time
12
10
6
6.5
15
Slew Rate
Digital-to-Analog Glitch Impulse
Bandwidth
Short Circuit Current
Output Noise Voltage Density
DAC Output Impedance
Digital Feedthrough
WARMUP TIME 5
LOGIC INPUTS
Input Currents
VINH, Input High Voltage
VINL, Input Low Voltage
CIN, Input Capacitance
LOGIC OUTPUTS
VOL, Output Low Voltage
Floating-State Output
Typ 2
20
25
85
0.35
0.5
12
0.5
±0.1
2
0.8
3
0.4
8
Rev. C | Page 3 of 24
kHz
mA
nV/Hz
Ω
nV-s
sec
f = 1 kHz; midscale loaded
μA
V
V
pF
V
pF
ISINK = 1 mA
AD5570
Parameter 1
POWER REQUIREMENTS
VDD/VSS
IDD
ISS
Power-Down Current
Power-Supply Sensitivity 6
Power Dissipation
Min
Typ 2
±11.4
4
3.5
16
0.1
100
Max
Unit
Test Conditions/Comments
±16.5
5
5
V
mA
mA
μA
LSB/V
mW
VOUT unloaded
VOUT unloaded
VOUT unloaded
±15 supplies ±10%; full-scale loaded
VOUT unloaded
1
Temperature ranges: A and B versions = − 40°C to +85°C; W and Y versions = −40°C to +125°C.
Typical specifications at ±12 V/±15 V, +25°C.
3
These numbers are generated from the life test of the part.
4
Guaranteed by design.
5
Warmup time is required for the device to reach thermal equilibrium, thus achieving rated performance.
6
Sensitivity of negative full-scale error and positive full-scale error to VDD, VSS variations.
2
Rev. C | Page 4 of 24
AD5570
TIMING CHARACTERISTICS
STANDALONE
VDD = +12 V ± 5%, VSS = −12 V ± 5% or VDD = +15 V ± 10%, VSS = −15 V ± 10%, VREF = 5 V, REFGND = AGND = DGND = 0 V, RL = 5 kΩ,
CL = 200 pF to AGND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
fMAX
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
2
Limit at TMIN, TMAX
10
100
35
35
10
35
0
45
45
0
50
0
0
20
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SCLK frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to LDAC falling edge
LDAC pulse width
LDAC falling edge to SYNC falling edge (no update)
LDAC rising edge to SYNC rising edge (no update)
CLR pulse width
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
t1
SCLK
t2
t8
t3
t4
t7
SYNC
t6
t5
SDIN
DB15
DB0
t9
t10
LDAC1
t11
t12
LDAC2
t13
CLR
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC.
2SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC.
Figure 2. Serial Interface Timing Diagram
Rev. C | Page 5 of 24
03760-002
1
1, 2
AD5570
TIMING CHARACTERISTICS
DAISY-CHAINING AND READBACK
VDD = +12 V ± 5%, VSS = −12 V ± 5% or VDD = +15 V ± 10%, VSS = −15 V ± 10%, VREF = 5 V, REFGND = AGND = DGND = 0 V, RL = 5 kΩ,
CL = 200 pF to AGND; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter 1, 2
fMAX
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t14 3
Limit at TMIN, TMAX
2
500
200
200
10
35
0
45
45
0
50
200
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
SCLK frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to LDAC falling edge
LDAC pulse width
Data delay on SDO
1
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2. SDO; RPULLUP = 5 kΩ, CL = 15 pF.
3
With CL = 0 pF, t14 = 100 ns.
2
t1
SCLK
t8
t3
t4
t2
t7
SYNC
t10
LDAC1
t9
LDAC2
t5
SDIN
t6
DB15 (N)
DB0 (N)
DB15
(N + 1)
DB0
(N + 1)
t14
SDO
DB15 (N)
03760-003
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
DB0 (N)
DB15
(N + 1)
Figure 3. Daisy-Chaining Timing Diagram
Rev. C | Page 6 of 24
AD5570
t1
SCLK
t2
t8
t4
t3
t7
SYNC
t6
t5
SDIN
DB15 (N)
DB0 (N)
DB15
(N + 1)
DB0
(N + 1)
t10
LDAC
t9
DB15 (N)
SDO
Figure 4. Readback Timing Diagram
Rev. C | Page 7 of 24
DB14 (N)
DB0 (N)
03760-004
t14
AD5570
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to AGND, AGNDS, DGND
VSS to AGND, AGNDS, DGND
AGND, AGNDS to DGND
REFGND to AGND, ADNDS
REFIN to AGND, AGNDS
REFIN to REFGND
Digital Inputs to DGND
VOUT to AGND, AGNDS
SDO to DGND
Operating Temperature Range
W/Y Grades
A/B Grades
Storage Temperature Range
Maximum Junction Temperature (TJ max)
16-Lead SSOP Package
Power Dissipation
θJA Thermal Impedance
Lead Temperature (Soldering, 10 sec)
IR Reflow, Peak Temperature
ESD1
1
Rating
−0.3 V to +17 V
+0.3 V to −17 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +17 V
−0.3 V to +17 V
−0.3 V to VDD + 0.3 V
VSS − 0.3 V to
VDD + 0.3 V
−0.3 V to +6.5 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +125°C
−40°C to +85°C
−65°C to +150°C
150°C
(TJ max – TA)/θJA
139°C/W
300°C
230°C
5 kV
HBM classification.
Rev. C | Page 8 of 24
AD5570
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VSS 1
16 REFGND
VDD 2
15 REFIN
CLR 3
LDAC 4
AD5570
14 REFGND
SDIN 7
10 PD
SDO 8
9
DGND
03760-005
13 VOUT
TOP VIEW
SYNC 5 (Not to Scale) 12 AGNDS
SCLK 6
11 AGND
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
VSS
VDD
CLR
4
LDAC
5
SYNC
6
SCLK
7
8
SDIN
SDO
9
10
11
12
13
14, 16
15
DGND
PD
AGND
AGNDS
VOUT
REFGND
REFIN
Description
Negative Analog Supply Voltage. −12 V ± 5% to −15 V ± 10% for specified performance.
Positive Analog Supply Voltage. 12 V ± 5% to 15 V ± 10% for specified performance.
Level Sensitive, Active Low Input. A falling edge of CLR resets VOUT to AGND. The contents of the registers
are untouched.
Active Low Control Input. Transfers the contents of the input register to the DAC register. LDAC can be tied
permanently low, enabling the outputs to be updated on the rising edge of SYNC.
Active Low Control Input. This is the frame synchronization signal for the data. When SYNC goes low, it powers
on the SCLK and SDIN buffers and enables the input shift register. Data is transferred in on the falling edges of
the following 16 clocks.
Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can
be transferred at rates of up to 8 MHz.
Serial Data Input. Data is clocked into the 16-bit register on the falling edge of the serial clock input.
Serial Data Output. Can be used for daisy-chaining a number of devices together or for reading back the data in
the shift register for diagnostic purposes. This is an open-drain output; it must be pulled to logic high with an
external pull-up resistor of ~5 kΩ.
Digital Ground. Ground reference for all digital circuitry.
Active Low Control Input. Allows the DAC to be put into a power-down state.
Analog Ground. Ground reference for all analog circuitry.
Analog Ground Sense. This is normally tied to AGND.
Analog Output Voltage.
Reference Ground. Tie this pin to 0 V.
Voltage Reference Input. This is internally buffered before being applied to the DAC. For bipolar ±10 V output
range, REFIN is 5 V.
Rev. C | Page 9 of 24
AD5570
TERMINOLOGY
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input change.
Relative Accuracy or Integral Nonlinearity (INL)
Relative accuracy or integral nonlinearity is a measure of
the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital inputs. The AD5570 is monotonic over its full operating temperature range.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent codes.
A specified differential nonlinearity of ±1 LSB maximum ensures
monotonicity.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is
the deviation in slope of the DAC transfer characteristic from
the ideal.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change in
gain error with changes in temperature. It is expressed in ppm/°C.
Negative Full-Scale Error/Zero Scale Error
Negative full-scale error is the error in the DAC output voltage
when all 0s are loaded into the DAC latch. Ideally, the output
voltage, with all 0s in the DAC latch, is −2 VREF.
Full-Scale Error
Full-scale error is the error in the DAC output voltage when all
1s are loaded to the DAC latch. Ideally, the output voltage with
all 1s loaded into the DAC latch is 2 VREF − 1 LSB.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog input from the
ideal half-scale output of 0.0000 V when the inputs are loaded
with 0x8000.
Slew Rate
The slew rate of a device is a limitation in the rate of change of
output voltage. The output slewing speed of a voltage-output
DAC converter is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90%
of the output signal and is given in V/μs.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the amount of charge injected
into the analog output when the input codes in the DAC register
change state. It is specified as the area of the glitch in nV-s and
is measured when the digital input code changes by 1 LSB at the
major carry transition, that is, from code 0x7FFF to 0x8000.
Bandwidth
The reference amplifiers within the DAC have a finite bandwidth to optimize noise performance. To measure it, a sine
wave is applied to the reference input (REFIN), with full-scale
code loaded to the DAC. The bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
SYNC is held high, while the SCLK and SDIN signals are toggled. Digital feedthrough is specified in nV-s and is measured
with a full-scale code change on the data bus, that is, from all
0s to all 1s, and vice versa.
Power Supply Sensitivity
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.
Rev. C | Page 10 of 24
AD5570
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
TA = 25°C
VDD/VSS = ±15V
REFIN = +5V
0.8
0.6
0.4
0.2
0.2
DNL (LSB)
0.4
0
–0.2
–0.4
–0.6
–0.6
–0.8
–0.8
0
10k
20k
30k
CODE
40k
50k
60k
–1.0
Figure 6. Integral Nonlinearity vs. Code, VDD/VSS = ±15 V
30k
CODE
40k
50k
60k
0.8
0.6
0.4
0.2
0.2
INL (LSB)
0.4
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
10k
20k
30k
CODE
40k
50k
60k
–1.0
–40
03760-007
0
VDD/VSS = ±15V
REFIN = +5V
Figure 7. Differential Nonlinearity vs. Code, VDD/VSS = ±15 V
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
03760-018
0.6
DNL (LSB)
20k
1.0
TA = 25°C
VDD/VSS = ±15V
REFIN = +5V
0.8
Figure 10. Integral Nonlinearity vs. Temperature, VDD/VSS = ±15 V
1.0
1.0
TA = 25°C
VDD/VSS = ±12V
REFIN = +5V
0.8
0.6
0.8
0.2
DNL (LSB)
0.4
0.2
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
10k
20k
30k
CODE
40k
50k
60k
Figure 8. Integral Nonlinearity vs. Code, VDD/VSS = ±12 V
–1.0
–40
03760-008
0
VDD/VSS = ±15V
REFIN = +5V
0.6
0.4
–1.0
10k
Figure 9. Differential Nonlinearity vs. Code, VDD/VSS = ±12 V
1.0
–1.0
0
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
03760-019
–1.0
INL (LSB)
0
–0.2
–0.4
03760-006
INL (LSB)
0.6
TA = 25°C
VDD/VSS = ±12V
REFIN = +5V
0.8
03760-009
1.0
Figure 11. Differential Nonlinearity vs. Temperature, VDD/VSS = ±15 V
Rev. C | Page 11 of 24
AD5570
1.0
1.0
0.4
0.2
0.2
DNL (LSB)
0.6
0.4
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
–1.0
11.4
03760-020
Figure 12. Integral Nonlinearity vs. Temperature, VDD/VSS = ±12 V
VDD/VSS = ±16.5V
TA = 125°C
0.8
0.6
0.4
0.2
0.2
INL (LSB)
0.4
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
–1.0
03760-021
DNL (LSB)
16.0 16.5
1.0
VDD/VSS = ±12V
REFIN = +5V
0.6
0
100
Figure 13. Differential Nonlinearity vs. Temperature, VDD/VSS = ±12 V
200
300
400 500 600
TIME (Hours)
700
800
900
1000
Figure 16. INL Drift over Time
1.0
2.0
TA = 25°C
REFIN = 5V
0.8
VDD/VSS = ±12V
TA = 25°C
1.5
0.6
INL ERROR (LSB)
0.4
0
–0.2
–0.4
–0.6
–1.0
11.4
12.0
13.0
14.0
15.0
SUPPLY VOLTAGE (V)
0
–1.0
2.0
16.0 16.5
Figure 14. Integral Nonlinearity vs. Supply Voltage
0.5
–0.5
03760-023
–0.8
1.0
03760-026
0.2
INL (LSB)
13.0
14.0
15.0
SUPPLY VOLTAGE (V)
Figure 15. Differential Nonlinearity vs. Supply Voltage
1.0
0.8
12.0
03760-052
INL (LSB)
0.6
–1.0
–40
TA = 25°C
REFIN = 5V
0.8
03760-024
VDD/VSS = ±12V
REFIN = +5V
0.8
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
5.0
5.5
Figure 17. Integral Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±12 V
Rev. C | Page 12 of 24
AD5570
0.5
1.0
VDD/VSS = ±12V
TA = 25°C
0.3
0.6
0.2
0.4
0.1
0
–0.1
–0.2
–0.3
0.2
0
–0.2
–0.4
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
5.0
–0.8
–1.0
2.0
5.5
Figure 18. Differential Nonlinearity Error vs. Reference Voltage,
VDD/VSS = ±12 V
4.0
5.5
6.0
6.5
3.5
|ISS|
0
3.0
–2.5
2.5
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
5.0
2.0
11.4
5.5
12.4
13.4
14.4
VDD/VSS (V)
15.4
16.4
03760-029
2.5
|IDD|
15.4
16.4
03760-030
IDD/ISS (mA)
5.0
03760-028
TUE ERROR (LSB)
4.5
Figure 19. TUE Error vs. Reference Voltage, VDD/VSS = ±15 V or ±12 V
Figure 22. IDD/ISS vs. VDD/VSS
25
2.0
0.5
0
–0.5
–1.0
03760-048
–1.5
2.5
3.0
3.5
4.0
4.5
5.0
REFERENCE VOLTAGE (V)
5.5
6.0
IDD/ISS POWER-DOWN CURRENT (µA)
TA = 25°C
REFIN = +5V
VDD/VSS = ±15V
TA = 25°C
1.0
INL ERROR (LSB)
3.5
4.0
4.5
5.0
REFERENCE VOLTAGE (V)
TA = 25°C
REFIN = 5V
7.5
–2.0
2.0
3.0
5.0
VDD/VSS = ±15V OR ±12V
TA = 25°C
1.5
2.5
Figure 21. Integral Nonlinearity Error vs. Reference Voltage,
VDD/VSS = ±15 V
10.0
–5.0
2.0
03760-049
03760-027
–0.6
–0.4
–0.5
2.0
VDD/VSS = ±15V
TA = 25°C
0.8
INL ERROR (LSB)
DNL ERROR (LSB)
0.4
6.5
Figure 20. Integral Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±15 V
Rev. C | Page 13 of 24
20
|IDD IN POWER-DOWN|
15
10
5
|ISS IN POWER-DOWN|
0
11.4
12.4
13.4
14.4
SUPPLY VOLTAGE (V)
Figure 23. IDD/ISS in Power-Down vs. Supply Voltage
AD5570
4.15
0
VDD/VSS = ±12V OR ±15V
REFIN = 5V
–1
–3
4.00
–4
–5
–6
–7
INCREASING
3.95 DECREASING
3.90
INCREASING
3.85
12V SUPPLIES
–8
–20
0
20
40
60
TEMPERATURE (°C)
80
100
3.75
120
Figure 24. Offset Error vs. Temperature
03760-035
3.80
03760-031
–9
–10
–40
0
0.5
1.0
1.5
3.5
4.0
4.5
5.0
11
10
REFIN = +5V
8
VDD/VSS = ±15V
–2
6
–3
4
VDD/VSS = ±12V
–5
–6
2
0
–2
–7
–4
–8
–6
–9
–8
0
20
40
60
TEMPERATURE (°C)
80
100
120
03760-032
–20
–10
1µs/DIV
VDD = +15V
VSS = –15V
REFIN = +5V
TA = 25°C
TIME (µs)
Figure 25. Bipolar Zero Error vs. Temperature
Figure 28. Settling Time
40
10
TA = 25°C
REFIN = +5V
REFIN = +5V
35
6
30
VDD/VSS = ±12V
4
25
TIME (µs)
2
VDD/VSS = ±15V
0
–2
–4
5
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
03760-034
–8
–10
–40
VDD/VSS = ±15V
15
10
VDD/VSS = ±12V
–6
20
0
0
1
2
3
4
5
6
CAPACITANCE (nF)
7
8
Figure 29.14-Bit Settling Time vs. Load Capacitance
Figure 26. Gain Error vs. Temperature
Rev. C | Page 14 of 24
9 9.4
03760-037
8
03760-046
VOUT (V)
–4
–10
–40
GAIN ERROR (LSB)
2.0
2.5
3.0
VLOGIC (V)
Figure 27. Supply Current vs. Logic Input Current for SCLK, SYNC, SDIN,
and LDAC Increasing and Decreasing
0
BIPOLAR ZERO ERROR (LSB)
15V SUPPLIES
DECREASING
4.05
IDD (mA)
OFFSET ERROR (LSB)
–2
–1
TA = 25°C
REFIN = 5V
4.10
AD5570
10.0000
–0.022
TA = 25°C
REFIN = 5V
–0.027
–0.032
–0.037
9.9982
9.9979
15V SUPPLIES
9.9976
9.9973
9.9970
9.9967
9.9964
12V SUPPLIES
–0.047
–0.052
–0.057
03760-038
9.9961
9.9958
9.9955
9.9952
–10
–0.042
–8
–6
–4
–2
SOURCE CURRENT (mA)
0
2
4
6
8
SINK CURRENT (mA)
10
–0.062
–0.067
VDD = +12V
VSS = –12V
REFIN = +5V
TA = 25°C
8000 → 7FFFH
03760-051
9.9994
9.9991
9.9988
9.9985
VOLTAGE (V)
OUTPUT VOLTAGE (V)
9.9997
–0.072
1µs/DIV
Figure 30. Source and Sink Capability of Output Amplifier
with Full-Scale Loaded
Figure 33. Major Code Transition Glitch Energy, VDD/VSS = ±12 V
–9.9973
–9.9976
TA = 25°C
REFIN = 5V
VDD = +15V
VSS = –15V
MIDSCALE LOADED
20µV/DIV
VREFIN = 0V
OUTPUT VOLTAGE (V)
–9.9979
12V SUPPLIES
–9.9982
–9.9985
–9.9988
15V SUPPLIES
–9.9991
–9.9994
–8
–6
–4
–2
SOURCE CURRENT (mA)
0
2
4
6
8
SINK CURRENT (mA)
10
CH1 20µV/DIV
Figure 31. Source and Sink Capability of Output Amplifier
with Zero-Scale Loaded
M 1.0Ωms 500kS/s
A CH1
0.0V
20µs/PT
03760-047
–10.0000
–10
03760-039
–9.9997
Figure 34. Peak-to-Peak Noise (100 kHz Bandwidth)
–0.05
–0.06
VDD
VDD = +15V
VSS = –15V
REFIN = +5V
TA = 25°C
RAMP TIME = 100µs
VSS
–0.08
–0.10
VOUT
VDD = +15V
VSS = –15V
REFIN = +5V
TA = 25°C
7 FFF → 8000H
1µs/DIV
Figure 32. Major Code Transition Glitch Energy, VDD/VSS = ±15 V
VDD/VSS = 10V/DIV
VOUT = 10mV/DIV
100µs/DIV
Figure 35. VOUT vs. VDD/VSS on Power-Up
Rev. C | Page 15 of 24
03760-042
–0.09
03760-040
VOUT (V)
–0.07
AD5570
GENERAL DESCRIPTION
On power-up, the input shift register and DAC register are
loaded with midscale (0x8000). The DAC coding is straight
binary; all 0s produce an output of −2 VREF; all 1s produce an
output of +2 VREF − 1 LSB.
The AD5570 is a single 16-bit serial input, voltage output DAC. It
operates from supply voltages of ±11.4 V to ±16.5 V, and has a
buffered voltage output of up to ±13.6 V. Data is written to the
AD5570 in a 16-bit word format, via a 3-wire serial interface. The
device also offers an SDO pin, available for daisy-chaining or
readback.
The AD5570 incorporates a power-on reset circuit to ensure the
DAC output powers up to 0 V. The device also has a power-down
pin to reduce the typical current consumption to 16 μA.
DAC ARCHITECTURE
The DAC architecture of the AD5570 consists of a 16-bit, currentmode, segmented R-2R DAC. The simplified circuit diagram for
the DAC section is shown in Figure 36.
The four MSBs of the 16-bit data word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one
of the 15 matched resistors to either AGND or IOUT. The
remaining 12 bits of the data word drive switches S0 to S11
of the 12-bit R-2R ladder network.
R
VREF
2R
2R
2R
R
2R
After the end of the serial data transfer, data is automatically
transferred from the input shift register to the input register
of the DAC.
When data has been transferred into the input register of the DAC,
the DAC register and DAC output can be updated by taking
LDAC low while SYNC is high.
R
2R
2R
The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. SYNC must frame the
serial word being loaded into the device. Data can be transferred
into the device only while SYNCis low. To start the serial data
transfer, SYNC is taken low, observing the minimum SYNC to
SCLK falling edge setup time, t4. After SYNC goes low, serial data
on SDIN is shifted into the device’s input shift register on the
falling edges of SCLK. SYNC can be taken high after the falling
edge of the 16th SCLK pulse, observing the minimum SCLK
falling edge to SYNC rising edge time, t7.
2R
Load DAC Input (LDAC)
E14
E1
S11
S10
S0
R/8
There are two ways that the DAC register and DAC output can
be updated when data has been transferred into the input register
of the DAC. Depending on the status of both SYNC and LDAC,
one of two update modes is selected.
IOUT
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
VOUT
03760-010
AGND
12-BIT R-2R LADDER
Figure 36. DAC Ladder Structure
REFERENCE BUFFERS
The AD5570 operates with an external reference. The reference
input (REFIN) has an input range of up to 7 V. This input voltage is
then used to provide a buffered positive and negative reference
for the DAC core. The positive reference is given by
+V REF = 2 × V REFIN
The first mode is synchronous LDAC. In this mode, LDAC is low
while data is being clocked into the input shift register. The DAC
output is updated when SYNC is taken high. The update here
occurs on the rising edge of SYNC.
The second mode is asynchronous LDAC. In this mode, LDAC
is high while data is being clocked in. The DAC output is updated
by taking LDAC low any time after SYNC has been taken high.
The update now occurs on the falling edge of LDAC.
Figure 37 shows a simplified block diagram of the input loading
circuitry.
and the negative reference to the DAC core is given by
−V REF = 2 × V REFIN
OUTPUT
I/V AMPLIFIER
These positive and negative reference voltages define the DAC
output range.
VREFIN
SERIAL INTERFACE
LDAC
The AD5570 is controlled over a versatile 3-wire serial interface
that operates at clock rates up to 10 MHz and is compatible with
SPI, QSPI, MICROWIRE, and DSP interface standards.
SYNC
SDIN
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in Figure 2.
16-BIT
DAC
VOUT
DAC
REGISTER
INPUT SHIFT
REGISTER
SDO
03760-012
E15
Figure 37. Simplified Serial Interface Showing Input Loading Circuitry
Rev. C | Page 16 of 24
AD5570
TRANSFER FUNCTION
POWER-DOWN (PD)
Table 6 shows the ideal input code to the output voltage relationship for the AD5570.
The power-down pin allows the user to place the AD5570 into
a power-down mode. In power-down mode, power consumption is at a minimum; the device typically consumes only 16 μA.
Table 6. Binary Code Table
POWER-ON RESET
Digital Input
MSB
1111
1000
1000
0111
0000
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
LSB
1111
0001
0000
1111
0000
The AD5570 contains a power-on reset circuit that controls the
output during power-up and power-down. This is useful in applications where the known state of the output of the DAC during
power-up is important. On power-up and power-down, the output
of the DAC and VOUT, is held at AGND.
Analog Output (VOUT)
+2 VREF × (32,767/32,768)
+2 VREF × (1/32,768)
0V
−2 VREF × (1/32,768)
−2 VREF
SERIAL DATA OUTPUT (SDO)
The SDO is the internal shift registers output. For the AD5570,
SDO is an internal pull-down only; an external pull-up resistor
of ~5 kΩ to external logic high is required. SDO pull-down is
disabled when the device is in power-down, thus saving current.
The output voltage expression is given by
VOUT = −2 VREFIN + 4 × V REFIN [D / 65536]
where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage available at the REFIN pin.
CLEAR (CLR)
CLR is an active low digital input that allows the output to be
cleared to 0 V. When the CLR signal is brought back high, the
output stays at 0 V until LDAC is brought low. The relationship
between LDAC and CLR is explained further in Table 7.
Table 7. Relationships Among PD, CLR, and LDAC
PD
CLR
LDAC
Comments
0
x
x
PD has priority over LDAC and CLR. The
output remains at 0 V through an internal
20 kΩ resistor. It is still possible to address
both the input register and DAC register
when the AD5570 is in power-down.
Data is written to the input register and
DAC register. CLR has higher priority over
LDAC; therefore, the output is at 0 V.
Data is written to the input register only.
The output is at 0 V and remains at 0 V
when CLR is taken back high.
Data is written to the input register and the
DAC register. The output is driven to the
DAC level.
Data is written to the input register only.
The output of the DAC register is unchanged.
1
0
0
1
0
1
1
1
0
1
1
1
The availability of SDO allows any number of AD5570s to be
daisy-chained together. It also allows for the contents of the DAC
register, or any number of DACs daisy-chained together, to be
read back for diagnostic purposes.
Daisy Chaining
This mode of operation is designed for multi DAC systems,
where several AD5570s can be connected in cascade as shown
in Figure 38. This is done by connecting the control inputs in
parallel and then daisy-chaining the SDIN and SDO I/Os of
each device. An external pull-up resistor of ~5 kΩ on SDO is
required when using the part in daisy-chain mode.
As described earlier, when SYNC goes low, serial data on SDIN
is shifted into the input shift register on the falling edge of SCLK.
If more than 16 clock pulses are applied, the data ripples out of
the shift resister and appears on the SDO line. By connecting
this line to the SDIN input on the next AD5570 in the chain, a
multi DAC interface can be constructed.
One data transfer cycle of 16 SCLK pulses is required for each
DAC in the system. Therefore, the total number of clock cycles
must equal 16 N, where N is the total number of devices in the
chain. The first data transfer cycle written into the chain appears at
the last DAC in the system on the final data transfer cycle.
When the serial transfer to all devices is complete, take SYNC high.
This prevents any further data from being clocked into the devices.
A continuous SCLK source can be used if SYNC is held low
for the correct number of clock cycles. Alternatively, a burst
clock containing the exact number of clock cycles can be used
and SYNC is taken high some time later. The outputs of all the
DACs in the system can be updated simultaneously using the
LDAC signal.
Rev. C | Page 17 of 24
AD5570
Readback
The AD5570 allows the data contained in the DAC register to
be read back, if required. As with daisy chaining, an external
pull-up resistor of ~5 kΩ on SDO is required. The data in the
DAC register is available on SDO on the falling edges of SCLK
when SYNC is low. On the 16th SCLK edge, SDO is updated to
repeat SDIN with a delay of 16 clock cycles.
68HC11*
To read back the contents of the DAC register without writing
to the part, take SYNC low while LDAC is held high.
Daisy-chaining readback is also possible through the SDO pin
of the last device in the DAC chain because the DAC data passes
through the DAC chain with the appropriate latency.
AD5570*
MOSI
SDIN
SCK
SCLK
PC7
SYNC
PC6
LDAC
VLOGIC
SDO
MISO
R
SDIN
AD5570*
SCLK
SYNC
LDAC
SDO
R
SDIN
AD5570*
SCLK
SYNC
SDO
R
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 38. Daisy-Chaining Using the AD5570
Rev. C | Page 18 of 24
03760-013
LDAC
AD5570
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
1
VSS
Figure 39 shows the typical operating circuit for the AD5570.
The only external component needed for this precision 16-bit
DAC is a single external positive reference. Because the device
incorporates reference buffers, it eliminates the need for a negative
reference, external inverters, precision amplifiers, and resistors.
This leads to an overall savings of both cost and board space.
2
VDD
REFIN 15
3
CLR
REFGND 14
4
LDAC
5
SYNC
AGNDS 12
6
SCLK
AGND 11
7
SDIN
PD 10
8
SDO
DGND 9
In the circuit shown in Figure 39, VDD and VSS are both connected
to ±15 V, but VDD and VSS can operate supplies from 11.4 V to
16.5 V. AGNDS is connected to AGND, but the option of force/
sense is included on this device if required by the user.
1
VSS
2
VDD
REFIN 15
3
CLR
REFGND 14
LDAC
4
LDAC
SYNC
5
SYNC
AGNDS 12
SCLK
6
SCLK
AGND 11
SDIN
7
SDIN
PD 10
8
SDO
DGND 9
+15V
0.1µF
10µF
SDO
VOUT 13
VOUT 13
6
2
3
OP177*
03760-045
*FOR OPTIMUM SETTLING TIME PERFORMANCE,
THE AD845 IS RECOMMENDED.
Figure 40. Driving AGND and AGNDS Using a Force/Sense Amplifier
REFGND 16
AD5570
AD5570
(OTHER CONNECTIONS OMITTED
FOR CLARITY)
10µF
The four possible sources of error to consider when choosing
a voltage reference for high accuracy applications are initial
accuracy, long-term drift, temperature coefficient of the output voltage, and output voltage noise.
ADR435
VOUT
03760-044
0.1µF
–15V
REFGND 16
5kΩ
5V
Figure 39. Typical Operating Circuit
Force/Sense of AGND
Because of the extremely high accuracy of this device, system
design issues (such as grounding and contact resistance) are
very important. The AD5570, with ±10 V output, has an LSB
size of 305 μV. Therefore, series wiring and connector resistances
of very small values can cause voltage drops of an LSB. For this
reason, the AD5570 offers a force/sense output configuration.
Figure 40 shows how to connect the AD5570 to the force/sense
amplifier. Where accuracy of the output is important, an amplifier such as the OP177 is ideal. The OP177 is ultraprecise with
offset voltages of 10 μV maximum at room temperature, and offset drift of 0.1 μV/°C maximum. Alternative recommended
amplifiers are the OP1177 and the OP77. For applications where
optimization of the circuit for settling time is needed, the AD845
is recommended.
Precision Voltage Reference Selection
To achieve the optimum performance from the AD5570, give
special attention to the selection of a precision voltage reference.
The AD5570 has just one reference input, REFIN. This voltage
on REFIN is used to provide a buffered positive and negative
reference for the DAC core. Therefore, any error in the voltage
reference is reflected in the output of the device.
Initial accuracy on the output voltage of an external reference can
lead to a full-scale error in the DAC. Therefore, to minimize
these errors, a reference with low initial accuracy specification
is preferred. Also, choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim out
system errors by setting the reference voltage to a voltage other
than the nominal. The trim adjustment can also be used at temperature to trim out any error.
Long-term drift (LTD) is a measure of how much the reference
drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable
over its entire lifetime.
The temperature coefficient of a references output voltage
affects INL, DNL, and TUE. Choose a reference with a tight
temperature coefficient specification to reduce the depend
ence of the DAC output voltage on ambient conditions.
In high accuracy applications that have a relatively low noise
budget, reference output voltage noise needs to be considered.
It is important to choose a reference with as low an output noise
voltage as practical for the system resolution required. Precision
voltage references, such as the ADR435 (XFET® design), produce
low output noise in the 0.1 Hz to 10 Hz region. However, as the
circuit bandwidth increases, filtering the output of the reference
can be required to minimize the output noise.
Rev. C | Page 19 of 24
AD5570
Table 8. Partial List of Precision References Recommended
for Use with the AD5570
Part No.
Initial
Accuracy
(mV max)
Long-Term
Drift
(ppm typ)
Temp Drift
(ppm/
°C max)
0.1 Hz to
10 Hz Noise
(μV p-p typ)
ADR435
ADR425
ADR021
ADR395
AD586
±6
±6
±5
±6
±2.5
30
50
50
50
15
3
3
3
25
10
3.4
3.4
15
5
4
OPTO-ISOLATORS
Available in SC70 package.
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board that
the AD5570 is mounted on is designed so the analog and digital sections are separated and confined to certain areas of the
board. If the AD5570 is in a system where multiple devices
require an AGND-to-DGND connection, the connection is
made at one point only. The star ground point is established
as close as possible to the device.
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators provide voltage isolation in excess of
3 kV. The serial loading structure of the AD5570 makes it ideal
for opto-isolated interfaces, because the number of interface lines
is kept to a minimum. Figure 41 shows a 4-channel isolated interface to the AD5570. To reduce the number of opto-isolators, the
LDAC pin can be tied permanently low if the simultaneous
updating of the DAC is not required. The DAC can then be
updated on the rising edge of SYNC.
The AD5570 has ample supply bypassing of 10 μF in parallel
with 0.1 μF on each supply located as close to the package as
possible, ideally right up against the device. The 10 μF capacitors
are the tantalum bead type. The 0.1 μF capacitor has low effective
series resistance (ESR) and effective series inductance (ESI)
such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient
currents due to internal logic switching.
The power supply lines of the AD5570 use as large a trace as possible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals such as
clocks are shielded with digital ground to avoid radiating noise
to other parts of the board, and are never be run near the reference inputs. A ground line routed between the SDIN and SCLK
lines reduces crosstalk between them; this is not required on a
multilayer board that has a separate ground plane, but separating
the lines helps. It is essential to minimize noise on the REFIN
line because it couples through to the DAC output.
Rev. C | Page 20 of 24
VCC
µCONTROLLER
CONTROL OUT
TO LDAC
SYNC OUT
TO SYNC
SERIAL CLOCK OUT
TO SCLK
TO SDIN
SERIAL DATA OUT
OPTO-COUPLER
Figure 41. Opto-Isolated Interface
03760-050
1
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board must run at right angles to each other.
This reduces the effects of feed through the board. A microstrip technique is by far the best, but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground plane, while signal
traces are placed on the solder side.
AD5570
Microprocessor interfacing to the AD5570 is via a serial bus
that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5570 requires a 16-bit
data word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update can be done automatically when all the data is clocked in, or it can be done under
the control of LDAC. The contents of the DAC register can be
read using the readback function.
AD5570 to MC68HC11 Interface
Figure 42 shows an example of a serial interface between the
AD5570 and the MC68HC11 microcontroller. The serial peripheral interface (SPI) on the MC68HC11 is configured for master
mode (MSTR = 1), clock polarity bit (CPOL = 0), and the clock
phase bit (CPHA = 1). The SPI is configured by writing to the SPI
control register (SPCR); see documentation on the MC68HC11.
SCK of the MC68HC11 drives the SCLK of the AD5570, the
MOSI output drives the serial data line (SDIN) of the AD5570,
and the MISO input is driven from SDO. The SYNC is driven
from one of the port lines, in this case, PC7.
When data is being transmitted to the AD5570, the SYNC line
(PC7) is taken low and data is transmitted MSB first. Data appearing on the MOSI output is valid on the falling edge of SCK. Eight
falling clock edges occur in the transmit cycle; therefore, in order
to load the required 16-bit word, PC7 is not brought high until
the second 8-bit word has been transferred to the DACs input
shift register.
SDO
SDIN
SCLK
SCLK
PC7
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
The AD5570 requires a clock synchronized to the serial data. For
this reason, the 8xC51 must be operated in Mode 0. In this mode,
serial data enters and exits through RxD, and a shift clock is
output on TxD.
P3.3 and P3.4 are bit-programmable pins on the serial port and
are used to drive SYNC and LDAC, respectively.
The 8xC51 provides the LSB of its SBUF register as the first bit
in the data stream. The user must ensure that the data in the SBUF
register is arranged correctly because the DAC expects MSB first.
8xC51*
AD5570*
RxD
SDIN
TxD
SCLK
P3.3
SYNC
P3.4
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 43. AD5570 to 8xC51 Interface
When data is to be transmitted to the DAC, P3.3 is taken low. Data
on RxD is clocked out of the microcontroller on the rising edge
of TxD and is valid on the falling edge. As a result, no glue logic
is required between this DAC and the microcontroller interface.
03760-014
MISO
MOSI
AD5570 to 8xC51 Interface
The 8xC51 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC
expects a 16-bit word, SYNC (P3.3) must be left low after the first
eight bits are transferred. After the second byte has been transferred, the P3.3 line is taken high. The DAC can be updated using
LDAC via P3.4 of the 8xC51.
AD5570*
MC68HC11*
LDAC is controlled by the PC6 port output. The DAC can be
updated after each 2-byte transfer by bringing LDAC low. This
example does not show other serial lines for the DAC. If CLR
were used, control it by the Port Output PC5.
03760-015
MICROPROCESSOR INTERFACING
Figure 42. AD5570 to MC68HC11 Interface
Rev. C | Page 21 of 24
AD5570
An interface between the AD5570 and the ADSP21xx family is
shown in Figure 44. The ADSP21xx must be set up to operate in
the SPORT transmit alternate framing mode. The ADSP21xx is
programmed through the SPORT control register and is configured as follows: internal clock operation, active low framing,
and 16-bit word length.
Transmission is initiated by writing a word to the Tx register, after
the SPORT has been enabled. As the data is clocked out of the
DSP on the rising edge of SCLK, no glue logic is required to interface the DSP to the DAC. In the interface shown, the DAC output
is updated using the LDAC pin via the DSP. Alternatively, the
LDAC input can be tied permanently low, and then the update
is automatic when TFS is taken high.
ADSP21xx
SDO
DT
SDIN
SCLK
SYNC
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
03760-016
FO
SDI/RC4
SDO
SDO/RC5
SDIN
SCLK/RC3
SCLK
RA1
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 45. AD5570 to PIC16C6x/7x Interface
EVALUATION BOARD
The AD5570 evaluation kit includes a populated and tested
AD5570 printed circuit board. The evaluation board interfaces to the parallel interface of a PC. Software is available
with the evaluation board that allows the user to easily program the AD5570. A schematic of the evaluation board is
shown in Figure 46. The software runs on any PC installed
with Microsoft® Windows® 95/ Windows® 98/Windows® ME/
Windows® 2000/Windows® XP.
SCLK
TFS
RFS
AD5570*
PIC16C6x/7x*
The AD5570 comes with a full evaluation board to aid designers
in evaluating the high performance of the part with minimal
effort. The evaluation board requires a power supply, a PC,
and an oscilloscope.
AD5570*
DR
eight bits of data during each serial transfer operation; therefore,
two consecutive write operations are needed. Figure 45 shows
the connection diagram.
03760-017
AD5570 to ADSP21xx
Figure 44. AD5570 to ADSP21xx Interface
AD5570 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured as
an SPI master with the clock polarity bit set to 0. This is done
by writing to the synchronous serial port control register, SSPCON
(see documentation on the PIC16/17 microcontroller). In this
example, I/O port RA1 is being used to pulse SYNC and enable
the serial port of the AD5570. This microcontroller transfers only
An application note containing full details on operating the
evaluation board comes supplied with the AD5570 evaluation board.
Rev. C | Page 22 of 24
Figure 46. Evaluation Board Schematic
SCLK_ADC
SDATA_ADC
DATA
SYNC
LDAC
CLR
CONVST
DIN
SCLK
PD
J11–30
J11–29
J11–28
J11–27
J11–26
J11–25
J11–24
J11–23
J11–22
J11–21
J11–20
J11–19
J11–9
J11–10
J11–12
J11–4
J11–6
J11–7
J11–8
J11–2
J11–5
J11–3
J11–13
J12–3
+
+
PD
+
C30
10µF
20V
J5
J7
DVDD
J8
+
+
DGND
J9
LK4
VSS
+
+
+
C13 C21 C22 C23 C24 C15
10µF 10µF 10µF 0.1µF 0.1µF 0.1µF
A0
A1
A2
A3
OE
0.33µF
C2
74ACT244
AVDD
VSS
AGND
Y0
Y1
Y2
Y3
2
4
6
8
1
9
7
5
3
74ACT244
A0
A1
A2
A3
OE
U9–B
74ACT244
A0
A1
A2
A3
11
A0
A1 13
15
A2
17
A3
OE 19
74ACT244
VIN
VOUT
U6
GND4 GND2
GND3 GND1
AVDD
5
6
7
8
4
3
2
1
C17
0.1µF
+
C18
10µF
PD
SDO
SDIN
SCLK
SYNC
LDAC
CLR
9
3
REF/2
2
4
VSS
V–
OP177
7
V+
13
+
C5
10µF
C3
0.1µF
VOUT
REF/2
6
C36
0.1µF
OP
6
+VIN
GND
4
U2
TRIM
ADR435
VOUT
5
2
REF
TP5 R1
WHITE PLASTIC SSOP CLAMP
C16
0.1µF
LK3
C35
0.1µF
15
U1
+
C34
10µF
TP4
16 14
REFGND
U3 AVDD
VIN
AGND
3
2
12 11
1
J2
AD5570
2
1
VSS
AVDD
C4
0.01µF
AD7895-10
U5 8
4
SCLK
5 SDATA
6
BUSY
7
CONVST
DGND
LK2
LK1
10
8
7
6
5
4
3
TP8 TP3 TP9 TP2 TP1 TP7 TP10
AVDD LM78L05ACM
U4–B
Y0
Y1
Y2
Y3
9
7
5
3
18
Y0
Y1 16
14
Y2
12
Y3
U9–A
OE
U4–A
11
13
15
17
19
2
4
6
8
1
18
Y0
16 Y1
14
Y2
12
Y3
J10
SCLK LDAC SYNC CLR
C31
C32
C33
0.1µF 0.1µF 0.1µF
J6
DIN
C12 C11 C10
C9
C8
C7
C6 C14
10µF 10µF 10µF 10µF 0.1µF 0.1µF 0.1µF 0.1µF
AGND
J12–2
J12–1
AVDD
J13–2
DGND
J13–1
DVDD
J4
SDO
DVDD DVDD DVDD
R5
4.7kΩ
DOUT
R4
4.7kΩ
R7
4.7kΩ
J11 – CENTRONICS CONNECTOR
R6
4.7kΩ
VSS
DGND
VDD
AGND
REFIN
REFGND
REF
LK5
VDD
AGNDS
REFIN
GND
Rev. C | Page 23 of 24
C1
AVDD
R3
10kΩ
R2
10kΩ
J1
REF/2
VOUT
03760-043
DVDD
AD5570
AD5570
OUTLINE DIMENSIONS
6.50
6.20
5.90
9
5.60
5.30
5.00
1
8
0.25
0.09
1.85
1.75
1.65
2.00 MAX
0.05 MIN
COPLANARITY
0.10
8.20
7.80
7.40
0.65 BSC
0.38
0.22
SEATING
PLANE
8°
4°
0°
COMPLIANT TO JEDEC STANDARDS MO-150-AC
0.95
0.75
0.55
060106-A
16
Figure 47. 16-Lead Shrink Small Outline Package [SSOP]
(RS-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5570ARS
AD5570ARS-REEL
AD5570ARS-REEL7
AD5570ARSZ
AD5570ARSZ-REEL
AD5570ARSZ-REEL7
AD5570BRS
AD5570BRS-REEL
AD5570BRS-REEL7
AD5570BRSZ
AD5570BRSZ-REEL
AD5570BRSZ-REEL7
AD5570WRS
AD5570WRSZ
AD5570WRSZ-REEL
AD5570WRSZ-REEL7
AD5570YRS
AD5570YRS-REEL
AD5570YRS-REEL7
AD5570YRSZ
AD5570YRSZ-REEL
AD5570YRSZ-REEL7
EVAL-AD5570EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
16-Lead SSOP
Evaluation Board
Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03760-0-11/10(C)
Rev. C | Page 24 of 24
Package Option
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
RS-16
工商网监
湘ICP备2023018690号
