16 Input, 16 Output Analog I/O Port
with Integrated Amplifiers
AD5590
FEATURES
Low input bias current: 1 pA maximum
Single supply operation
Low noise: 22 nV/√Hz
Unity gain stable
Flexible serial interface
SPI-/QSPI-/MICROWIRE-/DSP-compatible
−40°C to +85°C operation
Available in 80-ball CSP_BGA package
Input channels
12-bit successive approximation ADC
16 inputs with sequencer
Fast throughput rate: 1 MSPS
Wide input bandwidth: 70 dB SNR at fIN = 50 kHz
Output channels
16 outputs with 12-bit DACs
On-chip 2.5 V reference
Hardware LDAC and LDAC override function
CLR function to programmable code
Rail-to-rail operation
Operational amplifiers
Offset voltage: 2.2 mV maximum
APPLICATIONS
Optical line cards
Base stations
General-purpose analog I/O
Monitoring and control
FUNCTIONAL BLOCK DIAGRAM
ADCV DD DACV DD (×2)
V1+ V2+ V1– V2– VREFIN1 /VREFOUT1
POWER-ON
RESET
DSCLK
LDAC
2.5V REF
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 7
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 8
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 15
POWER-DOWN
LOGIC
BUFFER
VOUT0
DSYNC1
DSYNC2
DDIN
LDAC
CLR
DAC
INTERFACE
LOGIC
BUFFER
BUFFER
BUFFER
VOUT7
VOUT8
VOUT15
POWER-DOWN
LOGIC
VDRIVE
ASCLK
ASYNC
ADIN
ADOUT
VREFIN2 /VREFOUT2
2.5V REF
VIN0
SEQUENCER
ADC
INTERFACE
LOGIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
INPUT
MUX
T/H
VIN15
IN0(–) IN0(+)
OUT0
IN7(–) IN7(+)
OUT7
DACGND (×2)
ADCGND
VREFA
07691-001
AD5590
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved.
AD5590
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC.............................................................................................. 14
Applications ....................................................................................... 1
ADC ............................................................................................. 18
Functional Block Diagram .............................................................. 1
Amplifier ..................................................................................... 19
Revision History ............................................................................... 2
Terminology .................................................................................... 23
General Description ......................................................................... 3
Theory of Operation ...................................................................... 26
Specifications..................................................................................... 4
DAC Section................................................................................ 26
ADC Specifications ...................................................................... 4
ADC Section ............................................................................... 27
DAC Specifications....................................................................... 6
ADC Converter Operation ....................................................... 27
Operational Amplifier Specifications ........................................ 8
Amplifier Section ....................................................................... 29
Timing Specifications .................................................................. 9
Serial Interface ................................................................................ 30
Absolute Maximum Ratings .......................................................... 11
Accessing the DAC Block .......................................................... 30
Thermal Resistance .................................................................... 11
Accessing the ADC Block ......................................................... 34
ESD Caution ................................................................................ 11
Outline Dimensions ....................................................................... 42
Pin Configuration and Function Descriptions ........................... 12
Ordering Guide .......................................................................... 42
Typical Performance Characteristics ........................................... 14
REVISION HISTORY
7/11—Rev. 0 to Rev. A
Changes to Features Section and Figure 1..................................... 1
Changes to VOUT10 Pin Number in Table 10 ........................... 13
10/08—Revision 0: Initial Version
Rev. A | Page 2 of 44
AD5590
GENERAL DESCRIPTION
The AD5590 is a 16-channel input and 16-channel output
analog I/O port with eight uncommitted amplifiers, operating
from a single 4.5 V to 5.25 V supply. The AD5590 comprises
16 input channels multiplexed into a 1 MSPS, 12-bit successive
approximation ADC with a sequencer to allow a preprogrammed
selection of channels to be converted sequentially. The ADC
contains a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 1 MHz.
The conversion process and data acquisition are controlled using
ASYNC and the serial clock signal, allowing the device to easily
interface with microprocessors or DSPs. The input signal is
sampled on the falling edge of ASYNC and conversion is also
initiated at this point. There are no pipeline delays associated
with the ADC. By setting the relevant bits in the control register,
the analog input range for the ADC can be selected to be a 0 V
to VREFA input or a 0 V to 2 × VREFA with either straight binary
or twos complement output coding. The conversion time is
determined by the ASCLK frequency because it is also used
as the master clock to control the conversion.
The DAC section of the AD5590 comprises sixteen 12-bit DACs
divided into two groups of eight. Each group has an on-chip
reference. The on-board references are off at power-up, allowing
the use of external references. The internal references are enabled
via a software write.
The AD5590 incorporates a power-on reset circuit that ensures
that the DAC outputs power up to 0 V and remain powered up
at this level until a valid write takes place. The DAC contains a
power-down feature that reduces the current consumption of
the device and provides software-selectable output loads while
in power-down mode for any or all DAC channels. The outputs
of all DACs can be updated simultaneously using the LDAC
function, with the added functionality of user-selectable DAC
channels to simultaneously update. There is also an asynchronous
CLR that updates all DACs to a user-programmable code: zero
scale, midscale, or full scale.
The AD5590 contains eight low noise, single-supply amplifiers.
These amplifiers can be used for signal conditioning for the
ADCs, DACs, or other independent circuitry, if required.
Rev. A | Page 3 of 44
AD5590
SPECIFICATIONS
ADC SPECIFICATIONS
ADCVDD = VDRIVE = 2.7 V to 5.25 VREFA = 2.5 V, fSCLK 1 = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD) 3
Min
Typ
68.5
70
70.5
70
70.5
−82
−82
−86
−80
dB
dB
dB
dB
dB
dB
dB
dB
−85
−85
10
50
−82
8.2
1.6
dB
dB
ns
ps
dB
MHz
MHz
Signal-to-Noise Ratio (SNR)3
69
Total Harmonic Distortion (THD)3
−74
Peak Harmonic or Spurious Noise (SFDR)3
−75
Intermodulation Distortion (IMD)3, 4
Second-Order Terms
Third-Order Terms
Aperture Delay4
Aperture Jitter4
Channel-to-Channel Isolation3, 4
Full Power Bandwidth4
DC ACCURACY3
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to VREFA Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
0 V to 2 × VREFA Input Range
Max
12
−1
−1
−10
±0.6
−2
−0.8
Unit
+1
+1.5
Bits
LSB
LSB
+10
3.5
+2
+0.8
LSB
LSB
LSB
LSB
Test Conditions/Comments 2
fIN = 50 kHz sine wave, fSCLK = 20 MHz
@5V
@3V
@5V
@3V
@5V
@3V
@5V
@3V
fa = 40.1 kHz, fb = 41.5 kHz
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missing codes to 12 bits
Straight binary output coding
−VREFA to +VREFA biased about VREFA with
twos complement output coding offset
Positive Gain Error
Positive Gain Error Match
Zero-Code Error
Zero-Code Error Match
Negative Gain Error
Negative Gain Error Match
ANALOG INPUT
Input Voltage Ranges
−2
−0.8
−8
DC Leakage Current
Input Capacitance4
REFERENCE INPUT
VREFA Input Voltage
DC Leakage Current
VREFA Input Impedance4
−1
±0.6
−1
−0.8
+2
+0.8
+8
2
+1
+0.8
0 to VREFA
0 to 2 × VREFA
V
V
+1
20
2.5
−1
LSB
LSB
LSB
LSB
LSB
LSB
+1
36
Rev. A | Page 4 of 44
Range bit set to 1
Range bit set to 0, ADCVDD/VDRIVE = 4.75 V
to 5.25 V for 0 V to 2 × VREFAS
µA
pF
V
µA
kΩ
±1% specified performance
fSAMPLE = 1 MSPS
AD5590
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN1, 4
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance4
Output Coding
Min
Typ
Unit
0.3 × VDRIVE
+1
10
V
V
µA
pF
0.7 × VDRIVE
−1
VDRIVE − 0.2
800
300
300
1
ns
ns
ns
MSPS
16 ASCLK cycles, ASCLK = 20 MHz
Sine wave input
Full-scale step input
@ 5 V (see the Serial Interface section)
5.25
5.25
0.15
V
V
µA
2.5
µA
mA
Digital inputs = 0 V or VDRIVE
VDD = 4.75 V to 5.25 V, ASCLK on or off
VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
0.5
0.5
mA
µA
µA
µA
µA
fSAMPLE = 500 kSPS
Static
fSAMPLE = 250 kSPS
Static
ASCLK on or off
12.5
500
2.5
2.5
mW
µW
µW
µW
ADCVDD = 5 V, fSCLK = 20 MHz
ADCVDD = 5 V
ADCVDD = 5 V
ADCVDD = 5 V
750
1.55
100
Autoshutdown Mode
Full Shutdown Mode
Power Dissipation
Normal Mode, Operational
Autostandby Mode, Static
Autoshutdown Mode, Static
Full Shutdown Mode
960
0.02
Typically 10 nA
ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V
ISINK = 200 µA
weak/TRI bit set to 0
weak/TRI bit set to 0
coding bit set to 1
coding bit set to 0
±10
10
Straight (Natural) Binary
Twos Complement
2.7
2.7
Test Conditions/Comments 2
V
V
µA
pF
0.4
CONVERSION RATE 4
Conversion Time
Track-and-Hold Acquisition Time3
Throughput Rate
POWER REQUIREMENTS
ADCVDD
VDRIVE
IDRIVE
IDD 5
Normal Mode, Static
Normal Mode, Operational
(fS = Maximum Throughput)
Autostandby Mode
Max
Specifications apply for fSCLK up to 20 MHz. For serial interfacing requirements, see the Timing Specifications section.
Temperature range: −40°C to +85°C.
3
See the Terminology section.
4
Guaranteed by design and characterization. Not production tested.
5
See the ADC Power vs. Throughput Rate section.
1
2
Rev. A | Page 5 of 44
AD5590
DAC SPECIFICATIONS
DACVDD = 4.5 V to 5.25 V, RL = 2 kΩ to DACGND, CL = 200 pF to DACGND, VREFIN1 = VREFIN1 = DACVDD. All specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 2
Resolution
Integrated Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero-Code Error
Zero-Code Error Drift3
Full-Scale Error
Gain Error
Gain Temperature Coefficient3
Offset Error
DC Power Supply Rejection Ratio3
DC Crosstalk 3
External Reference
Min
Typ
Max
12
−3
−0.25
±0.5
+3
+0.25
12
−1
−1
−11
Internal Reference
OUTPUT CHARACTERISTICS3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance3
REFERENCE OUTPUT
Output Voltage
Reference Temperature Coefficient3
Reference Output Impedance3
LOGIC INPUTS
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance3
1
±2
−0.2
+1
±2.5
±5
–80
+11
Unit
Bits
LSB
LSB
mV
µV/°C
% FSR
% FSR
ppm
mV
dB
10
µV
5
10
25
µV/mA
µV
µV
10
µV/mA
0
DACVDD
2
10
0.5
30
4
40
0
2
5
All 1s loaded to DAC register
Of FSR/°C
DACVDD ± 10%
Due to full-scale output change, RL = 2 kΩ to DACGND or
DACVDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change, RL = 2 kΩ to DACGND or
DACVDD
Due to load current change
RL = ∞
RL = 2 kΩ
DACVDD = 5 V
Coming out of power-down mode, DACVDD = 5 V
µA
V
kΩ
VREFINx = DACVDD = 5.5 V (per DAC channel)
2.505
V
ppm/°C
kΩ
At ambient
+3
0.8
µA
V
V
pF
All digital inputs
DACVDD = 5 V
DACVDD = 5 V
±10
7.5
−3
See Figure 6
Guaranteed monotonic by design; see Figure 7
All 0s loaded to DAC register; see Figure 11
50
DACVDD
14.6
2.495
V
nF
nF
Ω
mA
µs
Conditions/Comments 1
Rev. A | Page 6 of 44
AD5590
Parameter
POWER REQUIREMENTS
DACVDD
Min
Typ
Max
Unit
Conditions/Comments 1
5.5
V
2.6
4
3.2
5
mA
mA
All digital inputs at 0 or DACVDD, DAC active, excludes load
current
VIH = DACVDD = 4.5 V to 5.5 V, VIL = DACGND
Internal reference off
Internal reference on
0.8
2
µA
VIH = DACVDD = 4.5 V to 5.5 V, VIL = DACGND
4.5
IDD (Normal Mode) 4
DACIDD (All Power-Down Modes) 5
DACVDD
Temperature range is −40°C to +85°C, typical at 25°C.
Linearity calculated using a reduced code range of Code 32 to Code 4064. Output unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All sixteen DACs powered down.
1
2
DAC AC Characteristics
DACVDD = 4.5 V to 5.25 V, RL = 2 kΩ to DACGND, CL = 200 pF to DACGND, VREFIN1 = VREFIN1 = DACVDD. All specifications TMIN to TMAX,
unless otherwise noted.
Table 3.
Parameter 1, 2
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
Output Noise
Min
Typ
6
1.5
4
0.1
−90
0.5
2.5
3
340
−80
120
100
15
Max
10
Unit
µs
V/µs
nV-sec
nV-sec
dB
nV-sec
nV-sec
nV-sec
kHz
dB
nV/√Hz
nV/√Hz
μV p-p
Guaranteed by design and characterization; not production tested.
See the Terminology section.
3
Temperature range is −40°C to +85°C, typical at 25°C.
1
2
Rev. A | Page 7 of 44
Conditions/Comments 3
¼ to ¾ scale settling to ±2 LSB
1 LSB change around major carry (see Figure 17)
VREFIN1 = VREFIN2 = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz
VREFIN1 = VREFIN2 = 2 V ± 0.2 V p-p
VREFIN1 = VREFIN2 = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC Code = 0x8400, 1 kHz
DAC Code = 0x8400, 10 kHz
0.1 Hz to 10 Hz
AD5590
OPERATIONAL AMPLIFIER SPECIFICATIONS
Electrical characteristics @ VSY = 5 V, VCM = VSY/2, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Typ
Max
Unit
Conditions
VOS
0.4
Offset Voltage Drift 1
Input Bias Current1
∆VOS/∆T
IB
1
0.2
IOS
0.1
Common-Mode Rejection Ratio
CMRR
95
Large Signal Voltage Gain
Input Capacitance1
AVO
CDIFF
CCM
mV
mV
µV/°C
pA
pA
pA
pA
dB
dB
V/mV
pF
pF
−0.3 V < VCM < +5.3 V
−40°C < TA < +85°C, −0.3 V < VCM < +5.2 V
−40°C < TA < +85°C
Input Offset Current1
2.2
2.2
4.5
1
110
0.5
50
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
Min
68
235
4.95
4.9
400
2
7
4.98
4.7
4.50
Output Voltage Low
VOL
20
190
Short-Circuit Current1
Closed-Loop Output Impedance1
POWER SUPPLY
Power Supply Span (V+ to V−)
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE1
Slew Rate
Settling Time 0.1%
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE1
Peak-to-Peak Noise
Voltage Noise Density
Current Noise Density
1
ISC
ZOUT
PSRR
30
50
275
335
±80
15
67
64
ISY
SR
tS
GBP
ØO
en
in
5
94
38
50
60
0.1
23
400
350
70
2.3
25
22
0.05
3.5
Guaranteed by design and characterization. Not production tested.
Rev. A | Page 8 of 44
V
V
V
V
mV
mV
mV
mV
mA
Ω
−40°C < TA < +85°C
−40°C < TA < +85°C
0 V < VCM < 5 V
−40°C < TA < +85°C
RL = 10 kΩ, 0.5 V < VOUT < 4.5 V
IL = 1 mA
−40°C to +85°C
IL = 10 mA
−40°C to +85°C
IL = 1 mA
−40°C to +85°C
IL = 10 mA
−40°C to +85°C
f = 10 kHz, AV = 1
V
dB
dB
µA
µA
1.8 V < VSY < 5 V
−40°C < TA < +85°C
VOUT = VSY/2
−40°C