AD5592RBRUZ-RL7

8-Channel, 12-Bit, Configurable ADC/DAC with On-Chip Reference, SPI Interface AD5592R Data Sheet FEATURES When an I/Ox pin is configured as an analog input, it is connected to a 12-bit ADC via an analog multiplexer. The input range of the ADC is 0 V to VREF or 0 V to 2 × VREF. The ADC has a total throughput rate of 400 kSPS. The I/Ox pins can also be configured as digital, general-purpose input or output (GPIO) pins. The state of the GPIO pins can be set or read back by accessing the GPIO write data register or the GPIO read configuration register, respectively, via a serial peripheral interface (SPI) write or read operation. 8-channel, configurable ADC/DAC/GPIO Configurable as any combination of 8 × 12-bit DAC channels 8 × 12-bit ADC channels 8 × general-purpose digital input/output pins Integrated temperature sensor SPI interface Available in 16-ball, 2 mm × 2 mm WLCSP 16-lead, 3 mm × 3 mm LFCSP 16-lead TSSOP The AD5592R/AD5592R-1 have an integrated 2.5 V, 25 ppm/°C reference, which is turned off by default, and an integrated temperature indicator, which gives an indication of the die temperature. The temperature value is read back as part of an ADC read sequence. APPLICATIONS Control and monitoring General-purpose analog and digital inputs/outputs The AD5592R/AD5592R-1 are available in 16-ball, 2 mm × 2 mm WLCSP, 16-lead, 3 mm × 3 mm LFCSP, and 16-lead TSSOP. The AD5592R/AD5592R-1 operate over a temperature range of −40°C to +105°C. GENERAL DESCRIPTION The AD5592R/AD5592R-1 have eight I/Ox pins (I/O0 to I/O7) that can be independently configured as digital-to-analog converter (DAC) outputs, analog-to-digital converter (ADC) inputs, digital outputs, or digital inputs. When an I/Ox pin is configured as an analog output, it is driven by a 12-bit DAC. The output range of the DAC is 0 V to VREF or 0 V to 2 × VREF. Table 1. Related Products Part No. AD5593R Description AD5592R equivalent with VLOGIC and RESET pins and an I2C interface FUNCTIONAL BLOCK DIAGRAM VDD VREF AD5592R 2.5V REFERENCE POWER-ON RESET GPIO0 SYNC INPUT REGISTER DAC REGISTER DAC 0 INPUT REGISTER DAC REGISTER DAC 7 I/O0 SCLK SDI SDO GPIO7 SPI INTERFACE LOGIC RESET I/O7 MUX SEQUENCER 12-BIT SUCCESSIVE APPROXIMATION ADC T/H 12506-001 TEMPERATURE INDICATOR GND Figure 1. AD5592R Functional Block Diagram Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2020 Analog Devices, Inc. All rights reserved. Technical Support https://www.analog.com/ AD5592R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ................................................................................ 26 Applications ...................................................................................... 1 Power-Up Time .......................................................................... 26 General Description ......................................................................... 1 Write Mode ................................................................................. 26 Functional Block Diagram .............................................................. 1 Read Mode .................................................................................. 26 Revision History ............................................................................... 2 Configuring the AD5592R/AD5592R-1 ................................. 27 Functional Block Diagram (AD5592R-1) ...................................... 3 General-Purpose Control Register .......................................... 29 Specifications .................................................................................... 4 DAC Write Operation ............................................................... 30 Timing Characteristics ................................................................ 7 DAC Readback ........................................................................... 31 Absolute Maximum Ratings ........................................................... 9 ADC Operation .......................................................................... 32 Thermal Resistance ...................................................................... 9 GPIO Operation ......................................................................... 36 ESD Caution.................................................................................. 9 Three-State Pins ......................................................................... 38 Pin Configurations and Function Descriptions ......................... 10 85 kΩ Pull-Down Resistor Pins ............................................... 38 Typical Performance Characteristics ........................................... 15 Power-Down Mode ................................................................... 39 Terminology .................................................................................... 20 Reset Function ............................................................................. 40 ADC Terminology ..................................................................... 20 Readback and LDAC Mode Register ......................................... 40 DAC Terminology ..................................................................... 21 Applications Information ............................................................. 42 Theory of Operation ...................................................................... 23 Microprocessor Interfacing ...................................................... 42 DAC Section................................................................................ 23 AD5592R/AD5592R-1 to SPI Interface .................................. 42 ADC Section................................................................................ 24 AD5592R/AD5592R-1 to SPORT Interface ........................... 42 GPIO Section .............................................................................. 25 Layout Guidelines ...................................................................... 42 Internal Reference ...................................................................... 25 Outline Dimensions ....................................................................... 43 RESET Function ......................................................................... 25 Ordering Guide .......................................................................... 44 Temperature Indicator .............................................................. 25 REVISION HISTORY 8/2020—Rev. E to Rev. F Changes to Figure 32 ..................................................................... 18 11/2018—Rev. D to Rev. E Changes to Temperature Indicator Section................................ 25 Changes to Ordering Guide .......................................................... 44 8/2017—Rev. C to Rev. D Changed VLOGIC Parameter, Table 2 ............................................... 7 Changes to Table 4 ........................................................................... 8 Changed VLOGIC Pin Description, Table 10 .................................. 13 Changed VLOGIC Pin Description, Table 11 .................................. 14 2/2017—Rev. B to Rev. C Changes to Figure 9 Caption and Table 11 Title ....................... 14 Change to D15 Bit Description, Table 22 ................................... 19 2/2016—Rev. A to Rev. B Changes to Table 2 and Table 3...................................................... 7 Added Figure 7 and Table 9; Renumbered Sequentially .......... 12 Changes to ADC Section ............................................................... 24 Added Calculating ADC Input Current Section, Table 12, and Figure 39 .......................................................................................... 24 Changes to Temperature Indicator Section ............................... 25 Changes to Table 18 ....................................................................... 28 Changes to Table 33 ....................................................................... 36 Changes to Table 39 and Table 41 ............................................... 37 Changes to Ordering Guide .......................................................... 42 10/2014—Rev. 0 to Rev. A Added 16-Lead TSSOP ......................................................Universal Changes to Gain Error; Table 2 .......................................................4 Changes to Table 6 ......................................................................... 10 Added Figure 6 and Table 8 .......................................................... 12 Added Figure 8 and Table 10........................................................ 14 Changes to Table 12 ....................................................................... 25 Added Figure 48; Outline Dimensions ....................................... 40 Changes to Ordering Guide .......................................................... 41 8/2014—Revision 0: Initial Version Rev. F | Page 2 of 44 Data Sheet AD5592R FUNCTIONAL BLOCK DIAGRAM (AD5592R-1) VLOGIC VDD VREF AD5592R-1 2.5V REFERENCE POWER-ON RESET GPIO0 SYNC INPUT REGISTER DAC REGISTER DAC 0 INPUT REGISTER DAC REGISTER DAC 7 I/O0 SCLK SDI GPIO7 SPI INTERFACE LOGIC I/O7 MUX SEQUENCER 12-BIT SUCCESSIVE APPROXIMATION ADC T/H TEMPERATURE INDICATOR GND Figure 2. AD5592R-1 Functional Block Diagram Rev. F | Page 3 of 44 12506-202 SDO AD5592R Data Sheet SPECIFICATIONS VDD = 2.7 V to 5.5 V, VREF = 2.5 V (external), RL = 2 kΩ to GND, CL = 200 pF to GND, TA = TMIN to TMAX, temperature range = −40°C to +105°C, unless otherwise noted. Table 2. Parameter ADC PERFORMANCE Resolution Input Range Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Gain Error Throughput Rate2 Track Time (tTRACK)2 Conversion Time (tCONV)2 Signal-to-Noise Ratio (SNR) Min Max Unit 1 0 VREF Bits V 0 −2 −1 2 × VREF +2 +1 ±5 0.3 400 12 500 2 69 67 61 69 67 60 −91 −89 −72 91 91 72 15 12 50 −95 45 8.2 1.6 Signal-to-Noise-and-Distortion (SINAD) Ratio Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Aperture Delay 2 Aperture Jitter2 Channel-to-Channel Isolation Input Capacitance Full Power Bandwidth DAC PERFORMANCE 3 Resolution Output Range Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift2 Gain Error Typ 12 0 0 −1 −1 −3 0.65 ±0.03 ±0.015 Capacitive Load Stability2 Resistive Load Short-Circuit Current VREF 2 × VREF +1 +1 +3 Bits V V LSB LSB mV µV/°C ±0.2 ±0.1 % FSR % FSR 2 ±0.25 ±0.1 2 10 mV % FSR 8 Zero Code Error Total Unadjusted Error V LSB LSB mV % FSR kSPS ns µs dB dB dB dB dB dB dB dB dB dB dB dB ns ns ps dB pF MHz MHz 1 25 Rev. F | Page 4 of 44 nF nF kΩ mA Test Conditions/Comments fIN = 10 kHz sine wave When using the internal ADC buffer, there is a dead band of 0 V to 5 mV VDD = 2.7 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 2.7 V, input range = 0 V to VREF VDD = 3.3 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 2.7 V, input range = 0 V to VREF VDD = 3.3 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 2.7 V, input range = 0 V to VREF VDD = 3.3 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 3 V VDD = 5 V fIN = 5 kHz At 3 dB At 0.1 dB Output range = 0 V to VREF Output range = 0 V to 2 × VREF Output range = 0 V to VREF Output range = 0 V to 2 × VREF RLOAD = ∞ RLOAD = 1 kΩ Data Sheet Parameter DC Crosstalk2 DC Output Impedance DC Power Supply Rejection Ratio (PSRR)2 AD5592R Min −4 Load Impedance at Rails 4 Load Regulation Power-Up Time AC SPECIFICATIONS Slew Rate Settling Time DAC Glitch Impulse DAC to DAC Crosstalk Digital Crosstalk Analog Crosstalk Digital Feedthrough Multiplying Bandwidth Output Voltage Noise Spectral Density Signal-to-Noise Ratio (SNR) Peak Harmonic or Spurious Noise (SFDR) Signal-to-Noise-and-Distortion (SINAD) Ratio Total Harmonic Distortion (THD) REFERENCE INPUT VREF Input Voltage DC Leakage Current Reference Input Impedance REFERENCE OUTPUT VREF Output Voltage VREF Temperature Coefficient Capacitive Load Stability Output Impedance2 0.2 0.15 Unit 1 µV Ω mV/V 25 200 Ω µV/mA 200 µV/mA 7 µs 1.25 6 2 1 0.1 1 0.1 240 200 V/µs µs nV-sec nV-sec nV-sec nV-sec nV-sec kHz nV/√Hz 81 77 74 −76 dB dB dB dB 1 −1 Max +4 2.495 Test Conditions/Comments Due to single channel, full-scale output change DAC code = midscale, VDD = 3 V ± 10% or 5 V ± 10% VDD = 5 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤ +10 mA VDD = 3 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤ +10 mA Coming out of power-down mode, VDD = 5 V Measured from 10% to 90% of full scale ¼ scale to ¾ scale settling to 1 LSB DAC code = full scale, output range = 0 V to VREF DAC code = midscale, output range = 0 V to 2 × VREF, measured at 10 kHz VDD +1 V µA kΩ kΩ 2.505 V ppm/°C μF Ω Ω µV p-p nV/√Hz µV/V µV/V RL = 2 kΩ VDD = 2.7 V VDD = 5 V 0.1 Hz to 10 Hz At ambient, f = 10 kHz, CL = 10 nF At ambient, sweeping VDD from 2.7 V to 5.5 V At ambient, sweeping VDD from 2.7 V to 3.3 V 210 120 ±5 µV/mA µV/mA mA At ambient, −5 mA ≤ load current ≤ +5 mA At ambient, −5 mA ≤ load current ≤ +5 mA VDD ≥ 3 V 1.6 mA 12 24 Output Voltage Noise Output Voltage Noise Density Line Regulation Load Regulation Sourcing Sinking Output Current Load Capability GPIO OUTPUT ISOURCE, ISINK Output Voltage High (VOH) Low (VOL) Typ 2.5 20 5 0.15 0.7 10 240 20 10 VDD − 0.2 0.4 Rev. F | Page 5 of 44 V V No I/Ox pins configured as DACs DAC output range = 0 V to 2 × VREF DAC output range = 0 V to VREF At ambient ISOURCE = 1 mA ISOURCE = 1 mA AD5592R Parameter GPIO INPUT Input Voltage High (VIH) Low (VIL) Input Capacitance Hysteresis Input Current LOGIC INPUTS AD5592R Input Voltage High (VINH) Low (VINL) AD5592R-1 Input Voltage High (VINH) Data Sheet Min Typ 0.7 × VDD 0.3 × VDD 20 0.2 ±1 0.7 × VDD 0.3 × VDD 0.7 × VLOGIC Output Low Voltage (VOL) Floating-State Output Capacitance TEMPERATURE SENSOR2 Resolution Operating Range Accuracy Track Time POWER REQUIREMENTS VDD IDD Power-Down Mode VDD = 5 V (Normal Mode) Unit 1 Test Conditions/Comments V V pF V µA V V V 0.3 × VLOGIC +1 10 Low (VINL) Input Current (IIN) Input Capacitance (CIN) LOGIC OUTPUT (SDO) Output High Voltage (VOH) AD5592R AD5592R-1 Max −1 VDD − 0.2 VLOGIC − 0.2 0.4 10 12 V µA pF Typically 10 nA, RESET = 1 µA typical V V ISOURCE = 200 µA, VDD = 2.7 V to 5. 5 V ISOURCE = 200 µA, VDD = 2.7 V to 5. 5 V V pF ISINK = 200 µA 5 20 Bits °C °C µs µs 5.5 2.7 V mA 3.5 1.6 µA mA 1 mA 2.4 mA 1.1 mA 1 mA 0.75 mA 0.5 0.5 0.5 mA mA mA −40 +105 ±3 2.7 Rev. F | Page 6 of 44 5 sample averaging ADC buffer enabled ADC buffer disabled Digital inputs = 0 V or VDD, I/O0 to I/O7 configured as DACs and ADCs, internal reference on, ADC buffer on, DAC code = 0xFFF, range is 0 V to 2 × VREF for DACs and ADCs I/O0 to I/O7 are DACs, internal reference, gain = 2 I/O0 to I/O7 are DACs, external reference, gain = 2 I/O0 to I/O7 are DACs and sampled by the ADC, internal reference, gain = 2 I/O0 to I/O7 are DACs and sampled by the ADC, external reference, gain = 2 I/O0 to I/O7 are ADCs, internal reference, gain = 2 I/O0 to I/O7 are ADCs, external reference, gain = 2 I/O0 to I/O7 are general-purpose outputs I/O0 to I/O7 are general-purpose inputs I/O0 to I/O3 are general-purpose outputs, I/O4 to I/O7 are general-purpose inputs Data Sheet AD5592R Parameter VDD = 3 V (Normal Mode) Min VLOGIC ILOGIC 1.62 Typ 1.1 Max Unit 1 mA 1 mA 1.1 mA 0.78 mA 0.75 mA 0.5 mA 0.45 0.45 mA mA V µA VDD 3 Test Conditions/Comments I/O0 to I/O7 are DACs, internal reference, gain = 1 I/O0 to I/O7 are DACs, external reference, gain = 1 I/O0 to I/O7 are DACs and sampled by the ADC, internal reference, gain = 1 I/O0 to I/O7 are DACs and sampled by the ADC, external reference, gain = 1 I/O0 to I/O7 are ADCs, internal reference, gain = 1 I/O0 to I/O7 are ADCs, external reference, gain = 1 I/O0 to I/O7 are general-purpose outputs I/O0 to I/O7 are general-purpose inputs AD5592R-1 only AD5592R-1 only All specifications expressed in decibels are referred to full-scale input (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted. Guaranteed by design and characterization; not production tested. 3 DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a code range of 8 to 4095. There is an upper dead band of 10 mV when VREF = VDD. 4 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 33). 1 2 TIMING CHARACTERISTICS Guaranteed by design and characterization, not production tested; all input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; TA = TMIN to TMAX, unless otherwise noted. Table 3. AD5592R Timing Characteristics Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 1 2.7 V ≤ VDD < 3 V 33 50 16 16 15 2 7 5 15 30 60 0 25 250 3 V ≤ VDD ≤ 5.5 V 20 50 10 10 10 2 7 5 10 30 60 0 25 250 Unit ns min ns min ns min ns min ns min µs max ns min ns min ns min ns min ns min ns min ns max ns min When reading an ADC conversion. Rev. F | Page 7 of 44 Test Conditions/Comments SCLK cycle time, write operation SCLK cycle time, read operation SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time SYNC falling edge to SCLK falling edge setup time 1 Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time for register write operations Minimum SYNC high time for register read operations SYNC rising edge to next SCLK falling edge SCLK rising edge to SDO valid RESET low pulse width (not shown in Figure 4) AD5592R Data Sheet Table 4. AD5592R-1 Timing Characteristics t5 t6 t7 t8 t9 t10 3 V ≤ VLOGIC ≤ 5.5 V 20 50 10 10 10 2 7 5 10 30 60 0 25 Unit ns min ns min ns min ns min ns min µs max ns min ns min ns min ns min ns min ns min ns max 200µA TO OUTPUT PIN Test Conditions/Comments SCLK cycle time, write operation SCLK cycle time, read operation SCLK high time SCLK low time SYNC to SCLK falling edge setup time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time for write operations Minimum SYNC high time for register read operations SYNC rising edge to next SCLK falling edge SCLK rising edge to SDO valid IOL 1.6V CL 25pF 200µA IOH Figure 3. Load Circuit for Logic Output (SDO) Timing Specifications t1 t9 SCLK t8 t2 t3 t4 t7 SYNC t6 t5 SDI DB0 DB15 t10 SDO DB15 DB0 Figure 4. Timing Diagram Rev. F | Page 8 of 44 12506-002 t2 t3 t4 1.62 V ≤ VLOGIC < 3 V 33 65 16 16 15 2 7 5 15 30 60 0 56 12506-203 Parameter t1 Data Sheet AD5592R ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter VDD to GND VLOGIC to GND Analog Input Voltage to GND AD5592R Digital Input Voltage to GND Digital Output Voltage to GND AD5592R-1 Digital Input Voltage to GND Digital Output Voltage to GND VREF to GND Operating Temperature Range Storage Temperature Range Junction Temperature (TJ max) Lead Temperature Soldering Rating −0.3 V to + 7 V −0.3 V to + 7 V −0.3 V to VDD + 0.3 V THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type 16-Ball WLCSP 16-Lead LFCSP 16-Lead TSSOP −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VLOGIC + 0.3 V −0.3 V to VLOGIC + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +105°C −65°C to +150°C 150°C JEDEC industry standard J-STD-020 ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. F | Page 9 of 44 θJA 60 137 112 Unit °C/W °C/W °C/W AD5592R Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 2 1 3 4 SCLK RESET SYNC SDI A GND I/O7 I/O0 VDD I/O6 I/O3 I/O2 I/O1 I/O4 SDO VREF I/O5 B C D 12506-003 AD5592R TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 5. AD5592R 16-Ball WLCSP Pin Configuration Table 7. AD5592R 16-Ball WLCSP Pin Function Descriptions Pin No. A1 Mnemonic SDI A2 SCLK A3 RESET A4 SYNC B1 B2 GND I/O7 B3, C4, C3, C2, D1, D4, C1 I/O0 to I/O6 B4 VDD D2 SDO D3 VREF Description Data In. Logic input. Data that is to be written to the DACs and control registers is provided on this input and is clocked into the register on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of 20 MHz when performing a conversion or clocking data from the AD5592R. Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5592R is reset to its default configuration. Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks. Ground Reference Point for All Circuitry on the AD5592R. Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place (see Table 30 and Table 31). Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or general-purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). Power Supply Input. The AD5592R operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF capacitor to GND. Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor information are provided on this output as a serial data stream. The bits are clocked out on the rising edge of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK while SYNC is low (see Figure 4). Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5592R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. Rev. F | Page 10 of 44 Data Sheet AD5592R RESET 1 16 SCLK SYNC 2 15 SDI VDD 3 14 GND I/O1 5 AD5592R I/O7 TOP VIEW (Not to Scale) 12 I/O6 13 I/O2 6 11 I/O3 7 10 I/O4 9 SDO VREF 8 I/O5 12506-303 I/O0 4 Figure 6. AD5592R 16-Lead TSSOP Pin Configuration Table 8. AD5592R 16-Lead TSSOP Pin Function Descriptions Pin No. 15 Mnemonic SDI 16 SCLK 1 RESET 2 SYNC 14 13 GND I/O7 4, 5, 6, 7, 10, 11, 12 I/O0 to I/O6 3 VDD 9 SDO 8 VREF Description Data In. Logic input. Data that is to be written to the DACs and control registers is provided on this input and is clocked into the register on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of 20 MHz when performing a conversion or clocking data from the AD5592R. Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5592R is reset to its default configuration. Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks. Ground Reference Point for All Circuitry on the AD5592R. Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place (see Table 30 and Table 31). Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or general-purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). Power Supply Input. The AD5592R operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF capacitor to GND. Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor information are provided on this output as a serial data stream. The bits are clocked out on the rising edge of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK while SYNC is low (see Figure 4). Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5592R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. Rev. F | Page 11 of 44 13 SDI 14 SCLK 16 SYNC Data Sheet 15 RESET AD5592R V DD 1 I/O1 3 12 GND AD5592R 11 I/O7 TOP VIEW (Not to Scale) 10 I/O6 9 I/O4 8 SDO 7 I/O3 5 VREF 6 I/O2 4 I/O5 12506-007 I/O0 2 Figure 7. AD5592R 16-Lead LFCSP Pin Configuration Table 9. AD5592R 16-Lead LFCSP Pin Function Descriptions Pin No. 1 Mnemonic VDD 2, 3, 4, 5, 8, 9, 10 I/O0 to I/O6 6 VREF 7 SDO 11 I/O7 12 13 GND SDI 14 SCLK 15 RESET 16 SYNC Description Power Supply Input. The AD5592R operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF capacitor to GND. Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or generalpurpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5592R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor information are provided on this output as a serial data stream. The bits are clocked out on the rising edge of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK while SYNC is low (see Figure 4). Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place (see Table 30 and Table 31). Ground Reference Point for All Circuitry on the AD5592R. Data In. Logic input. Data that is to be written to the DACs and control registers is provided on this input and is clocked into the register on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of 20 MHz when performing a conversion or clocking data from the AD5592R. Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5592R is reset to its default configuration. Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks. Rev. F | Page 12 of 44 13 SDI 14 SCLK 16 SYNC AD5592R 15 V LOGIC Data Sheet V DD 1 I/O1 3 12 GND AD5592R-1 11 I/O7 TOP VIEW (Not to Scale) 10 I/O6 9 I/O4 8 SDO 7 I/O3 5 VREF 6 I/O2 4 I/O5 12506-004 I/O0 2 Figure 8. AD5592R-1 16-Lead LFCSP Pin Configuration Table 10. AD5592R-1 16-Lead LFCSP Pin Function Descriptions Pin No. 1 Mnemonic VDD 2 to 5, 8 to 10 I/O0 to I/O6 6 VREF 7 SDO 11 I/O7 12 13 GND SDI 14 SCLK 15 16 VLOGIC SYNC Description Power Supply Input. The AD5592R-1 operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF capacitor to GND. Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or general-purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5592R-1. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor information are provided on this output as a serial data stream. The bits are clocked out on the rising edge of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK while SYNC is low (see Figure 4). Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place (see Table 30 and Table 31). Ground Reference Point for All Circuitry on the AD5592R-1. Data In. Logic input. Data to be written to the DACs and control registers is provided on this input and is clocked into the register on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of 20 MHz when performing a conversion or clocking data from the AD5592R-1. Interface Power Supply. The voltage of this pin ranges from 1.62 V to 5.5 V. Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks. Rev. F | Page 13 of 44 AD5592R Data Sheet BALL A1 INDICATOR 2 1 SDI 3 4 SCLK VLOGIC SYNC A GND I/O7 I/O0 VDD I/O6 I/O3 I/O2 I/O1 I/O4 SDO VREF I/O5 B C AD5592R-1 TOP VIEW (BALL SIDE DOWN) Not to Scale 12506-308 D Figure 9. AD5592R-1 16-Ball WLCSP Pin Configuration Table 11. AD5592R-1 16-Lead WLCSP Pin Function Descriptions Pin No. B4 Mnemonic VDD B3, C4, C3, C2, D1, D4, C1 I/O0 to I/O6 D3 VREF D2 SDO B2 I/O7 B1 A1 GND SDI A2 SCLK A3 A4 VLOGIC SYNC Description Power Supply Input. The AD5592R-1 operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF capacitor to GND. Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or general-purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5592R-1. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor information are provided on this output as a serial data stream. The bits are clocked out on the rising edge of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK while SYNC is low (see Figure 4). Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place (see Table 30 and Table 31). Ground Reference Point for All Circuitry on the AD5592R-1. Data In. Logic input. Data to be written to the DACs and control registers is provided on this input and is clocked into the register on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of 20 MHz when performing a conversion or clocking data from the AD5592R-1. Interface Power Supply. The voltage of this pin ranges from 1.62 V to 5.5 V. Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks. Rev. F | Page 14 of 44 Data Sheet AD5592R TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.5 0.4 0.8 0.3 0.2 DNL (LSB) INL (LSB) 0.6 0.4 0.2 0.1 0 –0.1 –0.2 –0.3 0 1000 2000 3000 4000 ADC CODE –0.5 12506-102 0 0 1000 Figure 10. ADC INL, VDD = 5.5 V 3000 4000 Figure 13. ADC DNL, VDD = 2.7 V 0.5 35000 0.4 30000 NUMBER OF OCCURRENCES 0.3 0.2 DNL (LSB) 2000 ADC CODE 12506-105 –0.4 –0.2 0.1 0 –0.1 –0.2 –0.3 25000 VDD = 2.7V SAMPLES = 60000 VIN = 1.5V GAIN = 1 EXTERNAL REFERENCE = 2.5V 20000 15000 10000 5000 –0.4 1000 2000 3000 4000 ADC CODE 0 2528 2530 ADC CODE Figure 11. ADC DNL, VDD = 5.5 V Figure 14. Histogram of ADC Codes, VDD = 2.7 V 0.5 35000 0.4 30000 NUMBER OF OCCURRENCES 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 VDD = 5.5V SAMPLES = 60000 VIN = 1.5V GAIN = 1 EXTERNALREFERENCE = 2.5V 25000 20000 15000 10000 5000 –0.5 0 1000 2000 3000 ADC CODE 4000 Figure 12. ADC INL, VDD = 2.7 V 0 2520 2521 2522 2523 2524 2525 ADC CODE Figure 15. Histogram of ADC Codes, VDD = 5.5 V Rev. F | Page 15 of 44 2526 12506-101 –0.4 12506-104 INL (LSB) 2529 12506-100 0 12506-103 –0.5 AD5592R Data Sheet 1 4 0 2 GLITCH (nV-sec) –1 –2 –3 –4 0 –2 –6 1k 100k 10k 1M 10M 100M FREQUENCY (Hz) –4 0 3072 4095 Figure 19. DAC Adjacent Code Glitch 1.0 2.510 0.5 2.505 VOUT (V) 0 –0.5 2.500 0 1024 2048 3072 4095 DAC CODE 2.490 –10 12506-130 –1.0 0 10 20 TIME (µs) Figure 17. DAC INL 12506-115 2.495 Figure 20. DAC Digital-to-Analog Glitch (Rising) 2.510 0.5 2.505 VOUT (V) 1.0 0 –0.5 2.500 –1.0 0 1024 2048 DAC CODE 3072 4095 12506-127 2.495 Figure 18. DAC DNL 2.490 –10 0 10 TIME (µs) Figure 21. DAC Digital-to-Analog Glitch (Falling) Rev. F | Page 16 of 44 20 12506-116 INL (LSB) 2048 DAC CODE Figure 16. ADC Multiplying Bandwidth DNL (LSB) 1024 12506-126 –5 12506-124 ADC MULTIPLYING BANDWIDTH (dB) VDD = 3V, 5V Data Sheet AD5592R 2.58 4.0 1/4 SCALE TO 3/4 SCALE 2.56 3.5 RL = 2kΩ CL = 200pF 2.54 3.0 VOUT (V) VOUT (V) 2.52 2.50 2.5 2.48 2.0 2.46 1.5 2.44 0 5 10 0 1 2 3 4 5 TIME (µs) Figure 25. DAC Settling Time, Output Range = 0 V to 2 × VREF 2.58 4.0 2.56 3.5 2.54 3.0 2.52 2.5 VOUT (V) Figure 22. DAC Settling Time (100 Code Change, Rising Edge) 2.50 2.0 2.48 1.5 2.46 1.0 2.44 0.5 2.42 –10 –5 0 5 10 TIME (µs) 0 –5 12506-120 VOUT (V) TIME (µs) 1.0 0nF LOAD 10nF LOAD 22nF LOAD 47nF LOAD 0 5 10 15 TIME (µs) Figure 23. DAC Settling Time (100 Code Change, Falling Edge) 12506-121 –5 12506-119 2.42 –10 12506-132 3/4 SCALE TO 1/4 SCALE Figure 26. DAC Settling Time for Various Capacitive Loads 2.00 0 1/4 SCALE TO 3/4 SCALE fS = 250kHz fOUT = 999.45Hz SNR = 81dB THD = –77dB SFDR = 77dB SINAD = 74dB –20 1.75 RL = 2kΩ CL = 200pF –40 VOUT (dBV) 1.25 –60 –80 1.00 –100 0.75 0.50 0 1 2 3 4 TIME (µs) 5 Figure 24. DAC Settling Time, Output Range = 0 V to VREF –140 0 5000 10000 15000 20000 FREQUENCY (Hz) Figure 27. DAC Sine Wave Output, Output Range = 0 V to 2 × VREF, Bandwidth = 0 Hz to 20 kHz Rev. F | Page 17 of 44 12506-106 –120 3/4 SCALE TO 1/4 SCALE 12506-131 VOUT (V) 1.50 AD5592R Data Sheet 2500 0 FULL SCALE 3/4 SCALE MIDSCALE 1/4 SCALE ZERO SCALE fS = 250kHz fOUT = 999.45Hz –20 SNR = 80dB THD = –67dB SFDR = 67dB SINAD = 65dB 2000 NSD (nV/√Hz) VOUT (dBV) –40 –60 –80 1500 1000 –100 500 5000 10000 15000 20000 FREQUENCY (Hz) 0 10 10k 200 6 150 5 OUTPUT VOLTAGE (V) 50 0 –50 –100 2 4 6 8 10 TIME (Seconds) 3 FULL SCALE 3/4 SCALE 2 1/2 SCALE 1 –1 –30 12506-109 0 1M 4 1/4 SCALE ZERO SCALE 0 –150 –200 100k Figure 31. DAC Output Noise Spectral Density (NSD) 100 –20 –10 0 10 20 30 LOAD CURRENT (mA) Figure 32. DAC Output Sink and Source Capability, Output Range = 0 V to VREF Figure 29. DAC 1/f Noise with External Reference 200 6 150 5 FULL SCALE OUTPUT VOLTAGE (V) 100 50 0 –50 –100 3/4 SCALE 4 3 1/2 SCALE 2 1/4 SCALE 1 ZERO SCALE –150 –200 0 2 4 6 8 TIME (Seconds) 10 –1 –30 –20 –10 0 10 20 LOAD CURRENT (mA) Figure 33. DAC Output Sink and Source Capability, Output Range = 0 V to 2 × VREF Figure 30. DAC 1/f Noise with Internal Reference Rev. F | Page 18 of 44 30 12506-134 0 12506-110 VOUT (µV p-p) 1k FREQUENCY (Hz) Figure 28. DAC Sine Wave Output, Output Range = 0 V to VREF, Bandwidth = 0 Hz to 20 kHz VOUT (µV p-p) 100 12506-133 0 12506-107 –140 12506-112 –120 Data Sheet AD5592R 20 2.5005 15 2.5003 5 VREF (V) VOUT (µV p-p) 10 0 2.5001 2.4999 –5 –10 2.4997 0 2 4 6 8 10 TIME (Seconds) Figure 34. Internal Reference 1/f Noise 1000 600 400 200 1k 10k 100k FREQUENCY (Hz) 1M 12506-113 NSD (nV/√Hz) 800 100 3.0 3.3 3.6 3.9 4.2 VDD (V) 4.5 4.8 Figure 36. Reference Line Regulation 1200 0 10 2.4995 2.7 Figure 35. Reference Noise Spectral Density (NSD) Rev. F | Page 19 of 44 5.1 5.4 12506-204 –20 12506-111 –15 AD5592R Data Sheet TERMINOLOGY ADC TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end-points of the transfer function are zero scale, a point that is 1 LSB below the first code transition, and full scale, a point that is 1 LSB above the last code transition. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the measured ratio of signal-to-noise-and-distortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input is given by SINAD (dB) = 6.02N + 1.76 Thus, for a 12-bit converter, SINAD is 74 dB. Offset Error Offset error is the deviation of the first code transition (00 … 000) to (00 … 001) from the ideal, that is, AGND + 1 LSB. Offset Error Match Offset error match is the difference in offset error between any two channels. Gain Error Gain error is the deviation of the last code transition (111 … 110) to (111 … 111) from the ideal (that is, VREF − 1 LSB) after the offset error has been adjusted out. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale, 5 kHz sine wave signal to all nonselected ADC input channels and determining how much that signal is attenuated in the selected channel. This specification is the worst case across all ADC channels for the AD5592R/AD5592R-1. Track-and-Hold Acquisition Time The track-and-hold amplifier enters hold mode on the falling edge of SYNC and returns to track mode when the conversion is complete. The track-and-hold acquisition time is the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within ±1 LSB of the applied input signal, given a step change to the input signal. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD5592R/AD5592R-1, it is defined as THD (dB ) = 20 × log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise (SFDR) Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Rev. F | Page 20 of 44 Data Sheet AD5592R DAC TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 17. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 18. Zero Code Error Zero code error is a measurement of the output error when zero code (0x000) is loaded to the DAC register. Ideally, the output is 0 V. The zero code error is always positive in the AD5592R/ AD5592R-1 because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero code error is expressed in mV. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % FSR. Offset Error Drift Offset error drift is a measurement of the change in offset error with a change in temperature. It is expressed in µV/°C. Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/°C. Offset Error Offset error is a measurement of the difference between VOUT (actual) and VOUT (ideal), expressed in mV, in the linear region of the transfer function. Offset error can be negative or positive. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for a full-scale output of the DAC. It is measured in mV/V. VREF is held at 2 V, and VDD is varied by ±10%. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Noise Spectral Density Noise spectral density is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC maintained at midscale. It is expressed in μV. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec. Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa), then executing a software LDAC (see Table 45 and Table 46), and monitoring the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change and is measured from the rising edge of SYNC. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa), using the write to and update commands while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-sec. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FF to 0x800). Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth; the multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Rev. F | Page 21 of 44 AD5592R Data Sheet Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The voltage reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows:  VREF ( MAX ) − VREF ( MIN )  6 TC =   × 10 V Temp Range ×  REF ( NOM )  where: VREF(MAX) is the maximum reference output measured over the total temperature range. VREF(MIN) is the minimum reference output measured over the total temperature range. VREF(NOM) is the nominal reference output voltage, 2.5 V. Temp Range is the specified temperature range of −40°C to +105°C. Rev. F | Page 22 of 44 Data Sheet AD5592R THEORY OF OPERATION The AD5592R/AD5592R-1 are 8-channel configurable analog and digital input/output ports. The AD5592R/AD5592R-1 have eight pins that can be independently configured as a 12-bit DAC output channel, a 12-bit ADC input channel, a digital input pin, or a digital output pin. The function of each pin is determined by programming the ADC, DAC, or GPIO configuration registers as appropriate. See the Configuring the AD5592R/AD5592R-1 section and Table 16 for more information. Resistor String The simplified segmented resistor string DAC structure is shown in Figure 38. The code loaded to the DAC register determines the switch on the string that is connected to the output buffer. Because each resistance in the string has the same value, R, the string DAC is guaranteed monotonic. R DAC SECTION The AD5592R/AD5592R-1 contain eight 12-bit DACs and implement a segmented string DAC architecture with an internal output buffer. Figure 37 shows the internal block diagram of the DAC architecture. R R TO OUTPUT BUFFER VREF REF (+) REF (–) I/Ox OUTPUT AMPLIFIER GND R 12506-011 DAC REGISTER RESISTOR STRING R The DAC channels have a shared gain bit that sets the output range as 0 V to VREF or 0 V to 2 × VREF. Because the gain bit is shared by all channels, it is not possible to set different output ranges on a per channel basis. The input coding to the DAC is straight binary. The ideal output voltage is given by  D VOUT = G × VREF ×   2N     where: D is the decimal equivalent of the binary code (0 to 4095) that is loaded to the DAC register. G = 1 for an output range of 0 V to VREF, or G = 2 for an output range of 0 V to 2 × VREF. N = 12. 12506-012 Figure 37. Internal Block Diagram of the DAC Architecture Figure 38. Simplified Resistor String Structure Output Buffer The output buffer is designed as an input/output rail-to-rail buffer. The output buffer can drive 2 nF capacitance with a 1 kΩ resistor in parallel. The slew rate is 1.25 V/µs with a ¼ to ¾ scale settling time of 6 µs. By default, the DAC outputs update directly after data has been written to the input register. The LDAC register is used to delay the updates until additional channels have been written to, if required. See the Readback and LDAC Mode Register section for more information. Rev. F | Page 23 of 44 AD5592R Data Sheet ADC SECTION Calculating ADC Input Current The 12-bit, single-supply ADC is capable of throughput rates of 400 kSPS. The ADC is preceded by a multiplexer that switches selected I/Ox pins to the ADC. A sequencer is included to automatically switch the multiplexer to the next selected channel. Channels are selected for conversion by writing to the ADC sequence register. When the write to the ADC sequence register has completed, the first channel in the conversion sequence is put into track mode. Allow each channel to track the input signal for a minimum of 500 ns. The first SYNC falling edge following the write to the ADC sequence register begins the conversion of the first channel in the sequence. The next SYNC falling edge starts a conversion on the second channel in the sequence and also begins to clock the first ADC result onto the serial interface. ADC data is clocked out of the AD5592R in a 16-bit frame. D15 is 0 to indicate that the data contains ADC data, D14 to D12 is the binary representation of the ADC address, and D11 to D0 is the ADC result (see Table 12). The current flowing into the I/Ox pins configured as ADC inputs vary with the sampling rate (fS), the voltage difference between successive channels (VDIFF), and whether buffered or unbuffered mode is used. Figure 39 shows a simplified version of the ADC input structure. When a new channel is selected for conversion, the 5.8 pF capacitor must be charged or discharged of the voltage that was on the previously selected channel. The time required by the charge or discharge depends on the voltage difference between the two channels. This affects the input impedance of the multiplexer and therefore the input current flowing into the I/Ox pins. In buffered mode, Switch S1 is open and Switch S2 is closed, in which case the U1 buffer is directly driving the 23.1 pF capacitor, and its charging time is negligible. In unbuffered mode, Switch S1 is closed and Switch S2 is closed. In unbuffered mode, the 23.1 pF capacitor must be charged from the I/Ox pins, which contributes to the input current. For applications where the ADC input current is too high, an external input buffer may be required. The choice of buffer is a function of the particular application. Each conversion takes 2 µs, and the conversion must be completed before another conversion is initiated. Only write to the AD5592R/AD5592R-1 when no conversion is taking place. I/O7 can be configured as a BUSY signal to indicate when a conversion is taking place. BUSY goes low while a conversion is in progress, and high when an ADC result is available. The ADC has an input range selection bit (Bit D5 in the generalpurpose control register), which sets the input range as 0 V to VREF or 0 V to 2 × VREF. All input channels share the same range. The output coding of the ADC is straight binary. It is possible to set each I/Ox pin as both a DAC and an ADC. When an I/Ox pin is set as both a DAC and an ADC, the primary function is that of the DAC. If the pin is selected for inclusion in an ADC conversion sequence, the voltage on the pin is converted and made available via the serial interface, allowing the DAC voltage to be monitored. Calculate the input current for buffered mode as follows: fS × C × VDIFF + 1 nA where: fS is the ADC sample rate in Hertz. C is the sampling capacitance in Farads. VDIFF is the voltage change between successive channels. 1 nA is the dc leakage current associated with buffered mode. Calculate the input current for unbuffered mode as follows: fS × C × VDIFF An example solution is as follows: for the ADC input current in buffered mode, where I/O0 = 0.5 V, I/O1 = 2 V, and fS = 10 kHz, (10,000 × 5.8 × 10−12 × 1.5) + 1 nA = 88 nA Under the same conditions, the ADC input current in unbuffered mode is as follows: (10,000 × 28.9 × 10−12 × 1.5) = 433.5 nA Table 12. ADC Conversion Format LSB D13 D12 ADC address D11 to D0 12-bit ADC data S1 I/O0 I/O7 S2 5.8pF U1 300Ω S3 23.1pF S4 CONTROL LOGIC COMPARATOR Figure 39. ADC Input Structure Rev. F | Page 24 of 44 12506-039 D14 MUX MSB D15 0 Data Sheet AD5592R GPIO SECTION RESET FUNCTION Each of the eight I/Ox pins can be configured as a generalpurpose digital input pin by programming the GPIO read configuration register or as a digital output pin by programming the GPIO write configuration register. When an I/Ox pin is configured as an output, the pin can be set high or low by programming the GPIO write data register. Logic levels for general-purpose outputs are relative to VDD and GND. When an I/Ox pin is configured as an input, its status can be determined by setting Bit D10 in the GPIO read configuration register (see Table 37). The next SPI operation clocks out the state of the GPIO pins. When an I/Ox pin is set as an output, it is possible to read its status by also setting it as an input pin. When reading the status of the I/Ox pins set as inputs, the status of an I/Ox pin set as both an input and output pin is also returned. The AD5592R/AD5592R-1 have an asynchronous RESET pin. For normal operation, RESET is tied high. A falling edge on RESET resets all registers to their default values and reconfigures the I/Ox pins to their default values (85 kΩ pull-down to GND). The reset function takes 250 µs maximum; do not write new data to the AD5592R/AD5592R-1 during this time. The AD5592R/AD5592R-1 have a software reset that performs the same function as the RESET pin. The reset function is activated by writing 0x5AC to the reset register (see Table 44). INTERNAL REFERENCE The AD5592R/AD5592R-1 contain an on-chip 2.5 V reference. The reference is powered down by default and is enabled by setting Bit D9 in the power-down register to 1 (see Table 43). When the on-chip reference is powered up, the reference voltage appears on the VREF pin and may be used as a reference source for other components. When the internal reference is used, it is recommended to decouple the internal reference to GND using a 100 nF capacitor. It is recommended that the internal reference be buffered before using it elsewhere in the system. When the reference is powered down, an external reference must be connected to the VREF pin. Suitable external reference sources for the AD5592R/AD5592R-1 include the AD780, AD1582, ADR431, REF193, and ADR391. TEMPERATURE INDICATOR The AD5592R/AD5592R-1 contain an integrated temperature indicator, which can be read to provide an estimation of the die temperature. The temperature reading can be used in fault detection where a sudden rise in die temperature may indicate a fault condition such as a shorted output. Temperature readback is enabled by setting Bit D8 in the ADC sequence register to 1 (see Table 28). The temperature result is then added to the ADC sequence. The temperature result has an address of 0b1000; take care that this result is not confused with the readback from DAC0. The temperature conversion takes 5 µs with the ADC buffer enabled and 20 µs when the buffer is disabled. Calculate the temperature by using the following formulae: For ADC gain = 1, Temperature (°C) = 25 + ( ADC Code − ( 0.5/V ) × 4095) ( 2.654 × ( 2.5/V ) ) REF REF For ADC gain = 2, Temperature (°C) = 25 + ( ADC Code − ( 0.5/( 2 × V REF ) ) × 4095) (1.327 × ( 2.5/V ) ) REF The range of codes returned by the ADC when reading from the temperature indicator is approximately 645 to 1035, corresponding to a temperature between −40°C to +105°C. The accuracy of the temperature indicator, averaged over five samples, is typically 3°C. Rev. F | Page 25 of 44 AD5592R Data Sheet SERIAL INTERFACE WRITE MODE The AD5592R/AD5592R-1 have a serial interface (SYNC, SCLK, SDI, and SDO), which is compatible with SPI standards, as well as with most DSPs. The input shift register is 16 bits wide (see Table 13). The MSB (D15) determines what type of write function is required. When D15 is 0, a write to the control register is selected. The control register address is selected by D14 to D11. D10 and D9 are reserved and are 0s. D8 to D0 set the data that is written to the selected control register. When D15 is 1, data is written to a DAC channel (assuming that channel has been set to be a DAC). D14 to D12 select which DAC is addressed. D11 to D0 is the 12-bit data loaded to the selected DAC, with D11 being the MSB of the DAC data. Table 14 shows the control register map for the AD5592R/AD5592R-1. The register map allows the operation of each of the I/Ox pins to be configured. ADCs can be selected for inclusion in sampling sequences. DACs can be updated individually or simultaneously (see the LDAC Mode Operation section). GPIO settings are also controlled via the register map. Figure 4 shows the read and write timing for the AD5592R/ AD5592R-1. A write sequence begins by bringing the SYNC line low. Data on SDI is clocked into the 16-bit shift register on the falling edge of SCLK. After the 16th falling clock edge, the last data bit is clocked in. SYNC is brought high, and the programmed function is executed (that is, a change in a DAC input register or a change in a control register). SYNC must be brought high for a minimum of 20 ns before the next write. All interface pins must be operated close to the VDD or VLOGIC rails to minimize power consumption in the digital input buffers. READ MODE The AD5592R/AD5592R-1 allow data readback from the ADCs and control registers via the serial interface. ADC conversions are automatically clocked out on the serial interface as part of a sequence or as a single ADC conversion. Reading from a register first requires a write to the readback and LDAC mode register to select the register to read back. The contents of the selected register are clocked out on the next 16 SCLKs following a falling edge of SYNC. Note that due to timing requirements of t10 (25 ns), the maximum speed of the SPI interface during a read operation must not exceed 20 MHz. POWER-UP TIME When power is applied to the AD5592R/AD5592R-1, the poweron reset block begins to configure the device and to load the registers with their default values. The configuration process takes 250 µs; do not write to any of the registers during this time. Table 13. Input Shift Register Format MSB D15 0 1 D14 D13 D12 D11 Control register address DAC address D10 0 D9 0 D8 D7 D6 D5 D4 D3 Control register data 12-bit DAC data D2 D1 LSB D0 Table 14. Control Register Map MSB (D15) 0 0 0 0 0 0 0 0 Address (D14 to D11) 0000 0001 0010 0011 0100 0101 0110 0111 Name NOP DAC readback ADC sequence register General-purpose control register ADC pin configuration DAC pin configuration Pull-down configuration Readback and LDAC mode 0 0 0 0 0 0 0 0 1 1000 1001 1010 1011 1100 1101 1110 1111 XXX 2 GPIO write configuration1 GPIO write data GPIO read configuration Power-down/reference control GPIO open-drain configuration Three-state configuration Reserved Software reset DAC write 1 2 Description No operation Selects and enables DAC readback Selects ADCs for conversion DAC and ADC control register Selects which pins are ADC inputs Selects which pins are DAC outputs Selects which pins have a 85 kΩ pull-down resistor to GND Selects the operation of the Load DAC (LDAC) function and/or which configuration register is read back Selects which pins are general-purpose outputs Writes data to the general-purpose outputs Selects which pins are general-purpose inputs Powers down DACs and enables/disables the reference Selects open-drain or push/pull for general-purpose outputs Selects which pins are three-state Reserved Resets the AD5592R/AD5592R-1 Writes to addressed DAC register This register is also used to set I/O7 as a BUSY output. D14 to D11 is the DAC register address (see Table 13). Rev. F | Page 26 of 44 Default Value 0x000 0x000 0x000 0x000 0x000 0x000 0x0FF 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x000 Data Sheet AD5592R CONFIGURING THE AD5592R/AD5592R-1 The AD5592R/AD5592R-1 I/Ox pins are configured by writing to a series of configuration registers. The control registers are accessed when the MSB of a serial write is 0, as shown in Table 13. The control register map for the AD5592R/AD5592R-1 is shown in Table 14. At power-up, the I/Ox pins are configured as 85 kΩ pull-down resistors connected to GND. The input/output channels of the AD5592R/AD5592R-1 can be configured to operate as DAC outputs, ADC inputs, digital outputs, digital inputs, three-state, or connected to GND with 85 kΩ pull-down resistors. When configured as digital outputs, the I/Ox pins have the additional option of being configured as push/pull or open-drain. The input/output channels are configured by writing to the appropriate configuration registers, as shown in Table 15 and Table 16. To assign a particular function to an input/output channel, the user writes to the appropriate register and sets the corresponding bit to 1. For example, setting Bit D0 in the DAC configuration register to 1 configures I/O0 as a DAC (see Table 20). In the event that the bit for an input/output channel is set in multiple configuration registers, the input/output channel takes the function dictated by the last write operation. The exceptions to this rule are that an I/Ox pin can be set as both a DAC and an ADC or as a digital input and output. When an I/Ox pin is configured as a DAC and ADC, its primary function is as a DAC, and the ADC can measure the voltage being provided by the DAC. This feature can monitor the output voltage to detect short circuits or overload conditions. When a pin is configured as both a general-purpose input and output, the primary function is as an output pin. This configuration allows the status of the output pin to be determined by reading the GPIO register. Figure 40 shows a typical configuration example where I/O0 and I/O1 are configured as ADCs, I/O2 and I/O3 are configured as DACs, I/O4 is a generalpurpose output pin, I/O5 is a general-purpose input pin, and I/O6 and I/O7 are three-state. The general-purpose control register also contains other functions associated with the DAC and ADC, such as the lock configuration bit. When the lock configuration bit is set to 1, any writes to the pin configuration registers are ignored, thus preventing the function of the I/Ox pins from being changed. The I/Ox pins can be reconfigured at any time when the AD5592R/ AD5592R-1 is in an idle state, that is, no ADC conversions are taking place and no registers are being read back. The lock configuration bit must also be 0. Table 15. I/Ox Pin Configuration Registers MSB D15 0 D14 D13 D12 Register address D11 D10 D9 D8 Reserved D7 IO7 D6 IO6 D5 IO5 D4 IO4 Table 16. Bit Descriptions for the I/Ox Pin Configuration Registers Bit(s) D15 D14 to D11 Bit Name MSB Register address D10 to D8 D7 to D0 Reserved IO7 to IO0 Description Set this bit to 0. Selects which pin configuration register is addressed. 0100: ADC pin configuration. 0101: DAC pin configuration. 0110: pull-down configuration. (Default condition at power-up.) 1000: GPIO write configuration. 1010: GPIO read configuration. 1100: GPIO open-drain configuration. 1101: three-state configuration. Reserved. Set these bits to 0. Enable register function on selected I/Ox pin. 0: no function selected. 1: set the selected I/Ox pin to the register function. Rev. F | Page 27 of 44 D3 IO3 D2 IO2 D1 IO1 LSB D0 IO0 AD5592R Data Sheet SYNC CONFIGURE I/O0 AND I/O1 AS ADCS CONFIGURE I/O2 AND I/O3 AS DACS SDI 0b0010 0000 0000 00 11 0b0010 1000 0000 1100 SDI SYNC SDI CONFIGURE I/O4 AS GPO CONFIGURE I/O5 AS GPI 0b0100 0000 0001 0000 0b0101 0100 0010 0000 CONFIGURE I/O6 AND I/O7 AS THREE-STATE PINS 0b0110 1000 1100 0000 Figure 40. Typical Configuration Example Rev. F | Page 28 of 44 12506-205 SYNC Data Sheet AD5592R The general-purpose control register also enables/disables the ADC buffer and precharge function (see the ADC Section for more details). The register can also be used to lock the I/Ox pin configuration to prevent accidental change. When Bit D7 is set to 1, writes to the configuration registers are ignored. GENERAL-PURPOSE CONTROL REGISTER The general-purpose control register enables or disables certain functions associated with the DAC, ADC, and I/Ox pin configuration (see Table 17 and Table 18). The general-purpose control register sets the gain of the DAC and ADC. Bit D5 sets the input range for the ADC, and Bit D4 sets the output range of the DAC. Table 17. General-Purpose Control Register MSB D15 0 D14 D13 D12 D11 Register address D10 Reserved D9 ADC buffer precharge D8 ADC buffer enable D7 Lock D6 All DACs D5 ADC range D4 DAC range D3 LSB D2 D1 D0 Reserved Table 18. Bit Descriptions for the General-Purpose Control Register Bit(s) D15 D14 to D11 D10 D9 Bit Name MSB Register address Reserved ADC buffer precharge D8 ADC buffer enable D7 Lock D6 All DACs D5 ADC range D4 DAC range D3 to D0 Reserved Description Set this bit to 0. Set these bits to 0b0011. Reserved. Set this bit to 0. ADC buffer precharge. 0: ADC buffer is not used to precharge the ADC. If the ADC buffer is enabled, it is always powered up (default). 1: ADC buffer is used to precharge the ADC. If the ADC buffer is enabled, it is powered up while the conversion takes place and then powered down until the next conversion takes place. ADC buffer enable. 0: ADC buffer is disabled (default). 1: ADC buffer is enabled. Lock configuration. 0: the contents of the I/Ox pin configuration registers can be changed (default). 1: the contents of the I/Ox pin configuration registers cannot be changed. Write all DACs. 0: for future DAC writes, the DAC address bits determine which DAC is written to (default). 1: for future DAC writes, the DAC address bits are ignored, and all channels configured as DACs are updated with the same data. ADC input range select. 0: ADC gain is 0 V to VREF (default). 1: ADC gain is 0 V to 2 × VREF. DAC output range select. 0: DAC output range is 0 V to VREF (default). 1: DAC output range is 0 V to 2 × VREF. Reserved. Set these bits to 0. Rev. F | Page 29 of 44 AD5592R Data Sheet DAC WRITE OPERATION LDAC Mode Operation To set a pin as a DAC, set the appropriate bit in the DAC pin configuration register to 1 (see Table 19 and Table 20). For example, setting Bit 0 to Bit 1 enables I/O0 as a DAC output. Data is written to a DAC when the MSB (D15) of the serial write is 1. D14, D13, and D12 determine which DAC is addressed, and D11 to D0 contain the 12-bit data to be written to the DAC, as shown in Table 21 and Table 22. Data is written to the selected DAC input register. Data written to the input register can be automatically copied to the DAC register, if required. Data is transferred to the DAC register based on the setting of the LDAC mode register (see Table 45 and Table 46). When the LDAC mode bits (D1 and D0) are 00 respectively, new data is automatically transferred from the input register to the DAC register, and the analog output updates. When the LDAC mode bits are 01, data remains in the input register. This LDAC mode allows writes to input registers without affecting the analog outputs. When the input registers have been loaded with the desired values, setting the LDAC mode bits to 10 transfers the values in the input registers to the DAC registers, and the analog outputs update simultaneously. The LDAC mode bits then revert back to 01, assuming their previous setting was 01. See Table 45 and Table 46. Table 19. DAC Pin Configuration Register MSB D15 0 D14 D13 D12 D11 Register address D10 D9 D8 Reserved D7 DAC7 D6 DAC6 D5 DAC5 D4 DAC4 D3 DAC3 D2 DAC2 D1 DAC1 LSB D0 DAC0 Table 20. Bit Descriptions for the DAC Pin Configuration Register Bit(s) D15 D14 to D11 D10 to D8 D7 to D0 Bit Name MSB Register address Reserved DAC7 to DAC0 Description Set this bit to 0. Set these bits to 0b0101. Reserved. Set these bits to 0. Select I/Ox pins as DAC outputs. 1: I/Ox is a DAC output. 0: I/Ox function is determined by the pin configuration registers (default). Table 21. DAC Write Register MSB D15 1 D14 D13 D12 DAC address D11 (MSB) D10 D9 D8 D7 D6 D5 12-bit DAC data D4 D3 D2 D1 Table 22. Bit Descriptions for the DAC Data Register Bit(s) D15 D14 to D12 Bit Name MSB DAC address D11 to D0 12-bit DAC data Description Set this bit to 1. Bit D14 to Bit D12 select the DAC register to which the data in D11 to D0 is loaded. 000: DAC0 001: DAC1 010: DAC2 011: DAC3 100: DAC4 101: DAC5 110: DAC6 111: DAC7 12-bit DAC data. Rev. F | Page 30 of 44 LSB D0 Data Sheet AD5592R DAC READBACK The input register of each DAC can be read back via the SPI interface. Reading back the DAC register value can be used to confirm that the data was received correctly before writing to the LDAC register, or to check what value was last loaded to a DAC. Data can only be read back from a DAC when there is no ADC conversion sequence taking place. To read back a DAC input register, it is first necessary to enable the readback function and select which DAC register is required. This is achieved by writing to the DAC read back register (shown in Table 23 and Table 24). Set the D4 and D3 bits to 1 to enable the readback function. The D2 to D0 bits select which DAC data is required. The DAC data is clocked out of the AD5592R/ AD5592R-1 on the subsequent SPI operation. Figure 41 shows an example of setting I/O3, configured as a DAC, to midscale. The input data is then read back. D14 to D12 contain the address of the DAC register being read back, and D15 is 1. Table 23. DAC Readback Register MSB D15 0 D14 D13 D12 D11 Register address D10 D9 D8 D7 Reserved D6 D5 D4 D3 Enable DAC readback Table 24. Bit Descriptions for the DAC Readback Register Bit(s) D15 D14 to D11 D10 to D5 D4 and D3 Bit Name MSB Register address Reserved Enable DAC readback D2 to D0 DAC channel SDI SYNC SDI SET I/O3 (DAC) TO MIDSCALE 0b1011 1000 0000 0000 SELECT I/O3 (DAC) FOR READBACK 0b0000 1000 0001 10 11 NOP 0b0000 0000 0000 0000 I/O3 (DAC) DATA D15 = 1 D14 TO D12 = DAC ADDRESS D11 TO D0 = DAC DATA Figure 41. DAC Readback Operation Rev. F | Page 31 of 44 12506-206 SYNC Description Set this bit to 0. Set these bits to 0b0001. Reserved. Set these bits to 0. Enable readback of the DAC input register. 11: readback enabled. 00: readback disabled (default). Select DAC channel. 000: DAC0 001: DAC1 … 110: DAC6 111: DAC7 LSB D2 D1 D0 DAC channel AD5592R Data Sheet ADC OPERATION To set a pin as an ADC, set the appropriate bit in the ADC pin configuration register to 1 (see Table 25 and Table 26). For example, setting Bit 0 to Bit 1 enables I/O0 as an ADC input. The ADC channels of the AD5592R/AD5592R-1 operate as a traditional multichannel ADC, where each serial transfer selects the next channel for conversion. Writing to the ADC sequence register (see Table 27 and Table 28) selects the ADC channels to be included in the sequence, and the REP bit determines if the sequence is repeated. The SYNC signal is used to frame the write to the converter on the SDI pin. The data that appears on the SDO pin during the initial write to the ADC sequence register is invalid. When the sequence register is written to, the ADC begins to track the first channel in the sequence. Tracking takes 500 ns; do not initiate a conversion until this time has passed. The next SYNC falling edge initiates a conversion on the selected channel. The subsequent SYNC falling edge begins clocking out the ADC result and also initiates the next conversion. The ADC operates with one cycle latency, thus the conversion result corresponding to each conversion is available one serial read cycle after the cycle in which the conversion was initiated. If more than one channel is selected in the ADC sequence register, the ADC converts all selected channels sequentially in ascending order on successive SYNC falling edges. Once all the selected channels in the control register are converted, the ADC repeats the sequence if the REP bit is set. If the REP bit is clear, the ADC goes three-state. Figure 42 to Figure 45 show typical ADC modes of operation. I/O7 can be configured as a BUSY output pin to indicate when a conversion result is available. BUSY goes low while a conversion takes place and goes high when the conversion result is available. The conversion result is clocked out on the SDO pin on the following read/write operation. For an ADC conversion, D15 is 0, D14 to D12 contain the ADC address, and D11 to D0 contain the 12-bit conversion result, as shown in Table 29. Changing an ADC Sequence The channels included in an ADC sequence can be changed by first stopping an existing conversion sequence (see Figure 46). The ADC conversion sequence is stopped by clearing the REP, TEMP, and ADC7 to ADC0 bits in the ADC sequence register to 0. As the command to stop the sequence is written, an ADC conversion is also taking place. This conversion must finish before a new sequence can be written to the ADC sequence register. Allow a minimum of 2 µs between starting the write to end the current sequence and starting the write to select a new sequence. After selecting the new sequence, allow an ADC track time of 500 ns before initiating the next conversion. Table 25. ADC Pin Configuration Register MSB D15 0 D14 D13 D12 D11 Register address D10 D9 D8 Reserved D7 ADC7 D6 ADC6 D5 ADC5 D4 ADC4 D3 ADC3 Table 26. Bit Descriptions for the ADC Pin Configuration Register Bit(s) D15 D14 to D11 D10 to D8 D7 to D0 Bit Name MSB Register address Reserved ADC7 to ADC0 Description Set this bit to 0. Set these bits to 0b0100. Reserved. Set these bits to 0. Select I/Ox pins as ADC inputs. 1: I/Ox is an ADC input. 0: I/Ox function is determined by the pin configuration registers (default). Rev. F | Page 32 of 44 D2 ADC2 D1 ADC1 LSB D0 ADC0 Data Sheet AD5592R Table 27. ADC Sequence Register MSB D15 0 D14 D13 D12 D11 Register address D10 Reserved D9 REP D8 TEMP D7 ADC7 D6 ADC6 D5 ADC5 D4 ADC4 D3 ADC3 D2 ADC2 D1 ADC1 LSB D0 ADC0 D1 LSB D0 Table 28. Bit Descriptions for the ADC Sequence Register Bit(s) D15 D14 to D11 D10 D9 Bit Name MSB Register address Reserved REP D8 TEMP D7 to D0 ADC7 to ADC0 Description Set this bit to 0. Set these bits to 0b0010. Reserved. Set these bits to 0. ADC sequence repetition. 0: sequence repetition disabled (default). 1: sequence repetition enabled. Include temperature indicator in ADC sequence. 0: disable temperature indicator readback (default). 1: enable temperature indicator readback. Include ADC channels in conversion sequence. 0: the selected ADC channel is not included in the conversion sequence. 1: include the selected ADC channel in the conversion sequence. Table 29. ADC Conversion Result MSB D15 0 1 D14 D13 D12 ADC address1 D11 D10 D9 D8 D7 D6 D5 D4 12-bit ADC result D3 D2 The ADC addresses are as follows: 000 = ADC0 … 111 = ADC7. CONVERSION STARTS ON CHANNEL 1 SYNC 1 12 16 1 16 1 16 1 16 SCLK DATA WRITTEN TO SEQUENCE REGISTER CHANNEL 1 SELECTED NOP, DAC, OR CONTROL REGISTER WRITE INVALID DATA SDO NOP, DAC, OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE 12506-207 SDI CONVERSION RESULT FOR CHANNEL 1 INVALID DATA Figure 42. Single-Channel ADC Conversion Sequence, No Repeat NEW CONVERSION STARTS ON CHANNEL 1 CONVERSION STARTS ON CHANNEL 1 SYNC 1 12 16 1 16 1 16 1 16 SCLK SDO DATA WRITTEN TO SEQUENCE REGISTER CHANNEL 1 SELECTED INVALID DATA NOP, DAC, OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE CONVERSION RESULT FOR CHANNEL 1 INVALID DATA Figure 43. Single-Channel, Repeating, ADC Conversion Sequence Rev. F | Page 33 of 44 NOP, DAC, OR CONTROL REGISTER WRITE NEW CONVERSION RESULT FOR CHANNEL 1 12506-208 SDI AD5592R Data Sheet CONVERSION STARTS ON CHANNEL 2 CONVERSION STARTS ON CHANNEL 1 SYNC 1 16 1 16 12 16 1 SCLK SDI WRITE TO SEQUENCE REGISTER CH 1 AND CH 2 SELECTED NOP, DAC, OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE INVALID DATA INVALID DATA CONVERSION RESULT FOR CHANNEL 1 SDO SYNC 1 16 1 16 SCLK NOP, DAC, OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE 12506-209 SDI CONVERSION RESULT FOR CHANNEL 2 SDO Figure 44. Multichannel ADC Conversion Sequence, No Repeat CONVERSION STARTS ON CHANNEL 1 CONVERSION STARTS ON CHANNEL 2 SYNC 1 12 16 1 16 1 16 SCLK SDI WRITE TO SEQUENCE REGISTER CH 1 AND CH 2 SELECTED NOP, DAC, OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE INVALID DATA INVALID DATA CONVERSION RESULT FOR CHANNEL 1 SDO NEW CONVERSION STARTS ON CHANNEL 1 SYNC 1 16 1 16 SDI SDO NOP, DAC, OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE CONVERSION RESULT FOR CHANNEL 2 NEW CONVERSION RESULT FOR CHANNEL 1 Figure 45. Multichannel, Repeating, ADC Conversion Sequence Rev. F | Page 34 of 44 12506-210 SCLK Data Sheet AD5592R CONVERSION STARTS ON CHANNE L 2 CONVERSION STARTS ON CHANNE L 1 SYNC 1 12 16 1 16 1 16 SCLK SDI WRITE TO SEQUENCE REGISTER CH 1 AND CH 2 SELECTED NOP, DAC, OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE INVALID DATA INVALID DATA CONVERSION RESULT FOR CHANNEL 1 SDO CONVERSION STARTS ON CHANNEL 1 CONVERSION STARTS ON CHANNEL 2 CONVERSION STARTS ON CHANNEL 1 SYNC 1 12 16 1 16 1 16 SCLK SDI SDO NOP, DAC, OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE WRITE TO SEQUENCE REGISTER TO END SEQUENCE CONVERSION RESULT FOR CHANNEL 2 CONVERSION RESULT FOR CHANNEL 1 CONVERSION RESULT FOR CHANNEL 2 CONVERSION STARTS ON CHANNEL 4 CONVERSION STARTS ON CHANNEL 5 SYNC 1 12 16 1 16 1 16 SCLK WRITE TO SEQUENCE REGISTER CH 4 AND CH 5 SELECTED SDI SDO INVALID DATA CONVERSION STARTS ON CHANNEL 4 NOP, DAC OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE INVALID DATA CONVERSION RESULT FOR CHANNEL 4 CONVERSION STARTS ON CHANNEL 5 SYNC 1 16 1 16 1 16 SDI SDO NOP, DAC, OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE NOP, DAC, OR CONTROL REGISTER WRITE CONVERSION RESULT FOR CHANNEL 5 CONVERSION RESULT FOR CHANNEL 4 CONVERSION RESULT FOR CHANNEL 5 12506-211 SCLK Figure 46. Changing a Multichannel, Repeating, ADC Conversion Sequence SYNC SDI SET I/O4 TO I/O7 AS INPUTS 0b0101 0000 1111 0000 SELECT THE GPIO INPUT REGISTER FOR READBACK 0b0101 0100 1111 0000 0b0101 0100 0011 0000 I/O7 to I/O4 PINS STATES SDO DAC WRITE SET I/O3 TO MIDSCALE SDI 0b1011 1000 0000 0000 SDO I/O5 AND I/04 PINS STATES 12506-212 SYNC SELECT THE GPIO INPUT REGISTER FOR READBACK Figure 47. Configuring and Reading General-Purpose Input Pins Rev. F | Page 35 of 44 AD5592R Data Sheet the open-drain configuration allows for one pin to pull down the others pins. This method is commonly used where multiple pins are used to trigger an alarm or an interrupt pin. GPIO OPERATION Each of the I/Ox pins of the AD5592R/AD5592R-1 can operate as a general-purpose, digital input or output pin. The function of the pins is determined by writing to the appropriate bit in the GPIO read configuration and GPIO write configuration registers. To change the state of the I/Ox pins, a write to the GPIO write data register is required. Setting a bit to 1 gives a Logic 1 on the selected output. Clearing a bit to 0 gives a Logic 0 on the selected output. Setting Pins as Outputs Setting Pins as Inputs To set a pin as a general-purpose output, set the appropriate bit in the GPIO write configuration register to 1 (see Table 30 and Table 31). For example, setting Bit 0 to Bit 1 enables I/O0 as a general-purpose output. The state of the output pin is controlled by setting or clearing the bits in the GPIO write data register (see Table 34). A data bit is ignored if it is written to a location that is not configured as an output. To set a pin as a general-purpose input, set the appropriate bit in the GPIO read configuration register to 1 (see Table 36 and Table 37). For example, setting Bit 0 to Bit 1 enables I/O0 as a general-purpose input. To read the state of the general-purpose inputs, write to the GPIO read and configuration register to set Bit D10 to 1 and also any of Bit D7 to Bit D0 that correspond to a general-purpose input pin. The following SPI operation clocks out the state of any pins set as general-purpose inputs. Figure 47 shows an example where I/O4 to I/O7 are set as generalpurpose inputs. I/O3 is assumed to be a DAC. To read the status of I/O7 to I/O4, Bit D10 and Bit D7 to Bit D4 are set to 1. To read the status of I/O5 and I/O4, only Bit D10, Bit D5, and Bit D4 need to be set to 1. The status of I/O7 and I/O6 are not read, and Bit D7 and Bit D6 are read as 0. Figure 47 also has a write to a DAC to show that other operations can be included when reading the status of the general-purpose pins. The outputs can be independently configured as push/pull or open-drain outputs. When in a push/pull configuration, the output is driven to VDD or GND, as determined by the data in the GPIO write data register. To set a pin as an open-drain output, set the appropriate bit in the GPIO open-drain configuration register to 1 (see Table 32 and Table 33). When in an open-drain configuration, the output is driven to GND when a data bit in the GPIO write data register sets the pin low. When the pin is set high, the output is not driven and must be pulled high by an external resistor. Open-drain configuration allows for multiple output pins to be tied together. If all the pins are normally high, Table 30. GPIO Write Configuration Register MSB D15 0 D14 D13 D12 D11 Register address D10 D9 Reserved D8 Enable BUSY D7 GPIO7 D6 GPIO6 D5 GPIO5 D4 GPIO4 D3 GPIO3 D2 GPIO2 D1 GPIO1 Table 31. Bit Descriptions for the GPIO Write Configuration Register Bit(s) D15 D14 to D11 D10 to D9 D8 Bit Name MSB Register address Reserved Enable BUSY Description Set this bit to 0. Set these bits to 0b1000. Reserved. Set this bit to 0. Enable the I/O7 pin as BUSY. 0: Pin I/O7 is not configured as BUSY. 1: Pin I/O7 is configured as BUSY. D7 must also be set to 1 to enable the I/O7 pin as an output. D7 to D0 GPIO7 to GPIO0 Select I/Ox pins as GPIO outputs. 1: I/Ox is a general-purpose output pin. 0: I/Ox function is determined by the pin configuration registers (default). Rev. F | Page 36 of 44 LSB D0 GPIO0 Data Sheet AD5592R Table 32.GPIO Open-Drain Configuration Register MSB D15 0 D14 D13 D12 D11 Register address D10 D9 D8 Reserved D7 Open Drain 7 D6 Open Drain 6 D5 Open Drain 5 D4 Open Drain 4 D3 Open Drain 3 D2 Open Drain 2 D1 Open Drain 1 LSB D0 Open Drain 0 Table 33. Bit Descriptions for the GPIO Open-Drain Configuration Register Bit(s) D15 D14 to D11 D10 to D8 D7 to D0 Bit Name MSB Register address Reserved Open Drain 7 to Open Drain 0 Description Set this bit to 0. Set these bits to 0b1100. Reserved. Set these bits to 0. Set output pins as open-drain. The pins must also be set as digital output pins. See Table 31. 1: I/Ox is an open-drain output pin. 0: I/Ox is a push/pull output pin (default). Table 34. GPIO Write Data Register MSB D15 0 D14 D13 D12 D11 Register address D10 D9 D8 Reserved D7 GPIO7 D6 GPIO6 D5 GPIO5 D4 GPIO4 D3 GPIO3 D2 GPIO2 D1 GPIO1 LSB D0 GPIO0 Table 35. Bit Descriptions for the GPIO Write Data Register Bit(s) D15 D14 to D11 D10 to D8 D7 to D0 Bit Name MSB Register address Reserved GPIO7 to GPIO0 Description Set this bit to 0. Set these bits to 0b1001. Reserved. Set these bits to 0. Set state of output pins. 1: I/Ox is a Logic 1. 0: I/Ox is a Logic 0. Table 36. GPIO Read Configuration Register MSB D15 0 D14 D13 D12 D11 Register address D10 Enable readback D9 D8 Reserved D7 GPIO7 D6 GPIO6 D5 GPIO5 D4 GPIO4 D3 GPIO3 Table 37. Bit Descriptions for the GPIO Read Configuration Register Bit(s) D15 D14 to D11 D10 Bit Name MSB Register address Enable readback D9 to D8 D7 to D0 Reserved GPIO7 to GPIO0 Description Set this bit to 0. Set these bits to 0b1010. Enable GPIO readback. 1: the next SPI operation clocks out the state of the GPIO pins. 0: Bit D7 to Bit D0 determine which pins are set as general-purpose inputs. Reserved. Set these bits to 0. Set I/Ox pins as GPIO inputs. 1: I/Ox is a general-purpose input pin. 0: I/Ox function is determined by the pin configuration registers (default). Rev. F | Page 37 of 44 D2 GPIO2 D1 GPIO1 LSB D0 GPIO0 AD5592R Data Sheet THREE-STATE PINS 85 kΩ PULL-DOWN RESISTOR PINS The I/Ox pins can be set to three-state by writing to the threestate configuration register, as shown in Table 38 and Table 39. The I/Ox pins can be connected to GND via a pull-down resistor (85 kΩ) by setting the appropriate bits in the pull-down configuration register, as shown in Table 40 and Table 41. Table 38. Three-State Configuration Register MSB D15 0 D14 D13 D12 D11 Register address D10 D9 D8 Reserved D7 TSO7 D6 TSO6 D5 TSO5 D4 TSO4 D3 TSO3 D2 TSO2 D1 TSO1 LSB D0 TSO Table 39. Bit Descriptions for the Three-State Configuration Register Bit(s) D15 D14 to D11 D10 to D8 D7 to D0 Bit Name MSB Register address Reserved TSO7 to TSO0 Description Set this bit to 0. Set these bits to 0b1101. Reserved. Set these bits to 0. Set I/Ox pins as three-state outputs. 1: I/Ox is a three-state output pin. 0: I/Ox function is determined by the pin configuration registers (default). Table 40. Pull-Down Configuration Register MSB D15 0 D14 D13 D12 D11 Register address D10 D9 D8 Reserved D7 Pull Down 7 D6 Pull Down 6 D5 Pull Down 5 D4 Pull Down 4 D3 Pull Down 3 D2 Pull Down 2 D1 Pull Down 1 Table 41. Bit Descriptions for the Pull-Down Configuration Register Bit(s) D15 D14 to D11 D10 to D8 D7 to D0 Bit Name MSB Register address Reserved Pull Down 7 to Pull Down 0 Description Set this bit to 0. Set these bits to 0b0110. Reserved. Set these bits to 0. Set I/Ox pins as weak pull-down outputs. 1: I/Ox is connected to GND via an 85 kΩ pull-down resistor. 0: I/Ox function is determined by the pin configuration registers (default). Rev. F | Page 38 of 44 LSB D0 Pull Down 0 Data Sheet AD5592R its buffer are powered down by default and are enabled by setting the EN_REF bit in the power-down register. The internal reference voltage then appears at the VREF pin. POWER-DOWN MODE The AD5592R/AD5592R-1 have a power configuration register to reduce the power consumption when certain functions are not needed. The power-down register allows any channels set as DACs to be individually placed in a power-down state. When in a power-down state, the DAC outputs are three-state. When a DAC channel is put back into normal mode, the DAC output returns to its previous value. The internal reference and There is no dedicated power-down function for the ADC, but the ADC is automatically powered down if none of the I/Ox pins are selected as ADCs. The PD_ALL bit powers down all the DACs, the reference and its buffer, and the ADC simultaneously. Table 42 and Table 43 show the power-down register. Table 42. Power-Down/Reference Control Register MSB D15 0 D14 D13 D12 D11 Register address D10 PD_ALL D9 EN_REF D8 Reserved D7 PD7 D6 PD6 D5 PD5 D4 PD4 D3 PD3 D2 PD2 D1 PD1 LSB D0 PD0 Table 43. Bit Descriptions for the Power-Down/Reference Control Register Bit(s) D15 D14 to D11 D10 Bit Name MSB Register address PD_ALL D9 EN_REF D8 D7 to D0 Reserved PD7 to PD0 Description Set this bit to 0. Set these bits to 0b1011. Power down DACs and internal reference. 0: the reference and DACs power-down states are determined by D9 and D7 to D0 (default). 1: the reference, DACs and ADC are powered down. Enable internal reference. 0: the reference and its buffer are powered down (default). Set this bit if an external reference is used. 1: the reference and its buffer are powered up. The reference is available on the VREF pin. Reserved. Set this bit to 0. Power down DACs. 0: the channel is in normal operating mode (default). 1: the channel is powered down if it is configured as a DAC. Rev. F | Page 39 of 44 AD5592R Data Sheet RESET FUNCTION READBACK AND LDAC MODE REGISTER The AD5592R/AD5592R-1 can be reset to their default conditions by writing to the reset register, as shown in Table 44. This write resets all registers to their default values and reconfigures the I/Ox pins to their default values (85 kΩ pull-down resistor to GND). The reset function takes 250 µs maximum; do not write new data to the AD5592R/AD5592R-1 during this time. The AD5592R has a RESET pin that performs the same function. For normal operation, RESET is tied high. A falling edge on RESET triggers the reset function. The values contained in the AD5592R/AD5592R-1 registers can be read back to ensure that the registers are correctly set up. The register readback is initiated by writing to the readback and LDAC mode register with Bit D6 set to 1. Bit D5 to Bit D2 select which register is to be read back. The register data is clocked out of the AD5592R/AD5592R-1 on the next SPI transfer. Bit D1 to Bit D0 of the readback and LDAC mode register select the LDAC mode. The LDAC mode determines if data written to a DAC input register is also transferred to the DAC register. See the LDAC Mode Operation section for details of the LDAC mode function. Table 44. Software Reset MSB D15 0 Control register write D14 1 D13 D12 D11 1 1 1 Write to reset register D10 1 D9 0 D8 1 D7 D6 D5 D4 D3 1 0 1 0 1 Reset the AD5592R/AD5592R-1 D2 1 D1 0 LSB D0 0 Table 45. Readback and LDAC Mode Register MSB D15 0 D14 D13 D12 D11 Register address D10 D9 D8 Reserved D7 Rev. F | Page 40 of 44 D6 EN D5 D4 D3 D2 REG_READBACK LSB D1 D0 LDAC mode Data Sheet AD5592R Table 46. Bit Descriptions for the Readback and LDAC Mode Register Bit(s) D15 D14 to D11 D10 to D7 D6 Bit Name MSB Register address Reserved EN D5 to D2 REG_READBACK D1 to D0 LDAC mode Description Set this bit to 0. Set these bits to 0b0111. Reserved. Set these bits to 0. Enable readback. Note that the LDAC mode bits are always used regardless of the EN bit. 1: Bit D5 to Bit D2 select which register is read back. Bit D6 automatically clears when the read is complete. 0: no readback is initiated. If Bit D6 is 1, Bits D5 to Bit D2 determine which register is to be read back. 0000: NOP. 0001: DAC readback. 0010: ADC sequence. 0011: general-purpose configuration. 0100: ADC pin configuration. 0101: DAC pin configuration. 0110: pull-down configuration. 0111: LDAC configuration. 1000: GPIO write configuration. 1001: GPIO write data. 1010: GPIO read configuration. 1011: power-down and reference control. 1100: open-drain configuration. 1101: three-state pin configuration. 1110: reserved. 1111: software reset. Determines how data written to an input register of a DAC is handled. 00: data written to an input register is immediately copied to a DAC register, and the DAC output updates (default). 01: data written to an input register is not copied to a DAC register. The DAC output is not updated. 10: data in the input registers is copied to the corresponding DAC registers. When the data has been transferred, the DAC outputs are updated simultaneously. 11: reserved. Rev. F | Page 41 of 44 AD5592R Data Sheet AD5592R/AD5592R-1 TO SPORT INTERFACE APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5592R/AD5592R-1 is via a serial bus that uses a standard protocol compatible with DSPs and microcontrollers. The communications channel requires a 4-wire interface consisting of a clock signal, a data input signal, a data output signal, and a synchronization signal. The devices require a 16-bit data-word with data valid on the falling edge of SCLK. The Analog Devices ADSP-BF527 has two serial ports (SPORT). Figure 49 shows how a SPORT interface can be used to control the AD5592R/AD5592R-1. The ADSP-BF527 has an SPI port that can also be used. This method is the same as when using the ADSP-BF531. AD5592R/ AD5592R-1 AD5592R/AD5592R-1 TO SPI INTERFACE ADSP-BF527 The SPI interface of the AD5592R/AD5592R-1 is designed to be easily connected to industry-standard DSPs and microcontrollers. Figure 48 shows the AD5592R/AD5592R-1 connected to the Analog Devices, Inc., ADSP-BF531 Blackfin® DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5592R/AD5592R-1. Figure 48. ADSP-BF531 SPI Interface 12506-164 SYNC SCLK SDI SD0 RESET SPORT_TSCK SCLK SPORT_DR SDO SPORT_DT SDI GPIO1 RESET 12506-165 SPORT_RSCK LAYOUT GUIDELINES ADSP-BF531 PF8 SYNC Figure 49. ADSP-BF527 SPORT Interface AD5592R/ AD5592R-1 SPISELx SCK MOSI MISO SPORT_TFS SPORT_RFS In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board (PCB) on which the AD5592R or the AD5592R-1 is mounted must be designed so that the AD5592R/AD5592R-1 lie on the analog plane. The AD5592R/AD5592R-1 must have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI). Ceramic capacitors, for example, provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. F | Page 42 of 44 Data Sheet AD5592R OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 SEATING PLANE COPLANARITY 0.10 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 50. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.30 0.25 0.20 0.50 BSC 16 13 12 1 4 9 TOP VIEW 0.80 0.75 0.70 PKG-004132 SEATING PLANE 0.50 0.40 0.30 8 5 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.152 REF COMPLIANT TO JEDEC STANDARDS MO-220-WEED. Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-32) Dimensions shown in millimeters Rev. F | Page 43 of 44 09-03-2013-A PIN 1 INDICATOR 3.10 3.00 SQ 2.90 AD5592R Data Sheet 2.000 1.960 SQ 1.920 4 3 2 1 A BALL A1 IDENTIFIER B 1.50 REF C D 0.50 BSC TOP VIEW BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.640 0.595 0.540 SIDE VIEW 0.340 0.320 0.300 SEATING PLANE 0.270 0.240 0.210 10-17-2012-B COPLANARITY 0.05 Figure 52. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5592RBCBZ-1-RL7 AD5592RBCPZ-1-RL7 AD5592RBRUZ AD5592RBRUZ-RL7 AD5592RBCBZ-RL7 AD5592RBCPZ-RL7 EVAL-AD5592R-1SDZ EVAL-SDP-CB1Z 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Controller Board Z = RoHS Compliant Part. ©2014–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12506-8/20(F) Rev. F | Page 44 of 44 Package Option CB-16-3 CP-16-32 RU-16 RU-16 CB-16-3 CP-16-32 Marking Code DMD DMG