AD5593RBCPZ-RL7

Data Sheet AD5593R 8-Channel, 12-Bit, Configurable ADC/DAC with On-Chip Reference, I2C Interface GENERAL DESCRIPTION FEATURES The AD5593R has eight input/output (I/O) pins, which can be independently configured as digital-to-analog converter (DAC) outputs, analog-to-digital converter (ADC) inputs, digital outputs, or digital inputs. When an I/O pin is configured as an analog output, it is driven by a 12-bit DAC. The output range of the DAC is 0 V to VREF or 0 V to 2 × VREF. When an I/O pin is configured as an analog input, it is connected to a 12-bit ADC via an analog multiplexer. The input range of the ADC is 0 V to VREF or 0 V to 2 × VREF. The I/O pins can also be configured to be general-purpose, digital input or output (GPIO) pins. The state of the GPIO pins can be set or read back by accessing the GPIO write data register and GPIO read configuration registers, respectively, via an I2C write or read operation. 8-channel, configurable ADC/DAC/GPIO Configurable as any combination of ► 8 12-bit DAC channels ► 8 12-bit ADC channels ► 8 general-purpose I/O pins ► Integrated temperature sensor ► 16-lead TSSOP and LFCSP and 16-ball WLCSP packages ► I2C interface ► ► APPLICATIONS Control and monitoring ► General-purpose analog and digital I/O ► The AD5593R has an integrated 2.5 V, 20 ppm/°C reference that is turned off by default and an integrated temperature indicator that gives an indication of the die temperature. The temperature value is read back as part of an ADC read sequence. The AD5593R is available in 16-lead TSSOP and LFCSP, as well as a 16-ball WLCSP, and operates over a temperature range of −40°C to +105°C. Table 1. Related Products Product Description AD5592R AD5592R-1 AD5593R equivalent with SPI interface AD5593R equivalent with SPI interface and VLOGIC pin FUNCTIONAL BLOCK DIAGRAM Figure 1. Rev. F DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet AD5593R TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 General Description...............................................1 Functional Block Diagram......................................1 Specifications........................................................ 4 Timing Characteristics........................................7 Absolute Maximum Ratings...................................8 Thermal Resistance........................................... 8 Electrostatic Discharge (ESD) Ratings...............8 ESD Caution.......................................................8 Pin Configuration and Function Descriptions........ 9 Typical Performance Characteristics................... 10 Terminology......................................................... 15 Theory of Operation.............................................18 DAC Section.....................................................18 ADC Section.....................................................19 GPIO Section................................................... 19 Internal Reference............................................20 Reset Function................................................. 20 Temperature Indicator...................................... 20 Serial Interface.................................................... 21 Write Operation................................................ 21 Read Operation................................................ 22 Pointer Byte......................................................23 Control Registers..............................................23 General-Purpose Control Register................... 23 Configuring the AD5593R................................ 23 DAC Write Operation........................................25 DAC Readback.................................................25 ADC Operation ................................................ 26 GPIO Operation................................................27 Three-State Pins.............................................. 27 85 kΩ Pull-Down Pins...................................... 27 Power-Down/Reference Control.......................27 Reset Function................................................. 27 Applications Information...................................... 28 Microprocessor Interfacing............................... 28 AD5593R to ADSP-BF537 Interface................ 28 Layout Guidelines.............................................28 Register Map....................................................... 29 Register Summary: AD5593R Pointer Byte Map ............................................................... 29 Register Summary (Bit-Wise): AD5593R Pointer Byte Map ...........................................29 Register Summary: AD5593R Control Register Map.................................................. 29 Register Details: AD5593R Pointer Byte Map..30 Register Details: AD5593R Control Register Map................................................................ 32 Register Details: AD5593R ADC and DAC Readback ...................................................... 45 Outline Dimensions............................................. 47 Ordering Guide.................................................48 Evaluation Boards............................................ 48 REVISION HISTORY 8/2022—Rev. E to Rev. F Changes to Specifications Section and Table 2...............................................................................................4 Changes to Thermal Resistance Section and Table 5..................................................................................... 8 Added Electrostatic Discharge (ESD) Ratings Section....................................................................................8 Added ESD Ratings for AD5593R Section and Table 6; Renumbered Sequentially....................................... 8 Deleted Table 7 and Table 8; Renumbered Sequentially................................................................................. 9 Changes to Table 7.......................................................................................................................................... 9 Changes to Terminology Section................................................................................................................... 15 Changes to DAC Section Section.................................................................................................................. 18 Added DAC Output Range Section, Figure 33, and Figure 34; Renumbered Sequentially...........................18 Changes to ADC Section Section.................................................................................................................. 19 Changes to GPIO Section Section.................................................................................................................19 Changes to Reset Function Section.............................................................................................................. 20 Changes to Temperature Indicator Section....................................................................................................20 Moved Figure 36............................................................................................................................................ 21 Change to Read Operation Section............................................................................................................... 22 Changes to Pointer Byte Section................................................................................................................... 23 Deleted Table 9 and Table 10........................................................................................................................ 23 Changes to Control Registers Section...........................................................................................................23 analog.com Rev. F | 2 of 48 Data Sheet AD5593R TABLE OF CONTENTS Deleted Table 11 to Table 13..........................................................................................................................23 Deleted Table 14............................................................................................................................................ 23 Changes to LDAC Mode Operation Section.................................................................................................. 25 Deleted Table 15............................................................................................................................................ 25 Changes to DAC Readback Section..............................................................................................................25 Deleted Table 16 and Table 17...................................................................................................................... 25 Changes to ADC Operation Section.............................................................................................................. 26 Deleted Table 18 to Table 20......................................................................................................................... 26 Changes to Setting Pins as Outputs Section................................................................................................. 27 Deleted Table 21 to Table 23......................................................................................................................... 27 Changes to Setting Pins as Inputs Section....................................................................................................27 Changes to Three-State Pins Section............................................................................................................27 Deleted Table 24............................................................................................................................................ 27 Changes to 85 kΩ Pull-Down Pins Section....................................................................................................27 Deleted Table 25............................................................................................................................................ 27 Changes to Power-Down/Reference Control Section....................................................................................27 Changes to Reset Function Section.............................................................................................................. 27 Deleted Table 26 and Table 27...................................................................................................................... 27 Added Register Map Section......................................................................................................................... 29 Added Register Summary: AD5593R Pointer Byte Map Section and Table 8............................................... 29 Added Register Summary (Bit-Wise): AD5593R Pointer Byte Map Section and Table 9.............................. 29 Added Register Summary: AD5593R Control Register Map Section and Table 10.......................................29 Added Register Details: AD5593R Pointer Byte Map Section....................................................................... 30 Added Configuration Mode Register Section and Table 11........................................................................... 30 Added DAC Write Mode Register Section and Table 12................................................................................30 Added ADC Readback Mode Register Section and Table 13........................................................................31 Added DAC Readback Mode Register Section and Table 14........................................................................31 Added GPIO Readback Mode Register Section and Table 15...................................................................... 32 Added Register Readback Mode Section and Table 16................................................................................ 32 Added Register Details: AD5593R Control Register Map Section.................................................................32 Added NOP Register Section and Table 17...................................................................................................32 Added ADC Sequence Register Section and Table 18..................................................................................33 Added ADC Pin Configuration Register Section and Table 20...................................................................... 35 Added DAC Pin Configuration Register Section and Table 21...................................................................... 36 Added Pull-Down Configuration Register Section and Table 22....................................................................37 Added LDAC Mode Register Section and Table 23....................................................................................... 38 Added GPIO Write Configuration Register Section and Table 24..................................................................38 Added GPIO Write Data Register Section and Table 25................................................................................39 Added GPIO Read Configuration Register Section and Table 26..................................................................40 Added Power-Down/Reference Control Register Section and Table 27........................................................41 Added GPIO Open-Drain Configuration Register Section and Table 28........................................................42 Added Three-State Configuration Register Section and Table 29................................................................. 43 Added Software Reset Register Section and Table 30.................................................................................. 44 Added DAC Write Register Section and Table 31..........................................................................................45 Added Register Details: AD5593R ADC and DAC Readback Section.......................................................... 45 Added DAC Data Read Back Register Section and Table 32........................................................................45 Added ADC Conversion Result Register Section and Table 33.....................................................................46 Added Temperature Reading Register Section and Table 34........................................................................ 46 analog.com Rev. F | 3 of 48 Data Sheet AD5593R SPECIFICATIONS VDD = 2.7 V to 5.5 V, VLOGIC = 2.7 V to 5.5 V, VREF = 2.5 V (internal), Temperature Range TA = TMIN to TMAX, unless otherwise noted. Typical specs are verified by characterization, not production tested. Table 2. Parameter Min TEMPERATURE RANGE (TA) Specified Performance −40 ADC PERFORMANCE Resolution Input Range1 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Gain Error Track Time (tTRACK)2 Conversion Time (tCONV)2 Signal to Noise Ratio (SNR)3 °C VREF 2 × VREF +2 +1 ±5 0.3 2 69 67 61 69 67 60 −91 −89 −72 91 91 72 15 12 50 −95 8.2 1.6 Aperture Delay2 Aperture Jitter2 Channel-to-Channel Isolation Full Power Bandwidth 12 0 0 −1 −1 −3 VREF 2 × VREF +1 +1 +3 8 Zero Code Error Total Unadjusted Error (TUE) 0.65 ±0.03 ±0.015 Capacitive Load Stability analog.com +105 500 Spurious Free Dynamic Range (SFDR) Resistive Load Unit 12 0 0 −2 −1 Total Harmonic Distortion (THD) INL DNL Offset Error Offset Error Drift2 Gain Error Max Test Conditions/Comments fIN = 10 kHz sine wave Signal-to-Noise + Distortion (SINAD) Ratio DAC PERFORMANCE4 Resolution Output Range Typ 1 ±0.2 ±0.1 2 ±0.25 ±0.1 2 10 Bits V V LSB LSB mV % FSR ns µs dB dB dB dB dB dB dB dB dB dB dB dB ns ns ps dB MHz MHz Bits V V LSB LSB mV µV/°C % FSR % FSR mV % FSR % FSR nF nF kΩ ADC range select bit = 0 ADC range select bit = 1 VDD = 2.7 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 2.7 V, input range = 0 V to VREF VDD = 3.3 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 2.7 V, input range = 0 V to VREF VDD = 3.3 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 2.7 V, input range = 0 V to VREF VDD = 3.3 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 3 V VDD = 5 V fIN = 5 kHz At 3 dB At 0.1 dB DAC range select bit = 0 DAC range select bit = 1 Output range = 0 V to VREF Output range = 0 V to 2 × VREF Output range = 0 V to VREF Output range = 0 V to 2 × VREF RLOAD = ∞ RLOAD = 1 kΩ Rev. F | 4 of 48 Data Sheet AD5593R SPECIFICATIONS Table 2. Parameter Short-Circuit Current DC Crosstalk2 DC Output Impedance DC Power Supply Rejection Ratio (PSRR)2 Load Impedance at Rails5 Load Regulation Min REFERENCE OUTPUT VREF Output Voltage VREF Temperature Coefficient Capacitive Load Stability Output Impedance analog.com 0.2 0.15 25 200 200 7 1.25 6 2 1 0.1 1 0.1 240 200 V/µs µs nV-sec nV-sec nV-sec nV-sec nV-sec kHz nV/√Hz 81 77 74 −76 dB dB dB dB +4 1 −1 Test Conditions/Comments Single channel, full-scale output change DAC code = midscale, VDD = 3 V ± 10% or 5 V ± 10% VDD = 5 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤ +10 mA VDD = 3 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤ +10 mA Exiting power-down mode, VDD = 5 V DAC code = full scale, output range = 0 V to 2 × VREF DAC code = midscale, output range = 0 V to 2 × VREF, measured at 10 kHz VDD +1 V µA kΩ kΩ No I/Ox pins configured as DACs DAC output range = 0 V to 2 × VREF DAC output range = 0 V to VREF 2.505 V ppm/°C μF Ω Ω µV p-p nV/√Hz µV/V µV/V RLOAD = 2 kΩ VDD = 2.7 V VDD = 5 V 0.1 Hz to 10 Hz At ambient, f = 1 kHz, CL = 10 nF At ambient, sweeping VDD from 2.7 V to 5.5 V At ambient, sweeping VDD from 2.7 V to 3.3 V 210 120 ±5 µV/mA µV/mA mA At ambient, −5 mA ≤ load current ≤ +5 mA At ambient, −5 mA ≤ load current ≤ +5 mA VDD ≥ 3 V 1.6 mA 12 24 2.495 Unit mA µV Ω mV/V Ω µV/mA µV/mA µs −4 Output Voltage Noise Output Voltage Noise Density Line Regulation Load Regulation Sourcing Sinking Output Current Load Capability GPIO OUTPUT ISOURCE and ISINK Output Voltage High, VOH Low, VOL GPIO INPUT Input Voltage Max 25 Power-Up Time DAC AC SPECIFICATIONS Slew Rate Settling Time DAC Glitch Impulse DAC to DAC Crosstalk Digital Crosstalk Analog Crosstalk Digital Feedthrough Multiplying Bandwidth Output Voltage Noise Spectral Density SNR SFDR SINAD Total Harmonic Distortion REFERENCE INPUT VREF Input Voltage DC Leakage Current VREF Input Impedance Typ 2.5 20 5 0.15 0.7 10 240 20 10 VDD − 0.2 0.4 V V ISOURCE = 1 mA ISINK = 1 mA Rev. F | 5 of 48 Data Sheet AD5593R SPECIFICATIONS Table 2. Parameter Min High, VIH Low, VIL Input Capacitance Hysteresis Input Current LOGIC INPUTS Input Voltage High, VINH Low, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUT (SDA) Output High Voltage, VOH Output Low Voltage, VOL Floating-State Output Capacitance TEMPERATURE SENSOR2 Resolution Operating Range Accuracy Track Time VDD × 0.7 POWER REQUIREMENTS VDD IDD Power-Down Mode Normal Mode VDD = 5 V analog.com Max VDD × 0.3 20 0.2 ±1 0.7 × VLOGIC −1 +0.01 0.3 × VLOGIC +1 10 VLOGIC − 0.2 0.4 10 12 −40 2.7 Unit Test Conditions/Comments V V pF V µA V V µA pF V V pF 5 20 Bits °C °C µs µs 5.5 V 3.5 µA +105 ±3 ISOURCE = 200 µA; VLOGIC = 2.7 V to 5.5 V ISINK = 200 µA ADC buffer enabled ADC buffer disabled Digital inputs = 0 V or VLOGIC VDD = 3 V VLOGIC ILOGIC Typ 1.8 1.6 1 2.4 mA mA mA 1.1 mA 1 0.75 0.5 0.5 1.1 1 1.1 mA mA mA mA mA mA mA 0.78 mA 0.75 0.5 0.45 0.45 mA mA mA mA V μA VDD 3.5 I/O0 to I/O7 are DACs, internal reference, gain = 2 I/O0 to I/O7 are DACs, external reference, gain = 2 I/O0 to I/O7 are DACs and sampled by the ADC, internal reference, gain = 2 I/O0 to I/O7 are DACs and sampled by the ADC, external reference, gain = 2 I/O0 to I/O7 are ADCs, internal reference, gain = 2 I/O0 to I/O7 are ADCs, external reference, gain = 2 I/O0 to I/O7 are general-purpose outputs I/O0 to I/O7 are general-purpose inputs I/O0 to I/O7 are DACs, internal reference, gain = 1 I/O0 to I/O7 are DACs, external reference, gain = 1 I/O0 to I/O7 are DACs and sampled by the ADC, internal reference, gain = 1 I/O0 to I/O7 are DACs and sampled by the ADC, external reference, gain = 1 I/O0 to I/O7 are ADCs, internal reference, gain = 1 I/O0 to I/O7 are ADCs, external reference, gain = 1 I/O0 to I/O7 are general-purpose outputs I/O0 to I/O7 are general-purpose inputs Rev. F | 6 of 48 Data Sheet AD5593R SPECIFICATIONS 1 When using the internal ADC buffer, there is a dead band of 0 V to 5 mV. 2 Guaranteed by design and characterization; not production tested. 3 All specifications expressed in decibels are referred to full-scale input, FSR, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a reduced code range of 8 to 4085. An upper dead band of 10 mV exists when VREF = VDD. 5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 26 and Figure 27). TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD; 2.5 V ≤ VREF ≤ VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1 Min t1 t2 t3 t4 t5 t 62 t7 t8 t9 t10 2.5 0.6 1.3 0.6 100 Typ Max 0.9 0.6 0.6 1.3 300 0 t11 250 0 300 20 + 0.1 × CB3 CB3 400 Unit Conditions/Comments µs µs µs µs ns µs µs µs µs ns ns ns ns ns ns pF SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD,STA, start/repeated start condition hold time tSU,DAT, data setup time tHD,DAT, data hold time tSU,STA, setup time for repeated start tSU,STO, stop condition setup time tBUF, bus free time between a stop and a start condition tR, rise time of SCL and SDA when receiving tR, rise time of SCL and SDA when receiving (CMOS compatible) tF, fall time of SDA when transmitting tF, fall time of SDA when receiving (CMOS compatible) tF, fall time of SCL and SDA when receiving tF, fall time of SCL and SDA when transmitting Capacitive load for each bus line 1 Guaranteed by design and characterization; not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3 CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VLOGIC and 0.7 VLOGIC. Timing Diagram Figure 2. 2-Wire Serial Interface Timing Diagram analog.com Rev. F | 7 of 48 Data Sheet AD5593R ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. measurement points. The thermal resistances are directly dependent on the PCB design and environment. Table 4. If direct measurement of the package is required, the ΨJT and ΨJB values must be used because they more accurately reflect the true thermal dissipation paths. Parameter Rating VDD to GND VLOGIC to GND I/Ox to GND Digital Inputs to GND Digital Outputs to GND VREF to GND Operating Temperature Range Storage Temperature Range Junction Temperature (TJ max) Lead Temperature Soldering −0.3 V to +7 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VLOGIC + 0.3 V −0.3 V to VLOGIC +0.3 V −0.3 V to VDD +0.3 V −40°C to +105°C −65°C to +150°C +150°C JEDEC industry-standard J-STD-020 θJC must only be used where an external heat sink is attached directly to the package. System level thermal simulation is highly recommended. For more details about the thermal resistances, refer to JEDEC51-12: Guidelines for Reporting and Using Electronic Package Thermal Information. Table 5. Thermal Resistance Package Type θJA θJB θJC-TOP ΨJT ΨJB Unit CP-16-32 RU-16 CB-16-3 92.4 127 103.2 39.6 60.2 64 48.2 42.2 0 37.4 59.1 78 °C/W °C/W °C/W 0.9 2.6 0 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ELECTROSTATIC DISCHARGE (ESD) RATINGS THERMAL RESISTANCE Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Field induced charged device model (FICDM) and charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. Thermal characteristics are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Thermal resistance values specified in Table 5 are simulated based on JEDEC specifications using a 2S2P thermal test board (see JEDEC JESD51), except for θJC-TOP, which uses a JEDEC 1S test board. ESD Ratings for AD5593R θJA is the junction to ambient thermal resistance, measured in a JEDEC natural convection environment. ESD CAUTION θJC is the junction to case thermal resistance, measured at the centre of the package top surface, with an infinite heat sink attached to the package surface. θJB is the junction to board thermal resistance, measured at a point on the board 1mm from the package edge, along the package centre line, measured in a JEDEC θJB environment. The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. Table 6. AD5593R, 16-Ball WLCSP, 16-Ball LFCSP, and 16-Lead TSSOP ESD Model Withstand Voltage (V) Class HBM 500 1B FICDM 1250 C3 ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. ΨJB is the junction to board thermal characterization parameter, measured in a JEDEC natural convection environment. ΨJT is the junction to package top thermal characterization parameter, measured in a JEDEC natural convection environment. Do not use θJA, θJC, and θJB thermal resistances to perform direct calculation/measurement of the die temperature because doing so results in incorrect values. The thermal resistances assume 100% of the power that is dissipated along the specified path between the analog.com Rev. F | 8 of 48 Data Sheet AD5593R PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. 16-Lead TSSOP Pin Configuration Figure 5. 16-Ball WLCSP Pin Configuration Figure 4. 16-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. TSSOP LFCSP WLCSP Mnemonic Description 1 15 A3 RESET 2 3 4 to 7, 10 to 13 16 1 2 to 5, 8 to 11 A0 VDD I/O0 to I/O7 8 6 A4 B4 B3, C4, C3, C2, D1, D4, C1, B2 D3 9 14 15 7 12 13 D2 B1 A1 VLOGIC GND SDA 16 14 A2 SCL Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5593R is reset to its default configuration. Address Input. Sets the LSB of the 7-bit slave address. Power Supply Input. The AD5593R can operate from 2.7 V to 5.5 V. Decouple the supply with a 0.1 µF capacitor to GND. Input/Output 0 Through Input/Output 7. These pins can be independently configured as DACs, ADCs, or general-purpose digital inputs or outputs. The function of each pin is determined by programming the appropriate bits in the configuration registers. Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on the VREF pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5593R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. Interface Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V. Ground Reference Point for All Circuitry. Serial Data Input. This pin is used with the SCL line to clock data in to or out of the input shift register. SDA is a bidirectional, open-drain line that must be pulled to the VLOGIC supply with an external pull-up resistor. Serial Clock Line. This pin is used with the SDA line to clock data in to or out of the 16-bit input register. analog.com VREF Rev. F | 9 of 48 Data Sheet AD5593R TYPICAL PERFORMANCE CHARACTERISTICS analog.com Figure 6. ADC INL; VDD = 5.5 V Figure 9. ADC DNL; VDD = 2.7 V Figure 7. ADC DNL; VDD = 5.5 V Figure 10. Histogram of ADC Codes; VDD = 2.7 V Figure 8. ADC INL; VDD = 2.7 V Figure 11. Histogram of Codes; VDD = 5.5 V Rev. F | 10 of 48 Data Sheet AD5593R TYPICAL PERFORMANCE CHARACTERISTICS analog.com Figure 12. ADC Bandwidth Figure 15. DAC Adjacent Code Glitch Figure 13. DAC INL Figure 16. DAC Digital to Analog Glitch (Rising) Figure 14. DAC DNL Figure 17. DAC Digital to Analog Glitch (Falling) Rev. F | 11 of 48 Data Sheet AD5593R TYPICAL PERFORMANCE CHARACTERISTICS Figure 18. DAC Settling Time (100 Code Change, Rising Edge) Figure 21. DAC Settling Time, Output Range = 0 V to 2 × VREF Figure 19. DAC Settling Time (100 Code Change, Falling Edge) Figure 22. DAC Settling Time vs. Capacitive Load Figure 20. DAC Settling Time, Output Range = 0 V to VREF Figure 23. DAC 1/f Noise with External Reference analog.com Rev. F | 12 of 48 Data Sheet AD5593R TYPICAL PERFORMANCE CHARACTERISTICS Figure 24. DAC 1/f Noise with Internal Reference Figure 27. DAC Output Sink and Source Capability, Output Range = 0 V to 2 × VREF Figure 25. DAC Output Noise Spectral Density Figure 28. Internal Reference 1/f Noise Figure 26. DAC Output Sink and Source Capability, Output Range = 0 V to VREF analog.com Figure 29. Reference Noise Spectral Density Rev. F | 13 of 48 Data Sheet AD5593R TYPICAL PERFORMANCE CHARACTERISTICS Figure 30. Reference Line Regulation analog.com Rev. F | 14 of 48 Data Sheet AD5593R TERMINOLOGY ADC Integral Nonlinearity (INL) Total Harmonic Distortion (THD) For the ADC, INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end points of the transfer function are zero scale, a point that is 1 LSB below the first code transition, and full scale, a point that is 1 LSB above the last code transition. THD is the ratio of the rms sum of harmonics to the fundamental. For the AD5593R, it is defined as ADC Differential Nonlinearity (DNL) For the ADC, DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error Offset error is the deviation of the first code transition (00 … 000) to (00 … 001) from the ideal, that is, AGND + 1 LSB. Gain Error Gain error is the deviation of the last code transition (111 … 110) to (111 … 111) from the ideal (that is, VREF − 1 LSB) after the offset error has been adjusted out. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale 5 kHz sine wave signal to all non-selected ADC input channels and determining how much that signal is attenuated in the selected channel. This specification is the worst case across all ADC channels for the AD5593R. Track-and-Hold Acquisition Time The track-and-hold amplifier goes into track mode when the ADC sequence register has been written to. The track and hold amplifier goes into hold mode when the conversion starts (see ). Track-and-hold acquisition time is the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within ±1 LSB of the applied input signal, given a step change to the input signal. Signal-to-Noise Distortion Ratio SINAD SINAD is the measured ratio of signal to (noise + distortion) at the output of the analog-to-digital converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all non-fundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical SINAD for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) (dB) = 6.02N + 1.76 Thus, for a 12-bit converter, this is 74 dB. analog.com THD dB = 20 × log V22 + V32 + V42 + V52 + V62 V1 (1) where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. DAC Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 13. DAC Differential Nonlinearity (DNL) For the DAC, differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 14. Zero Code Error Zero code error is a measurement of the output error when zero code (0x000) is loaded to the DAC register. Ideally, the output is 0 V. The zero code error is always positive in the AD5593R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero code error is expressed in mV. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % of FSR. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error can be negative or positive. Rev. F | 15 of 48 Data Sheet AD5593R TERMINOLOGY Offset Error Drift Digital Crosstalk Offset error drift is a measurement of the change in offset error with a change in temperature. It is expressed in µV/°C. Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec. DAC DC Power Supply Rejection Ratio (PSRR) For the DAC, PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in mV/V. VREF is held at 2 V, and VDD is varied by ±10%. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change and is measured from the rising edge of SDA that generates the stop condition. Digital-to-Analog Glitch Impulse Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is first measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then it is measured by executing a software LDAC and monitoring the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. DAC-to-DAC Crosstalk Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FF to 0x800) (see Figure 16 and Figure 17). DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa), using the write to and update commands while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-sec. Digital Feedthrough Multiplying Bandwidth Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this finite bandwidth. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Reference Feedthrough DAC Total Harmonic Distortion (THD) Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. For the DAC, THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Noise Spectral Density (NSD) NSD is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. A plot of noise spectral density is shown in Figure 25. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA. analog.com Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The voltage reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows: TC = VREF(MAX) − VREF(MIN) VREF(NOM) × Temp Range × 106 (2) where: VREF(MAX) is the maximum reference output measured over the total temperature range. VREF(MIN) is the minimum reference output measured over the total temperature range. Rev. F | 16 of 48 Data Sheet AD5593R TERMINOLOGY VREF(NOM) is the nominal reference output voltage, 2.5 V. Temp Range is the specified temperature range of −40°C to +105°C. analog.com Rev. F | 17 of 48 Data Sheet AD5593R THEORY OF OPERATION The AD5593R is an 8-channel, configurable analog and digital I/O port. The AD5593R has eight pins that can be independently configured as a 12-bit DAC output channel, a 12-bit ADC input channel, a digital input pin, or a digital output pin. The function of each pin is determined by programming the ADC, DAC, or GPIO configuration registers as appropriate. DAC SECTION The AD5593R contains eight 12-bit DACs. Each DAC consists of a string of resistors followed by an output buffer amplifier. Figure 31 shows a block diagram of the DAC architecture. Figure 32. Resistor String DAC Output Buffer Figure 31. DAC Channel Architecture Block Diagram The DAC channels share a single DAC range bit (in the GeneralPurpose Control Register section, see Bit 4 in Table 19) that sets the output range to 0 V to VREF or 0 V to 2 × VREF. Because the range bit is shared by all channels, it is not possible to set different output ranges on a per channel basis. The input coding to the DAC is straight binary. Therefore, the ideal output voltage is given by VOUT = G × VREF × D 2N (3) where: G = 1 for an output range of 0 V to VREF or G = 2 for an output range of 0 V to 2 × VREF. VREF is the voltage on the VREF pin. D is the decimal equivalent of the binary code (0 to 4095) that is loaded to the DAC register. N = 12. The output buffer is designed as an input/output rail-to-rail buffer. The output buffer can drive 2 nF capacitance with a 1 kΩ resistor in parallel. The slew rate is 1.25 V/µs with a ¼ to ¾ scale settling time of 6 µs. By default, the DAC outputs update directly after data has been written to the input register. The LDAC register delays the updates until additional channels have been written to if required. See the LDAC Mode Operation section for more information. DAC Output Range The DAC output voltage range can be configured to 0 V to VREF (gain = 1) or 0 V to 2 × VREF (gain = 2) using DAC range bit of the general-purpose control register, as shown in Figure 33 and Figure 34, respectively. When VREF = VDD, the 0 V to 2 × VREF range does not allow the DAC to swing the output beyond VDD. Resistor String The simplified segmented resistor string DAC structure is shown in Figure 32. The code loaded to the DAC register determines the switch on the string that is connected to the output buffer. Because each resistance in the string has the same value, R, the string DAC is guaranteed monotonic. Figure 33. Output Voltage Range of the DAC with Gain = 1 (Unloaded Condition) analog.com Rev. F | 18 of 48 Data Sheet AD5593R THEORY OF OPERATION input structure. When a new channel is selected for conversion, 5.8 pF must be charged to or discharged from the voltage that on the previously selected channel. The time required for the charge or discharge depends on the voltage difference between the two channels. This dependence affects the input impedance of the multiplexer and, therefore, the input current flowing into the I/Ox pins. Figure 34. Output Voltage Range of the DAC with Gain = 2 (Unloaded Condition) When VREF = VDD for gain = 1 or VREF = 0.5 × VDD for gain = 2, there is an upper dead band of 10 mV at the DAC channel output in unloaded conditions. Additionally, there is a lower dead band of ~4.88 mV at the DAC channel output in unloaded conditions. When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the DAC channel. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV. ADC SECTION The ADC section is a fast, 12-bit, single-supply ADC with a conversion time of 2 µs. The ADC is preceded by a multiplexer that switches selected I/O pins to the ADC. A sequencer is included to switch the multiplexer to the next selected channel automatically. Channels are selected for conversion by writing to the ADC sequence register. When the write to the ADC sequence register has completed, the first channel in the conversion sequence is put into track mode. Each channel can track the input signal for a minimum of 500 ns. The conversion is initiated on the rising edge of the clock for the acknowledge (ACK) that occurs after the slave address (see Figure 39). Each conversion takes 2 µs. The ADC has a range bit (ADC range select in the general-purpose control register, see Bit 5 in Table 19) that sets the input range as 0 V to VREF or 0 V to 2 × VREF. All input channels share the same range. The output coding of the ADC is straight binary. It is possible to set each I/Ox pin as both a DAC and an ADC. In this case, the primary function is that of the DAC. If the pin is selected for inclusion in an ADC conversion sequence, the voltage on the pin is converted and made available via the serial interface. This allows the DAC voltage to be monitored. Calculating ADC Input Current The current flowing into the I/Ox pins configured as ADC inputs varies with sampling rate (fS), the voltage difference between successive channels (VDIFF), and whether buffered or unbuffered mode is used. Figure 35 shows a simplified version of the ADC analog.com In buffered mode, Switch S1 is open and Switch S2 is closed. In buffered mode, the U1 buffer directly drives the 23.1 pF capacitor and the charging time of the capacitors is negligible. In unbuffered mode, Switch S1 is closed and Switch S2 is closed. In unbuffered mode, the 23.1 pF capacitor must be charged from the I/Ox pins; this charging contributes to the input current. For applications where the ADC input current is too high, an external input buffer may be required. The choice of buffer is a function of the particular application. Calculate the input current for buffered mode as follows: fS × C × VDIFF + 1 nA where: fS is the ADC sample rate in Hz. C is the sampling capacitance in farads. VDIFF is the voltage change between successive channels. Calculate the input current for buffered mode as follows: fS × C × VDIFF where 1 nA is the dc leakage current associated with unbuffered mode. The input current for the ADC in buffered mode, where I/O0 = 0.5 V, I/O1 = 2 V, and fS = 10 kHz, is as follows: (10,000 × 5.8 × 10−12 × 1.5) + 1 nA = 88 nA Under the same conditions, the ADC input current in unbuffered mode is as follows: (10,000 × 28.9 × 10−12 × 1.5) = 433.5 nA Figure 35. ADC Input Structure GPIO SECTION Each of the eight I/Ox pins can be configured as a general-purpose digital input by programming the GPIO read configuration register or output pin by programming the GPIO write configuration register. When an I/Ox pin is configured as an output, the pin can be set high or low by programming the GPIO write data register. Logic levels for general-purpose outputs are relative to VDD and GND. When an I/Ox pin is configured as an input, its status can be Rev. F | 19 of 48 Data Sheet AD5593R THEORY OF OPERATION determined by setting the pointer byte to 0b01100000 . When an I/Ox pin is set as an output, it is possible to read its status by also setting it as an input pin. When reading the status of the I/Ox pins set as inputs the status of an I/Ox pin set as both and input and output pin is also returned. INTERNAL REFERENCE The AD5593R contains an on-chip 2.5 V reference. The reference is powered down by default and is enabled by setting Bit 9 in the power-down/reference control register to 1. When the on-chip reference is powered up, the reference voltage appears on the VREF pin and may be used as a reference source for other components. When the internal reference is used, it is recommended to decouple VREF to GND using a 100 nF capacitor. It is recommended that the internal reference be buffered before using it elsewhere in the system. When the reference is powered down, an external reference must be connected to VREF. Suitable external reference sources for the AD5593R include the AD780, AD1582, ADR431, REF193, and ADR391. Temperature (°C) = 25 + ADC Code − 0.5 / 2 × VREF 1.327 × 2.5 / VREF × 4095 The range of codes returned by the ADC when reading from the temperature indicator is approximately 645 to 1035, (for ADC gain = 1) corresponding to a temperature between −40°C and +105°C. The accuracy of the temperature indicator is typically 3°C when averaged over five samples. RESET FUNCTION The AD5593R has an asynchronous RESET pin. For normal operation, RESET is tied high. A falling edge on RESET resets all registers to their default values and reconfigures the I/O pins to their default values (85 kΩ pull-down resistor to GND). The reset function takes 250 µs maximum; do not write new data to the AD5593R during this time. The AD5593R has a software reset that performs the same function as the RESET pin. The reset function is activated by writing 0x0F to the pointer byte and 0x0D and 0xAC to the most significant and least significant bytes of the software reset register, respectively. TEMPERATURE INDICATOR The AD5593R contains an integrated temperature indicator that can be read to provide an estimation of the die temperature. This can be used in fault detection where a sudden rise in die temperature may indicate a fault condition, such as a shorted output. Temperature readback is enabled by setting Bit 8 in the ADC sequence register. The temperature result is then added to the ADC sequence. The temperature result has an address of 0b1000 (see Table 34) and care must be taken that this result is not confused with the readback from DAC0 (see Table 32). The temperature conversion takes 5 µs with the ADC buffer enabled and 20 µs when the buffer is disabled. Calculate the temperature using the following formulae: For ADC gain = 1, Temperature (°C) = 25 + For ADC gain = 2, analog.com ADC Code − 0.5 / VREF × 4095 2.654 × 2.5 / VREF Rev. F | 20 of 48 Data Sheet AD5593R SERIAL INTERFACE The AD5593R has a 2-wire, I2C-compatible serial interface (refer to The I2C -Bus Specification, Version 2.1, January 2000). The AD5593R is connected to an I2C bus as a slave device under the control of a master device. See Figure 2 for a timing diagram of a typical write sequence. The AD5593R supports standard mode (100 kHz) and fast mode (400 kHz). Support is not provided for 10-bit addressing and general call addressing. The AD5593R has a 7-bit slave address; its six MSBs are set to 001000. The LSB is set by the state of the A0 address pin, which determines the state of the A0 bit. The facility to change the logic level of the A0 pin before a read or write operation allows the user to incorporate multiple AD5593R devices on one bus. The 2-wire serial bus protocol operates as follows: the master initiates data transfer by establishing a start condition when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave address corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. tions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master brings the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition. WRITE OPERATION When writing to the AD5593R, the user must begin with a start command followed by an address byte R/W = 0), after which the AD5593R acknowledges that it is prepared to receive data by pulling SDA low. The AD5593R requires three bytes of data. The first byte is the pointer byte. This byte contains information defining the type of operation that is required of the AD5593R, such as configuring the I/O pins and writing to a DAC. The pointer byte is followed by the most significant byte and the least significant byte, as shown in Figure 36. After these data bytes are acknowledged by the AD5593R, a stop condition follows. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transi- Figure 36. 4-Byte I2C Write analog.com Rev. F | 21 of 48 Data Sheet AD5593R SERIAL INTERFACE READ OPERATION When reading data back from the AD5593R, the user begins with a start command followed by an address byte (R/W = 0), after which the AD5593R acknowledges that it is prepared to transmit data by pulling SDA low. The pointer byte is then written to select what is to be read back. A repeat start or a new I2C transmission can then follow to read two bytes of data from the AD5593R. Both bytes are acknowledged by the master, as shown in Figure 37. It is also possible to perform consecutive readbacks without having to provide interim start and stop conditions or slave addresses. This method can be used to read blocks of conversions from the ADC, as shown in Figure 39. Figure 37. Read One 16-Bit Word Figure 38. Read One 16-Bit Word, Maintain Control of the Bus analog.com Rev. F | 22 of 48 Data Sheet AD5593R SERIAL INTERFACE Figure 39. I2C Block Read POINTER BYTE GENERAL-PURPOSE CONTROL REGISTER The pointer byte contains eight bits. Bits[7:4] are mode bits that select the operation to be executed. The data contained in Bits[3:0] depend on the operation required. Table 8 and Table 9 show the configuration of the pointer byte. When Bits[7:4] are 0b0000, the mode dependent bits (Bits[3:0]) select a control register (see Table 10) to write data to. The data written to a control register is contained in the MSB and LSB as shown in Figure 36. The mode dependent data bits also select which DAC is updated during a DAC write operation and which register is selected for readback. The general-purpose control register enables or disables certain functions associated with the DAC, ADC, and I/O pin configuration (see Table 19). The register sets the output range of the DAC and input range of the ADC, which sets their transfer functions, enables/disables the ADC buffer, and enables the precharge function (see the ADC Section section for more details). The register is also used to lock the I/O pin configuration to prevent accidental change. When Bit 7 is set to 1, writes to the configuration registers are ignored. CONTROL REGISTERS CONFIGURING THE AD5593R Table 11 shows the control register map for the AD5593R. The control registers configure the I/O pins and set various operating parameters in the AD5593R, such as enabling the reference, selecting the LDAC mode function, or selecting power-down modes. The control registers are written to using the 4-byte I2C write sequence shown in Figure 36. To write to a control register, the mode bits (Bits[7:4]) of the pointer byte are zeros. The mode dependent data bits (Bits[3:0]) of the pointer byte select which control register is to be accessed. The data to be written to the control register is contained in the most significant and least significant data bytes. These contain a total of 16 bits and are shown as Bits[15:0] in the Register Details: AD5593R Control Register Map section. The contents of the control registers can be read back using the read sequence shown in Figure 37 or Figure 38. The AD5593R I/O pins are configured by writing to a series of pin configuration registers. The control registers are accessed when Bits[7:4] of the pointer byte are 0b0000. Bits[3:0] determine which register is accessed as shown in Table 11. analog.com On power-up, the I/O pins are configured as 85 kΩ resistors connected to GND. The I/O channels of the AD5593R can be configured to operate as DAC outputs, ADC inputs, digital outputs, digital inputs, three-state, or connected to GND with 85 kΩ pulldown resistors. When configured as digital outputs, the pins have the additional option of being configured as push/pull or open-drain. The I/O channels are configured by writing to the appropriate configuration registers, as shown in Table 11. To assign a particular function for an I/O channel, write to the appropriate register and Rev. F | 23 of 48 Data Sheet AD5593R SERIAL INTERFACE set the corresponding bit to 1. For example, setting Bit 0 in the DAC pin configuration register configures I/O0 as a DAC. In the event that the bit for an I/O channel is set in multiple configuration registers, the I/O channel adopts the function dictated by the last write operation. The exceptions to this rule are that an I/Ox pin can be set as both a DAC and ADC or as a digital input and output. When an I/Ox pin is configured as a DAC and ADC, the primary function is as a DAC and the ADC can be used to measure the voltage being provided by the DAC. This feature can be used to monitor the output voltage to detect short circuits or overload conditions. Figure 40 shows an example of how to configure I/O1 and I/O7 as DACs. When a pin is configured as both a general-purpose input and output, the primary function is as an output pin. This configuration allows the status of the output pin to be determined by programming the GPIO read configuration register and then setting the pointer byte to 0b01100000 . The general-purpose control register contains a lock configuration bit. When the lock configuration bit is set to 1, any writes to the pin configuration registers are ignored, thus preventing the function of the I/O pins from being changed. The I/O pins can be reconfigured any time when the AD5593R is in an idle state, that is, no ADC conversions are taking place and no registers are being read back. The lock configuration bit must also be set to 0. Figure 40. Configuring I/O1 and I/O7 as DACs analog.com Rev. F | 24 of 48 Data Sheet AD5593R SERIAL INTERFACE DAC WRITE OPERATION Data is written to a DAC when the mode bits (Bits[7:4]) of the pointer byte are 0b0001 (see Table 8). Bits[2:0] determine which DAC is addressed (see Table 12). Data to be written to the DAC is contained in the MSB and LSB, as shown in Table 31. Data is written to the selected DAC input register. Data written to the input register can be automatically copied to the DAC register, if required. Data is transferred to the DAC register based on the setting of the LDAC mode register (see Table 23). LDAC Mode Operation The transfer of data from an input register to a DAC register is controlled by Bits[1:0] of the LDAC mode register (pointer byte = 0b00000111). When the LDAC mode bits (Bits[1:0]) are set to 00, new data is automatically transferred from the input register to the DAC register and the analog output updates. When the LDAC mode bits are set to 01, data remains in the input register. This allows writes to input registers without affecting the analog outputs. After loading the input registers with the desired values and setting the LDAC mode bits to 10, the values in the input registers transfer to the DAC registers and the analog outputs update simultaneously. The LDAC mode bits then revert to 01. DAC READBACK The input register of each DAC can be read back via the I2C interface. This can be useful to confirm that the data was received correctly before writing to the LDAC mode register or simply checking what value was last loaded to a DAC. Data can be read back from a DAC only when no ADC conversion sequence is taking place. A DAC input register can be read back using the sequence shown in Figure 37 or Figure 38. The mode dependent bits, Bits[3:0], of the DAC readback mode register (pointer byte = 0b0101XXXX), select which DAC input register is to be read back (see Table 14). When the DAC register is read back as shown in Table 32, the MSB of the most significant data byte is a 1 to indicate that the result is a DAC register. The next three bits (Bits[14:12]) contain the DAC register address (see Table 32) and Bits[11:0] contain the DAC register value. Figure 41 shows an example of reading the input register of DAC2. Figure 41. DAC Input Register Readback analog.com Rev. F | 25 of 48 Data Sheet AD5593R SERIAL INTERFACE ADC OPERATION The ADC channels of the AD5593R operate as a traditional multichannel ADC, where each serial transfer selects the next channel for conversion. The user must write to the ADC pin configuration register (see Table 20) to select the input channels as ADC inputs to be included in the conversion sequence before initiating any conversions. This is done using the I2C write sequence shown in Figure 36. When writing to the ADC sequence register (see Table 18), select which channels are to be converted in sequence. The user can also set the REP bit to have the ADC repeat conversions in the sequence. When the sequence register has been written to, the ADC begins to track the first channel in the sequence. ADC data can be read from the AD5593R using any of the three read operations shown in Figure 37, Figure 38, and Figure 39, with the I2C block read (Figure 39) being the most efficient. If more than one channel is selected in the ADC sequence register, the ADC converts all selected channels sequentially in ascending order. Conversion is started by the rising edge of SCL at the acknowledge (ACK) preceding the MSB (see Figure 39). sequence. If the REP bit is clear, the ADC clocks out the last result on subsequent I2C reads. When ADC data is clocked out by the serial interface, Bit 15 = 0 to indicate that the result is ADC data. Bits[14:12] contain a 3-bit address to indicate which ADC the data is coming from, and Bits[11:0] contain the 12-bit ADC result (see Table 33). Figure 42 shows how to configure the AD5593R to perform ADC conversions. In Step 1, I/O7 and I/O0 are configured as ADCs. Step 2 writes to the ADC sequence register, sets the REP bit, and selects ADC7 and ADC0 for inclusion in the conversion sequence. Step 3 selects the ADCs for reading and Step 4 begins reading the ADC results (see Table 33). The conversions are repeated until a stop condition is given by the controller. The ADC sequence can be changed by writing the new sequence to the ADC sequence register when conversions are not taking place. When a new sequence is written, any channels remaining to be converted from the earlier sequence are ignored and the ADC starts converting the first channel of the new sequence. To stop the ADC conversion sequence, clear the REP, TEMP, and ADC7 to ADC0 bits in the ADC sequence register to 0. If the REP bit is set after all of the selected channels in the sequence register have been converted, the ADC repeats the Figure 42. Configuring the ADC for Conversion analog.com Rev. F | 26 of 48 Data Sheet AD5593R SERIAL INTERFACE GPIO OPERATION Each of the I/Ox pins of the AD5593R can be configured to operate as a general-purpose, digital input or output pin. The function of the pins is determined by writing to the appropriate bit in the GPIO read configuration register and the GPIO write configuration register using the 4-byte I2C write shown in Figure 36. Setting Pins as Outputs To set a pin as a general-purpose output, set the appropriate bit in the GPIO write configuration register (pointer byte = 0b00001000) to 1. For example, setting Bit 0 to 1 enables I/O0 as a general-purpose output. The outputs can be independently configured as push/pull or opendrain outputs. When in push/pull configuration, the output is driven to VDD or GND as determined by the data in the GPIO write data register (pointer byte = 0b00001001). When in open-drain configuration (pointer byte = 0b00001100), the output is driven to GND when a data bit in the GPIO write data register sets the pin low. When the pin is set high, the output is not driven and must be pulled high by an external resistor. This allows multiple output pins to be tied together. If all the pins are normally high, it allows one pin to pull down the others. This is commonly used where multiple pins are used to trigger an alarm or interrupt pin. The state of the output pin is controlled by setting or clearing the bits in the GPIO write data register (pointer byte = 0b00001001). A data bit is ignored if it is written to a location that is not configured as an output. any channels set as DACs to be placed in a power-down state individually. When in power-down, the DAC outputs are three-stated. When a DAC channel is returned into normal mode, the DAC output returns to its previous value. The internal reference and its buffer are powered down by default and are enabled by setting the EN_REF bit in the power-down/reference control register. The internal reference voltage then appears at the VREF pin. There is no dedicated power-down function for the ADC, but the ADC is automatically powered down if none of the I/Ox pins are selected as ADCs. The ADC powers up if a read of the temperature indicator is initiated. The PD_ALL bit powers down all the DACs, the reference, its buffer, and the ADC. The PD_ALL bit also overrides the settings of Bits[9:0]. Table 27 shows the power-down register. RESET FUNCTION The AD5593R can be reset to its default conditions by writing 0x0DAC to the software reset register (pointer byte = 0b00001111). This resets all registers to their default values and reconfigures the I/Ox pins to their default values (85 kΩ pull-down to GND). The reset function is triggered on the SCL falling edge of the eighth bit of the least significant byte (Bit 0 of Frame 4 in Figure 36), and the AD5593R does not generate an ACK signal for this byte of data. The AD5593R has a RESET pin that performs the same function. For normal operation, RESET is tied high. A falling edge on RESET triggers the reset function. Both the hardware and the software reset functions take 100 µs maximum and there must be no activity on the SCL pin of the AD5593R during this time. Setting Pins as Inputs To set an I/Ox pin as a general-purpose input, set the appropriate bit in the GPIO read configuration register (pointer byte = 0b00001010) to 1. For example, setting Bit 0 to 1 enables I/O0 as a general-purpose input. To read the state of general-purpose inputs, set the pointer byte to 0b01100000 (see Table 9) using any of the read operations shown in Figure 37, Figure 38, and Figure 39. The status of any I/O pin set as a general-purpose input appears in the appropriate bit location in the least significant data byte. THREE-STATE PINS The I/Ox pins can be set to three-state by writing to the three-state configuration register (pointer byte = 0b00001101) as shown in Table 29. 85 KΩ PULL-DOWN PINS The I/Ox pins can be connected to GND via a pull-down resistor (85 kΩ) by setting the appropriate bits in the pull-down configuration register (pointer byte = 0b00000110) as shown in Table 22. POWER-DOWN/REFERENCE CONTROL The AD5593R has a power-down/reference control register (pointer byte = 0b00001011) that reduces the power consumption when certain functions are not needed. The power-down register allows analog.com Rev. F | 27 of 48 Data Sheet AD5593R APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5593R is via a serial bus using a standard I2C protocol. The communications channel requires a 2-wire interface consisting of a clock signal and a data signal. AD5593R TO ADSP-BF537 INTERFACE The I2C interface of the AD5593R is designed to be easily connected to industry-standard DSPs and microcontrollers. Figure 43 shows the AD5593R connected to the Analog Devices Blackfin® DSP. The Blackfin has an integrated I2C port that can be connected directly to the I2C pins of the AD5593R. Figure 43. ADSP-BF537 Interface LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board (PCB) on which the AD5593R is mounted must be designed so that the AD5593R lies on the analog plane. The AD5593R must have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. analog.com Rev. F | 28 of 48 Data Sheet AD5593R REGISTER MAP The AD5593R has programmable user configuration registers that are used to configure the device. Table 8 shows a complete list of the pointer byte registers that select the operation to be executed. See Table 9 and the Register Details: AD5593R Pointer Byte Map section for details about the functions of each of the bits. See the Register Details: AD5593R Control Register Map section for details about the functions of each of the bits. The Register Details: AD5593R ADC and DAC Readback section provides data formats for the ADC and the DAC readback. Table 10 shows a complete list of the control registers that configure the I/O pins and various operating parameters in the AD5593R. REGISTER SUMMARY: AD5593R POINTER BYTE MAP Table 8. POINTER_BYTE Register Summary Pointer Byte Bits[7:4] Name Description 0x0 CONFIG_MODE_POINTER Configuration mode. 0x1 DAC_WR_POINTER DAC write mode. 0x2 ADC_RD_POINTER ADC readback mode. 0x3 DAC_RD_POINTER DAC readback mode. 0x4 GPIO_RD_POINTER GPIO readback mode. 0x5 REG_RD_POINTER Register readback mode. REGISTER SUMMARY (BIT-WISE): AD5593R POINTER BYTE MAP Table 9. AD5593R_POINTER MAP Register Summary Mode Bits Mode Dependent Data Bits Mode Bits Bits[7:4] Name Bits 0x0 CONFIG_MODE_POINTER [7:0] CONFIG_MODE_SEL CONFIG_MODE_BITS 0x1 DAC_WR_POINTER [7:0] DAC_WR_SEL DAC_CH_SEL_WR 0x2 ADC_RD_POINTER [7:0] ADC_RD_SEL RESERVED 0x3 DAC_RD_POINTER [7:0] DAC_RD_SEL DAC_CH_SEL_RD 0x4 GPIO_RD_POINTER [7:0] GPIO_RD_SEL RESERVED 0x5 REG_RD_POINTER [7:0] REG_RD_SEL REG_SEL_RD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REGISTER SUMMARY: AD5593R CONTROL REGISTER MAP Table 10. AD5593R_CORE Register Summary Pointer Byte Bits[7:0] Name Description Reset Data Bits[15:0] 0x00 NOP NOP. 0x0000 0x02 ADC_SEQ ADC Sequence Register. 0x0000 0x03 GEN_CTRL_REG General-Purpose Control Register. 0x0000 0x04 ADC_CONFIG ADC Pin Configuration Register. 0x0000 0x05 DAC_CONFIG DAC Pin Configuration Register. 0x0000 0x06 PULLDWN_CONFIG Pull-Down Configuration Register. 0x00FF 0x07 LDAC_MODE LDAC Mode Register. 0x0000 0x08 GPIO_CONFIG GPIO Write Configuration Register. 0x0000 0x09 GPIO_OUTPUT GPIO Write Data Register. 0x0000 0x0A GPIO_INPUT GPIO Read Configuration Register. 0x0000 0x0B PD_REF_CTRL Power-Down/Reference Control Register. 0x0000 0x0C GPIO_OPENDRAIN_CONFIG GPIO Open-Drain Configuration Register. 0x0000 0x0D IO_TS_CONFIG Three-State Configuration Register. 0x0000 analog.com Rev. F | 29 of 48 Data Sheet AD5593R REGISTER MAP Table 10. AD5593R_CORE Register Summary Pointer Byte Bits[7:0] Name Description Reset Data Bits[15:0] 0x0F SW_RESET Software Reset. 0x0000 0x10 DAC_WR DAC Write Register. 0x0000 REGISTER DETAILS: AD5593R POINTER BYTE MAP Configuration Mode Register Reset: 0x00, Name: CONFIG_MODE_POINTER Pointer byte configuration register. Table 11. Bit Descriptions for CONFIG_MODE_POINTER Bits Bit Name Description Reset Access [7:4] CONFIG_MODE_SEL Configuration mode address. 0x0 W [3:0] CONFIG_MODE_BITS Configuration mode dependent data bits. 0x0 W 0000: NOP. No operation. 0010: ADC sequence register. Selects ADCs for conversion. 0011: General-purpose control register. DAC and ADC control register. 0100: ADC pin configuration. Selects which pins are ADC inputs. 0101: DAC pin configuration. Selects which pins are DAC outputs. 0110: Pull-down configuration. Selects which pins have an 85 kΩ pull-down resistor to GND. 0111: LDAC mode. Selects the operation of the load DAC. 1000: GPIO write configuration. Selects which pins are general-purpose outputs. 1001: GPIO write data. Writes data to general-purpose outputs. 1010: GPIO read configuration. Selects which pins are general-purpose inputs. 1011: Power-down/reference control. Powers down the DACs and enables/disables the reference. 1100: Open-drain configuration. Selects open-drain or push-pull for general-purpose outputs. 1101: Three-state pins. Selects which pins are three-stated. 1111: Software reset. Resets the AD5593R. DAC Write Mode Register Reset: 0x10, Name: DAC_WR_POINTER Table 12. Bit Descriptions for DAC_WR_POINTER Bits Bit Name Description Reset Access [7:4] DAC_WR_SEL DAC write mode address. 0x1 W analog.com Rev. F | 30 of 48 Data Sheet AD5593R REGISTER MAP Table 12. Bit Descriptions for DAC_WR_POINTER Bits Bit Name Description Reset Access [3:0] DAC_CH_SEL_WR Select DAC channel for input register write. 0x0 W 000: DAC0. 001: DAC1. 010: DAC2. 011: DAC3. 100: DAC4. 101: DAC5. 110: DAC6. 111: DAC7. ADC Readback Mode Register Reset: 0x40, Name: ADC_RD_POINTER Table 13. Bit Descriptions for ADC_RD_POINTER Bits Bit Name Description Reset Access [7:4] ADC_RD_SEL ADC readback mode address. 0x4 W [3:0] RESERVED Reserved. 0x0 R DAC Readback Mode Register Reset: 0x50, Name: DAC_RD_POINTER Table 14. Bit Descriptions for DAC_RD_POINTER Bits Bit Name Description Reset Access [7:4] DAC_RD_SEL DAC readback mode address. 0x5 W [3:0] DAC_CH_SEL_RD Select DAC channel for input register readback. 0x0 W 000: DAC0. 001: DAC1. 010: DAC2. 011: DAC3. 100: DAC4. 101: DAC5. 110: DAC6. 111: DAC7. analog.com Rev. F | 31 of 48 Data Sheet AD5593R REGISTER MAP GPIO Readback Mode Register Reset: 0x60, Name: GPIO_RD_POINTER Table 15. Bit Descriptions for GPIO_RD_POINTER Bits Bit Name Description Reset Access [7:4] GPIO_RD_SEL GPIO readback mode address. 0x6 W [3:0] RESERVED Reserved. 0x0 R Register Readback Mode Reset: 0x70, Name: REG_RD_POINTER Table 16. Bit Descriptions for REG_RD_POINTER Bits Bit Name Description Reset Access [7:4] REG_RD_SEL Register readback mode address. 0x7 W [3:0] REG_SEL_RD Select control register for register readback. 0x0 W 0000: NOP. 0010: ADC sequence register. 0011: General-purpose control register. 0100: ADC pin configuration. 0101: DAC pin configuration. 0110: Pull-down configuration. 0111: LDAC mode. 1000: GPIO write configuration. 1001: GPIO write data. 1010: GPIO read configuration. 1011: Power-down/reference control. 1100: Open-drain configuration. 1101: Three-state pins. REGISTER DETAILS: AD5593R CONTROL REGISTER MAP NOP Register Reset: 0x0000, Name: NOP No operation. analog.com Rev. F | 32 of 48 Data Sheet AD5593R REGISTER MAP Table 17. Bit Descriptions for NOP Bits Bit Name Description Reset Access [15:11] RESERVED Reserved. 0x0 R [10:0] NOP No operation. 0x0 R/W ADC Sequence Register Reset: 0x0000, Name: ADC_SEQ Selects ADCs for conversion. Table 18. Bit Descriptions for ADC_SEQ Bits Bit Name Description Reset Access [15:10] RESERVED Reserved. 0x0 R 9 REP ADC sequence repetition. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0: Sequence repetition disabled. 1: Sequence repetition enabled. 8 TEMP Include temperature indicator in ADC sequence. 0: Disable temperature indicator readback. 1: Enable temperature indicator readback. 7 ADC7 Include the ADC7 channel in conversion sequence. 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 6 ADC6 Include the ADC6 channel in conversion sequence. 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 5 ADC5 Include the ADC5 channel in conversion sequence. 0: The selected ADC channel is not included in the conversion sequence. analog.com Rev. F | 33 of 48 Data Sheet AD5593R REGISTER MAP Table 18. Bit Descriptions for ADC_SEQ Bits Bit Name Description Reset Access 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 1: Include the selected ADC channel in the conversion sequence. 4 ADC4 Include the ADC4 channel in conversion sequence. 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 3 ADC3 Include the ADC3 channel in conversion sequence. 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 2 ADC2 Include the ADC2 channel in conversion sequence. 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 1 ADC1 Include the ADC1 channel in conversion sequence. 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 0 ADC0 Include the ADC0 channel in conversion sequence. 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. General-Purpose Control Register Reset: 0x0000, Name: GEN_CTRL_REG DAC and ADC control register. Table 19. Bit Descriptions for GEN_CTRL_REG Bits Bit Name Description Reset Access [15:10] RESERVED Reserved. 0x0 R 9 ADC_BUF_PRECH ADC buffer precharge. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0: ADC buffer is not used to precharge the ADC. If the ADC buffer is enabled, it is always powered up. 1: ADC buffer is used to precharge the ADC. If the ADC buffer is enabled, it is powered up while the conversion takes place and then powered down until the next conversion takes place. 8 ADC_BUF_EN ADC buffer enable. 0: ADC buffer is disabled. 1: ADC buffer is enabled. 7 IO_LOCK Lock configuration. 0: The contents of the I/Ox pin configuration register can be changed. 1: The contents of the I/Ox pin configuration register cannot be changed. 6 ALL_DAC analog.com Write all DACs. Rev. F | 34 of 48 Data Sheet AD5593R REGISTER MAP Table 19. Bit Descriptions for GEN_CTRL_REG Bits Bit Name Description Reset Access 0x0 R/W 0x0 R/W 0x0 R 0: For future DAC writes, the DAC address bits determine which DAC is written to. 1: For future DAC writes, the DAC address bits are ignored, and all channels configured as DACs are updated with the same data. 5 ADC_RANGE ADC input range select. 0: ADC gain is 0 V to VREF. 1: ADC gain is 0 V to 2 × VREF. 4 DAC_RANGE DAC output range select. 0: DAC output range is 0 V to VREF. 1: DAC output range is 0 V to 2 × VREF. [3:0] RESERVED Reserved. ADC Pin Configuration Register Reset: 0x0000, Name: ADC_CONFIG Selects which pins are ADC inputs. Table 20. Bit Descriptions for ADC_CONFIG Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R 7 ADC7 Select the I/O7 pin as ADC input. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 6 ADC6 Select the I/O6 pin as ADC input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 5 ADC5 Select the I/O5 pin as ADC input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 4 ADC4 Select the I/O4 pin as ADC input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 3 ADC3 Select the I/O3 pin as ADC input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. analog.com Rev. F | 35 of 48 Data Sheet AD5593R REGISTER MAP Table 20. Bit Descriptions for ADC_CONFIG Bits Bit Name Description Reset Access 2 ADC2 Select the I/O2 pin as ADC input. 0x0 R/W 0x0 R/W 0x0 R/W 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 1 ADC1 Select the I/O1 pin as ADC input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 0 ADC0 Select the I/O0 pin as ADC input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. DAC Pin Configuration Register Reset: 0x0000, Name: DAC_CONFIG Selects which pins are DAC outputs. Table 21. Bit Descriptions for DAC_CONFIG Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R 7 DAC7 Select the I/O7 pin as DAC output. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 6 DAC6 Select the I/O6 pin as DAC output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 5 DAC5 Select the I/O5 pin as DAC output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 4 DAC4 Select the I/O4 pin as DAC output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 3 DAC3 Select the I/O3 pin as DAC output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 2 DAC2 analog.com Select the I/O2 pin as DAC output. Rev. F | 36 of 48 Data Sheet AD5593R REGISTER MAP Table 21. Bit Descriptions for DAC_CONFIG Bits Bit Name Description Reset Access 0x0 R/W 0x0 R/W 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 1 DAC1 Select the I/O1 pin as DAC output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 0 DAC0 Select the I/O0 pin as DAC output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. Pull-Down Configuration Register Reset: 0x00FF, Name: PULLDWN_CONFIG Selects which pins have a 85 kΩ pull-down resistor to GND. Table 22. Bit Descriptions for PULLDWN_CONFIG Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R 7 PULL_DWN_7 Set the I/O7 pin as weak pull-down output. 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 6 PULL_DWN_6 Set the I/O6 pin as weak pull-down output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 5 PULL_DWN_5 Set the I/O5 pin as weak pull-down output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 4 PULL_DWN_4 Set the I/O4 pin as weak pull-down output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 3 PULL_DWN_3 Set the I/O3 pin as weak pull-down output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. analog.com Rev. F | 37 of 48 Data Sheet AD5593R REGISTER MAP Table 22. Bit Descriptions for PULLDWN_CONFIG Bits Bit Name Description Reset Access 2 PULL_DWN_2 Set the I/O2 pin as weak pull-down output. 0x1 R/W 0x1 R/W 0x1 R/W 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 1 PULL_DWN_1 Set the I/O1 pin as weak pull-down output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 0 PULL_DWN_0 Set the I/O0 pin as weak pull-down output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. LDAC Mode Register Reset: 0x0000, Name: LDAC_MODE Selects the operation of the load DAC (LDAC) function. Table 23. Bit Descriptions for LDAC_MODE Bits Bit Name Description Reset Access [15:2] RESERVED Reserved. 0x0 R [1:0] LDAC_MODE Determines how data written to an input register of a DAC is handled. 0x0 R/W 00: Data written to an input register is immediately copied to a DAC register, and the DAC output updates. 01: Data written to an input register is not copied to a DAC register. The DAC output is not updated. 10: Data in the input registers is copied to the corresponding DAC registers. When the data has been transferred, the DAC outputs are updated simultaneously. GPIO Write Configuration Register Reset: 0x0000, Name: GPIO_CONFIG Selects which pins are general-purpose outputs. analog.com Rev. F | 38 of 48 Data Sheet AD5593R REGISTER MAP Table 24. Bit Descriptions for GPIO_CONFIG Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R 7 GPIO7 Select the I/O7 pin as GPIO output. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 6 GPIO6 Select the I/O6 pin as GPIO output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 5 GPIO5 Select the I/O5 pin as GPIO output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 4 GPIO4 Select the I/O4 pin as GPIO output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 3 GPIO3 Select the I/O3 pin as GPIO output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 2 GPIO2 Select the I/O2 pin as GPIO output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 1 GPIO1 Select the I/O1 pin as GPIO output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 0 GPIO0 Select the I/O0 pin as GPIO output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. GPIO Write Data Register Reset: 0x0000, Name: GPIO_OUTPUT Writes data to the general-purpose outputs. analog.com Rev. F | 39 of 48 Data Sheet AD5593R REGISTER MAP Table 25. Bit Descriptions for GPIO_OUTPUT Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R 7 GPIO7 Set the GPIO7 output pin as logic high or low. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 6 GPIO6 Set the GPIO6 output pin as logic high or low. 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 5 GPIO5 Set the GPIO5 output pin as logic high or low. 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 4 GPIO4 Set the GPIO4 output pin as logic high or low. 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 3 GPIO3 Set the GPIO3 output pin as logic high or low. 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 2 GPIO2 Set the GPIO2 output pin as logic high or low. 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 1 GPIO1 Set the GPIO1 output pin as logic high or low. 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 0 GPIO0 Set the GPIO0 output pin as logic high or low. 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. GPIO Read Configuration Register Reset: 0x0000, Name: GPIO_INPUT Selects which pins are general-purpose inputs. Table 26. Bit Descriptions for GPIO_INPUT Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R analog.com Rev. F | 40 of 48 Data Sheet AD5593R REGISTER MAP Table 26. Bit Descriptions for GPIO_INPUT Bits Bit Name Description Reset Access 7 GPIO7 Set the I/O7 pin as GPIO input. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 6 GPIO6 Set the I/O6 pin as GPIO input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 5 GPIO5 Set the I/O5 pin as GPIO input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 4 GPIO4 Set the I/O4 pin as GPIO input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 3 GPIO3 Set the I/O3 pin as GPIO input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 2 GPIO2 Set the I/O2 pin as GPIO input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 1 GPIO1 Set the I/O1 pin as GPIO input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 0 GPIO0 Set the I/O0 pin as GPIO input. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. Power-Down/Reference Control Register Reset: 0x0000, Name: PD_REF_CTRL Powers down DACs and enables/disables the reference. analog.com Rev. F | 41 of 48 Data Sheet AD5593R REGISTER MAP Table 27. Bit Descriptions for PD_REF_CTRL Bits Bit Name Description Reset Access [15:11] RESERVED Reserved. 0x0 R 10 PD_ALL Power down DACs and Internal Reference. 0x0 R/W 0x0 R/W 0: The reference and DACs power-down states are determined by EN_REF and PD7 to PD0 bits. 1: The reference, DACs and ADC are powered down. 9 EN_REF Enable internal reference. Set this bit to 0 if an external reference is used. 0: The reference and its buffer are powered down. 1: The reference and its buffer are powered up. The reference is available on the VREF pin. 8 RESERVED Reserved. 0x0 R 7 PD7 Power down the DAC7 channel. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 6 PD6 Power down the DAC6 channel. 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 5 PD5 Power down the DAC5 channel. 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 4 PD4 Power down the DAC4 channel. 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 3 PD3 Power down the DAC3 channel. 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 2 PD2 Power down the DAC2 channel. 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 1 PD1 Power down the DAC1 channel. 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 0 PD0 Power down the DAC0 channel. 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. GPIO Open-Drain Configuration Register Reset: 0x0000, Name: GPIO_OPENDRAIN_CONFIG Selects open-drain or push/pull for general-purpose outputs. The selected I/Ox pin must be set as digital output pin in the GPIO_CONFIG register. analog.com Rev. F | 42 of 48 Data Sheet AD5593R REGISTER MAP Table 28. Bit Descriptions for GPIO_OPENDRAIN_CONFIG Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R 7 GPIO7 Set the I/O7 pin as open-drain. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 6 GPIO6 Set the I/O6 pin as open-drain. 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 5 GPIO5 Set the I/O5 pin as open-drain. 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 4 GPIO4 Set the I/O4 pin as open-drain. 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 3 GPIO3 Set the I/O3 pin as open-drain. 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 2 GPIO2 Set the I/O2 pin as open-drain. 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 1 GPIO1 Set the I/O1 pin as open-drain. 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 0 GPIO0 Set the I/O0 pin as open-drain. 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. Three-State Configuration Register Reset: 0x0000, Name: IO_TS_CONFIG Selects which pins are three-state. analog.com Rev. F | 43 of 48 Data Sheet AD5593R REGISTER MAP Table 29. Bit Descriptions for IO_TS_CONFIG Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R 7 TS7 Set the I/O7 pin as three-state output. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 6 TS6 Set the I/O6 pin as three-state output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 5 TS5 Set the I/O5 pin as three-state output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 4 TS4 Set the I/O4 pin as three-state output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 3 TS3 Set the I/O3 pin as three-state output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 2 TS2 Set the I/O2 pin as three-state output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 1 TS1 Set the I/O1 pin as three-state output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 0 TS0 Set the I/O0 pin as three-state output. 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. Software Reset Register Reset: 0x0000, Name: SW_RESET Resets the AD5593R. analog.com Rev. F | 44 of 48 Data Sheet AD5593R REGISTER MAP Table 30. Bit Descriptions for SW_RESET Bits Bit Name Description Reset Access [15:11] RESERVED Reserved. 0x0 R [10:0] SW_RESET Write to RESET register. 0x0 R/W 10110101100: Reset the AD5593R. DAC Write Register Reset: 0x0000, Name: DAC_WR Writes to addressed DAC register. Table 31. Bit Descriptions for DAC_WR Bits Bit Name Description Reset Access [15:12] [11:0] RESERVED DAC_DATA_WR Reserved. 12-bit DAC data. 0x0 0x0 R R/W REGISTER DETAILS: AD5593R ADC AND DAC READBACK DAC Data Readback Register Name: DAC_DATA_RD Read back the 12-bit DAC input register data. Table 32. Bit Descriptions for DAC_DATA_RD Bits Bit Name Description Reset 15 MSB MSB. 0x1 [14:12] DAC_ADDR DAC Address. 0x0 000: DAC0. 001: DAC1. 010: DAC2. 011: DAC3. 100: DAC4. 101: DAC5. 110: DAC6. 111: DAC7. [11:0] DAC_DATA analog.com 12-bit DAC Input Register Data. 0x0 Rev. F | 45 of 48 Data Sheet AD5593R REGISTER MAP ADC Conversion Result Register Name: ADC_RESULT ADC conversion result. Table 33. Bit Descriptions for ADC_RESULT Bits Bit Name Description Reset 15 MSB MSB. 0x0 [14:12] ADC_ADDR ADC address. 0x0 000: ADC0. 001: ADC1. 010: ADC2. 011: ADC3. 100: ADC4. 101: ADC5. 110: ADC6. 111: ADC7. [11:0] ADC_DATA 12-bit ADC result. 0x0 Temperature Reading Register Name: TMP_SENSE_RESULT Temperature reading. Table 34. Bit Descriptions for TMP_SENSE_RESULT Bits Bit Name Description Reset [15:12] TMPSENSE_ADDR Temperature Indicator Address. 0x8 [11:0] ADC_DATA 12-bit ADC Result. 0x0 analog.com Rev. F | 46 of 48 Data Sheet AD5593R OUTLINE DIMENSIONS Figure 44. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Figure 45. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-32) Dimensions shown in millimeters Figure 46. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-3) Dimensions shown in millimeters analog.com Rev. F | 47 of 48 Data Sheet AD5593R OUTLINE DIMENSIONS Updated: August 18, 2022 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity AD5593RBCBZ-RL7 AD5593RBCPZ-RL7 AD5593RBRUZ AD5593RBRUZ-RL7 -40°C to +105°C -40°C to +105°C -40°C to +105°C -40°C to +105°C 16-Ball WLCSP (1.96mm x 1.96mm) 16-Lead LFCSP (3mm x 3mm x 0.75mm) 16-Lead TSSOP 16-Lead TSSOP Reel, 3000 Reel, 1500 1 Reel, 1000 Package Option CB-16-3 CP-16-32 RU-16 RU-16 Marking Code DM6 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Description EVAL-AD5593RSDZ EVAL-SDP-CB1Z Evaluation Board Controller Board 1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2014-2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. F | 48 of 48