AD5660ARJ-2500RL7

Single, 12-/14-/16-Bit nanoDAC with 5 ppm/°C On-Chip Reference in SOT-23 AD5620/AD5640/AD5660 FEATURES FUNCTIONAL BLOCK DIAGRAM VREFOUT POWER-ON RESET DAC REGISTER INPUT CONTROL LOGIC GND 1.25/2.5V REF VDD AD5620/AD5640/AD5660 REF(+) VFB OUTPUT BUFFER 16-BIT DAC POWER-DOWN CONTROL LOGIC VOUT RESISTOR NETWORK 04539-001 Low power, single nanoDACs AD5660: 16 bits AD5640: 14 bits AD5620: 12 bits 12-bit accuracy guaranteed On-chip, 1.25 V/2.5 V, 5 ppm/°C reference Tiny 8-lead SOT-23/MSOP packages Power-down to 480 nA @ 5 V, 200 nA @ 3 V 3 V/5 V single power supply Guaranteed 16-bit monotonic by design Power-on reset to zero/midscale 3 power-down functions Serial interface with Schmitt-triggered inputs Rail-to-rail operation SYNC interrupt facility SYNC SCLK DIN Figure 1. GENERAL DESCRIPTION APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 12-/14-/16-bit nanoDAC—12-bit accuracy guaranteed. On-chip, 1.25 V/2.5 V, 5 ppm/°C reference. Available in 8-lead SOT-23 and 8-lead MSOP packages. Power-on reset to 0 V or midscale. 10 μs settling time. Table 1. Related Device Part No. AD5662 Description 2.7 V to 5.5 V, 16-bit DAC in SOT-23, external reference The AD5620/AD5640/AD5660, members of the nanoDAC™ family of devices, are low power, single, 12-/14-/16-bit, buffered voltage-out DACs and are guaranteed monotonic by design. The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/°C reference, giving a full-scale output voltage range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output voltage range of 5 V. The reference associated with each part is available at the VREFOUT pin. The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2) or midscale (AD5620-3 and AD5660-3) and remains there until a valid write takes place. The parts contain a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The power consumption is 2.5 mW at 5 V, reducing to 1 μW in power-down mode. The AD5620/AD5640/AD5660 on-chip precision output amplifier allows rail-to-rail output swing to be achieved. For remote sensing applications, the output amplifier’s inverting input is available to the user. The AD5620/AD5640/AD5660 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved. AD5620/AD5640/AD5660 TABLE OF CONTENTS Features .............................................................................................. 1  Internal Reference ...................................................................... 17  Applications ....................................................................................... 1  Output Amplifier........................................................................ 17  Product Highlights ........................................................................... 1  Serial Interface ............................................................................ 17  Functional Block Diagram .............................................................. 1  Input Shift Register .................................................................... 18  General Description ......................................................................... 1  SYNC Interrupt .......................................................................... 18  Revision History ............................................................................... 2  Power-On Reset .......................................................................... 19  Specifications..................................................................................... 3  Power-Down Modes .................................................................. 19  AD5620/AD5640/AD5660-2-3 .................................................. 3  Microprocessor Interfacing ....................................................... 19  AD5620/AD5640/AD5660-1 ...................................................... 5  Applications Information .............................................................. 21  Timing Characteristics ................................................................ 7  Using a REF19x as a Power Supply for the AD5620/AD5640/AD5660 ....................................................... 21  Absolute Maximum Ratings............................................................ 8  ESD Caution .................................................................................. 8  Pin Configurations and Function Descriptions ........................... 9  Typical Performance Characteristics ........................................... 10  Bipolar Operation Using the AD5660 ..................................... 21  Using the AD5660 as an Isolated, Programmable, 4 mA to 20 mA Process Controller ......................................................... 22  Terminology .................................................................................... 16  Using the AD5620/AD5640/AD5660 with a Galvanically Isolated Interface ........................................................................ 22  Theory of Operation ...................................................................... 17  Power Supply Bypassing and Grounding ................................ 23  D/A Section ................................................................................. 17  Outline Dimensions ....................................................................... 24  Resistor String ............................................................................. 17  Ordering Guide .......................................................................... 25  REVISION HISTORY 12/10—Rev. E to Rev. F Changes to Ordering Guide .......................................................... 25 7/10—Rev. D to Rev. E Moved Using the AD5660 as an Isolated, Programmable, 4 mA to 20 mA Process Controller Section ........................................... 22 Moved Power Supply Bypassing and Grounding Section ......... 23 Changes to Ordering Guide .......................................................... 25 3/10—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 24 10/09—Rev. B to Rev. C Changes to Ordering Guide .......................................................... 23 5/06—Rev. A to Rev. B Updated Formatted ............................................................ Universal Updated Temperature Range ............................................ Universal Changes to Table 2.............................................................................3 Changes to Table 5.............................................................................8 Replaced Figure 17, Figure 18, and Figure 19............................. 12 Changes to Ordering Guides .................................................. 23, 24 9/05—Rev. 0 to Rev. A Changes to Specifications .................................................................5 Changes to Outline Dimensions .................................................. 23 7/05—Revision 0: Initial Version Rev. F | Page 2 of 28 AD5620/AD5640/AD5660 SPECIFICATIONS AD5620/AD5640/AD5660-2-3 VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, CREFOUT = 100 nF; all specifications TMIN to TMAX, unless otherwise noted. Table 2. A Grade1 B Grade1 C Grade1 Unit Conditions/Comments 16 ±32 ±1 16 ±16 ±1 16 ±16 ±1 Bits min LSB max LSB max Guaranteed monotonic by design 14 ±8 ±0.5 14 ±4 ±0.5 14 ±4 ±0.5 Bits min LSB max LSB max Guaranteed monotonic by design 12 ±6 ±0.25 2 10 ±10 −0.15 ±1 ±1.5 ±2 ±2.5 −75 12 ±1 ±0.25 2 10 ±10 −0.15 ±1 ±1.5 ±2 ±2.5 −75 12 ±1 ±0.25 2 10 ±10 −0.15 ±1 ±1.5 ±2 ±2.5 −75 Bits min LSB max LSB max mV typ mV max mV max % FSR typ % FSR max % FSR max μV/°C typ ppm typ dB typ 0 VDD 8 10 1.5 2 10 80 45 5 0.1 0.5 30 5 0 VDD 8 10 1.5 2 10 80 45 5 0.1 0.5 30 5 0 VDD 8 10 1.5 2 10 80 45 5 0.1 0.5 30 5 V min V max μs typ μs max V/μs typ nF typ nF typ nV/√Hz typ μV p-p typ nV-s typ nV-s typ Ω typ mA typ μs typ Reference TC3 2.495 2.505 ±10 2.495 2.505 ±10 Output Impedance 7.5 7.5 2.495 2.505 ±5 ±10 7.5 V min V max ppm/°C typ ppm/°C max kΩ typ Parameter STATIC PERFORMANCE2 AD5660 Resolution Relative Accuracy Differential Nonlinearity AD5640 Resolution Relative Accuracy Differential Nonlinearity AD5620 Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio OUTPUT CHARACTERISTICS3 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Output Noise Spectral Density Output Noise (0.1 Hz to 10 Hz) Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE OUTPUT Output Voltage Rev. F | Page 3 of 28 Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register Of FSR/°C DAC code = midscale; VDD = 5 V ± 10% ¼ to ¾ scale change settling to ±2 LSB RL = 2 kΩ; 0 pF < CL < 200 pF ¼ to ¾ scale RL = ∞ RL = 2 kΩ DAC code = midscale, 10 kHz DAC code = midscale 1 LSB change around major carry VDD = 5 V Coming out of power-down mode; VDD = 5 V At ambient AD5620/AD5640/AD5660 Parameter LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V A Grade1 B Grade1 C Grade1 Unit Conditions/Comments ±2 0.8 2 3 ±2 0.8 2 3 ±2 0.8 2 3 μA max V max V min pF typ All digital inputs VDD = 5 V VDD = 5 V 4.5 5.5 4.5 5.5 4.5 5.5 V min V max All digital inputs at 0 V or VDD DAC active and excluding load current 0.55 1 0.55 1 0.55 1 mA typ mA max VIH = VDD and VIL = GND VIH = VDD and VIL = GND 0.48 1 0.48 1 0.48 1 μA typ μA max VIH = VDD and VIL = GND VIH = VDD and VIL = GND 1 Temperature range is −40°C to +105°C, typical at +25°C. Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output unloaded. Linearity tested with VDD = 5.5 V. If part is operated with a VDD < 5 V, the output is clamped to VDD. 3 Guaranteed by design and characterization; not production tested. 2 Rev. F | Page 4 of 28 AD5620/AD5640/AD5660 AD5620/AD5640/AD5660-1 VDD1 = 2.7 V to 3.3 V, RL = 2 kΩ to GND, CL = 200 pF to GND, CREFOUT = 100 nF; all specifications TMIN to TMAX, unless otherwise noted. Table 3. A Grade2 B Grade2 C Grade2 Unit Conditions/Comments 16 ±32 ±1 16 ±16 ±1 16 ±16 ±1 Bits min LSB max LSB max Guaranteed monotonic by design 14 ±8 ±0.5 14 ±4 ±0.5 14 ±4 ±0.5 Bits min LSB max LSB max Guaranteed monotonic by design 12 ±6 ±0.25 2 8 ±9 ±0.15 ±0.85 ±0.85 ±2 ±2.5 −60 12 ±1 ±0.25 2 8 ±9 ±0.15 ±0.85 ±0.85 ±2 ±2.5 −60 12 ±1 ±0.25 2 8 ±9 ±0.15 ±0.85 ±0.85 ±2 ±2.5 −60 Bits min LSB max LSB max mV typ mV max mV max % FSR typ % FSR max % FSR max μV/°C typ ppm typ dB typ 0 VDD 8 10 1.5 2 10 80 20 5 0.1 0.5 30 6 0 VDD 8 10 1.5 2 10 80 20 5 0.1 0.5 30 6 VDD 8 10 1.5 2 10 80 20 5 0.1 0.5 30 6 V min V max μs typ μs max V/μs typ nF typ nF typ nV/√Hz typ μV p-p typ nV-s typ nV-s typ Ω typ mA typ μs typ Reference TC4 1.247 1.253 ±10 1.247 1.253 ±10 Output Impedance 7.5 7.5 1.247 1.253 ±5 ±15 7.5 V min V max ppm/°C typ ppm/°C max kΩ typ Parameter STATIC PERFORMANCE3 AD5660 Resolution Relative Accuracy Differential Nonlinearity AD5640 Resolution Relative Accuracy Differential Nonlinearity AD5620 Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio OUTPUT CHARACTERISTICS4 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Output Noise Spectral Density Output Noise (0.1 Hz to 10 Hz) Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE OUTPUT Output Voltage Rev. F | Page 5 of 28 Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register Of FSR/°C DAC code = midscale; VDD = 3 V ± 10% ¼ to ¾ scale change settling to ±2 LSB RL = 2 kΩ; 0 pF < CL < 200 pF ¼ to ¾ scale RL = ∞ RL = 2 kΩ DAC code = midscale, 10 kHz DAC code = midscale 1 LSB change around major carry VDD = 3 V Coming out of power-down mode; VDD = 3 V At ambient AD5620/AD5640/AD5660 Parameter LOGIC INPUTS4 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 2.7 V to 3.3 V VDD = 2.7 V to 3.3 V IDD (All Power-Down Modes) VDD = 2.7 V to 3.3 V VDD = 2.7 V to 3.3 V A Grade2 B Grade2 C Grade2 Unit Conditions/Comments ±1 0.8 2 3 ±1 0.8 2 3 ±1 0.8 2 3 μA max V max V min pF max All digital inputs VDD = 3 V VDD = 3 V 2.7 3.3 2.7 3.3 2.7 3.3 V min V max All digital inputs at 0 V or VDD DAC active and excluding load current 0.55 0.65 0.55 0.65 0.55 0.65 mA typ mA max VIH = VDD and VIL = GND VIH = VDD and VIL = GND 0.2 0.25 0.2 0.25 0.2 0.25 μA typ μA max VIH = VDD and VIL = GND VIH = VDD and VIL = GND 1 Part is functional with VDD up to 5.5 V. Temperature range is −40°C to +105°C, typical at +25°C. 3 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output unloaded. 4 Guaranteed by design and characterization; not production tested. 2 Rev. F | Page 6 of 28 AD5620/AD5640/AD5660 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V 50 33 13 13 13 13 13 13 5 5 4.5 4.5 0 0 50 33 13 13 0 0 Parameter t11 t2 t3 t4 t5 t6 t7 t8 t9 t10 Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to SCLK fall ignore SCLK falling edge to SYNC fall ignore Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V. t10 t1 t9 SCLK t8 t3 t4 t2 t7 SYNC t5 DIN t6 MSB LSB 04539-002 1 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min LSB = DB0 MSB = DB23 FOR AD5660 MSB = DB15 FOR AD5620/AD5640 Figure 2. Serial Write Operation Rev. F | Page 7 of 28 AD5620/AD5640/AD5660 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND VOUT to GND VFB to GND VREFOUT to GND Digital Input Voltage to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation SOT-23 Package (4-Layer Board) θJA Thermal Impedance MSOP Package (4-Layer Board) θJA Thermal Impedance θJC Thermal Impedance Reflow Soldering Peak Temperature SnPb Pb-Free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +105°C −65°C to +150°C 150°C (TJ max − TA)/θJA 119°C/W 141°C/W 44°C/W 240°C 260°C Rev. F | Page 8 of 28 AD5620/AD5640/AD5660 VREFOUT 2 AD5620/ AD5640/ AD5660 8 GND 7 DIN 6 SCLK TOP VIEW (Not to Scale) VOUT 4 5 SYNC VFB 3 VDD 1 VREFOUT 2 VFB 3 04539-003 VDD 1 VOUT 4 AD5620/ AD5640/ AD5660 TOP VIEW (Not to Scale) 8 GND 7 DIN 6 SCLK 5 SYNC 04539-004 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. MSOP Pin Configuration Figure 3. SOT-23 Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic VDD VREFOUT VFB VOUT SYNC 6 SCLK 7 DIN 8 GND Description Power Supply Input. These parts can operate from 2.7 V to 5.5 V. VDD should be decoupled to GND. Reference Voltage Output. Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation. Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle for the AD5660 and the 16th clock cycle for AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Ground Reference Point for all Circuitry on the Part. Rev. F | Page 9 of 28 AD5620/AD5640/AD5660 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 10 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.6 4 0.4 0 –0.2 –4 –0.4 –6 –0.6 55000 60000 65000 15000 16250 50000 13750 45000 40000 35000 30000 25000 0 20000 –1.0 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 5000 10000 –0.8 15000 –8 –10 10000 0 –2 0.2 5000 2 04539-008 DNL ERROR (LSB) 6 0 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.8 04539-005 INL ERROR (LSB) 8 CODE CODE Figure 5. INL—AD5660-2/AD5660-3 Figure 8. DNL—AD5660-2/AD5660-3 0.5 4 VDD = 5V VREFOUT = 2.5V TA = 25°C 3 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.4 0.3 DNL ERROR (LSB) INL ERROR (LSB) 2 1 0 –1 0.2 0.1 0 –0.1 –0.2 –2 04539-006 –0.4 12500 11250 10000 8750 7500 6250 5000 3750 2500 0 1250 –0.5 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 –4 04539-009 –0.3 –3 CODE CODE Figure 6. INL—AD5640-2/AD5640-3 Figure 9. DNL—AD5640-2/AD5640-3 1.0 0.20 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.8 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.15 0.6 DNL ERROR (LSB) 0.2 0 –0.2 0.05 0 –0.05 –0.4 –0.10 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 04539-010 –0.15 04539-007 INL ERROR (LSB) 0.10 0.4 –0.20 0 4000 Figure 7. INL—AD5620-2/AD6520-3 500 1000 1500 2000 2500 CODE 3000 Figure 10. DNL—AD5620-2/AD6520-3 Rev. F | Page 10 of 28 3500 4000 AD5620/AD5640/AD5660 10 1.0 VDD = 3V VREFOUT = 1.25V TA = 25C 0.6 4 0.4 0 –0.2 –4 –0.4 –6 –0.6 55000 60000 65000 15000 16250 50000 45000 40000 35000 13750 CODE 30000 25000 0 20000 –1.0 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 0 –0.8 15000 –8 –10 5000 0 –2 0.2 10000 2 04539-020 DNL ERROR (LSB) 6 5000 VDD = 3V VREFOUT = 1.25V TA = 25C 0.8 04539-017 INL ERROR (LSB) 8 CODE Figure 11. INL—AD5660-1 Figure 14. DNL—AD5660-1 4 0.5 VDD = 3V VREFOUT = 1.25V TA = 25C 3 VDD = 3V VREFOUT = 1.25V TA = 25C 0.4 0.3 DNL ERROR (LSB) INL ERROR (LSB) 2 1 0 –1 0.2 0.1 0 –0.1 –0.2 –2 04539-018 –0.4 CODE 12500 11250 8750 10000 7500 6250 5000 3750 2500 0 1250 –0.5 16250 15000 13750 12500 11250 8750 10000 7500 6250 5000 3750 2500 0 1250 –4 04539-021 –0.3 –3 CODE Figure 12. INL—AD5640-1 Figure 15. DNL—AD5640-1 1.0 0.20 VDD = 3V VREFOUT = 1.25V TA = 25C 0.8 0.6 VDD = 3V VREFOUT = 1.25V TA = 25C 0.15 DNL ERROR (LSB) 0.2 0 –0.2 0.05 0 –0.05 –0.4 –0.10 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 04539-025 –0.15 04539-019 INL ERROR (LSB) 0.10 0.4 –0.20 4000 0 Figure 13. INL—AD5620-1 500 1000 1500 2000 2500 CODE Figure 16. DNL—AD5620-1 Rev. F | Page 11 of 28 3000 3500 4000 AD5620/AD5640/AD5660 12 200 VDD = 5V 10 8 160 NUMBER OF DEVICES MAX INL 6 4 2 MAX DNL 0 –2 MIN DNL –4 –6 140 120 100 80 60 40 VDD = 3.3V –8 –20 0 20 40 60 80 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0.65 0.66 0.67 –10 –12 –40 20 04539-011 MIN INL 04539-014 ERROR (LSB) VDD = 5V TA = 25C 180 100 IDD (mA) TEMPERATURE (°C) Figure 17. INL Error and DNL Error vs. Temperature Figure 20. IDD Histogram 0.4 VDD = 5V 0.50 DAC LOADED WITH FULL-SCALE SOURCING CURRENT 0.40 0.30 GAIN ERROR 0 FULL SCALE ERROR –0.2 0.20 VDD = 3V VREFOUT = 1.25V 0.10 0 –0.10 –0.20 VDD = 5V VREFOUT = 2.5V –0.4 04539-012 –0.30 –40 –20 0 20 40 60 80 04539-022 ERROR VOLTAGE (V) ERROR (%FSR) 0.2 DAC LOADED WITH ZERO-SCALE SINKING CURRENT –0.40 –0.50 –10 100 –8 –6 –4 TEMPERATURE (°C) –2 0 2 CURRENT (mA) 4 6 8 10 Figure 21. Headroom at Rails vs. Source and Sink Figure 18. Gain Error and Full-Scale Error vs. Temperature 1.6 VDD = 5V 6.00 1.4 5.00 FULL SCALE 3/4 SCALE 4.00 ZERO CODE ERROR VOUT (V) 1.0 0.8 0.6 3.00 MIDSCALE 2.00 1/4 SCALE OFFSET ERROR 1.00 0.2 0 –40 –20 0 20 40 60 80 0 –1.00 –30 100 TEMPERATURE (°C) Figure 19. Zero-Code and Offset Error vs. Temperature ZERO SCALE –20 –10 0 10 CURRENT (mA) 20 Figure 22. Source and Sink Capability—AD5660-2/AD5660-3 Rev. F | Page 12 of 28 04539-023 0.4 04539-013 ERROR (mV) 1.2 VDD = 5V VREFOUT = 2.5V TA = 25C 30 AD5620/AD5640/AD5660 4.00 VDD = 3V VREFOUT = 1.25V TA = 25C 3.00 VDD = 5V TA = 25C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2k AND 200pF TO GND 3/4 SCALE 2.00 MIDSCALE 1.00 1/4 SCALE VOUT = 909mV/DIV 0 ZERO SCALE 04539-024 –1.00 –30 1 –20 –10 0 10 CURRENT (mA) 20 04539-028 VOUT (V) FULL SCALE 30 TIME BASE = 4s/DIV Figure 26. Full-Scale Settling Time, 5 V Figure 23. Source and Sink Capability—AD5660-1 0.7 VDD = 5V TA = 25C VDD 0.6 VDD = 3V 0.5 VREF 2 0.3 0.2 VOUT 0 512 3 04539-015 0.1 10512 20512 30512 40512 CODE 50512 60512 04539-029 IDD (mA) 1 0.4 CH1 2.00V CH2 2.00V CH3 100mV Figure 24. Supply Current vs. Code M40.0ms CH1 Figure 27. Power-On Reset to 0 V—AD5660-2 1400 TA = 25C 1200 VDD 1000 800 2 VDD = 5V VREF 600 VDD = 3V 200 VOUT 0 0 1 2 3 4 04539-030 400 04539-016 IDD (A) 1 3 CH1 2.00V CH2 2.00V CH3 200mV 5 VLOGIC (V) M20.0s CH1 1.88V Figure 28. Power-On Reset to Midscale—AD5660-3 Figure 25. Supply Current vs. Logic Input Voltage Rev. F | Page 13 of 28 AD5620/AD5640/AD5660 1.250800 1.250600 1.250400 VDD 1.250200 1 VREF 1.249800 1.249600 1.249400 VDD = 3V VREFOUT = 1.25V TA = 25C 13nS/SAMPLE NUMBER 1LSB CHANGE AROUND MIDSCALE (0x7FFF TO 0x8000) GLITCH IMPULSE = 0.284nV-s 1.249200 VOUT 1.249000 1.248800 04539-031 3 CH1 1.20V CH2 1.00V CH3 100mV M100s CH1 1.248600 04539-033 2 AMPLITUDE 1.250000 1.248400 1.87V 0 Figure 29. Power-On Reset to 0 V—AD5660-1 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550 Figure 32. Digital-to-Analog Glitch Impulse—AD5660-1 2.500250 VDD = 3V SCLK VDD = 5V TA = 25C 20nS/SAMPLE NUMBER DAC LOADED WITH MIDSCALE DIGITAL FEEDTHROUGH = 0.06nV-s 2.500200 2.500150 1 2.500100 AMPLITUDE 2.500050 2.500000 2.499950 2.499900 2.499850 2.499800 3 2.499750 CH1 2.00V CH3 50.0mV M1.00s CH2 04539-034 2.499700 04539-055 VOUT 2.499650 2.499600 520mV 0 50 Figure 30. Exiting Power-Down to Midscale 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550 Figure 33. Digital Feedthrough 2.501250 16 TA = 25C 2.501000 2.500750 14 2.500500 VDD = 3V 12 TIME (s) 2.500000 2.499750 2.499500 VDD = 5V VREFOUT = 2.5V TA = 25C 13nS/SAMPLE NUMBER 1LSB CHANGE AROUND MIDSCALE (0x7FFF TO 0x8000) GLITCH IMPULSE = 0.497nV-s 2.499000 2.498750 2.498500 2.498250 2.498000 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 10 VDD = 5V 8 6 450 500 550 04539-036 2.499250 04539-032 AMPLITUDE 2.500250 4 0 1 2 3 4 5 6 7 CAPACITANCE (nF) 8 Figure 34. Settling Time vs. Capacitive Load Figure 31. Digital-to-Analog Glitch Impulse—AD5660-2/AD5660-3 Rev. F | Page 14 of 28 9 10 AD5620/AD5640/AD5660 800 1 500 400 300 VDD = 5V VREFOUT = 2.5V 200 0 100 Figure 35. 0.1 Hz to 10 Hz Output Noise—AD5660-2/AD5660-3 VDD = 3V VREFOUT = 1.25V 1000 10000 FREQUENCY (Hz) 100000 Figure 37. Noise Spectral Density VDD = 3V VREFOUT = 1.25V TA = 25C DAC LOADED WITH MIDSCALE 1 04539-054 5V/DIV 600 100 5s/DIV TA = 25C MIDSCALE LOADED 04539-038 OUTPUT NOISE (nVHz) 700 04539-037 10V/DIV VDD = 5V VREFOUT = 2.5V TA = 25C DAC LOADED WITH MIDSCALE 4s/DIV Figure 36. 0.1 Hz to 10 Hz Output Noise—AD5660-1 Rev. F | Page 15 of 28 1000000 AD5620/AD5640/AD5660 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Figure 5 through Figure 7 show typical INL vs. code. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Figure 8 through Figure 10 show typical DNL vs. code. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5620/AD5640/AD5660, because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. Figure 19 shows a plot of zero-code error vs. temperature. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed as a percentage of the full-scale range. Figure 18 shows a plot of fullscale error vs. temperature. Gain Error This is a measurement of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. Zero-Code Error Drift This is a measurement of the change in zero-code error with a change in temperature. It is expressed in μV/°C. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Offset Error Offset error is a measurement of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5660 with Code 512 loaded into the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. It is measured in dB. VREF is held at 2.5 V, and VDD is varied by ±10%. Output Voltage Settling Time This indicates the amount of time for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change. It is measured from the 24th falling edge of SCLK. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31 and Figure 32. Digital Feedthrough Digital feedthrough is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s or vice versa. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. Figure 37 shows a plot of noise spectral density. Rev. F | Page 16 of 28 AD5620/AD5640/AD5660 THEORY OF OPERATION D/A SECTION The AD5620/AD5640/AD5660 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/°C reference that is internally gained up by 2. Figure 38 shows a block diagram of the DAC architecture. VDD R VFB R REF (+) RESISTOR STRING VOUT
REF (–) OUTPUT AMPLIFIER GND 04777-022 DAC REGISTER Figure 38. DAC Architecture tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. INTERNAL REFERENCE The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/°C reference, giving a full-scale output voltage of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output voltage of 5 V. The reference associated with each part is available at the VREFOUT pin. A buffer is required if the reference output is used to drive external loads. It is recommended that a 100 nF capacitor is placed between the reference output and GND for reference stability. OUTPUT AMPLIFIER Because the input coding to the DAC is straight binary, the ideal output voltage is given by D VOUT  2  VREFOUT   N  2  where: D is the decimal equivalent of the binary code that is loaded to the DAC register. 0 to 4095 for AD5620 (12 bit) 0 to 16383 for AD5640 (14 bit) 0 to 65535 for AD5660 (16 bit) N is the DAC resolution. The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. This output buffer amplifier has a gain of 2 derived from a 50 kΩ resistor divider network in the feedback path. The inverting input of the output amplifier is available to the user, allowing for remote sensing. This VFB pin must be connected to VOUT for normal operation. It can drive a load of 2 kΩ in parallel with 1000 pF to GND. Figure 21 shows the source and sink capabilities of the output amplifier. The slew rate is 1.5 V/μs with a ¼ to ¾ fullscale settling time of 10 μs. SERIAL INTERFACE The AD5620/AD5640/AD5660 have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. R R TO OUTPUT AMPLIFIER R R 04539-040 R Figure 39. Resistor String RESISTOR STRING The resistor string section is shown in Figure 39. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register (AD5620/AD5640) or the 24-bit shift register (AD5660) on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5620/AD5640/AD5660 compatible with high speed DSPs. On the 16th falling clock edge (AD5620/ AD5640) or the 24th falling clock edge (AD5660), the last data bit is clocked in and the programmed function is executed, that is, a change in the DAC register contents and/or a change in the mode of operation is executed. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when VIN = 2 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the parts. As is mentioned previously, however, SYNC must be brought high again just before the next write sequence. Rev. F | Page 17 of 28 AD5620/AD5640/AD5660 INPUT SHIFT REGISTER SYNC INTERRUPT AD5620/AD5640 In a normal write sequence for the AD5660, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 43). Similarly, in a normal write sequence for the AD5620/AD5640, the SYNC line is kept low for at least 16 falling edges of SCLK, and the DAC is updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an interrupt to the write sequence. The input shift register is 16 bits wide for the AD5620/AD5640 (see Figure 40 and Figure 41). The first two bits are control bits that control which mode of operation the part is in (normal mode or any of the three power-down modes). The next 14/12 bits, respectively, are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK. AD5660 The input shift register is 24 bits wide for the AD5660 (see Figure 42). The first six bits are don’t care bits. The next two are control bits that control which mode of operation the part is in (normal mode or any of the three power-down modes). For a more complete description of the various modes, see the Power-Down Modes section. The next 16 bits are the data bits. These are transferred to the DAC register on the 24th falling edge of SCLK. PD1 PD0 DB0 (LSB) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 04539-041 DB15 (MSB) DATA BITS Figure 40. AD5620 Input Register Contents PD1 PD0 DB0 (LSB) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 04539-042 DB15 (MSB) DATA BITS Figure 41. AD5640 Input Register Contents X X DB0 (LSB) X X X X PD1 PD0 D15 D14 D13 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 04539-043 DB23 (MSB) DATA BITS Figure 42. AD5660 Input Register Contents SCLK SYNC MSB LSB MSB INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 16TH/24TH FALLING EDGE LSB VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 16TH/24TH FALLING EDGE Figure 43. SYNC Interrupt Facility Rev. F | Page 18 of 28 04539-044 DIN AD5620/AD5640/AD5660 POWER-ON RESET RESISTOR STRING DAC Table 7. Modes of Operation for the AD5660 1 0 1 MICROPROCESSOR INTERFACING AD5660 Operating Mode Normal operation Power-down modes: 1 kΩ to GND 100 kΩ to GND Three-state AD5660-to-Blackfin® ADSP-BF53x Interface Table 8. Modes of Operation for the AD5620/AD5640 DB15 0 DB14 0 0 1 1 1 0 1 The bias generator, output amplifier, reference, resistor string, and other associated linear circuitry are all shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 5 μs for VDD = 5 V and VDD = 3 V (see Figure 30). AD5620/AD5640 Operating Mode Normal operation Power-down modes: 1 kΩ to GND 100 kΩ to GND Three-state When both bits are set to 0, the part works normally with its normal power consumption of 550 μA at 5 V. However, for the three power-down modes, the supply current falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply current fall, but the output stage is internally switched from the output of the amplifier to a resistor network of known values. The advantage is that the output impedance of the part is known while the part is in power-down mode. There are three options: the output is connected internally to GND through a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited (three-stated). The output stage is shown in Figure 44. Figure 45 shows a serial interface between the AD5660 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5660, the setup for the interface is as follows: DT0PRI drives the DIN pin of the AD5660, while TSCLK0 drives the SCLK of the part and SYNC is driven from TFS0. ADSP-BF53x1 TFS0 1 ADDITIONAL Rev. F | Page 19 of 28 AD56601 SYNC DTOPRI DIN TSCLK0 SCLK PINS OMITTED FOR CLARITY Figure 45. AD5660-to-Blackfin ADSP-BF53x Interface 04539-046 0 1 1 RESISTOR NETWORK Figure 44. Output Stage During Power-Down The AD5620/AD5640/AD5660 have four separate modes of operation. These modes are software-programmable by setting two bits in the control register. Table 7 and Table 8 show how the state of the bits corresponds to the operating mode of the device. DB16 0 VOUT POWER-DOWN CIRCUITRY POWER-DOWN MODES DB17 0 AMPLIFIER 04539-045 The AD5620/AD5640/AD5660 family contains a power-on reset circuit that controls the output voltage during power-up. The AD5620/AD5640/AD5660-1-2 DAC output powers up to 0 V, and the AD5620/AD5660-3 DAC output powers up to midscale. The output remains at this level until a valid write sequence is made to the DAC, which is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up. AD5620/AD5640/AD5660 Figure 46 shows a serial interface between the AD5660 and the 68HC11/68L11 microcontroller. SCK of 68HC11/68L11 drives the SCLK of AD5660, and the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: The 68HC11/68L11 should be configured so that its CPOL bit is 0, and its CPHA bit is 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured in this way, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5660, PC7 is left low after the first eight bits are transferred, a second serial write operation is performed to the DAC, and PC7 is taken high at the end of this procedure. AD56601 PC7 SYNC SCK SCLK MOSI DIN 80C51/80L511 AD56601 P3.3 SYNC TxD SCLK RxD DIN 1 ADDITIONAL PINS OMITTED FOR CLARITY Figure 47. AD5660-to-80C51/80L51 Interface AD5660-to-MICROWIRE Interface 04539-047 68HC11/68L111 data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 output the serial data LSB first; however, the AD5660 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account. 04539-048 AD5660-to-68HC11/68L11 Interface Figure 48 shows an interface between the AD5660 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5660 on the rising edge of the SK. 1 ADDITIONAL PINS OMITTED FOR CLARITY MICROWIRE1 AD56601 AD5660-to-80C51/80L51 Interface Figure 47 shows a serial interface between the AD5660 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5660, and RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, Port Line P3.3 is used. When data is to be transmitted to the AD5660, P3.3 is taken low. The 80C51/80L51 transmit CS SYNC SK SCLK SO DIN 1 ADDITIONAL PINS OMITTED FOR CLARITY Rev. F | Page 20 of 28 Figure 48. AD5660-to-MICROWIRE Interface 04539-049 Figure 46. AD5660-to-68HC11/68L11 Interface AD5620/AD5640/AD5660 APPLICATIONS INFORMATION USING A REF19x AS A POWER SUPPLY FOR THE AD5620/AD5640/AD5660 BIPOLAR OPERATION USING THE AD5660 Because the supply current required by the AD5620/AD5640/ AD5660 is extremely low, an alternative option is to use a REF19x voltage reference (REF195 for 5 V or REF193 for 3 V) to supply the required voltage to the part (see Figure 49). This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The REF19x outputs a steady supply voltage for the AD5620/ AD5640/AD5660. If the low dropout REF195 is used, the current it needs to supply to the AD5660 is 500 μA. This is with no load on the output of the DAC. When the DAC output is loaded, the REF195 also must supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is The AD5660 is designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 50. Figure 50 gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as D   R1  R2    R2  VO  VDD      VDD     R1   65536   R1   where D represents the input code in decimal (0 to 65535). When VDD = 5 V, R1 = R2 = 10 kΩ, 10  D  VO   5 V  65536  500 μA + (5 V/5 kΩ) = 1.5 mA The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 3 ppm (15 μV) for the 1.5 mA current drawn from it. This corresponds to a 0.197 LSB error for the AD5660. This results in an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output and 0xFFFF corresponding to a +5 V output. R2 10k 15V 5V SCLK AD5660 VDD VOUT = 0V TO 5V DIN 10F 04539-050 3-WIRE SERIAL INTERFACE SYNC Figure 49. REF195 as the Power Supply to the AD5660 +5V R1 10k +5V 0.1F VFB VOUT AD5660 AD820/ OP295 –5V 3-WIRE SERIAL INTERFACE Figure 50. Bipolar Operation with the AD5660 Rev. F | Page 21 of 28 ±5V 04539-051 REF195 AD5620/AD5640/AD5660 ADR02 VLOOP 12V TO 36V R2 18.5k P2 4mA ADJUST AD5660 R1 4.7k P1 20mA ADJUST AD8627 R6 3.3k Q1 2N3904 D1 R3 1.5k 4–20mA RL R7 100 04539-052 SERIAL LOAD Figure 51. Programmable 4 mA to 20 mA Process Controller USING THE AD5660 AS AN ISOLATED, PROGRAMMABLE, 4 mA TO 20 mA PROCESS CONTROLLER In many process-control system applications, 2-wire current transmitters are used to transmit analog signals through noisy environments. These current transmitters use a zero-scale signal current of 4 mA to power the signal conditioning circuitry of the transmitter. The full-scale output signal in these transmitters is 20 mA. The converse approach to process control can also be used, in which a low-power, programmable current source is used to control remotely located sensors or devices in the loop. A circuit that performs this function is shown in Figure 51. Using the AD5660 as the controller, the circuit provides a programmable output current of 4 to 20 mA, proportional to the digital code of the DAC. Biasing for the controller is provided by the ADR02 and requires no external trim for two reasons: first, the ADR02’s tight initial output voltage tolerance, and second, the low supply current consumption of both the AD8627 and the AD5660. The entire circuit, including optocouplers, consumes less than 3 mA from the total budget of 4 mA. The AD8627 regulates the output current to satisfy the current summation at the noninverting node of the AD8627. Without this diode, such transients could cause phase reversal of the AD8627 and possible latch-up of the controller. The loop supply voltage compliance of the circuit is limited by the maximum applied input voltage to the ADR02 and is from 12 V to 40 V. USING THE AD5620/AD5640/AD5660 WITH A GALVANICALLY ISOLATED INTERFACE For process-control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from hazardous common-mode voltages that might occur in the area where the DAC is functioning. The iCoupler® provides isolation in excess of 2.5 kV. The AD5620/AD5640/AD5660 use a 3-wire serial logic interface; therefore, the ADuM1300 3-channel digital isolator provides the required isolation (see Figure 52). The power supply to the part also must be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5620/AD5640/AD5660. 5V REGULATOR 10F POWER 0.1F IOUT = 1/R7 (VDAC × R3/R1 + VREF × R3/R2) VDD SCLK VOA V1A IOUT = 0.2435 μA × D + 4 mA SCLK AD56x0 ADuM1300 where D = 0 ≤ D ≤ 65,535, giving a full-scale output current of 20 mA when the AD5660’s digital code equals 0xFFFF. Offset trim at 4 mA is provided by P2, and P1 provides the circuit gain trim at 20 mA. These two trims do not interact because the noninverting input of the AD8627 is at virtual ground. The Schottky diode, D1, is required in this circuit to prevent loop supply power-on transients from pulling the noninverting input of the AD8627 more than 300 mV below its inverting input. SDI V1B VOB SYNC DATA V1C VOC DIN VOUT GND 04539-053 For the values shown in Figure 51, Figure 52. AD5620/AD5640/AD5660 with a Galvanically Isolated Interface Rev. F | Page 22 of 28 AD5620/AD5640/AD5660 POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5620/ AD5640/AD5660 should have separate analog and digital sections, each having its own area of the board. If the AD5620/ AD5640/AD5660 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5620/AD5640/AD5660. The power supply to the AD5620/AD5640/AD5660 should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should be as close as physically possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor has a low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other components with fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. F | Page 23 of 28 AD5620/AD5640/AD5660 OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 8 7 6 5 1 2 3 4 3.00 2.80 2.60 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.30 1.15 0.90 0.22 MAX 0.08 MIN 0.15 MAX 0.05 MIN 8° 4° 0° SEATING PLANE 0.38 MAX 0.22 MIN 0.60 BSC 0.60 0.45 0.30 12-16-2008-A 1.45 MAX 0.95 MIN COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 53. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 54. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. F | Page 24 of 28 0.80 0.55 0.40 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 AD5620/AD5640/AD5660 ORDERING GUIDE Model1 AD5620ARJ-1500RL7 AD5620ARJZ-1500RL7 AD5620ARJ-1REEL7 AD5620ARJ-2500RL7 AD5620ARJZ-2500RL7 AD5620ARJ-2REEL7 AD5620ARJZ-2REEL7 AD5620ARMZ-2 AD5620ARMZ-2REEL7 AD5620BRJ-1500RL7 AD5620BRJZ-1500RL7 AD5620BRJ-1REEL7 AD5620BRJ-2500RL7 AD5620BRJZ-2500RL7 AD5620BRJ-2REEL7 AD5620BRJZ-2REEL7 AD5620CRM-1 AD5620CRMZ-1 AD5620CRM-1REEL7 AD5620CRMZ-1REEL7 AD5620CRM-2 AD5620CRM-2REEL7 AD5620CRMZ-2 AD5620CRMZ-2REEL7 AD5620CRM-3 AD5620CRMZ-3 AD5620CRM-3REEL7 AD5620CRMZ-3REEL7 EVAL-AD5620EBZ AD5640ARJ-2500RL7 AD5640ARJZ-2500RL7 AD5640ARJ-2REEL7 AD5640ARJZ-2REEL7 AD5640BRJ-1500RL7 AD5640BRJZ-1500RL7 AD5640BRJ-1REEL7 AD5640BRJZ-1REEL7 AD5640BRJ-2500RL7 AD5640BRJZ-2500RL7 AD5640BRJ-2REEL7 AD5640BRJZ-2REEL7 AD5640CRM-1 AD5640CRM-1REEL7 AD5640CRMZ-1 AD5640CRMZ-1REEL7 AD5640CRM-2 AD5640CRM-2REEL7 AD5640CRMZ-2 AD5640CRMZ-2REEL7 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead MSOP 8-Lead MSOP 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Evaluation Board 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RM-8 RM-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding D2K D6V D2K D2L D5D D2L D5D DGY DGY D2H D87 D2H D2J D5C D2J D5C D2M DGM D2M DGM D2N D2N D59 D59 D2P DGN D2P DGN Power-On Reset to Code Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Midscale Midscale Midscale Midscale Accuracy ±6 LSB INL ±6 LSB INL ±6 LSB INL ±6 LSB INL ±6 LSB INL ±6 LSB INL ±6 LSB INL ±6 LSB INL ±6 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL Internal Reference 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 D2T DC6 D2T DC6 D2Q DC3 D2Q DC3 D2R DC0 D2R DC0 D2U D2U DG1 DG1 D2V D2V DEW DEW Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero ±8 LSB INL ±8 LSB INL ±8 LSB INL ±8 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V Rev. F | Page 25 of 28 AD5620/AD5640/AD5660 Model1 AD5660ARJ-1500RL7 AD5660ARJZ-1500RL7 AD5660ARJ-1REEL7 AD5660ARJZ-1REEL7 AD5660ARJ-2500RL7 AD5660ARJZ-2500RL7 AD5660ARJ-2REEL7 AD5660ARJZ-2REEL7 AD5660ARJ-3500RL7 AD5660ARJZ-3500RL7 AD5660ARJ-3REEL7 AD5660ARJZ-3REEL7 AD5660BRJ-1500RL7 AD5660BRJZ-1500RL7 AD5660BRJ-1REEL7 AD5660BRJZ-1REEL7 AD5660BRJ-2500RL7 AD5660BRJZ-2500RL7 AD5660BRJ-2REEL7 AD5660BRJZ-2REEL7 AD5660BRJ-3500RL7 AD5660BRJZ-3500RL7 AD5660BRJ-3REEL7 AD5660BRJZ-3REEL7 AD5660CRM-1 AD5660CRM-1REEL7 AD5660CRMZ-1 AD5660CRMZ-1REEL7 AD5660CRM-2 AD5660CRM-2REEL7 AD5660CRMZ-2 AD5660CRMZ-2REEL7 AD5660CRM-3 AD5660CRM-3REEL7 AD5660CRMZ-3 AD5660CRMZ-3REEL7 EVAL-AD5660EBZ EVAL-AD5660DKZ 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Evaluation Board Demonstration Board Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Z = RoHS Compliant Part. Rev. F | Page 26 of 28 Branding D30 D5G D30 D5G D31 D6K D31 D6K D32 DAV D32 DAV D2X D6C D2X D6C D2Y D6L D2Y D6L D2Z DAN D2Z DAN D33 D33 DEX DEX D34 D34 DEY DEY D35 D35 DBY DBY Power-On Reset to Code Zero Zero Zero Zero Zero Zero Zero Zero Midscale Midscale Midscale Midscale Zero Zero Zero Zero Zero Zero Zero Zero Midscale Midscale Midscale Midscale Zero Zero Zero Zero Zero Zero Zero Zero Midscale Midscale Midscale Midscale Accuracy ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL Internal Reference 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V AD5620/AD5640/AD5660 NOTES Rev. F | Page 27 of 28 AD5620/AD5640/AD5660 NOTES ©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04539-0-12/10(F) Rev. F | Page 28 of 28