AD5663R

Dual 12-/14-/16-Bit nanoDAC® with 5 ppm/°C On-Chip Reference AD5623R/AD5643R/AD5663R FEATURES Low power, smallest pin-compatible, dual nanoDAC AD5663R: 16 bits AD5643R: 14 bits AD5623R: 12 bits User-selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP and 3 mm × 3 mm LFCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface up to 50 MHz Hardware LDAC and CLR functions FUNCTIONAL BLOCK DIAGRAM VDD LDAC INPUT REGISTER INTERFACE LOGIC INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB DAC REGISTER STRING DAC A VREFIN /VREFOUT 1.25V/2.5V REFERENCE BUFFER VOUTA SCLK SYNC DIN AD5623R/AD5643R/AD5663R POWER-ON RESET POWER-DOWN LOGIC 05858-001 LDAC CLR GND Figure 1. APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Table 1. Related Devices Part No. AD5663 Description 2.7 V to 5.5 V, dual 16-bit nanoDAC, with external reference GENERAL DESCRIPTION The AD5623R/AD5643R/AD5663R, members of the nanoDAC family, are low power, dual 12-, 14-, and 16-bit buffered voltageout digital-to-analog converters (DAC) that operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. The AD5623R/AD5643R/AD5663R have an on-chip reference. The AD5623R-3/AD5643R-3/AD5663R-3 have a 1.25 V, 5 ppm/°C reference, giving a full-scale output of 2.5 V; and the AD5623R-5/ AD5643R-5/AD5663R-5 have a 2.5 V, 5 ppm/°C reference, giving a full-scale output of 5 V. The on-chip reference is off at power-up, allowing the use of an external reference; and all devices can be operated from a single 2.7 V to 5.5 V supply. The internal reference is turned on by writing to the DAC. The parts incorporate a power-on reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in powerdown mode. The low power consumption of this part in normal operation makes it ideally suited to portable, battery-operated equipment. The AD5623R/AD5643R/AD5663R use a versatile, 3-wire serial interface that operates at clock rates up to 50 MHz, and they are compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The on-chip precision output amplifier enables rail-to-rail output swing to be achieved. PRODUCT HIGHLIGHTS 1. Dual 12-, 14-, and 16-bit DAC. 2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. 3. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP. 4. Low power; typically consumes 0.6 mW at 3 V and 1.25 mW at 5 V. 5. 4.5 μs maximum settling time for the AD5623R. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD5623R/AD5643R/AD5663R TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AD5623R-5/AD5643R-5/AD5663R-5 ....................................... 3 AD5623R-3/AD5643R-3/AD5663R-3 ....................................... 5 AC Characteristics........................................................................ 6 Timing Characteristics ................................................................ 7 Timing Diagram ........................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 18 Theory of Operation ...................................................................... 20 Digital-to-Analog Section ......................................................... 20 Resistor String ............................................................................. 20 Output Amplifier........................................................................ 20 Internal Reference ...................................................................... 20 External Reference ..................................................................... 20 Serial Interface ............................................................................ 20 Input Shift Register .................................................................... 21 SYNC Interrupt .......................................................................... 21 Power-On Reset.......................................................................... 22 Software Reset............................................................................. 22 Power-Down Modes .................................................................. 22 LDAC Function .......................................................................... 23 Internal Reference Setup ........................................................... 24 Microprocessor Interfacing....................................................... 25 Applications Information .............................................................. 26 Using a Reference as a Power Supply....................................... 26 Bipolar Operation Using the AD5663R .................................. 26 Using the AD5663R with a Galvanically Isolated Interface . 26 Power Supply Bypassing and Grounding................................ 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 REVISION HISTORY 12/06—Rev. 0 to Rev. A Changes to Table 2............................................................................ 3 Changes to Table 3............................................................................ 5 Changes to Figure 3.......................................................................... 9 Changes to Ordering Guide .......................................................... 28 4/06—Revision 0: Initial Version Rev. A | Page 2 of 28 AD5623R/AD5643R/AD5663R SPECIFICATIONS AD5623R-5/AD5643R-5/AD5663R-5 VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 2 AD5663R Resolution Relative Accuracy Differential Nonlinearity AD5643R Resolution Relative Accuracy Differential Nonlinearity AD5623R Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Offset Error Full-Scale Error Gain Error Zero-Scale Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk (External Reference) Min B Grade 1 Typ Max Unit Conditions/Comments 16 ±8 ±16 ±1 Bits LSB LSB Bits LSB LSB Bits LSB LSB mV mV % of FSR % of FSR μV/°C ppm dB μV μV/mA μV μV μV/mA μV Guaranteed monotonic by design 14 ±2 ±4 ±0.5 Guaranteed monotonic by design 12 ±0.5 +2 ±1 −0.1 ±2 ±2.5 −100 10 10 5 25 20 10 ±1 ±0.25 +10 ±10 ±1 ±1.5 Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register DC Crosstalk (Internal Reference) Of FSR/°C DAC code = midscale ; VDD = 5 V ± 10% Due to full-scale output change; RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change; RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) OUTPUT CHARACTERISTICS 3 Output Voltage Range Capacitive Load Stability DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT Output Voltage Reference Temperature Coefficient3 Output Impedance 0 2 10 0.5 30 4 170 0.75 26 2.495 ±5 ±10 7.5 VDD V nF nF Ω mA μs μA V kΩ V ppm/°C ppm/°C kΩ RL = ∞ RL = 2 kΩ VDD = 5 V Coming out of power-down mode; VDD = 5 V VREF = VDD = 5.5 V 200 VDD 2.505 ±10 At ambient MSOP package models LFCSP package models Rev. A | Page 3 of 28 AD5623R/AD5643R/AD5663R Parameter LOGIC INPUTS3 Input Current Input Low Voltage (VINL) Input High Voltage (VINH) Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V IDD (All Power-Down Modes) 5 VDD = 4.5 V to 5.5 V 1 2 Min B Grade 1 Typ Max ±2 0.8 Unit μA V V pF pF Conditions/Comments All digital inputs VDD = 5 V VDD = 5 V DIN, SCLK, and SYNC LDAC and CLR 2 3 19 4.5 0.25 0.8 0.48 5.5 0.45 1 1 V mA mA μA VIH = VDD and VIL = GND Internal reference off Internal reference on VIH = VDD and VIL = GND Temperature range: B grade = −40°C to +105°C. Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 Both DACs powered down. Rev. A | Page 4 of 28 AD5623R/AD5643R/AD5663R AD5623R-3/AD5643R-3/AD5663R-3 VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter STATIC PERFORMANCE 2 AD5663R Resolution Relative Accuracy Differential Nonlinearity AD5643R Resolution Relative Accuracy Differential Nonlinearity AD5623R Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Offset Error Full-Scale Error Gain Error Zero-Scale Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk (External Reference) Min B Grade 1 Typ Max Unit Conditions/Comments 16 ±8 ±16 ±1 Bits LSB LSB Bits LSB LSB Bits LSB LSB mV mV % of FSR % of FSR μV/°C ppm dB μV μV/mA μV μV μV/mA μV Guaranteed monotonic by design 14 ±2 ±4 ±0.5 Guaranteed monotonic by design 12 ±0.5 +2 ±1 −0.1 ±2 ±2.5 −100 10 10 5 25 20 10 ±1 ±0.25 +10 ±10 ±1 ±1.5 Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register DC Crosstalk (Internal Reference) Of FSR/°C DAC code = midscale; VDD = 3 V ± 10% Due to full-scale output change; RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change; RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) OUTPUT CHARACTERISTICS 3 Output Voltage Range Capacitive Load Stability DC Output Impedance Short Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT Output Voltage Reference Temperature Coefficient3 Output Impedance 0 2 10 0.5 30 4 170 0.75 26 1.247 ±5 ±10 7.5 VDD V nF nF Ω mA μs μA V kΩ V ppm/°C ppm/°C kΩ RL = ∞ RL = 2 kΩ VDD = 3 V Coming out of power-down mode; VDD = 3 V VREF = VDD = 3.6 V 200 VDD 1.253 ±15 At ambient MSOP package models LFCSP package models Rev. A | Page 5 of 28 AD5623R/AD5643R/AD5663R Parameter LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 2.7 V to 3.6 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) 5 VDD = 2.7 V to 3.6 V 1 2 Min B Grade 1 Typ Max ±2 0.8 Unit μA V V pF pF Conditions/Comments All digital inputs VDD = 3 V VDD = 3 V DIN, SCLK, and SYNC LDAC and CLR 2 3 19 2.7 200 800 0.2 3.6 425 900 1 V μA μA μA VIH = VDD and VIL = GND Internal reference off Internal reference on VIH = VDD and VIL = GND Temperature range: B grade = −40°C to +105°C. Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 Both DACs powered down. AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1 , 2 Output Voltage Settling Time AD5623R AD5643R AD5663R Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise 1 2 Min Typ 3 3.5 4 1.8 10 0.1 −90 0.1 1 4 1 4 340 −80 120 100 15 Max 4.5 5 7 Unit μs μs μs V/μs nV-s nV-s dB nV-s nV-s nV-s nV-s nV-s kHz dB nV/√Hz nV/√Hz μV p-p Conditions/Comments 3 ¼ to ¾ scale settling to ±0.5 LSB ¼ to ¾ scale settling to ±0.5 LSB ¼ to ¾ scale settling to ±2 LSB 1 LSB change around major carry VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz External reference Internal reference External reference Internal reference VREF = 2 V ± 0.1 V p-p VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz DAC code = midscale, 1 kHz DAC code = midscale, 10 kHz 0.1 Hz to 10 Hz Guaranteed by design and characterization, not production tested. See the Terminology section. 3 Temperature range: B grade = −40°C to +105°C, typical at +25°C. Rev. A | Page 6 of 28 AD5623R/AD5643R/AD5663R TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 5. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 1 2 Limit at TMIN, TMAX VDD = 2.7 V to 5.5 V 20 9 9 13 5 5 0 15 13 0 10 15 5 0 300 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to SCLK fall ignore SCLK falling edge to SYNC fall ignore LDAC pulse width low SCLK falling edge to LDAC rising edge CLR pulse width low SCLK falling edge to LDAC falling edge CLR pulse activation time Guaranteed by design and characterization, not production tested. Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. TIMING DIAGRAM t10 SCLK t1 t9 t8 SYNC t4 t3 t2 t7 t5 DIN DB23 t6 DB0 t14 LDAC1 t11 t12 LDAC2 CLR t13 t15 05858-002 VOUT 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation Rev. A | Page 7 of 28 AD5623R/AD5643R/AD5663R ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to GND VOUT to GND VREFIN/VREFOUT to GND Digital Input Voltage to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation LFCSP Package (4-Layer Board) θJA Thermal Impedance MSOP Package (4-Layer Board) θJA Thermal Impedance θJC Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +105°C −65°C to +150°C 150°C (TJ max − TA)/θJA 61°C/W 142°C/W 43.7°C/W 260(+0/−5)°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. A | Page 8 of 28 AD5623R/AD5643R/AD5663R PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOUTA 1 VOUTB 2 GND 3 LDAC 4 CLR 5 10 AD5623R/ AD5643R/ AD5663R TOP VIEW (Not to Scale) VREFIN/VREFOUT VDD DIN SCLK SYNC 05858-003 9 8 7 6 NOTE: EXPOSED PAD TIED TO GND ON LFCSP PACKAGE. Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic VOUTA VOUTB GND LDAC CLR Description Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Ground. Reference point for all circuitry on the part. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted. Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input. 6 SYNC 7 8 9 10 SCLK DIN VDD VREFIN/VREFOUT Rev. A | Page 9 of 28 AD5623R/AD5643R/AD5663R TYPICAL PERFORMANCE CHARACTERISTICS 10 8 6 VDD = VREF = 5V TA = 25°C 1.0 0.8 0.6 VDD = VREF = 5V TA = 25°C 2 0 –2 –4 –6 –8 05858-005 DNL ERROR (LSB) INL ERROR (LSB) 4 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –10 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE 0 10k 20k 30k CODE 40k 50k 60k Figure 4. INL—AD5663R, External Reference 4 3 2 1 0 –1 –2 –0.3 –3 05858-006 Figure 7. DNL—AD5663R, External Reference 0.5 VDD = VREF = 5V TA = 25°C 0.4 0.3 DNL ERROR (LSB) VDD = VREF = 5V TA = 25°C 0.2 0.1 0 –0.1 –0.2 INL ERROR (LSB) –4 –0.5 0 2.5k 5.0k 7.5k 10.0k CODE 12.5k 15.0k 0 2.5k 5.0k 7.5k 10.0k CODE 12.5k 15.0k Figure 5. INL—AD5643R, External Reference 1.0 VDD = VREF = 5V 0.8 TA = 25°C 0.6 0.4 0.10 0.20 0.15 Figure 8. DNL—AD5643R, External Reference VDD = VREF = 5V TA = 25°C DNL ERROR (LSB) INL ERROR (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 05858-007 0.05 0 –0.05 –0.10 –0.15 05858-010 –1.0 0 0.5k 1.0k 1.5k 2.0k 2.5k CODE 3.0k 3.5k 4.0k –0.20 0 0.5k 1.0k 1.5k 2.0k 2.5k CODE 3.0k 3.5k 4.0k Figure 6. INL—AD5623R, External Reference Figure 9. DNL—AD5623R, External Reference Rev. A | Page 10 of 28 05858-009 –0.4 05858-008 AD5623R/AD5643R/AD5663R 10 8 6 VDD = 5V VREFOUT = 2.5V TA = 25°C 1.0 0.8 0.6 VDD = 5V VREFOUT = 2.5V TA = 25°C DNL ERROR (LSB) INL ERROR (LSB) 4 2 0 –2 –4 –6 –8 05858-011 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE Figure 10. INL—AD5663R-5 4 3 2 1 0 –1 –2 –0.3 –3 –4 –0.4 –0.5 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.5 0.4 0.3 Figure 13. DNL—AD5663R-5 VDD = 5V VREFOUT = 2.5V TA = 25°C DNL ERROR (LSB) INL ERROR (LSB) 0.2 0.1 0 –0.1 –0.2 0 0 1250 2500 3750 5000 6250 7500 1250 2500 3750 5000 6250 7500 8750 8750 10000 11250 12500 13750 15000 10000 11250 12500 13750 15000 16250 16250 4.0k CODE CODE Figure 11. INL—AD5643R-5 1.0 0.8 0.6 INL ERROR (LSB) Figure 14. DNL—AD5643R-5 0.20 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.15 0.10 DNL ERROR (LSB) VDD = 5V VREFOUT = 2.5V TA = 25°C 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 05858-013 0.05 0 –0.05 –0.10 –0.15 05858-016 –1.0 0 0.5k 1.0k 1.5k 2.0k 2.5k CODE 3.0k 3.5k 4.0k –0.20 0 0.5k 1.0k 1.5k 2.0k 2.5k CODE 3.0k 3.5k Figure 12. INL—AD5623R-5 Figure 15. DNL—AD5623R-5 Rev. A | Page 11 of 28 05858-015 05858-012 05858-014 –10 –1.0 AD5623R/AD5643R/AD5663R 10 8 6 VDD = 3V VREFOUT = 1.25V TA = 25°C 1.0 0.8 0.6 DNL ERROR (LSB) VDD = 3V VREFOUT = 1.25V TA = 25°C INL ERROR (LSB) 4 2 0 –2 –4 –6 –8 –10 05858-017 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE Figure 16. INL—AD5663R-3 4 VDD = 3V V = 1.25V 3 T REFOUT A = 25°C 2 1 0 –1 –2 –3 –4 0 1250 2500 3750 5000 6250 7500 8750 10000 11250 12500 13750 15000 16250 05858-018 Figure 19. DNL—AD5663R-3 0.5 0.4 0.3 DNL ERROR (LSB) VDD = 3V VREFOUT = 1.25V TA = 25°C INL ERROR (LSB) 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 1250 2500 3750 5000 6250 7500 8750 10000 11250 12500 13750 15000 16250 05858-021 05858-022 CODE CODE Figure 17. INL—AD5643R-3 1.0 0.8 0.6 DNL ERROR (LSB) Figure 20. DNL—AD5643R-3 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 05858-019 VDD = 3V VREFOUT = 1.25V TA = 25°C VDD = 3V VREFOUT = 1.25V TA = 25°C INL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 0.5k 1.0k 1.5k 2.0k 2.5k CODE 3.0k 3.5k 4.0k –0.20 0 0.5k 1.0k 1.5k 2.0k 2.5k CODE 3.0k 3.5k 4.0k Figure 18. INL—AD5623R-3 Figure 21. DNL—AD5623R-3 Rev. A | Page 12 of 28 05858-020 AD5623R/AD5643R/AD5663R 8 6 VDD = VREF = 5V 4 ERROR (LSB) 0 MAX INL –0.02 –0.04 –0.06 VDD = 5V GAIN ERROR MAX DNL 0 –2 –4 MIN INL 05858-080 ERROR (% FSR) 2 –0.08 –0.10 –0.12 –0.14 –0.16 –0.18 –20 0 20 40 60 TEMPERATURE (°C) 80 100 05858-023 05858-025 05858-024 MIN DNL FULL-SCALE ERROR –6 –8 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 –0.20 –40 Figure 22. INL Error and DNL Error vs. Temperature Figure 25. Gain Error and Full-Scale Error vs. Temperature 10 8 6 4 VDD = 5V TA = 25°C MAX DNL 0 –2 –4 –6 –8 –10 0.75 1.25 1.75 2.25 2.75 3.25 VREF (V) 3.75 05858-081 1.5 MAX INL 1.0 0.5 ZERO-SCALE ERROR ERROR (LSB) ERROR (mV) 2 0 –0.5 –1.0 –1.5 MIN DNL MIN INL OFFSET ERROR –2.0 –2.5 –40 4.25 4.75 –20 0 20 40 60 TEMPERATURE (°C) 80 100 Figure 23. INL Error and DNL Error vs. VREF Figure 26. Zero-Scale Error and Offset Error vs. Temperature 8 6 TA = 25°C 4 MAX INL 1.0 0.5 GAIN ERROR ERROR (LSB) MAX DNL 0 –2 –4 MIN INL 05858-082 ERROR (% FSR) 2 0 FULL-SCALE ERROR –0.5 MIN DNL –1.0 –6 –8 2.7 –1.5 3.2 3.7 4.2 VDD (V) 4.7 5.2 –2.0 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 Figure 24. INL Error and DNL Error vs. Supply Figure 27. Gain Error and Full-Scale Error vs. Supply Rev. A | Page 13 of 28 AD5623R/AD5643R/AD5663R 1.0 TA = 25°C 0.5 0 ZERO-SCALE ERROR 0.5 0.4 0.3 DAC LOADED WITH FULL-SCALE SOURCING CURRENT DAC LOADED WITH ZERO-SCALE SINKING CURRENT ERROR VOLTAGE (V) 0.2 0.1 0 –0.1 –0.2 –0.3 VDD = 5V VREFOUT = 2.5V VDD = 3V VREFOUT = 1.25V ERROR (mV) –0.5 –1.0 –1.5 –2.0 –2.5 2.7 OFFSET ERROR 05858-026 –0.4 –8 –6 –4 –2 0 2 CURRENT (mA) 4 6 8 10 05858-029 05858-031 05858-030 3.2 3.7 4.2 VDD (V) 4.7 5.2 –0.5 –10 Figure 28. Zero-Scale Error and Offset Error vs. Supply VDD = 5.5V TA = 25°C 8 6 5 4 Figure 31. Headroom at Rails vs. Source and Sink VDD = 5V VREFOUT = 2.5V TA = 25°C FULL SCALE NUMBER OF UNITS 3/4 SCALE 6 VOUT (V) 3 2 MIDSCALE 4 1/4 SCALE 1 2 0 05858-090 ZERO SCALE 0 0.230 0.235 0.240 0.245 IDD (mA) 0.250 0.255 –1 –30 –20 –10 0 10 CURRENT (mA) 20 30 Figure 29. IDD Histogram with External Reference 5 VDD = 5.5V TA = 25°C 4 NUMBER OF UNITS Figure 32. AD56x3R-5 Source and Sink Capability 4 VDD = 3V VREFOUT = 1.25V TA = 25°C FULL SCALE 3/4 SCALE MIDSCALE 1 1/4 SCALE 3 2 1 VOUT (V) 3 2 0 ZERO SCALE 0.78 0.80 0.82 IDD (mA) 0.84 05858-091 0 –1 –30 –20 –10 0 10 CURRENT (mA) 20 30 Figure 30. IDD Histogram with Internal Reference Figure 33. AD56x3R-3 Source and Sink Capability Rev. A | Page 14 of 28 AD5623R/AD5643R/AD5663R 0.30 TA = 25°C 0.25 SYNC VDD = VREFIN = 5V 1 3 SLCK 0.20 IDD (mA) VDD = VREFIN = 3V 0.15 0.10 VOUT 0.05 VDD = 5V 2 05858-044 –20 0 20 40 60 TEMPERATURE (°C) 80 100 CH1 5.0V CH3 5.0V CH2 500mV M400ns A CH1 1.4V Figure 34. Supply Current vs. Temperature 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 2.522 2.521 Figure 37. Exiting Power-Down to Midscale VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER GLITCH IMPULSE = 9.494nV 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) VDD = VREF = 5V TA = 25°C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND VOUT = 909mV/DIV 1 05858-060 VOUT (V) 05858-062 0 –40 0 50 100 150 TIME BASE = 4µs/DIV 200 250 300 350 SAMPLE NUMBER 400 450 512 Figure 35. Full-Scale Settling Time, 5 V Figure 38. Digital-to-Analog Glitch Impulse (Negative) 2.498 VDD = VREF = 5V TA = 25°C 2.497 2.496 2.495 2.494 2.493 VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 0.424nV VDD 1 MAX(C2)* 420.0mV 2 VOUT 05858-061 VOUT (V) 2.491 CH1 2.0V CH2 500mV M100µs 125MS/s A CH1 1.28V 8.0ns/pt 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 512 Figure 36. Power-On Reset to 0 V Figure 39. Analog Crosstalk, External Reference Rev. A | Page 15 of 28 05858-059 2.492 05858-058 AD5623R/AD5643R/AD5663R 2.496 2.494 2.492 2.490 2.488 2.486 2.484 2.482 2.480 2.478 2.476 2.474 2.472 2.470 2.468 2.466 2.464 2.462 2.460 2.458 2.456 VDD = 3V VREFOUT = 1.25V TA = 25°C DAC LOADED WITH MIDSCALE VOUT (V) 5µV/DIV 05858-057 1 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 512 4s/DIV Figure 40. Analog Crosstalk, Internal Reference Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 800 700 TA = 25°C MIDSCALE LOADED OUTPUT NOISE (nV/√Hz) VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALE 600 500 400 300 200 100 VDD = 3V VREFOUT = 1.25V 1k 10k FREQUENCY (Hz) 1M 10M 05858-066 1 VDD = 5V VREFOUT = 2.5V Y AXIS = 2µV/DIV X AXIS = 4s/DIV Figure 41. 0.1 Hz to 10 Hz Output Noise Plot, External Reference –20 05858-063 0 100 Figure 44. Noise Spectral Density, Internal Reference VDD = 5V VREFOUT = 2.5V TA = 25°C DAC LOADED WITH MIDSCALE –30 –40 –50 VDD = 5V TA = 25°C DAC LOADED WITH FULL SCALE VREF = 2V ± 0.3V p-p 10µV/DIV (dB) 1 –60 –70 –80 –90 05858-064 2k 5s/DIV 4k 6k FREQUENCY (Hz) 8k 10k Figure 42. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference Figure 45. Total Harmonic Distortion Rev. A | Page 16 of 28 05858-067 –100 05858-065 VDD = 5V VREFOUT = 2.5V TA = 25°C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 4.462nV AD5623R/AD5643R/AD5663R 16 VREF = VDD TA = 25°C 14 VDD = 3V 12 3 CLR VOUT A TIME (µs) 10 8 VDD = 5V VOUT B 6 05858-050 4 05858-068 4 0 1 2 3 4 5 6 7 CAPACITANCE (nF) 8 9 10 2 CH3 5.0V CH2 1.0V CH4 1.0V M200ns A CH3 1.10V Figure 46. Settling Time vs. Capacitive Load 5 0 –5 –10 –15 –20 –25 –30 –35 05858-069 Figure 48. CLR Pulse Activation Time VDD = 5V TA = 25°C (dB) –40 10k 100k 1M FREQUENCY (Hz) 10M Figure 47. Multiplying Bandwidth Rev. A | Page 17 of 28 AD5623R/AD5643R/AD5663R TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 5. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot is shown in Figure 9. Zero-Scale Error Zero-scale error is the measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-scale error is always positive in the AD56x3R because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and the output amplifier. Zero-scale error is expressed in mV. A plot of zero-scale error vs. temperature is shown in Figure 26. Full-Scale Error Full-scale error is the measurement of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error vs. temperature is shown in Figure 25. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal, expressed as a percent of the full-scale range. Zero-Scale Error Drift Zero-scale error drift is the measurement of the change in zeroscale error with a change in temperature. It is expressed in microvolts/°C (μV/°C). Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD56x3R with code 512 loaded in the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V, and VDD is varied by ±10%. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change and is measured from the 24th falling edge of SCLK. Digital-to-Analog Glitch Impulse The impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 38. Digital Feedthrough A measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, digital feedthrough is measured when the DAC output is not updated. It is specified in nV-s, and it is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is, LDAC is high). It is expressed in decibels (dB). Noise Spectral Density Noise spectral density is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. A plot of noise spectral density is shown in Figure 44. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in microvolts (μV). DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in microvolts/ milliamps (μV/mA). Rev. A | Page 18 of 28 AD5623R/AD5643R/AD5663R Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nanovolts-second (nV-s). Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nanovolts-second (nV-s). DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nanovolts-second (nV-s). Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in decibels (dB). Rev. A | Page 19 of 28 AD5623R/AD5643R/AD5663R THEORY OF OPERATION DIGITAL-TO-ANALOG SECTION The AD5623R/AD5643R/AD5663R DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 49 shows a block diagram of the DAC architecture. VDD REF (+) DAC REGISTER RESISTOR STRING REF (–) OUTPUT AMPLIFIER (GAIN = +2) VOUT R R R R TO OUTPUT AMPLIFIER GND Figure 49. DAC Architecture 05858-032 R 05858-033 Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by Figure 50. Resistor String D VOUT = VREFIN × ⎛ N ⎞ ⎜⎟ ⎝2 ⎠ The ideal output voltage when using the internal reference is given by D VOUT = 2 × VREFOUT × ⎛ N ⎞ ⎜⎟ ⎝2 ⎠ where: D is the decimal equivalent of the binary code that is loaded to the DAC register: 0 to 4095 for AD5623R (12-bit) 0 to 16,383 for AD5643R (14-bit) 0 to 65,535 for AD5663R (16-bit) N is the DAC resolution. INTERNAL REFERENCE The AD5623R/AD5643R/AD5663R on-chip reference is off at power-up and is enabled via a write to a control register. See the Internal Reference Setup section for details. The AD56x3R-3 has a 1.25 V, 5 ppm/°C reference, giving a fullscale output of 2.5 V. The AD56x3R-5 has a 2.5 V, 5 ppm/°C reference, giving a full-scale output of 5 V. The internal reference associated with each part is available at the VREFOUT pin. A buffer is required if the reference output is used to drive external loads. When using the internal reference, it is recommended that a 100 nF capacitor be placed between reference output and GND for reference stability. EXTERNAL REFERENCE The VREFIN pins on the AD56x3R-3 and the AD56x3R-5 allows the use of an external reference if the application requires it. The on-chip reference is off at power-up, and this is the default condition. The AD56x3R-3 and the AD56x3R-5 can be operated from a single 2.7 V to 5.5 V supply. RESISTOR STRING The resistor string section is shown in Figure 50. It is simply a string of resistors, each of Value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. SERIAL INTERFACE The AD5623R/AD5643R/AD5663R have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards, as well as with most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5623R/AD5643R/AD5663R compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed, for example, a change in DAC register contents and/or a change in the mode of operation. OUTPUT AMPLIFIER The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It can drive a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 31. The slew rate is 1.8 V/μs with a 1/4 to 3/4 full-scale settling time of 10 μs. Rev. A | Page 20 of 28 AD5623R/AD5643R/AD5663R At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 15 ns before the next write sequence, so that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when VIN = 2 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation. As mentioned previously, it must, however, be brought high again just before the next write sequence. Table 8. Command Definition C2 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 Command Write to Input Register n Update DAC Register n Write to Input Register n, update all (software LDAC) Write to and update DAC Channel n Power down DAC (power up) Reset LDAC register setup Internal reference setup (on/off ) INPUT SHIFT REGISTER The input shift register is 24 bits wide (see Figure 52). The first two bits are don’t cares. The next three are Command Bit C2 to Command Bit C0 (see Table 8), followed by the 3-bit DAC Address A2 to DAC Address A0 (see Table 9), and, finally, the 16-, 14-, and 12-bit data-word. The data-word comprises the 16-, 14-, and 12-bit input codes, followed by zero, two, or four don’t care bits, for the AD5663R, AD5643R, and AD5623R, respectively (see Figure 51, Figure 52, and Figure 53). The data bits are transferred to the DAC register on the 24th falling edge of SCLK. Table 9. Address Command A2 0 0 0 0 1 A1 0 0 1 1 1 A0 0 1 0 1 1 ADDRESS (n) DAC A DAC B Reserved Reserved All DACs SYNC INTERRUPT In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 54). DB0 (LSB) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 05858-034 DB23 (MSB) X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 DATA BITS COMMAND BITS ADDRESS BITS Figure 51. AD5663R Input Shift Register Contents DB23 (MSB) X X C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DB0 (LSB) X X 05858-071 DATA BITS COMMAND BITS ADDRESS BITS Figure 52. AD5643R Input Shift Register Contents DB23 (MSB) X X C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DB0 (LSB) X X 05858-072 DATA BITS COMMAND BITS ADDRESS BITS Figure 53. AD5623R Input Shift Register Contents SCLK SYNC DIN DB23 DB0 DB23 DB0 05858-035 INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 24TH FALLING EDGE Figure 54. SYNC Interrupt Facility Rev. A | Page 21 of 28 AD5623R/AD5643R/AD5663R POWER-ON RESET The AD5623R/AD5643R/AD5663R contain a power-on reset circuit that controls the output voltage during power-up. The AD5623R/AD5643R/AD5663R DACs output power up to 0 V, and the output remains there until a valid write sequence is made to the DACs. This is useful in applications where it is important to know the state of the output of the DACs while they are in the process of powering up. Any events on LDAC or CLR during power-on reset are ignored. Again, to select which combination of DAC channels to power up, set the corresponding bits (Bit DB1 and Bit DB0) to 1. See Table 13 for contents of the input shift register during powerdown/power-up operation. The DAC output powers up to the value in the input register while LDAC is low. If LDAC is high, the DAC ouput powers up to the value held in the DAC register before power-down. Table 11. Modes of Operation DB5 0 0 1 1 DB4 0 1 0 1 Operating Mode Normal operation Power-down modes 1 kΩ to GND 100 kΩ to GND Three-state SOFTWARE RESET The AD5623R/AD5643R/AD5663R contain a software reset function. Command 101 is reserved for the software reset function (see Table 8). The software reset command contains two reset modes that are software-programmable by setting bit DB0 in the control register. Table 10 shows how the state of the bit corresponds to the mode of operation of the device. Table 12 shows the contents of the input shift register during the software reset mode of operation. Table 10. Software Reset Modes DB0 0 1 (Power-on Reset) Registers Reset to Zero DAC register Input register DAC register Input register LDAC register Power-down register Internal reference setup register When both Bit DB1 and Bit DB2 are set to 0, the part works normally, with its normal power consumption of 250 μA at 5 V. However, for the three power-down modes, the supply current falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. The outputs can either be connected internally to GND through a 1 kΩ or 100 kΩ resistor or left open-circuited (three-state) (see Figure 55). RESISTOR STRING DAC AMPLIFIER VOUT POWER-DOWN MODES The AD5623R/AD5643R/AD5663R contain four separate modes of operation. Command 100 is reserved for the powerdown function (see Table 8). These modes are softwareprogrammable by setting Bit DB5 and Bit DB4 in the control register. Table 11 shows how the state of the bits corresponds to the mode of operation of the device. Any or all DACs (DAC B and DAC A) can be powered down to the selected mode by setting the corresponding two bits (Bit DB1 and Bit DB0) to 1. By executing the same Command 100, any combination of DACs can be powered up by setting Bit DB5 and Bit DB4 to normal operation mode. 05858-036 POWER-DOWN CIRCUITRY RESISTOR NETWORK Figure 55. Output Stage During Power-Down The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 μs for both VDD = 5 V and VDD = 3 V (see Figure 37). Table 12. 24-Bit Input Shift Register Contents for Software Reset Command MSB DB23 to DB22 x Don’t care LSB DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 x Don’t care DB0 1/0 Determines software reset mode 1 0 1 Command bits (C2 to C0) x x x Address bits (A2 to A0) Rev. A | Page 22 of 28 AD5623R/AD5643R/AD5663R Table 13. 24-Bit Input Shift Register Contents of Power Up/Down Function MSB DB23 to DB22 x Don’t care LSB DB21 DB20 DB19 1 0 0 Command bits (C2 to C0) DB18 DB17 DB16 x x x Address bits (A2 to A0) Don’t care DB15 to DB6 x Don’t care DB5 DB4 PD1 PD0 Power-down mode DB3 DB2 x x Don’t care DB1 DB0 DAC B DAC A Power down/Power up channel selection; set bit to 1 to select channel Table 14. 24-Bit Input Shift Register Contents for LDAC Setup Command MSB DB23 to DB22 x Don’t care LSB DB21 DB20 DB19 DB110 DB17 DB16 x DB15 to DB2 x Don’t care DB1 DB0 1 1 0 Command bits (C2 to C0) x x Address bits (A3 to A0) Don’t care DAC B DAC A Set DAC to 0 or 1 for required mode of operation LDAC FUNCTION The AD5623R/AD5643R/AD5663R DACs have doublebuffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected directly to the input shift register, and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings. Access to the DAC registers is controlled by the LDAC pin. When the LDAC pin is high, the DAC registers are latched and the input registers can change state without affecting the contents of the DAC registers. When LDAC is brought low, however, the DAC registers become transparent and the contents of the input registers are transferred to them. The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. The user can write to one of the input registers individually and then, by bringing LDAC low when writing to the other DAC input register, all outputs will update simultaneously. These parts each contain an extra feature whereby a DAC register is not updated unless its input register has been updated since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5623R/AD5643R/AD5663R, the DAC register updates only if the input register has changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. The outputs of all DACs can be simultaneously updated, using the hardware LDAC pin. Asynchronous LDAC The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register. The LDAC register gives the user full flexibility and control over the hardware LDAC pin. This register allows the user to select which combination of channels to simultaneously update when the hardware LDAC pin is executed. Setting the LDAC bit register to 0 for a DAC channel means that the update of this channel is controlled by the LDAC pin. If this bit is set to 1, this channel synchronously updates; that is, the DAC register is updated after new data is read in, regardless of the state of the LDAC pin. It effectively sees the LDAC pin as being pulled low. See Table 15 for the LDAC register mode of operation. This flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. Writing to the DAC using Command 110 loads the 2-bit LDAC register [DB1:DB0]. The default for each channel is 0; that is, the LDAC pin works normally. Setting the bits to 1 means the DAC register is updated, regardless of the state of the LDAC pin. See Table 14 for contents of the input shift register during the LDAC register setup command. Table 15. LDAC Register Mode of Operation LDAC Bits (DB1 to DB0) 0 1 LDAC Pin 1/0 x = don’t care LDAC Operation Determined by LDAC pin The DAC registers are updated after new data is read in on the falling edge of the 24th SCLK pulse. Synchronous LDAC The DAC registers are updated after new data is read in on the falling edge of the 24th SCLK pulse. LDAC can be permanently low or pulsed as shown in Figure 2. Rev. A | Page 23 of 28 AD5623R/AD5643R/AD5663R INTERNAL REFERENCE SETUP The on-chip reference is off at power-up by default. This reference can be turned on or off by setting a software programmable bit, DB0, in the control register. Table 16 shows how the state of the bit corresponds to the mode of operation. Command 111 is reserved for setting up the internal reference (see Table 8). See Table 17 for the contents of the input shift register during the internal reference set-up command. Table 16. Reference Setup Register Internal Reference Setup Register (DB0) 0 1 Action Reference off (default) Reference on Table 17. 32-Bit Input Shift Register Contents for Reference Setup Function MSB DB23 to DB22 x Don’t care DB21 DB20 1 1 Command bits (C2 to C0) DB19 1 DB18 DB17 x x Address bits (A2 to A0) DB16 x DB15 to DB1 x Don’t care LSB DB0 1/0 Reference setup register Rev. A | Page 24 of 28 AD5623R/AD5643R/AD5663R MICROPROCESSOR INTERFACING AD5623R/AD5643R/AD5663R to Blackfin® ADSP-BF53X Interface Figure 56 shows a serial interface between the AD5623R/ AD5643R/AD5663R and the Blackfin ADSP-BF53X microprocessor. The ADSP-BF53X processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5623R/AD5643R/AD5663R, the setup for the interface is as follows: DT0PRI drives the DIN pin of the AD5623R/AD5643R/AD5663R, while TSCLK0 drives the SCLK of the parts. The SYNC is driven from TFS0. ADSP-BF53x1 TFS0 DTOPRI TSCLK0 Data is transmitted MSB first. To load data to the AD5623R/ AD5643R/AD5663R, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. AD5623R/AD5643R/AD5663R to 80C51/80L51 Interface Figure 58 shows a serial interface between the AD5623R/ AD5643R/AD5663R and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/ 80L51 drives SCLK of the AD5623R/AD5643R/AD5663R, and RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, Port Line P3.3 is used. When data is to be transmitted to the AD5623R/AD5643R/AD5663R, P3.3 is taken low. The 80C51/ 80L51 transmit data in 8-bit bytes only; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 output the serial data in a format that has the LSB first. The AD5623R/AD5643R/AD5663R must receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account. 80C51/80L511 P3.3 TxD RxD AD5643R/ AD5663R1 SYNC DIN SCLK 05858-037 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 56. AD5623R/AD5643R/AD5663R to Blackfin ADSP-BF53X Interface AD5623R/AD5643R/AD5663R to 68HC11/68L11 Interface Figure 57 shows a serial interface between the AD5623R/ AD5643R/AD5663R and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5623R/ AD5643R/AD5663R, and the MOSI output drives the serial data line of the DAC. 68HC11/68L111 PC7 SCK MOSI AD5643R/ AD5663R1 SYNC SCLK DIN 05858-039 05858-040 AD5643R/ AD5663R1 SYNC SCLK DIN 05858-038 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 58. AD5623R/AD5643R/AD5663R to 80C512/80L51 Interface AD5623R/AD5643R/AD5663R to MICROWIRE Interface Figure 59 shows an interface between the AD5623R/AD5643R/ AD5663R and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5623R/AD5643R/AD5663R on the rising edge of the SK. MICROWIRE1 CS SK SO 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 57. AD5623R/AD5643R/AD5663R to 68HC11/68L11 Interface The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 is configured with its CPOL bit as 0, and its CPHA bit as 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as described previously, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. AD5643R/ AD5663R1 SYNC SCLK DIN 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 59. AD5623R/AD5643R/AD5663R to MICROWIRE Interface Rev. A | Page 25 of 28 AD5623R/AD5643R/AD5663R APPLICATIONS INFORMATION USING A REFERENCE AS A POWER SUPPLY Because the supply current required by the AD5623R/AD5643R/ AD5663R is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the parts (see Figure 60). This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The voltage reference outputs a steady supply voltage for the AD5623R/AD5643R/ AD5663R. If the low dropout REF195 is used, it must supply 500 μA of current to the AD5623R/AD5643R/AD5663R, with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is 500 μA + (5 V/5 kΩ) = 1.25 mA The load regulation of the REF195 is typically 2 ppm/mA, which results in a 3 ppm (15 μV) error for the 1.5 mA current drawn from it. This corresponds to a 0.196 LSB error. 15V REF195 5V +5V R1 = 10kΩ R2 = 10kΩ +5V AD820/ OP295 VDD 10µF 0.1µF VOUT –5V ±5V AD5663R Figure 61. Bipolar Operation with the AD5663R USING THE AD5663R WITH A GALVANICALLY ISOLATED INTERFACE In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that can occur in the area where the DAC is functioning. iCoupler® provides isolation in excess of 2.5 kV. The AD5663R uses a 3-wire serial logic interface, so the ADuM1300 3-channel digital isolator provides the required isolation (see Figure 62). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5663R. 5V REGULATOR POWER 10µF 0.1µF THREE-WIRE SERIAL INTERFACE SYNC SCLK DIN VDD AD5623R/ AD5643R/ AD5663R VOUT = 0V TO 5V Figure 60. REF195 as Power Supply to the AD5623R/AD5643R/AD5663R BIPOLAR OPERATION USING THE AD5663R The AD5663R has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 61. The circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as follows: ⎡ ⎛ D ⎞ ⎛ R1 + R2 ⎞ ⎛ R2 ⎞⎤ VO = ⎢VDD × ⎜ ⎟×⎜ ⎟ − VDD × ⎜ ⎟⎥ ⎝ R1 ⎠⎦ ⎝ 65,536 ⎠ ⎝ R1 ⎠ ⎣ SCLK VIA VOA SCLK 05858-041 VDD ADuM1300 SDI VIB VOB AD5663R SYNC VOUT DATA VIC VOC DIN 05858-043 GND Figure 62. AD5663R with a Galvanically Isolated Interface where D represents the input code in decimal (0 to 65,535). With VDD = 5 V, R1 = R2 = 10 kΩ, ⎛ 10 × D ⎞ VO = ⎜ ⎟ −5V ⎝ 65,536 ⎠ This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a +5 V output. Rev. A | Page 26 of 28 05858-042 THREE-WIRE SERIAL INTERFACE AD5623R/AD5643R/AD5663R POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5663R should have separate analog and digital sections, each having its own area of the board. If the AD5663R is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5663R. The power supply to the AD5663R should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should be located as close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor have low effective series resistance (ESR) and effective series inductance (ESI), which is found, for example, in common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. A | Page 27 of 28 AD5623R/AD5643R/AD5663R OUTLINE DIMENSIONS INDEX AREA 3.00 BSC SQ 10 PIN 1 INDICATOR 1 3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 10 6 1.50 BCS SQ TOP VIEW 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 2.48 2.38 2.23 5 1 5 5.15 4.90 4.65 6 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8° 0° 0.80 0.60 0.40 0.80 0.75 0.70 SEATING PLANE 0.80 MAX 0.55 TYP SIDE VIEW 0.50 0.40 0.30 0.05 MAX 0.02 NOM 0.20 REF 1.74 1.64 1.49 SEATING PLANE 0.23 0.08 0.30 0.23 0.18 Figure 63. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Figure 64. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model AD5623RBCPZ-3R2 1 AD5623RBCPZ-3REEL71 AD5623RBRMZ-31 AD5623RBRMZ-3REEL71 AD5623RBRMZ-51 AD5623RBRMZ-5REEL71 AD5643RBRMZ-31 AD5643RBRMZ-3REEL71 AD5643RBRMZ-51 AD5643RBRMZ-5REEL71 AD5663RBCPZ-3R21 AD5663RBCPZ-3REEL71 AD5663RBRMZ-31 AD5663RBRMZ-3REEL71 AD5663RBRMZ-51 AD5663RBRMZ-5REEL71 EVAL-AD5663REB 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Accuracy ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL Internal Reference 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V Package Description 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Package Option CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 Branding D85 D85 D85 D85 D86 D86 D81 D81 D7Q D7Q D7S D7S D7S D7S D7H D7H Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05858-0-12/06(A) Rev. A | Page 28 of 28