AD5664

2.7 V to 5.5 V, 450 μA, Rail-to-Rail Output, Quad, 12-/16-Bit nanoDACs® AD5624/AD5664 FEATURES Low power, quad nanoDACs AD5664: 16 bits AD5624: 12 bits Relative accuracy: ±12 LSBs max Guaranteed monotonic by design 10-lead MSOP and 3 mm × 3 mm LFCSP_WD 2.7 V to 5.5 V power supply Power-on reset to zero Per channel power-down Serial interface, up to 50 MHz FUNCTIONAL BLOCK DIAGRAM VDD GND VREF AD5624/AD5664 INPUT REGISTER SCLK INTERFACE LOGIC INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB DAC REGISTER STRING DAC A BUFFER VOUTA SYNC INPUT REGISTER DIN INPUT REGISTER DAC REGISTER STRING DAC C BUFFER VOUTC DAC REGISTER STRING DAC D BUFFER VOUTD APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Figure 1. Table 1. Related Devices Part No. AD5624R/AD5644R/AD5664R Description 2.7 V to 5.5 V quad, 12-, 14-, 16-bit DACs with internal reference GENERAL DESCRIPTION The AD5624/AD5664, members of the nanoDAC family, are low power, quad, 12-, 16-bit buffered voltage-out DACs that operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. The AD5624/AD5664 require an external reference voltage to set the output range of the DAC. The part incorporates a poweron reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place. The parts contain a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The power consumption is 2.25 mW at 5 V, going down to 2.4 μW in power-down mode. The AD5624/AD5664 on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The AD5624/AD5664 use a versatile 3-wire serial interface that operates at clock rates up to 50 MHz, and are compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. PRODUCT HIGHLIGHTS 1. 2. 3. 4. Relative accuracy: ±12 LSBs maximum. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm, LFCSP_WD. Low power, typically consumes 1.32 mW at 3 V and 2.25 mW at 5 V. Maximum settling time of 4.5 μs (AD5624) and 7 μs (AD5664). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 05943-001 POWER-ON RESET POWER-DOWN LOGIC AD5624/AD5664 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Specifications..................................................................................... 3 AC Characteristics........................................................................ 4 Timing Characteristics ................................................................ 5 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 13 Theory of Operation ...................................................................... 15 D/A Section................................................................................. 15 Resistor String ............................................................................. 15 Output Amplifier........................................................................ 15 Serial Interface ............................................................................ 15 Input Shift Register .................................................................... 16 SYNC Interrupt .......................................................................... 16 Power-On Reset.......................................................................... 16 Software Reset............................................................................. 17 Power-Down Modes .................................................................. 17 LDAC Function .......................................................................... 18 Microprocessor Interfacing....................................................... 19 Applications..................................................................................... 20 Choosing a Reference for the AD5624/AD5664.................... 20 Using a Reference as a Power Supply for the AD5624/AD5664........................................................................ 20 Bipolar Operation Using the AD5624/AD5664..................... 21 Using AD5624/AD5664 with a Galvanically Isolated Interface ....................................................................................... 21 Power Supply Bypassing and Grounding................................ 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22 REVISION HISTORY 6/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD5624/AD5664 SPECIFICATIONS VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 2 AD5664 Resolution Relative Accuracy Differential Nonlinearity AD5624 Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk 2 ±1 −0.1 ±2 ±2.5 −100 10 10 ±10 ±1 ±1.5 Min A Grade 1 Typ Max Min B Grade1 Typ Max Unit Conditions/Comments 16 ±8 ±16 ±1 16 ±6 ±12 ±1 Bits LSB LSB Guaranteed monotonic by design 12 ±0.5 ±1 ±0.25 10 ±10 ±1 ±1.5 Bits LSB LSB mV mV % of FSR % of FSR μV/°C ppm dB μV 2 ±1 −0.1 ±2 ±2.5 −100 10 Guaranteed monotonic by design All zeroes loaded to DAC register All ones loaded to DAC register of FSR/°C DAC code = midscale ; VDD ± 10% Due to full-scale output change RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) 10 5 OUTPUT CHARACTERISTICS 3 Output Voltage Range Capacitive Load Stability DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance 10 5 μV/mA μV 0 2 10 0.5 30 4 VDD 0 2 10 0.5 30 4 VDD V nF nF Ω mA μs RL = ∞ RL = 2 kΩ VDD = 5 V Coming out of power-down mode; VDD = 5 V VREF = VDD = 5.5 V 170 0.75 26 200 VDD 170 0.75 26 200 VDD μA V kΩ μA V V pF ±2 0.8 2 3 2 3 ±2 0.8 All digital inputs VDD = 5 V, 3 V VDD = 5 V, 3 V Rev. 0 | Page 3 of 24 AD5624/AD5664 Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) 5 VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V 1 2 3 Min 2.7 A Grade 1 Typ Max 5.5 0.45 0.44 0.9 0.85 Min 2.7 B Grade1 Typ Max 5.5 0.45 0.44 0.9 0.85 Unit V Conditions/Comments VIH = VDD, VIL = GND mA mA VIH = VDD, VIL = GND 0.48 0.2 1 1 0.48 0.2 1 1 μA μA Temperature range: A grade and B grade: −40°C to +105°C. Linearity calculated using a reduced code range: AD5664 (Code 512 to Code 65,024); AD5624 (Code 32 to Code 4064); output unloaded. Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter 2 , 3 Output Voltage Settling Time AD5664 AD5624 Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise 1 2 Min Typ 4 3 1.8 10 0.1 −90 0.1 1 1 340 −80 120 100 15 Max 7 4.5 Unit μs μs V/μs nV-s nV-s dBs nV-s nV-s nV-s kHz dB nV/√Hz nV/√Hz μV p-p Conditions/Comments ¼ to ¾ scale settling to ±2 LSB ¼ to ¾ scale settling to ±0.5 LSB 1 LSB change around major carry VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz VREF = 2 V ± 0.1 V p-p VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz DAC code = midscale, 1 kHz DAC code = midscale, 10 kHz 0.1 Hz to 10 Hz Guaranteed by design and characterization, not production tested. Temperature range: −40°C to +105°C; typical at 25°C. 3 See the Terminology section. Rev. 0 | Page 4 of 24 AD5624/AD5664 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1 t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 1 2 Limit at TMIN, TMAX VDD = 2.7 V to 5.5 V 20 9 9 13 5 5 0 15 13 0 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to SCLK fall ignore SCLK falling edge to SYNC fall ignore Guaranteed by design and characterization, not production tested. Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. TIMING DIAGRAM t10 SCLK t1 t9 t2 t8 SYNC t4 t6 t3 t7 t5 DIN DB23 DB0 Figure 2. Serial Write Operation Rev. 0 | Page 5 of 24 05943-002 AD5624/AD5664 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND VOUT to GND VREF to GND Digital Input Voltage to GND Operating Temperature Range Industrial (A Grade, B Grade) Storage Temperature Range Junction Temperature (TJ max) Power Dissipation LFCSP_WD Package (4-Layer Board) θJA Thermal Impedance MSOP Package (4-Layer Board) θJA Thermal Impedance θJC Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +105°C −65°C to +150°C 150°C ( TJ max − TA)/θJA 61°C/W 142°C/W 43.7°C/W 260°C ± 5°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 24 AD5624/AD5664 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOUTA 1 VOUTB 2 GND 3 VOUTC 4 VOUTD 5 10 VREF AD5624/ AD5664 TOP VIEW (Not to Scale) 9 8 7 6 VDD DIN SYNC 05943-003 SCLK Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic VOUTA VOUTB GND VOUTC VOUTD SYNC Description Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. Reference Voltage Input. 7 8 9 10 SCLK DIN VDD VREF Rev. 0 | Page 7 of 24 AD5624/AD5664 TYPICAL PERFORMANCE CHARACTERISTICS 10 8 6 DNL ERROR (LSB) 0.20 VDD = VREF = 5V TA = 25°C 0.15 0.10 0.05 0 –0.05 –0.10 VDD = VREF = 5V TA = 25°C 4 INL ERROR (LSB) 2 0 –2 –4 –6 –8 –10 0 05943-004 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE –0.20 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 Figure 4. INL AD5664 1.0 VDD = VREF = 5V 0.8 TA = 25°C 0.6 4 0.4 INL ERROR (LSB) Figure 7. DNL AD5624 8 6 VDD = VREF = 5V MAX INL 0.2 0 –0.2 –0.4 ERROR (LSB) 2 MAX DNL 0 –2 –4 MIN DNL –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 05943-005 MIN INL 05856-022 –6 –8 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 Figure 5. INL AD5624 1.0 0.8 0.6 DNL ERROR (LSB) 10 Figure 8. INL Error and DNL Error vs. Temperature VDD = VREF = 5V TA = 25°C 8 6 4 VDD = 5V TA = 25°C MAX INL 0.4 0.2 0 –0.2 –0.4 –0.6 05943-006 ERROR (LSB) 2 MAX DNL 0 –2 –4 –6 –8 –10 0.75 1.25 1.75 2.25 2.75 3.25 VREF (V) 3.75 05943-009 MIN DNL –0.8 –1.0 0 10k 20k 30k CODE 40k 50k 60k MIN INL 4.25 4.75 Figure 6. DNL AD5664 Figure 9. INL and DNL Error vs. VREF Rev. 0 | Page 8 of 24 05943-007 –0.15 AD5624/AD5664 8 6 TA = 25°C 4 ERROR (LSB) 1.0 MAX INL 0.5 GAIN ERROR ERROR (% FSR) 2 MAX DNL 0 –2 –4 MIN INL 05943-010 0 FULL-SCALE ERROR –0.5 MIN DNL –1.0 –8 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 –2.0 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 Figure 10. INL and DNL Error vs. Supply 0 –0.02 –0.04 –0.06 ERROR (% FSR) Figure 13. Gain Error and Full-Scale Error vs. Supply 1.0 TA = 25°C 0.5 ZERO-SCALE ERROR VDD = 5V GAIN ERROR ERROR (mV) 0 –0.5 –1.0 –1.5 –2.0 –2.5 2.7 –0.08 –0.10 –0.12 –0.14 –0.16 –0.18 –0.20 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 05943-011 FULL-SCALE ERROR 3.2 3.7 4.2 VDD (V) 4.7 5.2 Figure 11. Gain Error and Full-Scale Error vs. Temperature 1.5 1.0 0.5 ERROR (mV) Figure 14. Zero-Scale Error and Offset Error vs. Supply 6 VDD = 5.5V TA = 25°C ZERO-SCALE ERROR 5 –0.5 –1.0 –1.5 OFFSET ERROR 05943-012 FREQUENCY 0 4 3 2 –2.5 –40 0 –20 0 20 40 60 TEMPERATURE (°C) 80 100 0.41 0.42 0.43 IDD (mA) 0.44 0.45 Figure 12. Zero-Scale Error and Offset Error vs. Temperature Figure 15. IDD Histogram with VDD = 5.5 V Rev. 0 | Page 9 of 24 05943-017 –2.0 1 05943-014 OFFSET ERROR 05943-013 –6 –1.5 AD5624/AD5664 8 7 6 VDD = 3.6V TA = 25°C FREQUENCY 5 4 3 2 05943-018 VDD = VREF = 5V TA = 25°C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND VOUT = 909mV/DIV 1 05943-021 1 0 0.39 0.40 0.41 IDD (mA) 0.42 0.43 TIME BASE = 4µs/DIV Figure 16. IDD Histogram with VDD = 3.6 V 0.20 0.15 0.10 VDD = VREF = 5V, 3V TA = 25°C DAC LOADED WITH ZERO SCALE – SINKING CURRENT Figure 19. Full-Scale Settling Time, 5 V VDD = VREF = 5V TA = 25°C ERROR VOLTAGE (V) 0.05 0 –0.05 VDD 1 –0.10 –0.15 –0.20 –0.25 –5 –4 05943-016 VOUT CH1 2.0V CH2 500mV M100µs 125MS/s A CH1 1.28V 8.0ns/pt –3 –2 –1 0 I (mA) 1 2 3 4 5 Figure 17. Headroom at Rails vs. Source and Sink Current 0.50 0.45 0.40 0.35 VDD = VREFIN = 3V VDD = VREFIN = 5V Figure 20. Power-On Reset to 0 V SYNC 1 3 SLCK IDD (mA) 0.30 0.25 0.20 0.15 0.10 0.05 0 20 40 60 TEMPERATURE (°C) 80 100 05943-026 VOUT 2 VDD = 5V 05943-023 TA = 25°C 0 –40 –20 CH1 5.0V CH3 5.0V CH2 500mV M400ns A CH1 1.4V Figure 18. Supply Current vs. Temperature Figure 21. Exiting Power-Down to Midscale Rev. 0 | Page 10 of 24 05943-022 DAC LOADED WITH FULL SCALE – SOURCING CURRENT 2 MAX(C2) 420.0mV AD5624/AD5664 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 2.522 2.521 VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER GLITCH IMPULSE = 9.494nV 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) 16 VREF = VDD TA = 25°C 14 VDD = 3V 12 TIME (µs) VOUT (V) 10 8 VDD = 5V 6 05943-024 05943-028 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 512 4 0 1 2 3 4 5 6 7 CAPACITANCE (nF) 8 9 10 Figure 22. Digital-to-Analog Glitch Impulse (Negative) 2.498 2.497 2.496 2.495 2.494 2.493 2.492 2.491 VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 0.424nV Figure 25. Settling Time vs. Capacitive Load VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALE VOUT (V) 1 05943-025 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 512 Figure 23. Analog Crosstalk –20 –30 –40 –50 VDD = 5V TA = 25°C DAC LOADED WITH FULL SCALE VREF = 2V ± 0.3V p-p 800 700 Figure 26. 0.1 Hz to 10 Hz Output Noise Plot VDD = VREF = 5V TA = 25°C OUTPUT NOISE (nV/√Hz) 600 500 400 300 200 05943-030 (dB) –60 –70 –80 05943-027 –90 –100 100 0 10 2k 4k (Hz) 6k 8k 10k 100 1k 10k FREQUENCY (Hz) 100k Figure 24. Total Harmonic Distortion Figure 27. Noise Spectral Density Rev. 0 | Page 11 of 24 05943-029 Y AXIS = 2µV/DIV X AXIS = 4s/DIV 1M AD5624/AD5664 5 0 –5 –10 –15 –20 –25 –30 05943-031 VDD = 5V TA = 25°C (dB) –35 –40 10k 100k 1M FREQUENCY (Hz) 10M Figure 28. Multiplying Bandwidth Rev. 0 | Page 12 of 24 AD5624/AD5664 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 4 and Figure 5. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 6 and Figure 7. Zero-Scale Error Zero-scale error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5624/AD5664 because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 12. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed in % of FSR. A plot of full-scale error vs. temperature can be seen in Figure 11. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a % of FSR. Zero-Code Error Drift This is a measurement of the change in zero-code error with a change in temperature. It is expressed in μV/°C. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/°C. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5624/ AD5664 with code 512 loaded in the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V, and VDD is varied by ±10%. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change and is measured from the 24th falling edge of SCLK. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) as shown in Figure 22. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. A plot of noise spectral density can be seen in Figure 27. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA. Rev. 0 | Page 13 of 24 AD5624/AD5664 Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s (see Figure 23). DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) using the command write to and update while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Rev. 0 | Page 14 of 24 AD5624/AD5664 THEORY OF OPERATION D/A SECTION The AD5624/AD5664 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 29 shows a block diagram of the DAC architecture. VDD REF (+) DAC REGISTER RESISTOR STRING REF (–) OUTPUT AMPLIFIER (GAIN = +2) VOUT R R R TO OUTPUT AMPLIFIER 05943-032 R GND Figure 29. DAC Architecture R 05943-033 Since the input coding to the DAC is straight binary, the ideal output voltage is given by D VOUT = VREFIN × ⎛ N ⎞ ⎜ ⎟ ⎝2 ⎠ Figure 30. Resistor String SERIAL INTERFACE The AD5624/AD5664 have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as with most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5624/AD5664 compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in DAC register contents and/or a change in the mode of operation. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when VIN = 2.0 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation. It must, however, be brought high again just before the next write sequence. where: D is the decimal equivalent of the binary code that is loaded to the DAC register: 0 to 4095 for AD5624 (12 bit). 0 to 65535 for AD5664 (16 bit). N is the DAC resolution. RESISTOR STRING The resistor string is shown in Figure 30. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. OUTPUT AMPLIFIER The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It can drive a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 17. The slew rate is 1.8 V/μs with a ¼ to ¾ full-scale settling time of 7 μs. Rev. 0 | Page 15 of 24 AD5624/AD5664 INPUT SHIFT REGISTER The input shift register is 24 bits wide The first two bits are don’t care bits. The next three bits are the Command bits, C2 to C0 (see Table 7), followed by the 3-bit DAC address, A2 to A0 (see Table 8), and then the 16-, 12-bit data-word. The data-word comprises the 16-, 12- bit input code followed by 0 or 4 don’t care bits for the AD5664 and AD5624 respectively (see Figure 31 and Figure 32). These data bits are transferred to the DAC register on the 24th falling edge of SCLK. Table 7. Command Definition C2 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 Command Write to input register n Update DAC register n Write to input register n, update all (software LDAC) Write to and update DAC channel n Power down DAC (power-up) Reset Load LDAC register Reserved SYNC INTERRUPT In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, then this acts as an interrupt to the write sequence. The input shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 33). POWER-ON RESET The AD5624/AD5664 family contains a power-on reset circuit that controls the output voltage during power-up. The AD5624/ AD5664 DAC outputs power up to 0 V and the output remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. Table 8. Address Command A2 0 0 0 0 1 A1 0 0 1 1 1 A0 0 1 0 1 1 ADDRESS (n) DAC A DAC B DAC C DAC D All DACs DB23 (MSB) X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DB0 (LSB) D1 D0 05943-034 DATA BITS COMMAND BITS ADDRESS BITS Figure 31. AD5664 Input Shift Register Contents DB23 (MSB) X X C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DB0 (LSB) X X 05943-035 DATA BITS COMMAND BITS ADDRESS BITS Figure 32. AD5624 Input Shift Register Contents SCLK SYNC DIN DB23 DB0 DB23 DB0 05943-036 INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 24TH FALLING EDGE Figure 33. SYNC Interrupt Facility Rev. 0 | Page 16 of 24 AD5624/AD5664 SOFTWARE RESET The AD5624/AD5664 contain a software reset function. Command 110 is reserved for the software reset function (see Table 7). The software reset command contains two reset modes that are software programmable by setting Bit DB0 in the control register. Table 9 shows how the state of the bit corresponds to the software reset modes of operation of the devices. Table 9. Software Reset Modes for the AD5624/AD5664 DB0 0 1 (Power-On Reset) Registers Reset to Zero DAC register Input shift register DAC register Input shift register LDAC register Power-down register Table 10. Modes of Operation for the AD5624/AD5664 DB5 0 0 1 1 DB4 0 1 0 1 Operating Mode Normal operation Power-down modes 1 kΩ to GND 100 kΩ to GND Three-state When both bits are set to 0, the parts work normally with their normal power consumption of 450 μA at 5 V. However, for the three power-down modes, the supply current falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This allows the output impedance of the part to be known while the part is in power-down mode. The outputs can either be connected internally to GND through a 1 kΩ or 100 kΩ resistor, or left open-circuited (three-state) (see Figure 34). POWER-DOWN MODES The AD5624/AD5664 contain four separate modes of operation. Command 100 is reserved for the power-down function (see Table 7). These modes are software programmable by setting two bits (DB5 and DB4) in the control register. Table 10 shows how the state of the bits corresponds to the mode of operation of the device. All DACs (DAC D to DAC A) can be powered down to the selected mode by setting the corresponding four bits (DB3, DB2, DB1, and DB0) to 1. By executing the same Command 100, any combination of DACs is powered up by setting Bit DB5 and Bit DB4 to normal operation mode. To select which combination of DAC channels to power-up, set the corresponding four bits (DB3, DB2, DB1, and DB0) to 1. See Table 11 for contents of the input shift register during the power-down/power-up operation. RESISTOR STRING DAC AMPLIFIER VOUT Figure 34. Output Stage During Power-Down The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shut down when powerdown mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 μs for VDD = 5 V and for VDD = 3 V (see Figure 21). DB15 to DB6 x Don’t care DB0 (LSB) DAC A Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation DB23 to DB22 (MSB) x Don’t care DB21 1 DB20 0 DB19 0 DB18 x DB17 x DB16 x DB5 PD1 DB4 PD0 DB3 DAC D DB2 DAC C DB1 DAC B Command bits (C2 to C0) Address bits (A2 to A0); don’t care Powerdown mode Power-down/power-up channel selection, set bit to 1 to select channel Rev. 0 | Page 17 of 24 05943-037 POWER-DOWN CIRCUITRY RESISTOR NETWORK AD5624/AD5664 LDAC FUNCTION The AD5624/AD5664 DACs have double-buffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings. The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. The user can write to three of the input registers individually and then write to the remaining input register and update all DAC registers, the outputs update simultaneously. Command 010 is reserved for this software LDAC. Access to the DAC registers is controlled by the LDAC function. The LDAC registers contain two modes of operation for each DAC channel. The DAC channels are selected by setting the bits of the 4-bit LDAC register (DB3, DB2, DB1, and DB0). Command 110 is reserved for setting up the LDAC register. When the LDAC bit register is set low, the corresponding DAC registers are latched and the input registers can change state without affecting the contents of the DAC registers. When the LDAC bit register is set high, however, the DAC registers become transparent and the contents of the input registers are transferred to them on the falling edge of the 24th SCLK pulse. This is equivalent to having an LDAC hardware pin tied permanently low for the selected DAC channel, that is, synchronous update mode. See Table 12 for the LDAC register mode of operation. See Table 13 for contents of the input shift register during the LDAC register setup command. This flexibility is useful in applications where the user wants to update select channels simultaneously, while the rest of the channels update synchronously. Table 12. LDAC Register Mode of Operation Load DAC Register LDAC Bits (DB3 to DB0) 0 1 LDAC Mode of Operation Normal operation (default), DAC register update is controlled by write command. The DAC registers are updated after new data is read in on the falling edge of the 24th SCLK pulse. Table 13. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624/AD5664 DB23 to DB22 (MSB) x Don’t Care DB15 to DB4 x Don’t cares DB0 (LSB) DacA DB21 1 DB20 1 DB19 0 DB18 x DB17 x DB16 x DB3 DacD DB2 DacC DB1 DacB Command bits (C2 to C0) Address bits (A3 to A0); don’t care Set bit to 0 or 1 for required mode of operation on respective channel Rev. 0 | Page 18 of 24 AD5624/AD5664 MICROPROCESSOR INTERFACING AD5624/AD5664 to Blackfin® ADSP-BF53x Interface Figure 35 shows a serial interface between the AD5624/AD5664 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5624/AD5664, the setup for the interface is as follows. DTOPRI drives the DIN pin of the AD5624/AD5664, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0. ADSP-BF53x1 TFS0 DTOPRI TSCLK0 AD5624/AD5664 to 80C51/80L51 Interface Figure 37 shows a serial interface between the AD5624/AD5664 and the 80C51/80L51 microcontroller. The setup for the interface is as follows. TxD of the 80C51/80L51 drives SCLK of the AD5624/AD5664, while RxD drives the serial data line of the part. The SYNC signal is derived from a bit-programmable pin on the port. In this case, port line P3.3 is used. When data is transmitted to the AD5624/AD5664, P3.3 is taken low. The 80C51/80L51 transmits data in 10-bit bytes only; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 output the serial data in a format that has the LSB first. The AD5624/AD5664 must receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account. 80C51/80L511 P3.3 TxD RxD AD5624/ AD56641 SYNC DIN SCLK 05943-038 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 35. Blackfin ADSP-BF53x Interface to AD5624/AD5664 AD5624/ AD56641 SYNC SCLK DIN 05943-040 05943-041 AD5624/AD5664 to 68HC11/68L11 Interface Figure 36 shows a serial interface between the AD5624/AD5664 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/ 68L11 drives the SCLK of the AD5624/AD5664, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows. The 68HC11/68L11 is configured with its CPOL bit as a 0 and its CPHA bit as a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as described previously, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 10-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5624/AD5664, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure. 68HC11/68L111 PC7 SCK MOSI 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 37. 80C51/80L51 Interface to AD5624/AD5664 AD5624/AD5664 to MICROWIRE Interface Figure 38 shows an interface between the AD5624/AD5664 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5624/AD5664 on the rising edge of the SK. MICROWIRE1 CS SK SO AD5624/ AD56641 SYNC SCLK DIN 1ADDITIONAL PINS OMITTED FOR CLARITY. AD5624/ AD56641 SYNC SCLK DIN 05943-039 Figure 38. MICROWIRE Interface to AD5624/AD5664 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 36. 68HC11/68L11 Interface to AD5624/AD5664 Rev. 0 | Page 19 of 24 AD5624/AD5664 APPLICATIONS CHOOSING A REFERENCE FOR THE AD5624/AD5664 To achieve the optimum performance from the AD5624/ AD5664, thought should be given to the choice of a precision voltage reference. The AD5624/AD5664 have only one reference input, VREF. The voltage on the reference input is used to supply the positive input to the DAC. Therefore, any error in the reference is reflected in the DAC. When choosing a voltage reference for high accuracy applications, the sources of error are initial accuracy, ppm drift, longterm drift, and output voltage noise. Initial accuracy on the output voltage of the DAC leads to a full-scale error in the DAC. To minimize these errors, a reference with high initial accuracy is preferred. Choosing a reference with an output trim adjustment, such as the ADR423, allows a system designer to trim out system errors by setting a reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error. Long-term drift is a measurement of how much the reference drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable during its entire lifetime. The temperature coefficient of a reference’s output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce temperature dependence of the DAC output voltage in ambient conditions. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. It is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. Precision voltage references such as the ADR425 produce low output noise in the 0.1 Hz to10 Hz range. Examples of recommended precision references for use as supply to the AD5624/AD5664 are shown in the Table 14. 3-WIRE SERIAL INTERFACE USING A REFERENCE AS A POWER SUPPLY FOR THE AD5624/AD5664 Because the supply current required by the AD5624/AD5664 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see Figure 39). This is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The voltage reference outputs a steady supply voltage for the AD5624/AD5664 (see Table 14 for a suitable reference). If the low dropout REF195 is used, it must supply 450 μA of current to the AD5624/AD5664, with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is 450 μA + (5 V/5 kΩ) = 1.45 mA The load regulation of the REF195 is typically 2 ppm/mA, which results in a 2.9 ppm (14.5 μV) error for the 1.45 mA current drawn from it. This corresponds to a 0.191 LSB error. 15V REF195 5V 500mA SYNC SCLK DIN VDD VREF VOUT = 0V TO 5V AD5624/ AD5664 Figure 39. REF195 as Power Supply to the AD5624/AD5664 Table 14. Partial List of Precision References for Use with the AD5624/AD5664 Part No. ADR425 ADR395 REF195 AD780 ADR423 Initial Accuracy (mV max) ±2 ±6 ±2 ±2 ±2 Temp Drift (ppmoC max) 3 25 5 3 3 0.1 Hz to 10 Hz Noise (μV p-p typ) 3.4 5 50 4 3.4 VOUT (V) 5 5 5 2.5/3 3 Rev. 0 | Page 20 of 24 05943-042 AD5624/AD5664 BIPOLAR OPERATION USING THE AD5624/AD5664 The AD5624/AD5664 have been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 40. The circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as follows: DATA V1C 5V REGULATOR POWER 10µF 0.1µF SCLK V1A VOA SCLK VDD ADuM1300 SDI V1B VOB AD5624/ AD5664 SYNC VOUT VOC DIN 05943-044 ⎡ ⎛ D ⎞ ⎛ R1 + R2 ⎞ ⎛ R2 ⎞⎤ VO = ⎢VDD × ⎜ ⎟×⎜ ⎟ − VDD × ⎜ ⎟⎥ ⎝ R1 ⎠⎦ ⎝ 65,536 ⎠ ⎝ R1 ⎠ ⎣ GND Figure 41. AD5624/AD5664 with a Galvanically Isolated Interface where D represents the input code in decimal (0 to 65536). With VDD = 5 V, R1 = R2 = 10 kΩ, ⎛ 10 × D ⎞ VO = ⎜ ⎟−5 V ⎝ 65,536 ⎠ POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to consider carefully the power supply and ground return layout on the board. The printed circuit board containing the AD5624/ AD5664 should have separate analog and digital sections, each having its own area of the board. If the AD5624/AD5664 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5624/AD5664. The power supply to the AD5624/AD5664 should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should be located as close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitor is the tantalum bead type. It is important that the 0.1 μF capacitor has low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a +5 V output. R2 = 10kΩ +5V +5V R1 = 10kΩ AD820/ OP295 VDD 10µF 0.1µF VOUT –5V ±5V AD5624/ AD5664 3-WIRE SERIAL INTERFACE Figure 40. Bipolar Operation with the AD5624/AD5664 USING AD5624/AD5664 WITH A GALVANICALLY ISOLATED INTERFACE In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur in the area where the DAC is functioning. Isocouplers provide isolation in excess of 3 kV. The AD5624/AD5664 use a 3-wire serial logic interface, so the ADuM130x 3-channel digital isolator provides the required isolation (see Figure 41). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5624/AD5664. Rev. 0 | Page 21 of 24 05943-043 AD5624/AD5664 OUTLINE DIMENSIONS INDEX AREA 3.00 BSC SQ 10 PIN 1 INDICATOR 1 1.50 BCS SQ TOP VIEW 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 2.48 2.38 2.23 5 6 0.80 0.75 0.70 SEATING PLANE 0.80 MAX 0.55 TYP SIDE VIEW 0.50 0.40 0.30 0.05 MAX 0.02 NOM 0.20 REF 1.74 1.64 1.49 0.30 0.23 0.18 Figure 42. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8° 0° 0.80 0.60 0.40 10 6 1 5 5.15 4.90 4.65 SEATING PLANE 0.23 0.08 Figure 43. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model AD5624BRMZ AD5624BRMZ-REEL7 AD5624BCPZ-250RL7 AD5624BCPZ-REEL7 AD5664ARMZ AD5664ARMZ-REEL7 AD5664BRMZ AD5664BRMZ-REEL7 AD5664BCPZ-250RL7 AD5664BCPZ-REEL7 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Accuracy ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±16 LSB INL ±16 LSB INL ±12 LSB INL ±12 LSB INL ±12 LSB INL ±12 LSB INL Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD Package Option RM-10 RM-10 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 Branding D5J D5J D5J D5J D7C D7C D78 D78 D78 D78 Rev. 0 | Page 22 of 24 AD5624/AD5664 NOTES Rev. 0 | Page 23 of 24 AD5624/AD5664 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05943-0-6/06(0) Rev. 0 | Page 24 of 24