Quad, 16-Bit DAC with 5 ppm/°C
On-Chip Reference in 14-Lead TSSOP
AD5666
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VREFIN/VREFOUT
VDD
AD5666
1.25V/2.5V
REF
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
VOUTA
SCLK
SYNC
INTERFACE
LOGIC
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC B
STRING
DAC C
BUFFER
VOUTB
BUFFER
VOUTC
DIN
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
VOUTD
SDO
LDAC CLR
POWER-ON
RESET
POWER-DOWN
LOGIC
POR
GND
05298-001
Low power quad 16-bit DAC
14-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware LDAC with LDAC override function
CLR function to programmable code
SDO daisy-chaining option
Rail-to-rail operation
Figure 1.
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5666 is a low power, quad, 16-bit, buffered voltageoutput DAC. The part operates from a single 2.7 V to 5.5 V
supply and is guaranteed monotonic by design.
The AD5666 has an on-chip reference with an internal gain of 2.
The AD5666-1 has a 1.25 V 5 ppm/°C reference, giving a full-scale
output of 2.5 V; the AD5666-2 has a 2.5 V 5 ppm/°C reference,
giving a full-scale output of 5 V. The on-board reference is off at
power-up, allowing the use of an external reference. The internal
reference is turned on by writing to the DAC.
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V (POR pin low) or to midscale
(POR pin high) and remains powered up at this level until a valid
write takes place. The part contains a power-down feature that
reduces the current consumption of the device to 400 nA at 5 V
and provides software-selectable output loads while in power-down
mode for any or all DAC channels.
The outputs of all DACs can be updated simultaneously using
the LDAC function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an
asynchronous CLR that clears all DACs to a software-selectable
code—0 V, midscale, or full scale.
The AD5666 utilizes a versatile 3-wire serial interface that operates
at clock rates of up to 50 MHz and is compatible with standard
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The
on-chip precision output amplifier enables rail-to-rail output
swing.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Quad, 16-bit DAC.
On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
Available in 14-lead TSSOP.
Selectable power-on reset to 0 V or midscale.
Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
AD5666
TABLE OF CONTENTS
Features .............................................................................................. 1
Resistor String ............................................................................. 20
Applications ....................................................................................... 1
Internal Reference ...................................................................... 20
Functional Block Diagram .............................................................. 1
Output Amplifier........................................................................ 21
General Description ......................................................................... 1
Serial Interface ............................................................................ 21
Product Highlights ........................................................................... 1
Input Shift Register .................................................................... 22
Revision History ............................................................................... 2
SYNC Interrupt .......................................................................... 22
Specifications..................................................................................... 3
Daisy-Chaining ........................................................................... 23
AC Characteristics........................................................................ 7
Internal Reference Register ....................................................... 23
Timing Characteristics ................................................................ 8
Power-On Reset .......................................................................... 23
Absolute Maximum Ratings.......................................................... 10
Power-Down Modes .................................................................. 23
ESD Caution ................................................................................ 10
Clear Code Register ................................................................... 25
Pin Configuration and Function Descriptions ........................... 11
LDAC Function .......................................................................... 25
Typical Performance Characteristics ........................................... 12
Power Supply Bypassing and Grounding ................................ 25
Terminology .................................................................................... 18
Outline Dimensions ....................................................................... 27
Theory of Operation ...................................................................... 20
Ordering Guide .......................................................................... 27
D/A Section ................................................................................. 20
REVISION HISTORY
6/10—Rev. C to Rev. D
Changes to Figure 19 and Figure 20 Captions ............................ 14
10/09—Rev. B to Rev. C
Changes to Table 7 .......................................................................... 21
2/09—Rev. A to Rev. B
Changes to Reference Current Parameter, Table 1 ....................... 3
Changes to Reference Current Parameter, Table 2 ....................... 5
Updated Outline Dimensions ....................................................... 27
11/05—Rev. 0 to Rev. A
Change to General Description ...................................................... 1
Change to Specifications .................................................................. 3
10/05—Revision 0: Initial Version
Rev. D | Page 2 of 28
AD5666
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE 2
Resolution
Relative Accuracy
Differential Nonlinearity
Min
16
16
1
±2
−0.2
±2.5
±1
–80
DC Crosstalk
(Internal Reference)
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Input Voltage
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
Reference TC3
Reference Output
Impedance
LOGIC INPUTS3
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
Min
B Grade1
Typ
Max
±32
±1
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection
Ratio
DC Crosstalk
(External Reference)
OUTPUT CHARACTERISTICS 3
Output Voltage Range
Capacitive Load Stability
A Grade 1
Typ
Max
±16
±1
9
1
±2
−0.2
−1
±1
±2.5
±1
–80
±9
9
−1
±1
±9
Unit
Bits
LSB
LSB
mV
μV/°C
% FSR
% FSR
ppm
mV
dB
10
10
μV
5
10
25
5
10
25
μV/mA
μV
μV
10
10
μV/mA
0
VDD
0
2
10
0.5
30
4
VDD
20
0
55
VDD
VDD
20
0
14.6
2.495
±5
7.5
VDD
2
10
0.5
30
4
14.6
2.505
±10
2.495
±5
7.5
±3
0.8
2
55
VDD
V
μA
V
kΩ
See Figure 6
Guaranteed monotonic by design
(see Figure 7)
All 0s loaded to DAC register (see Figure 13)
All 1s loaded to DAC register (see Figure 12)
Of FSR/°C
VDD ± 10%
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
RL = ∞
RL = 2 kΩ
VDD = 5 V
Coming out of power-down mode VDD = 5 V
VREF = VDD = 5.5 V
Per DAC channel
2.505
±10
V
ppm/°C
kΩ
At ambient
±3
0.8
μA
V
V
pF
All digital inputs
VDD = 5 V
VDD = 5 V
2
3
V
nF
nF
Ω
mA
μs
Conditions/Comments
3
Rev. D | Page 3 of 28
AD5666
Parameter
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage
Current
High Impedance Output
Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode) 4
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes) 5
VDD = 4.5 V to 5.5 V
Min
A Grade 1
Typ
Max
Min
B Grade1
Typ
Max
0.4
VDD −
1
Unit
Conditions/Comments
0.4
V
ISINK = 2 mA
ISOURCE = 2 mA
±0.25
μA
VDD −
1
±0.25
2
4.5
2
5.5
4.5
pF
5.5
V
0.7
1.3
0.9
1.6
0.7
1.3
0.9
1.6
mA
mA
All digital inputs at 0 or VDD,
DAC active, excludes load current
VIH = VDD and VIL = GND
Internal reference off
Internal reference on
0.4
1
0.4
1
μA
VIH = VDD and VIL = GND
1
Temperature range is −40°C to +105°C, typical at 25°C.
Linearity calculated using a reduced code range of 512 to 65,024. Output unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All four DACs powered down.
2
Rev. D | Page 4 of 28
AD5666
VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 2
Resolution
Relative Accuracy
Differential Nonlinearity
A Grade 1
Min
Typ Max
B Grade1
Min
Typ Max
16
16
±32
±1
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature
Coefficient
Offset Error
DC Power Supply Rejection
Ratio
DC Crosstalk
(External Reference)
1
±2
−0.2
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Input Voltage
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
Reference TC3
Reference Output
Impedance
LOGIC INPUTS3
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage
Current
High Impedance Leakage
9
1
±2
−0.2
−1
±1
±2.5
±1
–80
DC Crosstalk
(Internal Reference)
OUTPUT CHARACTERISTICS 3
Output Voltage Range
Capacitive Load Stability
±16
±1
9
−1
±1
±2.5
±9
±1
–80
±9
Unit
Bits
LSB
LSB
mV
μV/°C
% FSR
% FSR
ppm
mV
dB
10
10
μV
5
10
25
5
10
25
μV/mA
μV
μV
10
10
μV/mA
0
VDD
0
VDD
2
10
0.5
30
4
VDD
40
0
VDD
40
0
14.6
1.247
±5
7.5
1.247
±5
7.5
±3
0.8
2
0.4
2
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
kΩ
Per DAC channel
1.253
±15
V
ppm/°C
kΩ
At ambient
±3
0.8
μA
V
V
pF
0.4
V
±0.25
μA
VDD −
0.5
±0.25
VDD ± 10%
VREF = VDD = 3.6 V
3
VDD −
0.5
Of FSR/°C
V
μA
55
VDD
2
3
All 1s loaded to DAC register (see Figure 12)
VDD = 3 V coming out of power-down mode
Coming out of power-down VDD = 3 V
14.6
1.253
±15
See Figure 5
Guaranteed monotonic by design (see Figure
6)
All 0s loaded to DAC register (see Figure 13)
V
nF
nF
Ω
mA
μs
2
10
0.5
30
4
55
VDD
Conditions/Comments
2
Rev. D | Page 5 of 28
pF
RL = ∞
RL = 2 kΩ
VDD = 3 V
VDD = 3 V
ISINK = 2 mA
ISOURCE = 2 mA
AD5666
Parameter
Current
POWER REQUIREMENTS
VDD
IDD (Normal Mode) 4
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes) 5
VDD = 2.7 V to 3.6 V
A Grade 1
Min
Typ Max
B Grade1
Min
Typ Max
Unit
Conditions/Comments
2.7
2.7
3.6
V
3.6
0.65
1.3
0.85
1.5
0.65
1.3
0.85
1.5
mA
mA
All digital inputs at 0 or VDD,
DAC active, excludes load current
VIH = VDD and VIL = GND
Internal reference off
Internal reference on
0.2
1
0.2
1
μA
VIH = VDD and VIL = GND
1
Temperature range is −40°C to +105°C, typical at 25°C.
Linearity calculated using a reduced code range of 512 to 65,024. Output unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All four DACs powered down.
2
Rev. D | Page 6 of 28
AD5666
AC CHARACTERISTICS
VDD =2.7V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter 1, 2
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Reference Feedthrough
SDO Feedthrough
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
Output Noise
Min
Typ
6
1.5
4
−90
3
0.1
0.5
2.5
3
340
−80
120
100
15
Max
10
Unit
μs
V/μs
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
nV/√Hz
nV/√Hz
μV p-p
Conditions/Comments 3
¼ to ¾ scale settling to ±2 LSB
1 LSB change around major carry (see Figure 29)
VREF = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz
Daisy-chain mode; SDO load is 10 pF
VREF = 2 V ± 0.2 V p-p
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = 0x8400, 1 kHz
DAC code = 0x8400, 10 kHz
0.1 Hz to 10 Hz
1
Guaranteed by design and characterization; not production tested.
See the Terminology section.
3
Temperature range is −40°C to + 105°C, typical at 25°C.
2
Rev. D | Page 7 of 28
AD5666
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 5. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
t1 1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16 2, 3
t173
t183
t193
2
3
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
Measured with the load circuit of Figure 16. t16 determines the maximum SCLK frequency in daisy-chain mode.
Daisy-chain mode only.
2mA
TO OUTPUT
PIN
IOL
VOH (MIN)
CL
50pF
2mA
IOH
05298-002
1
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
8
8
13
4
4
0
15
13
0
10
15
5
0
300
22
5
8
0
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. D | Page 8 of 28
AD5666
t10
t1
t9
SCLK
t8
t2
t3
t4
t7
SYNC
t6
t5
DB31
DIN
DB0
t14
t11
LDAC1
t12
LDAC2
t13
CLR
05298-003
1ASYNCHRONOUS LDAC UPDATE MODE
2SYNCHRONOUS LDAC UPDATE MODE
Figure 3. Serial Write Operation
t1
SCLK
32
t7
t3
t4
64
t18
t2
t17
SYNC
t8
t9
DIN
DB31
DB0
DB0
DB31
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t16
DB0
DB31
SDO
UNDEFINED
INPUT WORD FOR DAC N
t19
t11
05298-004
LDAC
Figure 4. Daisy-Chain Timing Diagram
Rev. D | Page 9 of 28
AD5666
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUT to GND
VREFIN/VREFOUT to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ MAX)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
Reflow Soldering Peak Temperature
SnPb
Pb Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
+150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
(TJ MAX − TA)/θJA
150.4°C/W
240°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 10 of 28
AD5666
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC
1
14 SCLK
SYNC
2
13 DIN
VDD
3
VOUTA
4
VOUTC
5
POR
6
9
CLR
VREFIN/VREFOUT
7
8
SDO
12 GND
11 VOUTB
10 VOUTD
05298-005
AD5666
TOP VIEW
(Not to Scale)
Figure 5. 14-Lead TSSOP (RU-14)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
2
SYNC
3
VDD
4
5
6
VOUTA
VOUTC
POR
7
VREFIN/VREFOUT
8
SDO
9
CLR
10
11
12
13
VOUTD
VOUTB
GND
DIN
14
SCLK
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in
on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising
edge of SYNC acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up
the part to midscale.
The AD5666 has a common pin for reference input and reference output. When using the internal
reference, this is the reference output pin. When using an external reference, this is the reference input
pin. The default for this pin is as a reference input.
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading
back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge
of SCLK and is valid on the falling edge of the clock.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Rev. D | Page 11 of 28
AD5666
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
10
8
0.6
DNL ERROR (LSB)
6
4
2
0
–2
0.4
0.2
0
–0.2
–0.4
–4
05298-009
–0.6
–6
05298-006
–0.8
45000
50000
55000
60000
65000
50000
55000
60000
65000
50000
55000
40000
45000
35000
30000
25000
20000
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
15000
0
–1.0
5000
–10
0
–8
10000
INL ERROR (LSB)
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
0.8
VDD = VREF = 5V
TA = 25°C
CODE
Figure 9. DNL—AD5666-2
Figure 6. INL
10
1.0
0.8
6
INL ERROR (LSB)
0.6
0.4
0.2
0
–0.2
4
2
0
–2
–4
–0.4
05298-010
–6
–0.6
05298-007
–8
60k
CODE
Figure 7. DNL
Figure 10. INL—AD5666-1
1.0
0.6
4
0.4
–6
–0.6
CODE
CODE
Figure 11. DNL—AD5666-1
Figure 8. INL—AD5666-2
Rev. D | Page 12 of 28
60000
45000
–1.0
40000
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
5000
10000
–0.8
0
–8
–10
65000
–0.4
05298-008
–4
05298-011
–0.2
35000
–2
0
30000
0
0.2
25000
2
20000
DNL ERROR (LSB)
6
0
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.8
15000
8
5000
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
10000
10
INL ERROR (LSB)
40000
50k
35000
40k
30000
30k
CODE
25000
20k
20000
10k
15000
0
5000
–1.0
–10
0
–0.8
10000
DNL ERROR (LSB)
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
8
VDD = VREF = 5V
TA = 25°C
AD5666
1.0
0
VDD = 5V
TA = 25°C
–0.02
0.5
ZERO-SCALE ERROR
–0.04
GAIN ERROR
0
ERROR (mV)
ERROR (% FSR)
–0.06
–0.08
–0.10
–0.12
–0.14
–0.5
–1.0
–1.5
FULL-SCALE ERROR
–0.20
–40
–2.0
05298-030
–0.18
–20
0
20
40
60
TEMPERATURE (°C)
80
–2.5
2.7
100
Figure 12. Gain Error and Full-Scale Error vs. Temperature
3.7
4.2
VDD (V)
4.7
5.2
3.5
VDD = 3.6V
VDD = 5.5V
3.0
ZERO-SCALE ERROR
0.5
2.5
FREQUENCY
ERROR (mV)
3.2
Figure 15. Zero-Scale Error and Offset Error vs. Supply Voltage
1.5
1.0
OFFSET ERROR
05298-045
–0.16
0
–0.5
–1.0
2.0
1.5
1.0
–1.5
OFFSET ERROR
05298-021
–2.5
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
05298-028
0.5
–2.0
0
0.62 0.63 0.64 0.65 0.66 0.67 0.68 0.69
IDD (mA)
100
Figure 13. Zero-Scale Error and Offset Error vs. Temperature
0.7
0.71 0.72
Figure 16. IDD Histogram with External Reference
2.5
1.0
VDD = 3.6V
VDD = 5.5V
0.5
2.0
FREQUENCY
0
FULL-SCALE ERROR
–0.5
1.5
1.0
–1.0
0.5
–2.0
2.7
3.2
3.7
4.2
VDD (V)
4.7
05298-029
–1.5
05298-031
ERROR (% FSR)
GAIN ERROR
0
1.26
5.2
1.28
1.30
1.32
1.34
IDD (mA)
1.36
Figure 17. IDD Histogram with Internal Reference
Figure 14. Gain Error and Full-Scale Error vs. Supply Voltage
Rev. D | Page 13 of 28
1.38
AD5666
0.50
1.0
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
0.40
TA = 25°C
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
0.8
0.7
0.20
0
0.6
–0.10
0.4
–0.20
0.3
0.2
VDD = 5V
VREFOUT = 2.5V
–0.30
–0.40
–0.50
–10
–8
–6
–4
VDD = VREF = 3V
0.5
–2
0
2
CURRENT (mA)
4
6
8
0.1
0
512
10
Figure 18. Headroom at Rails vs. Source and Sink
10512
20512
30512
40512
CODE
50512
60512
Figure 21. Supply Current vs. Code
1.0
6.00
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
FULL SCALE
0.9
VDD = VREFIN = 5.5V
0.8
3/4 SCALE
4.00
3.00
0.7
IDD (mA)
5.00
05298-014
0.10
IDD (mA)
VDD = 3V
VREFOUT = 1.25V
05298-019
ERROR VOLTAGE (V)
0.30
VOUT (V)
VDD = VREF = 5V
0.9
MIDSCALE
2.00
1/4 SCALE
0.6
VDD = VREFIN = 3.6V
0.5
0.4
0.3
1.00
–20
–10
0
10
CURRENT (mA)
20
0.1
0
–40
30
Figure 19. Source and Sink Current Capability with VDD = 5 V
–20
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 22. Supply Current vs. Temperature
1.0
4.00
3.00
05298-015
–1.00
–30
ZERO SCALE
05298-012
0.2
0
TA = 25°C
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.9
0.8
FULL SCALE
IDD (mA)
2.00
MIDSCALE
1.00
0.6
0.5
0.4
1/4 SCALE
0.3
–1.00
–30
0.2
ZERO SCALE
–20
–10
0
10
CURRENT (mA)
20
30
Figure 20. Source and Sink Current Capability with VDD = 3 V
05298-016
0
05298-013
VOUT (V)
0.7
3/4 SCALE
0.1
0
2.7
3.2
3.7
4.2
VDD (V)
4.7
Figure 23. Supply Current vs. Supply Voltage
Rev. D | Page 14 of 28
5.2
AD5666
4.0
TA = 25°C
VDD = VREF = 5V
TA = 25°C
3.5
3.0
2.5
IDD (mA)
VDD
2.0
1
VDD = 5V
1.5
1.0
0
1
2
3
4
5
05298-033
VDD = 3V
0
2
05298-017
0.5
VOUT
6
CH1 2.0V
VLOGIC (V)
CH2 1.0V
M100μs 125MS/s
A CH1
1.28V
8.0ns/pt
Figure 27. Power-On Reset to Midscale
Figure 24. Supply Current vs. Logic Input Voltage
SYNC
1
SLCK
3
VDD = VREF = 5V
TA = 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
VOUT
VOUT = 909mV/DIV
VDD = 5V
05298-018
05298-034
2
1
CH1 5.0V
CH3 5.0V
TIME BASE = 4μs/DIV
VDD
1
MAX(C2)*
420.0mV
05298-020
2
VOUT
M100μs 125MS/s
A CH1
1.28V
A CH1
1.4V
8.0ns/pt
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
2.490
2.489
2.488
2.487
2.486
2.485
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4ns/SAMPLE NUMBER
GLITCH IMPULSE = 3.55nV-s
1 LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
05298-022
VOUT (V)
VDD = VREF = 5V
TA = 25°C
CH2 500mV
M400ns
Figure 28. Exiting Power-Down to Midscale
Figure 25. Full-Scale Settling Time
CH1 2.0V
CH2 500mV
0
64
128
192
256
320
SAMPLE
384
Figure 29. Digital-to-Analog Glitch Impulse
Figure 26. Power-On Reset to 0 V
Rev. D | Page 15 of 28
448
512
AD5666
2.5000
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
DAC LOADED WITH MIDSCALE
2.4995
2.4990
2.4980
10μV/DIV
VOUT (V)
2.4985
2.4975
2.4970
1
2.4965
2.4950
0
64
128
192
256
320
SAMPLE
384
448
05298-035
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4ns/SAMPLE NUMBER
2.4955
05298-038
2.4960
512
5s/DIV
Figure 33. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
Figure 30. Analog Crosstalk
2.4900
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
DAC LOADED WITH MIDSCALE
2.4895
2.4890
5μV/DIV
2.4880
2.4875
1
2.4870
2.4865
0
64
128
192
256
320
SAMPLE
384
448
05298-039
2.4855
05298-036
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4ns/SAMPLE NUMBER
2.4860
512
4s/DIV
Figure 31. DAC-to-DAC Crosstalk
Figure 34. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
800
TA = 25°C
MIDSCALE LOADED
700
1
600
500
400
300
VDD = 5V
VREFOUT = 2.5V
200
VDD = 3V
VREFOUT = 1.25V
100
Y AXIS = 2μV/DIV
X AXIS = 4s/DIV
0
100
Figure 32. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
1000
05298-040
OUTPUT NOISE (nV/ Hz)
VDD = VREF = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
05298-037
VOUT (V)
2.4885
10000
FREQUENCY (Hz)
100000
Figure 35. Noise Spectral Density, Internal Reference
Rev. D | Page 16 of 28
1000000
AD5666
–20
VDD = 5V
TA = 25°C
DAC LOADED WITH FULL SCALE
VREF = 2V ± 0.3Vp-p
–30
–40
CLR
3
VOUT F
(dB)
–50
–60
–70
–80
VOUT B
–100
2k
4k
6k
FREQUENCY (Hz)
8k
05298-043
4
05298-041
–90
2
10k
CH3 5.0V
Figure 36. Total Harmonic Distortion
CH2 1.0V
CH4 1.0V
M200ns A CH3
1.10V
Figure 38. Hardware CLR
5
16
VREF = VDD
TA = 25°C
VDD = 5V
TA = 25°C
0
14
–5
VDD = 3V
–10
(dB)
10
VDD = 5V
8
–15
–20
–25
–30
6
4
0
1
2
3
4
5
6
7
CAPACITANCE (nF)
8
9
10
Figure 37. Settling Time vs. Capacitive Load
–35
–40
10k
05298-044
05298-042
TIME (μs)
12
100k
1M
FREQUENCY (Hz)
Figure 39. Multiplying Bandwidth
Rev. D | Page 17 of 28
10M
AD5666
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer
function. Figure 6 shows a plot of typical INL vs. code.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Figure 7 shows a plot of typical DNL vs. code.
Offset Error
Offset error is a measure of the difference between the actual
VOUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
AD5666 with Code 512 loaded into the DAC register. It can be
negative or positive and is expressed in millivolts.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5666, because the output of the DAC cannot go below 0 V.
It is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in millivolts.
Figure 13 shows a plot of typical zero-code error vs.
temperature.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range. Figure 13 shows a plot of
typical full-scale error vs. temperature.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 29.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V, and VDD is varied ±10%.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is, LDAC is high). It is expressed in
decibels.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-s and measured with a
full-scale change on the digital input pins, that is, from all 0s to
all 1s or vice versa.
Rev. D | Page 18 of 28
AD5666
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping LDAC
high, and then pulsing LDAC low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
Total Harmonic Distortion (THD)
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-s.
Rev. D | Page 19 of 28
AD5666
THEORY OF OPERATION
D/A SECTION
R
The AD5666 DAC is fabricated on a CMOS process. The architecture consists of a string of DACs followed by an output buffer
amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/°C
reference with an internal gain of 2. Figure 40 shows a block
diagram of the DAC architecture.
R
TO OUTPUT
AMPLIFIER
R
VDD
REF (+)
RESISTOR
STRING
OUTPUT
AMPLIFIER
(GAIN = +2)
R
GND
R
05298-024
REF (–)
VOUT
05298-023
DAC REGISTER
Figure 40. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
Figure 41. Resistor String
INTERNAL REFERENCE
D
VOUT = VREFIN × ⎛⎜ N ⎞⎟
⎝2 ⎠
The ideal output voltage when using and internal reference is
given by
D
VOUT = 2 × V REFOUT × ⎛⎜ N ⎞⎟
⎝2 ⎠
The AD5666 has an on-chip reference with an internal gain of 2.
The AD5666-1 has a 1.25 V 5 ppm/°C reference, giving a full-scale
output of 2.5 V. The AD5666-2 has a 2.5 V 5 ppm/°C reference,
giving a full-scale output of 5 V. The on-board reference is off at
power-up, allowing the use of an external reference. The internal
reference is enabled via a write to a control register.
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register.
0 to 65,535 for AD5666 (16 bits).
N = the DAC resolution.
The internal reference associated with each part is available at
the VREFOUT pin. A buffer is required if the reference output is
used to drive external loads. When using the internal reference,
it is recommended that a 100 nF capacitor be placed between
the reference output and GND for reference stability.
RESISTOR STRING
Individual channel power-down is not supported while using
the internal reference.
The resistor string section is shown in Figure 41. It is simply a
string of resistors, each of value R. The code loaded into the
DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
Rev. D | Page 20 of 28
AD5666
Table 7. Command Definitions
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 2 kΩ in parallel with
1000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 19 and Figure 20. The slew rate
is 1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs.
SERIAL INTERFACE
The AD5666 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as most DSPs. See Figure 3 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5666 compatible with high speed
DSPs. On the 32nd falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change
in DAC register contents and/or a change in the mode of
operation. At this stage, the SYNC line can be kept low or be
brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when VIN = 2 V
than it does when VIN = 0.8 V, SYNC should be idled low
between write sequences for even lower power operation of the
part. As is mentioned previously, however, SYNC must be
brought high again just before the next write sequence.
C3
0
0
0
0
0
0
0
0
1
1
–
1
Command
C2 C1
0
0
0
0
0
1
0
1
1
1
1
0
0
–
1
1
0
0
1
1
0
0
–
1
C0
0
1
0
1
0
1
0
1
0
1
–
1
Description
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Set up DCEN/REF register
No operation
Reserved
Reserved
Table 8. Address Commands
Address (n)
A3
0
0
0
0
1
Rev. D | Page 21 of 28
A2
0
0
0
0
1
A1
0
0
1
1
1
A0
0
1
0
1
1
Selected DAC
Channel
DAC A
DAC B
DAC C
DAC D
All DACs
AD5666
INPUT SHIFT REGISTER
SYNC INTERRUPT
The input shift register is 32 bits wide (see Figure 42). The first
four bits are don’t cares. The next four bits are the command
bits, C3 to C0 (see Table 8), followed by the 4-bit DAC address
bits, A3 to A0 (see Table 9) and finally the 16-bit data-word.
The data-word comprises the 16-bit input code followed by four
don’t care bits for the AD5666 (see Figure 42). These data bits
are transferred to the DAC register on the 32nd falling edge of
SCLK.
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if SYNC is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 43).
DB31 (MSB)
X
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
COMMAND BITS
05298-025
DATA BITS
ADDRESS BITS
Figure 42. AD5666 Input Register Content
SCLK
SYNC
DIN
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
DB31
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
Figure 43. SYNC Interrupt Facility
Rev. D | Page 22 of 28
05298-026
X
DB0 (LSB)
AD5666
DAISY-CHAINING
POWER-ON RESET
For systems that contain several DACs, or where the user
wishes to read back the DAC contents for diagnostic purposes,
the SDO pin can be used to daisy-chain several devices together
and provide serial readback.
The AD5666 contains a power-on reset circuit that controls the
output voltage during power-up. By connecting the POR pin
low, the AD5666 output powers up to 0 V; by connecting the
POR pin high, the AD5666 output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
(see Table 7). Any events on LDAC or CLR during power-on
reset are ignored.
The daisy-chain mode is enabled through a software executable
DCEN command. Command 1000 is reserved for this DCEN
function (see Table 7). The daisy-chain mode is enabled by
setting a bit (DB1) in the DCEN register. The default setting is
standalone mode, where Bit DCEN = 0. Table 9 shows how the
state of the bits corresponds to the mode of operation of the
device.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than 32 clock pulses are applied, the
data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next DAC in the chain, a multi-DAC interface is
constructed. Each DAC in the system requires 32 clock pulses;
therefore, the total number of clock cycles must equal 32N,
where N is the total number of devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This prevents any further data from being clocked
into the input shift register.
If SYNC is taken high before 32 clocks are clocked into the part,
it is considered an invalid frame and the data is discarded.
The serial clock can be continuous or a gated clock. A continuous SCLK source can be used only if the SYNC can be held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and SYNC must be taken high after the final clock to
latch the data.
INTERNAL REFERENCE REGISTER
The on-board reference is off at power-up by default. This
allows the use of an external reference if the application requires
it. The on-board reference can be turned on/off by a userprogrammable REF register by setting Bit DB0 high or low (see
Table 9). Command 1000 is reserved for this internal REF setup command (see Table 7). Table 11 shows how the state of the
bits in the input shift register corresponds to the mode of
operation of the device.
POWER-DOWN MODES
The AD5666 contains four separate modes of operation.
Command 0100 is reserved for the power-down function (see
Table 7). These modes are software-programmable by setting
two bits, Bit DB19 and Bit DB18, in the control register. Table 11
shows how the state of the bits corresponds to the mode of
operation of the device. Any or all DACs (DAC D to DAC A)
can be powered down to the selected mode by setting the corresponding four bits (DB7, DB6, DB1, DB0) to 1. See Table 12
for the contents of the input shift register during power-down/
power-up operation. When using the internal reference, only
all channel power-down to the selected modes is supported.
When both bits are set to 0, the part works normally with its
normal power consumption of 700 μA at 5 V. However, for the
three power-down modes, the supply current falls to 400 nA at
5 V (200 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 44.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. The internal reference is powered down only
when all channels are powered down. However, the contents of
the DAC register are unaffected when in power-down. The time
to exit power-down is typically 4 μs for VDD = 5 V and for
VDD = 3 V (see Figure 28).
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (LDAC Low) or to the value in the
DAC register before powering down (LDAC high).
Rev. D | Page 23 of 28
AD5666
Table 9. Daisy-Chain Enable/Internal Reference Register
DCEN (DB1)
0
0
1
1
REF (DB0)
0
1
0
1
Action
Standalone mode, reference off (default)
Standalone mode, reference on
DCEN mode, reference off
DCEN mode, reference on
Table 10. 32-Bit Input Shift Register Contents for Daisy-Chain Enable and Reference Set-Up Function
MSB
DB31 to DB28
X
Don’t cares
DB27
DB26
DB25
DB24
1
0
0
0
Command bits (C3 to C0)
DB23
X
DB22
DB21
DB20
X
X
X
Address bits (A3 to A0)
DB19 to DB2
X
Don’t cares
LSB
DB1
DB0
1/0
1/0
DCEN/REF
register
Table 11. Modes of Operation
DB9
0
DB8
0
0
1
1
1
0
1
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
Table 12. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function
MSB
LSB
DB27
DB26
DB25
DB24
0
1
0
0
Command bits (C2 to C0)
DB23
DB22
DB21
DB20
X
X
X
X
Address bits (A3 to A0)—
don’t cares
RESISTOR
STRING DAC
DB19 to
DB10
X
Don’t
cares
DB9
DB8
PD1
PD0
Power-down
mode
AMPLIFIER
POWER-DOWN
CIRCUITRY
VOUT
RESISTOR
NETWORK
Figure 44. Output Stage During Power-Down
Rev. D | Page 24 of 28
DB7 to
DB4
X
Don’t
cares
05298-027
DB31 to
DB28
X
Don’t
cares
DB3
DB2
DB1
DB0
DAC D
DAC C
DAC B
DAC A
Power-down/power-up channel selection—
set bit to 1 to select
AD5666
CLEAR CODE REGISTER
The AD5666 has a hardware CLR pin that is an asynchronous
clear input. The CLR input is falling edge sensitive. Bringing the
CLR line low clears the contents of the input register and the
DAC registers to the data contained in the user-configurable
CLR register and sets the analog outputs accordingly. This
function can be used in system calibration to load zero scale,
midscale, or full scale to all channels together. These clear code
values are user-programmable by setting two bits, Bit DB1 and
Bit DB0, in the control register (see Table 13). The default
setting clears the outputs to 0 V. Command 0101 is reserved for
loading the clear code register (see Table 7).
The part exits clear code mode on the 32nd falling edge of the
next write to the part. If CLR is activated during a write
sequence, the write is aborted.
The CLR pulse activation time—the falling edge of CLR to when
the output starts to change—is typically 280 ns. However, if outside
the DAC linear region, it typically takes 520 ns after executing
CLR for the output to start changing (see Figure 38).
See Table 14 for contents of the input shift register during the
loading clear code register operation
LDAC FUNCTION
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin.
Synchronous LDAC: After new data is read, the DAC registers
are updated on the falling edge of the 32nd SCLK pulse. LDAC
can be permanently low or pulsed as in Figure 3.
Asynchronous LDAC: The outputs are not updated at the same
time that the input registers are written to. When LDAC goes
low, the DAC registers are updated with the contents of the
input register.
Alternatively, the outputs of all DACs can be updated
simultaneously using the software LDAC function by writing to
Input Register n and updating all DAC registers. Command
0011 is reserved for this software LDAC function.
An LDAC register gives the user extra flexibility and control
over the hardware LDAC pin. This register allows the user to
select which combination of channels to simultaneously update
when the hardware LDAC pin is executed. Setting the LDAC bit
register to 0 for a DAC channel means that this channel’s update
is controlled by the LDAC pin. If this bit is set to 1, this channel
updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the LDAC pin.
It effectively sees the LDAC pin as being tied low. (See Table 15
for the LDAC register mode of operation.) This flexibility is
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
Writing to the DAC using command 0110 loads the 4-bit LDAC
register (DB3 to DB0). The default for each channel is 0; that is,
the LDAC pin works normally. Setting the bits to 1 means the
DAC channel is updated regardless of the state of the LDAC
pin. See Table 16 for the contents of the input shift register
during the load LDAC register mode of operation.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5666 should
have separate analog and digital sections. If the AD5666 is in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the AD5666.
The power supply to the AD5666 should be bypassed with 10 μF
and 0.1 μF capacitors. The capacitors should physically be as
close as possible to the device, with the 0.1 μF capacitor ideally
right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), such as is typical of common ceramic types of
capacitors. This 0.1 μF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique, where the component side of the
board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a 2-layer board.
Rev. D | Page 25 of 28
AD5666
Table 13. Clear Code Register
DB1
CR1
0
0
1
1
Clear Code Register
DB0
CR0
0
1
0
1
Clears to Code
0x0000
0x8000
0xFFFF
No operation
Table 14. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
DB31 to DB28
X
Don’t cares
DB27
DB26
DB25
DB24
0
1
0
1
Command bits (C3 to C0)
DB23
X
DB22
DB21
DB20
X
X
X
Address bits (A3 to A0)
DB19 to DB2
X
Don’t cares
LSB
DB1
DB0
1/0
1/0
Clear code register
(CR1 to CR0)
Table 15. LDAC Overwrite Definition
Load DAC Register
LDAC Bits (DB3 to DB0)
LDAC Pin
LDAC Operation
0
1
Determined by LDAC pin
DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0.
1/0
X—don’t care
Table 16. 32-Bit Input Shift Register Contents for LDAC Overwrite Function
MSB
DB31
to
DB28
X
Don’t
cares
LSB
DB27
0
DB26
DB25
DB24
1
1
0
Command bits (C3 to C0)
DB23
DB22
DB21
X
X
X
Address bits (A3 to A0)—
don’t cares
DB20
X
Rev. D | Page 26 of 28
DB19
to
DB4
X
Don’t
cares
DB3
DB2
DB1
DB0
DAC D
DAC C
DAC B
DAC A
Setting LDAC bit to 1 override LDAC pin
AD5666
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
0.75
0.60
0.45
8°
0°
061908-A
1.05
1.00
0.80
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 45. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5666BRUZ-1
AD5666BRUZ-1REEL7
AD5666BRUZ-2
AD5666BRUZ-2REEL7
AD5666ARUZ-2
AD5666ARUZ-2REEL7
EVAL-AD5666EBZ
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
Evaluation Board
Z = RoHS Compliant Part.
Rev. D | Page 27 of 28
Package
Option
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
Power-On
Reset to Code
Zero
Zero
Zero
Zero
Zero
Zero
Accuracy
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±32 LSB INL
±32 LSB INL
Internal
Reference
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
AD5666
NOTES
©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05298–0–6/10(D)
Rev. D | Page 28 of 28
工商网监
湘ICP备2023018690号
