Octal, 12-/16-Bit nanoDAC+ with
2 ppm/°C Reference, I2C Interface
AD5671R/AD5675R
Data Sheet
FEATURES
GENERAL DESCRIPTION
High performance
High relative accuracy (INL): ±3 LSB maximum at 16 bits
Total unadjusted error (TUE): ±0.14% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.06% of FSR maximum
Low drift 2.5 V reference: 2 ppm/°C typical
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/bit)
1.8 V logic compatibility
400 kHz I2C-compatible serial interface
20-lead, RoHS-compliant TSSOP and LFCSP
The AD5671R/AD5675R are low power, octal, 12-/16-bit
buffered voltage output digital-to-analog converters (DACs).
They include a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The devices operate from a single
2.7 V to 5.5 V supply and are guaranteed monotonic by design.
The AD5671R/AD5675R are available in a 20-lead TSSOP and in
a 20-lead LFCSP and incorporate a power-on reset circuit and a
RSTSEL pin that ensures the DAC outputs power up to zero scale
or midscale and remain there until a valid write. The AD5671R/
AD5675R contain a power-down mode, reducing the current
consumption to 1 μA typical while in power-down mode.
Table 1. Octal nanoDAC+® Devices
Interface
SPI
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Data acquisition systems
Reference
Internal
External
Internal
I2C
16-Bit
AD5676R
AD5676
AD5675R
12-Bit
AD5672R
Not applicable
AD5671R
PRODUCT HIGHLIGHTS
1.
2.
High Relative Accuracy (INL)
AD5671R (12-bit): ±1 LSB maximum
AD5675R (16-bit): ±3 LSB maximum
Low Drift, 2.5 V On-Chip Reference
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFOUT
AD5671R/AD5675R
2.5V
REF
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 1
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 2
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 3
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 4
A0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 5
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 6
RESET
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 7
SDA
A1
INTERFACE LOGIC
SCL
BUFFER
VOUT0
BUFFER
VOUT1
BUFFER
VOUT2
BUFFER
VOUT3
BUFFER
VOUT4
BUFFER
VOUT5
BUFFER
VOUT6
BUFFER
VOUT7
GAIN
×1/×2
POWER-ON
RESET
RSTSEL
GAIN
POWER-DOWN
LOGIC
GND
12664-001
VLOGIC
Figure 1.
Rev. C
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AD5671R/AD5675R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
I2C Slave Address ........................................................................ 25
Applications ....................................................................................... 1
Serial Operation ......................................................................... 25
General Description ......................................................................... 1
Write Operation.......................................................................... 25
Product Highlights ........................................................................... 1
Read Operation........................................................................... 26
Functional Block Diagram .............................................................. 1
Multiple DAC Readback Sequence .......................................... 26
Revision History ............................................................................... 3
Power-Down Operation ............................................................ 27
Specifications..................................................................................... 4
Load DAC (Hardware LDAC Pin) ........................................... 27
AD5671R Specifications .............................................................. 4
LDAC Mask Register ................................................................. 28
AD5675R Specifications .............................................................. 6
Hardware Reset (RESET) .......................................................... 29
AC Characteristics ........................................................................ 8
Reset Select Pin (RSTSEL) ........................................................ 29
Timing Characteristics ................................................................ 9
Software Reset ............................................................................. 29
Absolute Maximum Ratings .......................................................... 10
Internal Reference and Amplifier Gain Selection .................. 29
Thermal Resistance .................................................................... 10
Solder Heat Reflow ..................................................................... 29
ESD Caution ................................................................................ 10
Long-Term Temperature Drift ................................................. 29
Pin Configurations and Function Descriptions ......................... 11
Thermal Hysteresis .................................................................... 30
Typical Performance Characteristics ........................................... 12
Applications Information .............................................................. 31
Terminology .................................................................................... 21
Power Supply Recommendations............................................. 31
Theory of Operation ...................................................................... 23
Microprocessor Interfacing ....................................................... 31
Digital-to-Analog Converter (DAC) ....................................... 23
AD5671R/AD5675R to ADSP-BF531 Interface .................... 31
Transfer Function ....................................................................... 23
Layout Guidelines....................................................................... 31
DAC Architecture ....................................................................... 23
Galvanically Isolated Interface ................................................. 31
Serial Interface ............................................................................ 24
Outline Dimensions ....................................................................... 32
Write and Update Commands .................................................. 25
Ordering Guide .......................................................................... 33
Rev. C | Page 2 of 33
Data Sheet
AD5671R/AD5675R
REVISION HISTORY
4/2018—Rev. B to Rev. C
Changes to Features Section ............................................................ 1
Change to AD56571R Specifications Section ................................ 4
Changed VLOGIC Parameter, Table 2 ................................................. 5
Deleted Endnote 2, Table 2; Renumbered Sequentially ............... 5
Change to AD5675R Specifications Section .................................. 6
Changed VLOGIC Parameter, Table 3 ................................................. 7
Deleted Endnote 2, Table 3; Renumbered Sequentially ............... 7
Change to AC Characteristics Section ........................................... 8
Changes to Timing Characteristics Section, Table 5, Figure 2,
and Figure 3 ....................................................................................... 9
Deleted ESD Parameter, Table 6 ....................................................10
Changes to Thermal Resistance Section ......................................10
Change to Table 8 ............................................................................11
Changes to Figure 32 ......................................................................16
Changes to Table 9 ..........................................................................24
Deleted Endnote 1, Table 10 ..........................................................24
Changes to Update DAC Register n with Contents of Input
Register n Section and Write to and Update DAC Channel n
(Independent of LDAC) Section....................................................25
Power-Down Operation Section ...................................................27
Changes to Hardware Reset (RESET) Section.............................29
Added Software Reset Section .......................................................29
Updated Outline Dimensions ........................................................32
Changes to Ordering Guide ...........................................................33
10/2015—Rev. A to Rev. B
Added 20-Lead LFCSP ...................................................... Universal
Changes to Features Section and Figure 1 ..................................... 1
Changes to Reference Temperature Coefficient Parameter,
Table 2 and ILOGIC Parameter, Table 2 .............................................. 3
Changes to Reference Temperature Coefficient Parameter,
Table 3 and ILOGIC parameter, Table 3 .............................................. 5
Changes to Table 6 ............................................................................ 9
Added Thermal Resistance Section and Table 7; Renumbered
Sequentially ....................................................................................... 9
Added Figure 5; Renumbered Sequentially ................................. 10
Changes to Table 8 .......................................................................... 10
Changes to Terminology Section .................................................. 20
Change to Table 9 ............................................................................ 23
Change to Read Operation Section .............................................. 25
Changes to LDAC Mask Register Section and Table 14 ............ 27
Changed Internal Reference Setup Section to Internal Reference
and Amplier Gain Selection Section ............................................ 28
Changes to Internal Reference and Amplier Gain Selection
(LFCSP Only) Section and Table 16 ............................................. 28
Changes to Table 17 ........................................................................ 29
Changes to Galvanically Isolated Interface Section and
Figure 70 ........................................................................................... 30
Updated Outline Dimensions........................................................ 31
Changes to Ordering Guide ........................................................... 31
2/2015—Rev. 0 to Rev. A
Added AD5671R Specifications Section ........................................ 3
Changes to Table 2 ............................................................................ 3
Added AD5675R Specifications Section and Table 3;
Renumbered Sequentially ................................................................ 5
Changes to Table 5 ............................................................................ 8
Added Figure 3; Renumbered Sequentially ................................... 8
Change to Terminology Section.................................................... 20
Change to Transfer Function Section ........................................... 22
Changes to Hardware Reset (RESET) Section ............................ 28
Changes to Ordering Guide ........................................................... 31
10/2014—Revision 0: Initial Version
Rev. C | Page 3 of 33
AD5671R/AD5675R
Data Sheet
SPECIFICATIONS
AD5671R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, resistive load (RL) = 2 kΩ, capacitive load (CL) = 200 pF, all specifications TA = −40°C to
+125°C, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 1
Resolution
Relative Accuracy (INL)
Min
Zero Code Error
Offset Error
Full-Scale Error
Gain Error
TUE
Offset Error Drift
DC Power Supply Rejection Ratio (PSRR)
DC Crosstalk
Short-Circuit Current 3
Load Impedance at Rails 4
Power-Up Time
REFERENCE OUTPUT
Output Voltage 5
Reference Temperature Coefficient 6, 7
20-Lead TSSOP
20-Lead LFCSP
Output Impedance
Output Voltage Noise
Output Voltage Noise Density
Load Regulation Sourcing
Load Regulation Sinking
±0.12
±0.12
±0.01
±0.01
0.8
−0.75
−0.1
−0.018
±1
±1
±0.1
±0.1
1.6
±2
±1.5
±0.14
−0.013
+0.04
−0.02
±0.03
±0.006
±1
0.25
±2
±3
±2
±0.07
±0.12
±0.06
±0.18
±0.14
0
0
Output Current Drive (IOUT)
Capacitive Load Stability
Resistive Load 2
Load Regulation
Max
12
Differential Nonlinearity (DNL)
OUTPUT CHARACTERISTICS
Output Voltage Range
Typ
2.5
5
15
Unit
Bits
LSB
LSB
LSB
LSB
mV
mV
mV
% of fullscale
range
(FSR)
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
mV/V
µV
µV/mA
µV
183
V
V
mA
nF
nF
kΩ
µV/mA
177
µV/mA
40
25
2.5
mA
Ω
µs
2
10
1
2.4975
2.5025
V
5
10
ppm/°C
ppm/°C
Ω
µV p-p
nV/√Hz
Test Conditions/Comments
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
DAC code = midscale, VDD = 5 V ± 10%
Due to single channel, full-scale output change
Due to load current change
Due to powering down (per channel)
Gain = 1
Gain = 2
RL = ∞
RL = 1 kΩ
VDD = 5 V ± 10%, DAC code = midscale,
−30 mA ≤ IOUT ≤ +30 mA
VDD = 3 V ± 10%, DAC code = midscale,
−20 mA ≤ IOUT ≤ +20 mA
Coming out of power-down mode, VDD = 5 V
See the Terminology section
2
5
0.04
13
240
29
74
µV/mA
µV/mA
Rev. C | Page 4 of 33
0.1 Hz to 10 Hz
At ambient, frequency (f) = 10 kHz, CL = 10 nF,
gain = 1 or 2
At ambient
At ambient
Data Sheet
Parameter
Output Current Load Capability
Line Regulation
Long-Term Stability/Drift
Thermal Hysteresis
LOGIC INPUTS
Input Current
Input Voltage
Low, VIL
High, VIH
Pin Capacitance
LOGIC OUTPUTS (SDA)
Output Voltage
Low, VOL
High, VOH
Floating State Output Capacitance
POWER REQUIREMENTS
VLOGIC
VLOGIC Supply Current (ILOGIC)
VDD
VDD Supply Current (IDD)
Normal Mode 8
All Power-Down Modes 9
AD5671R/AD5675R
Min
Typ
±20
43
12
125
25
Max
Unit
mA
µV/V
ppm
ppm
ppm
Test Conditions/Comments
VDD ≥ 3 V
At ambient
After 1000 hours at 125°C
First cycle
Additional cycles
±1
µA
Per pin
0.3 × VLOGIC
V
V
pF
0.4
V
V
pF
5.5
3
3
3
3
5.5
5.5
V
µA
µA
µA
µA
V
V
1.26
2.0
1.3
2.1
1.7
1.7
2.5
2.5
5.5
5.5
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
0.7 × VLOGIC
3
VLOGIC − 0.4
4
1.62
2.7
VREF + 1.5
1.1
1.8
1.1
1.8
1
1
1
1
1
1
IOL = 200 μA
IOH = −200 μA
Power-on, −40°C + 105°C
Power-on, −40°C + 125°C
Power-down, −40°C + 105°C
Power-down, −40°C + 125°C
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off, −40°C to +85°C
Internal reference on, −40°C to +85°C
Internal reference off
Internal reference on
Tristate to 1 kΩ, −40°C to +85°C
Power-down to 1 kΩ, −40°Cto +85°C
Tristate, −40°C to +105°C
Power-down to 1 kΩ, −40°C to +105°C
Tristate to 1 kΩ, −40°C to +125°C
Power-down to 1 kΩ, −40°C to +125°C
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when the internal reference voltage (VREF) = VDD
with gain = 1, or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 12 to 4080.
2
Together, Channel 0, Channel 1, Channel 2, and Channel 3 can source/sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source/sink
40 mA up to a junction temperature of 125°C.
3
VDD = 5 V. The devices include current limiting to protect the devices during temporary overload conditions. Junction temperature can be exceeded during current
limit. Operation above the specified maximum operation junction temperature can impair device reliability.
4
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
5
Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference and Amplifier Gain Selection
section.
6
Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.
7
Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
8
Interface inactive. All DACs active. DAC outputs unloaded.
9
All DACs powered down.
1
Rev. C | Page 5 of 33
AD5671R/AD5675R
Data Sheet
AD5675R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications TA = −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter
STATIC PERFORMANCE 1
Resolution
Relative Accuracy (INL)
Min
A Grade
Typ
Max
16
Min
B Grade
Typ
Max
16
Offset Error Drift
DC PSRR
DC Crosstalk
±2
±2
µV
±3
±2
±3
±2
µV/mA
µV
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
TUE
OUTPUT CHARACTERISTICS
Output Voltage Range
0
0
Output Current Drive
Capacitive Load Stability
Resistive Load 2
Load Regulation
±3
±3
±1
±1
1.6
±2
±1.5
±0.14
±0.07
±0.12
±0.06
±0.18
±0.14
183
183
V
V
mA
nF
nF
kΩ
µV/mA
2.5
5
15
177
177
µV/mA
40
25
2.5
40
25
2.5
mA
Ω
µs
2
10
1
1
2.4975
2.5025
2.4975
2.5025
V
5
10
ppm/°C
ppm/°C
Ω
µV p-p
nV/√Hz
Test Conditions/Comments
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
DAC code = midscale,
VDD = 5 V ± 10%
Due to single channel,
full-scale output change
Due to load current change
Due to powering
down (per channel)
Gain = 1
Gain = 2
RL = ∞
RL = 1 kΩ
VDD = 5 V ± 10%, DAC code =
midscale, −30 mA ≤ IOUT ≤ +30 mA
VDD = 3 V ± 10%, DAC code =
midscale, −20 mA ≤ IOUT ≤ +20 mA
Coming out of
power-down mode, VDD = 5 V
See the Terminology section
Output Impedance
Output Voltage Noise
Output Voltage Noise Density
5
5
0.04
13
240
Load Regulation Sourcing
Load Regulation Sinking
Output Current Load Capability
Line Regulation
29
74
±20
43
20-Lead TSSOP
20-Lead LFCSP
0
0
2
10
Short-Circuit Current 3
Load Impedance at Rails 4
Power-Up Time
REFERENCE OUTPUT
Output Voltage 5
Reference Temperature Coefficient 6, 7
2.5
5
15
±1.8
±1.7
±0.7
±0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
±0.03
±0.006
±1
0.25
Bits
LSB
LSB
LSB
LSB
mV
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
mV/V
±1.8
±1.7
±0.7
±0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
±0.03
±0.006
±1
0.25
Differential Nonlinearity (DNL)
±8
±8
±1
±1
4
±6
±4
±0.28
±0.14
±0.24
±0.12
±0.3
±0.25
Unit
20
20
2
2
0.04
13
240
29
74
±20
43
Rev. C | Page 6 of 33
µV/mA
µV/mA
mA
µV/V
0.1 Hz to 10 Hz
At ambient, f = 10 kHz,
CL = 10 nF, gain = 1 or 2
At ambient
At ambient
VDD ≥ 3 V
At ambient
Data Sheet
Parameter
Long-Term Stability/Drift
Thermal Hysteresis
AD5671R/AD5675R
Min
A Grade
Typ
12
125
25
LOGIC INPUTS
Input Current
Input Voltage
Low, VINL
High, VINH
Pin Capacitance
LOGIC OUTPUTS (SDA)
Output Voltage
Low, VOL
High, VOH
Floating State Output Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
Max
Min
B Grade
Typ
12
125
25
Max
Unit
ppm
ppm
ppm
Test Conditions/Comments
After 1000 hours at 125°C
First cycle
Additional cycles
±1
±1
µA
Per pin
0.3 ×
VLOGIC
0.3 ×
VLOGIC
V
0.7 ×
VLOGIC
0.7 ×
VLOGIC
3
V
3
0.4
VLOGIC −
0.4
pF
0.4
VLOGIC −
0.4
4
1.62
4
5.5
3
3
3
3
5.5
5.5
2.7
VREF +
1.5
1.62
V
µA
µA
µA
µA
V
V
IDD
Normal Mode 8
All Power-Down Modes 9
ISINK = 200 μA
ISOURCE = 200 μA
pF
5.5
3
3
3
3
5.5
5.5
2.7
VREF +
1.5
V
V
1.1
1.26
1.1
1.26
mA
1.8
2.0
1.8
2.0
mA
1.1
1.8
1
1.3
2.1
1.7
1.1
1.8
1
1.3
2.1
1.7
mA
mA
µA
1
1.7
1
1.7
µA
1
1
2.5
2.5
1
1
2.5
2.5
µA
µA
1
1
5.5
5.5
1
1
5.5
5.5
µA
µA
Power-on, −40°C + 105°C
Power-on, −40°C + 125°C
Power-down, −40°C + 105°C
Power-down, −40°C + 125°C
Gain = 1
Gain = 2
VIH = VDD, VIL = GND,
VDD = 2.7 V to 5.5 V
Internal reference off,
−40°C to +85°C
Internal reference on,
−40°C to +85°C
Internal reference off
Internal reference on
Tristate to 1 kΩ,
−40°C to +85°C
Power-down to 1 kΩ,
−40°C to +85°C
Tristate, −40°C to +105°C
Power-down to 1 kΩ,
−40°C to +105°C
Tristate to 1 kΩ, −40°C to +125°C
Power-down to 1 kΩ,
−40°C to +125°C
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
Together, Channel 0, Channel 1, Channel 2, and Channel 3 can source/sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source/sink
40 mA up to a junction temperature of 125°C.
3
VDD = 5 V. The devices include current limiting to protect the devices during temporary overload conditions. Junction temperature can be exceeded during current
limit. Operation above the specified maximum operation junction temperature can impair device reliability.
4
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
5
Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference and Amplifier Gain Selection
section.
6
Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.
7
Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
8
Interface inactive. All DACs active. DAC outputs unloaded.
9
All DACs powered down.
1
2
Rev. C | Page 7 of 33
AD5671R/AD5675R
Data Sheet
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 1.62 V ≤ VLOGIC ≤ 5.5 V, all specifications TA = −40°C to +125°C, unless
otherwise noted.
Table 4.
Parameter
OUTPUT VOLTAGE SETTLING TIME 2
AD5671R
AD5675R
SLEW RATE
DIGITAL-TO-ANALOG GLITCH IMPULSE2
DIGITAL FEEDTHROUGH2
CROSSTALK2
Digital
Analog
DAC-to-DAC
TOTAL HARMONIC DISTORTION (THD) 3
OUTPUT NOISE SPECTRAL DENSITY2
OUTPUT NOISE2
SIGNAL-TO-NOISE RATIO (SNR)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)
Min
Typ
Max
Unit
Test Conditions/Comments 1
5
5
0.8
1.4
0.13
8
8
µs
µs
V/µs
nV-sec
nV-sec
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
0.1
−0.25
−1.3
−2.0
−80
300
6
90
83
80
nV-sec
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
dB
dB
1 LSB change around major carry (internal reference, gain = 1)
Internal reference, gain = 2
Internal reference, gain = 2
At TA, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz; gain = 2
0.1 Hz to 10 Hz, gain = 1
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
The operating temperature range is −40°C to +125°C; TA = 25°C.
See the Terminology section. Measured using internal reference and gain = 1, unless otherwise noted.
3
Digitally generated sine wave (fOUT) at 1 kHz.
1
2
Rev. C | Page 8 of 33
Data Sheet
AD5671R/AD5675R
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, all specifications −40°C to +125°C, unless otherwise noted.
Table 5.
Parameter 1
t1
t2
t3
t4
t5
t6 2
t7
t8
t9
t10 3
t113
t12
t13
t14
t15
tSP 4
CB
Min
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
0
20 + 0.1CB
20
400
8
10
90
90
0
Max
Unit
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
0.9
300
300
50
400
Description
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tSU,STA, repeated start setup time
tSU,STO, stop condition setup time
tBUF, bus free time between a stop condition and a start condition
tR, rise time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting/receiving
LDAC pulse width
SCL rising edge to LDAC rising edge
RESET minimum pulse width low, 1.62 V ≤ VLOGIC ≤ 2.7 V
RESET minimum pulse width low, 2.7 V ≤ VLOGIC ≤ 5.5 V
RESET activation time, 1.62 V ≤ VLOGIC ≤ 2.7 V
RESET activation time, 2.7 V ≤ VLOGIC ≤ 5.5 V
Pulse width of suppressed spike
Capacitive load for each bus line
See Figure 2 and Figure 3.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the minimum VIH of the SCL signal) to bridge the undefined region of the
SCL falling edge.
3
tR and tF are measured from 0.3 × VDD to 0.7 × VDD.
4
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
1
2
Timing Diagrams
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
SDA
t9
t10
t11
t4
t3
SCL
t4
t2
t6
t1
t5
t7
t8
t12
t13
LDAC1
t12
LDAC2
12664-002
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. 2-Wire Serial Interface Timing Diagram
VOUTx
t15
12664-102
RESET
t14
Figure 3. RESET Timing Diagram
Rev. C | Page 9 of 33
AD5671R/AD5675R
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 6.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
VDD to GND
VLOGIC to GND
VOUTx to GND
VREFOUT to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak Temperature,
Pb Free (J-STD-020)
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +125°C
−65°C to +150°C
125°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 7.Thermal Resistance
Package Type
20-Lead TSSOP
(RU-20)1
20-Lead LFCSP
(CP-20-8)2
θJA
98.65
θJB
44.39
θJC
17.58
ΨJT
1.77
ΨJB
43.9
Unit
°C/W
82
16.67
32.5
0.43
22
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51
2
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
1
ESD CAUTION
Rev. C | Page 10 of 33
Data Sheet
AD5671R/AD5675R
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5671R/AD5675R
20
19
18
17
16
VOUT0
VOUT1
VOUT2
VOUT3
NIC
TOP VIEW
(Not to Scale)
VOUT1
1
20
VOUT0
2
19
VOUT3
VDD
3
18
VREFOUT
VLOGIC
4
17
RESET
SCL
5
16
SDA
A0
6
15
LDAC
A1
7
14
RSTSEL
GAIN
8
13
GND
VOUT7
9
12
VOUT4
VOUT6
10
11
VOUT5
15
14
13
12
11
1
2
3
4
5
VREFOUT
RESET
SDA
LDAC
GND
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE TIED TO GND.
Figure 4. TSSOP Pin Configuration
12664-105
VOUT7 6
VOUT6 7
VOUT5 8
VOUT4 9
NIC 10
TOP VIEW
(Not to Scale)
VDD
VLOGIC
SCL
A0
A1
12664-006
AD5671R/
AD5675R
VOUT2
Figure 5. LFCSP Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
TSSOP LFCSP
1
19
2
20
N/A 1
0
3
1
Mnemonic
VOUT1
VOUT0
EPAD
VDD
4
5
2
3
VLOGIC
SCL
6
7
8
4
5
N/A1
A0
A1
GAIN
9
10
11
12
N/A1
13
14
6
7
8
9
10, 16
11
N/A1
VOUT7
VOUT6
VOUT5
VOUT4
NIC
GND
RSTSEL
15
12
LDAC
16
13
SDA
17
14
RESET
18
15
VREFOUT
19
20
17
18
VOUT3
VOUT2
1
Description
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
Power Supply Input. These devices operate from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 µF
capacitor in parallel with a 0.1 µF capacitor to GND.
Digital Power Supply. The voltage on this pin ranges from 1.62 V to 5.5 V.
Serial Clock Line. In conjunction with the SDA line, this pin clocks data into or out of the 24-bit input shift
register.
Address Input. Sets the first LSB of the 7-bit slave address.
Address Input. Sets the second LSB of the 7-bit slave address.
Span Set Pin. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is
tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF.
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
No Internal Connection.
Ground Reference Point for All Circuitry on the Device.
Power-On Reset Pin. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to
power up all eight DACs to midscale. On models without RSTSEL, the outputs power up to zero scale.
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low updates
any or all DAC registers if the input registers have new data, which simultaneously updates all DAC outputs.
This pin can also be tied permanently low.
Serial Data Input. In conjunction with the SCL line, this pin clocks data into or out of the 24-bit input shift
register. SDA is a bidirectional, open-drain data line that must be pulled to the supply with an external
pull-up resistor.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are
ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or
midscale, depending on the state of the RSTSEL pin.
Reference Output Voltage. When using the internal reference, this is the reference output pin. This pin is
the reference output by default.
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
N/A means not applicable.
Rev. C | Page 11 of 33
AD5671R/AD5675R
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
2.0
0.8
1.5
0.6
DNL ERROR (LSB)
INL ERROR (LSB)
1.0
0.5
0
–0.5
0.4
0.2
0
–0.2
–0.4
–1.0
–0.6
–1.5
10000
20000
30000
40000
50000
60000
70000
CODE
–1.0
12664-007
0
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
Figure 6. AD5675R INL Error vs. Code
12664-010
–0.8
–2.0
Figure 9. AD5671R DNL Error vs. Code
0.04
2.0
1.5
0.03
0.02
TUE (% OF FSR)
INL ERROR (LSB)
1.0
0.5
0
–0.5
0.01
0
–1.0
–0.01
0
1000
500
1500
2000 2500
CODE
3000
3500
4000
–0.02
12664-008
–2.0
0
10000
Figure 7. AD5671R INL Error vs. Code
20000
30000
40000
CODE
50000
60000
70000
12664-011
–1.5
Figure 10. AD5675R TUE vs. Code
1.0
0.04
0.8
0.03
TUE (% of FSR)
0.4
0.2
0
–0.2
0.02
0.01
0
–0.4
–0.6
–0.01
–1.0
0
10000
20000
30000
40000
CODE
50000
60000
70000
Figure 8. AD5675R DNL Error vs. Code
–0.02
0
500
1000
1500
2000 2500
CODE
3000
Figure 11. AD5671R TUE vs. Code
Rev. C | Page 12 of 33
3500
4000
12664-012
–0.8
12664-009
DNL ERROR (LSB)
0.6
AD5671R/AD5675R
10
10
8
8
6
6
4
4
DNL ERROR (LSB)
2
0
–2
–2
0
20
40
–8
60
80
100
120
TEMPERATURE (°C)
–10
–40
8
0.09
6
0.08
4
0.07
TUE (% OF FSR)
INL ERROR (LSB)
0.10
2
0
–2
–4
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0.04
3.7
4.2
4.7
SUPPLY VOLTAGE (V)
5.2
0
–40
0.08
4
0.07
TUE (% OF FSR)
6
2
0
–2
40
–20
0
20
40
60
80
100
120
0.05
0.04
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0.02
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
20
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0.06
0.03
–4
0.01
60
80
100
TEMPERATURE (°C)
120
0
–40
12664-015
DNL ERROR (LSB)
0.09
0
120
Figure 16. AD5675R TUE vs. Temperature
0.10
–20
100
TEMPERATURE (°C)
8
–10
–40
80
0.01
10
–8
60
0.05
Figure 13. AD5671R INL Error vs. Supply Voltage
–6
40
0.02
12664-014
3.2
20
0.06
0.03
–10
2.7
0
Figure 15. AD5671R DNL Error vs. Temperature
10
–8
–20
TEMPERATURE (°C)
Figure 12. AD5675R INL Error vs. Temperature
–6
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
12664-017
–20
–6
12664-016
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
12664-013
–8
–10
–40
0
–4
–4
–6
2
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 17. AD5671R TUE vs. Temperature
Figure 14. AD5675R DNL Error vs. Temperature
Rev. C | Page 13 of 33
120
12664-018
INL ERROR (LSB)
Data Sheet
Data Sheet
10
0.10
8
0.08
6
0.06
4
0.04
TUE (% OF FSR)
2
0
–2
–0.02
3.2
3.7
4.2
–0.06
–0.08
4.7
5.2
SUPPLY VOLTAGE (V)
–0.10
2.7
8
0.08
6
0.06
4
0.04
TUE (% OF FSR)
2
0
–2
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0
–0.02
3.7
4.2
4.7
5.2
6
0.06
4
0.04
ERROR (% OF FSR)
0.08
2
0
–2
–4
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
4.2
4.7
5.2
0.02
FULL-SCALE ERROR
0
GAIN ERROR
–0.02
–0.04
–0.06
–0.08
4.7
5.2
SUPPLY VOLTAGE (V)
12664-028
DNL ERROR (LSB)
0.10
4.2
3.7
Figure 22. AD5671R TUE vs. Supply Voltage
8
3.7
3.2
SUPPLY VOLTAGE (V)
10
3.2
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.10
2.7
12664-027
3.2
–0.08
Figure 19. AD5675R DNL Error vs. Supply Voltage
–10
2.7
5.2
0.02
–0.06
SUPPLY VOLTAGE (V)
–8
4.7
–0.04
–4
–6
4.2
12664-030
DNL ERROR (LSB)
0.10
–10
2.7
3.7
Figure 21. AD5675R TUE vs. Supply Voltage
10
–8
3.2
SUPPLY VOLTAGE (V)
Figure 18. AD5675R INL Error vs. Supply Voltage
–6
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
12664-029
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
12664-025
–8
–10
2.7
0
–0.04
–4
–6
0.02
Figure 20. AD5671R DNL Error vs. Supply Voltage
–0.10
–40
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
12664-031
INL ERROR (LSB)
AD5671R/AD5675R
Figure 23. AD5675R Gain Error and Full-Scale Error vs. Temperature
Rev. C | Page 14 of 33
Data Sheet
AD5671R/AD5675R
0.10
1.8
0.08
1.5
0.06
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
ERROR (mV)
ERROR (% OF FSR)
1.2
0.04
0.02
0
GAIN ERROR
–0.02
ZERO CODE ERROR
0.9
0.6
OFFSET ERROR
0.3
FULL-SCALE ERROR
–0.04
0
–0.06
0
–20
20
40
–0.3
60
80
100
TEMPERATURE (°C)
120
–0.6
–40
0
–20
40
60
20
TEMPERATURE (°C)
80
100
120
12664-035
–0.10
–40
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
12664-032
–0.08
Figure 27. AD5675R Zero Code Error and Offset Error vs. Temperature
Figure 24. AD5671R Gain Error and Full-Scale Error vs. Temperature
0.10
1.8
0.08
1.5
0.06
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
ERROR (mV)
ERROR (% OF FSR)
1.2
0.04
0.02
GAIN ERROR
0
–0.02
FULL-SCALE ERROR
ZERO CODE ERROR
0.9
OFFSET ERROR
0.6
0.3
–0.04
0
–0.06
3.2
3.7
4.2
–0.3
4.7
5.2
SUPPLY VOLTAGE (V)
–0.6
–40
Figure 25. AD5675R Gain Error and Full-Scale Error vs. Supply Voltage
0
–20
60
20
40
TEMPERATURE (°C)
80
100
120
12664-036
–0.10
2.7
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
12664-033
–0.08
Figure 28. AD5671R Zero Code Error and Offset Error vs. Temperature
1.5
0.10
0.08
1.0
0.04
0.02
GAIN ERROR
–0.02
FULL-SCALE ERROR
–0.04
–0.5
–0.06
–1.0
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
3.2
3.7
4.2
SUPPLY VOLTAGE (V)
4.7
5.2
–1.5
2.7
12664-034
–0.10
2.7
OFFSET ERROR
0
Figure 26. AD5671R Gain Error and Full-Scale Error vs. Supply Voltage
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
3.2
3.7
4.2
SUPPLY VOLTAGE (V)
4.7
5.2
12664-037
0
–0.08
ZERO CODE ERROR
0.5
ERROR (mV)
ERROR (% OF FSR)
0.06
Figure 29. AD5675R Zero Code Error and Offset Error vs. Supply Voltage
Rev. C | Page 15 of 33
AD5671R/AD5675R
Data Sheet
6
1.5
0xFFFF
5
1.0
ZERO CODE ERROR
4
0xC000
3
VOUT (V)
ERROR (mV)
0.5
OFFSET ERROR
0
0x8000
2
0x4000
1
–0.5
0x0000
0
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
3.2
3.7
4.2
4.7
–2
–0.06
12664-038
–1.5
2.7
–1
5.2
SUPPLY VOLTAGE (V)
–0.02
0
0.02
0.04
0.06
LOAD CURRENT (A)
Figure 33. Source and Sink Capability at 5 V
Figure 30. AD5671R Zero Code Error and Offset Error vs. Supply Voltage
4.0
70
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
60
3.5
3.0
50
0xFFFF
2.5
VOUT (V)
HITS
–0.04
12664-042
–1.0
40
30
2.0
0xC000
1.5
0x8000
1.0
0x4000
0.5
20
0x0000
0
10
–1.0
–0.06
12664-039
1880
1895
1850
1865
1835
1820
1790
1805
1775
1745
1760
1715
1730
1700
IDD FULL SCALE (µA)
–0.04
Figure 31. IDD Histogram with Internal Reference
–0.02
0
0.02
LOAD CURRENT (A)
0.04
0.06
12664-043
–0.5
0
Figure 34. Source and Sink Capability at 3 V
1.6
DEVICE1
DEVICE2
DEVICE3
1.5
1.4
IDD (mA)
ΔVOUT (V)
SINKING, VDD = 2.7V
SINKING, VDD = 3.0V
SINKING, VDD = 5.0V
SOURCING, VDD = 5.0V
SOURCING, VDD = 3.0V
SOURCING, VDD = 2.7V
1.3
1.2
0.005
0.010
0.015
0.020
LOAD CURRENT (A)
0.025
0.030
Figure 32. Output Voltage Change (ΔVOUT) vs. Load Current
1.0
0
10000
20000
30000
40000
CODE
50000
Figure 35. IDD vs. Code
Rev. C | Page 16 of 33
60000
70000
12664-044
0
12664-041
1.1
Data Sheet
AD5671R/AD5675R
2.0
2.0
1.8
1.8
FULL-SCALE
1.6
1.6
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 5
DAC 7
DAC 8
1.4
ZERO CODE
1.2
1.0
1.2
VOUT (V)
IDD (mA)
1.4
1.0
0.8
EXTERNAL REFERENCE, FULL-SCALE
0.6
0.4
0.6
0.2
0
20
40
60
80
100
TEMPERATURE (°C)
120
0
80
100
6
1.8
5
1.6
180
200
0.006
0.005
VDD (V)
VOUT0 (V)
VOUT1 (V)
VOUT2 (V)
VOUT3 (V)
VOUT4 (V)
VOUT5 (V)
VOUT6 (V)
VOUT7 (V)
4
FULL-SCALE
VDD (V)
1.4
IDD (mA)
160
Figure 39. Full-Scale Settling Time
2.0
ZERO CODE
3
2
EXTERNAL REFERENCE, FULL-SCALE
1.0
140
TIME (µs)
Figure 36. IDD vs. Temperature
1.2
120
0.004
0.003
0.002
1
0.001
0
0
VOUT (V)
–20
12664-045
0.4
–40
VDD = 5.5V
GAIN = +1
INTERNAL REFERENCE = 2.5V
1/4 TO 3/4 SCALE
12664-048
0.8
0.8
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
–1
0
2
4
6
8
–0.001
10
12664-049
0.4
2.7
12664-046
0.6
TIME (ms)
Figure 37. IDD vs. Supply Voltage
Figure 40. Power-On Reset to 0 V and Midscale
2.2
3.0
2.0
MIDSCALE, GAIN = 2
2.5
FULL-SCALE
1.8
VOUT (V)
2.0
1.4
ZERO CODE
1.2
1.0
EXTERNAL REFERENCE, FULL-SCALE
1.5
MIDSCALE, GAIN = 1
1.0
0.8
0.5
0.4
2.7
3.2
3.7
4.2
4.7
SUPPLY VOLTAGE (V)
5.2
0
–5
0
5
TIME (µs)
Figure 41. Exiting Power-Down to Midscale
Figure 38. IDD vs. Logic Input Voltage
Rev. C | Page 17 of 33
10
12664-050
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0.6
12664-047
IDD (mA)
1.6
AD5671R/AD5675R
Data Sheet
0.004
0.003
0.002
1
VOUT (V)
0.001
0
VDD = 5V
GAIN = 1
TD = 25°C
REFERENCE = 2.5V
CODE = 7FFF TO 8000
ENERGY = 1.209376nV-s
–0.003
–0.004
15
16
17
18
19
20
21
22
TIME (µs)
2
12664-051
–0.002
CH1 50.0mV
Figure 42. Digital-to-Analog Glitch Impulse
M1.00s
401mV
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot
0.003
1200
VDD = 5V
TA = 25°C
GAIN = 1
INTERNAL REFERENCE = 2.5V
0.002
1000
0.001
0
800
NSD (nV/√Hz)
VOUT (V)
A CH1
12664-054
–0.001
–0.001
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
–0.002
–0.003
–0.004
FULL SCALE
MID SCALE
ZERO SCALE
600
400
200
0
2
4
6
8
10
12
14
16
18
20
TIME (µs)
0
10
12664-052
–0.006
100
100k
1M
Figure 46. Noise Spectral Density (NSD)
Figure 43. Analog Crosstalk
0
0.012
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
0.010
0.008
0.006
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–20
–40
–60
THD (dBV)
0.004
0.002
0
–0.002
–80
–100
–120
–0.004
–140
–0.006
–0.010
0
2
4
6
8
10
12
14
TIME (µs)
16
18
20
Figure 44. DAC-to-DAC Crosstalk
–180
0
2
4
6
8
10
12
FREQUENCY (kHz)
Figure 47. THD at 1 kHz
Rev. C | Page 18 of 33
14
16
18
20
12664-056
–160
–0.008
12664-053
VOUT (V)
1k
10k
FREQUENCY (Hz)
12664-055
–0.005
Data Sheet
AD5671R/AD5675R
2.0
1600
1.8
CL = 0nF
CL = 0.1nF
CL = 1nF
CL = 4.7nF
CL = 10nF
VOUT (V)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.20
TIME (ms)
1200
1000
800
600
400
200
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 48. Settling Time at Various Capacitive Loads
Figure 50. Internal Reference NSD vs. Frequency
0.3
3
VDD = 5V
TA = 25°C
0
10
12664-057
1.0
0.10
1400
12664-061
INTERNAL REFERENCE NSD (nV/√Hz)
1.9
2.5020
2.5015
DEVICE1
DEVICE2
DEVICE3
DEVICE4
DEVICE5
RESET
MIDSCALE, GAIN = 1
2.5005
VREF (V)
0.2
2
VOUT AT ZS (V)
2.5000
2.4995
0.1
1
2.4990
2.4985
0
–20
0
20
40
TIME (µs)
0
60
2.4980
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 51. VREF vs. Temperature (A Grade)
Figure 49. Hardware Reset
Rev. C | Page 19 of 33
100
120
12664-062
ZERO SCALE, GAIN = 1
12664-059
VOUT AT MS (V)
2.5010
AD5671R/AD5675R
Data Sheet
2.50050
2.5020
TA = 25°C
DEVICE1
DEVICE2
DEVICE3
DEVICE4
DEVICE5
2.5010
2.50045
2.50035
VREF (V)
2.5000
2.4990
2.50020
2.4985
2.50015
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 52. VREF vs. Temperature (B Grade)
VDD = 5V
TA = 25°C
2.5025
2.5020
2.5015
2.5010
2.5005
–0.025
–0.015
–0.005
0.005
0.015
LOAD CURRENT (A)
0.025
0.035
12664-064
2.5000
2.4995
–0.035
2.50010
2.5
3.0
3.5
4.0
4.5
VDD (V)
Figure 54. VREF vs. VDD
2.5035
VREF (V)
DEVICE3
2.50025
2.4980
–40
DEVICE2
2.50030
2.4995
12664-063
VREF (V)
2.5005
2.5030
DEVICE1
2.50040
Figure 53. VREF vs. Load Current and VDD
Rev. C | Page 20 of 33
5.0
5.5
12664-065
2.5015
Data Sheet
AD5671R/AD5675R
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. These DACs are guaranteed monotonic
by design.
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. The ideal output is
0 V. The zero code error is always positive because the output of
the DAC cannot go below 0 V due to a combination of the offset
errors in the DAC and the output amplifier. Zero code error is
expressed in mV.
Full-Scale Error
Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. The ideal
output is VREF − 1 LSB (Gain = 1) or 2 × VREF (Gain = 2). Fullscale error is expressed in percent of full-scale range (% of FSR).
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured with Code 256
loaded in the DAC register. It can be negative or positive.
DC Power Supply Rejection Ratio (PSRR)
The dc power supply rejection ratio indicates how the output of
the DAC is affected by changes in the supply voltage. PSRR is
the ratio of the change in VOUT to a change in VDD for full-scale
output of the DAC. It is measured in mV/V. VREF is held at 2 V,
and VDD is varied by ±10%.
Output Voltage Settling Time
The output voltage settling time is the amount of time it takes
for the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Noise Spectral Density (NSD)
Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. It is measured in
nV/√Hz.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has on
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by first loading one of the input registers with a fullscale code change (all 0s to all 1s and vice versa). Then, execute
a software LDAC and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-sec.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
to all 1s and vice versa), using the write to and update commands
while monitoring the output of the victim channel that is at
midscale. The energy of the glitch is expressed in nV-sec.
Rev. C | Page 21 of 33
AD5671R/AD5675R
Data Sheet
Multiplying Bandwidth
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Voltage Reference Temperature Coefficient (TC)
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows:
V
−V
TC = REF ( MAX ) REF ( MIN ) × 106
VREF ( NOM ) × TempRange
where:
VREF (MAX) is the maximum reference output measured over the
total temperature range.
VREF (MIN) is the minimum reference output measured over the
total temperature range.
VREF (NOM) is the nominal reference output voltage, 2.5 V.
TempRange is the specified temperature range of −40°C to
+125°C.
Rev. C | Page 22 of 33
Data Sheet
AD5671R/AD5675R
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
VREF
The AD5671R/AD5675R are octal, 12-/16-bit, serial input, voltage
output DACs with an internal reference. The devices operate from
supply voltages of 2.7 V to 5.5 V. Data is written to the AD5671R/
AD5675R in a 24-bit word format via a 2-wire serial interface.
The AD5671R/AD5675R incorporate a power-on reset circuit
to ensure that the DAC output powers up to a known output
state. The devices also have a software power-down mode that
reduces the typical current consumption to 1 µA.
R
R
R
TO OUTPUT
AMPLIFIER
TRANSFER FUNCTION
The internal reference is on by default.
R
Gain is the gain of the output amplifier and is set to 1 by default.
This gain can be set to ×1 or ×2 using the gain select pin (GAIN).
When this pin is tied to GND, all eight DAC outputs have a
span from 0 V to VREF. If this pin is tied to VLOGIC, all eight DACs
output a span of 0 V to 2 × VREF.
12664-067
R
Figure 56. Resistor String Structure
DAC ARCHITECTURE
Internal Reference
The AD5671R/AD5675R implement segmented string DAC
architecture with an internal output buffer. Figure 55 shows the
internal block diagram.
The AD5671R/AD5675R on-chip reference is enabled at power-up,
but can be disabled via a write to the control register. See the
Internal Reference and Amplifier Gain Selection section for
details.
VREF
2.5V
REF
REF (+)
DAC
REGISTER
RESISTOR
STRING
REF (–)
GND
VOUTX
GAIN
(GAIN = 1 OR 2)
12664-066
INPUT
REGISTER
Figure 55. Single DAC Channel Architecture Block Diagram
The resistor string structure is shown in Figure 56. The code
loaded to the DAC register determines the node on the string
where the voltage is tapped off and fed into the output amplifier.
The voltage is tapped off by closing one of the switches and
connecting the string to the amplifier. Because each resistance
in the string has same value, R, the string DAC is guaranteed
monotonic.
The AD5671R/AD5675R have a 2.5 V, 2 ppm/°C reference, giving
a full-scale output of 2.5 V or 5 V, depending on the state of the
GAIN pin. The internal reference associated with the device is
available at the VREFOUT pin. This buffered reference is capable of
driving external loads of up to 15 mA.
Output Amplifiers
The output buffer amplifier generates rail-to-rail voltages on its
output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, the offset
error, and the gain error. The GAIN pin selects the gain of the
output. If the GAIN pin is tied to GND, all eight outputs have a
gain of 1, and the output range is 0 V to VREF. If the GAIN pin is
tied to VLOGIC, all eight outputs have a gain of 2, and the output
range is 0 V to 2 × VREF.
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 10 nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to
¾ scale settling time of 5 µs.
Rev. C | Page 23 of 33
AD5671R/AD5675R
Data Sheet
Table 9. Command Definitions
SERIAL INTERFACE
The AD5671R/AD5675R use a 2-wire, I2C-compatible serial
interface. These devices can be connected to an I2C bus as a
slave device under the control of the master devices. The
AD5671R/AD5675R support standard (100 kHz) and fast
(400 kHz) data transfer modes. Support is not provided for
10-bit addressing and general call addressing.
C3
0
0
Input Shift Register
The input shift register of the AD5671R/AD5675R is 24 bits
wide. Data is loaded MSB first (DB23), and the first four bits are
the command bits, C3 to C0 (see Table 9), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 10), and finally, the 16-bit
data-word.
The data-word comprises 16-bit or 12-bit input code, followed by
zero or four don’t care bits for the AD5675R and AD5671R,
respectively (see Figure 57 and Figure 58). These data bits are
transferred to the input register on the 24 falling edges of SCL.
Command
C2 C1 C0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
1
…
1
1
…
1
0
…
1
0
…
1
Commands execute on individual DAC channels, combined DAC
channels, or on all DACs, depending on the address bits selected.
Description
No operation
Write to Input Register n (dependent on
LDAC)
Update DAC Register n with contents of
Input Register n
Write to and update DAC Channel n
Power down/power up DAC
Hardware LDAC mask register
Software reset (power-on reset)
Internal reference and gain setup register
Reserved
Set up the readback register (readback
enable)
Update all channels of input register
simultaneously with the input data
Update all channels of DAC register and
input register simultaneously with the
input data
Reserved
Reserved
Table 10. Address Commands
A2
0
0
0
0
1
1
1
1
Channel Address[3:0]
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Selected Channel
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
C3
C2
C1
C0
A3
COMMAND
A2
A1
A0
D15
D14
D13
DAC ADDRESS
COMMAND BYTE
D12
D11
D10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DAC DATA
DAC DATA
DATA HIGH BYTE
DATA LOW BYTE
12664-302
A3
0
0
0
0
0
0
0
0
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
C3
C2
C1
COMMAND
C0
A3
A2
A1
DAC ADDRESS
COMMAND BYTE
A0
D11
D10
D9
D8
D7
D6
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D5
D4
D3
D2
D1
D0
X
X
X
X
DAC DATA
DAC DATA
DATA HIGH BYTE
DATA LOW BYTE
Figure 58. AD5671R Input Shift Register Content
Rev. C | Page 24 of 33
12664-300
Figure 57. AD5675R Input Shift Register Content
Data Sheet
AD5671R/AD5675R
WRITE AND UPDATE COMMANDS
SERIAL OPERATION
Write to Input Register n (Dependent on LDAC)
The 2-wire I2C serial bus protocol operates as follows:
Command 0001 allows the user to write the dedicated input
register of each DAC individually. When LDAC is low, the input
register is transparent, if not controlled by the LDAC mask register.
1.
Update DAC Register n with Contents of Input Register n
2.
Command 0010 loads the DAC registers and outputs with the
contents of the input registers selected and updates the DAC
outputs directly. Data Bit D7 to Bit D0 determine which DACs
have data from the input register transferred to the DAC
register. Setting a bit to 1 transfers data from the input register
to the appropriate DAC register.
3.
Write to and Update DAC Channel n (Independent of LDAC)
Command 0011 allows the user to write to the DAC registers
and updates the DAC outputs directly. The DAC address bits
are used to select the DAC channel.
4.
I2C SLAVE ADDRESS
The AD5671R/AD5675R have a 7-bit I2C slave address. The five
MSBs are 00011, and the two LSBs (A1 and A0) are set by the
state of the A1 and A0 address pins. The ability to make hardwired
changes to A1 and A0 allows the user to incorporate up to four
AD5671R/AD5675R devices on one bus (see Table 11).
WRITE OPERATION
Table 11. Device Address Selection
A1 Pin Connection
GND
GND
VLOGIC
VLOGIC
A0 Pin Connection
GND
VLOGIC
GND
VLOGIC
A1
0
0
1
1
When writing to the AD5671R/AD5675R, begin with a start
command followed by an address byte (R/W = 0), after which
the DAC acknowledges that it is prepared to receive data by pulling
SDA low. The AD5671R/AD5675R require two bytes of data for the
DAC, and a command byte that controls various DAC functions.
Three bytes of data must therefore be written to the DAC with
the command byte followed by the most significant data byte and
the least significant data byte, as shown in Figure 59. All these data
bytes are acknowledged by the AD5671R/AD5675R. A stop
condition follows.
A0
0
1
0
1
1
9
The master initiates a data transfer by establishing a start
condition when a high to low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address.
The slave device with the transmitted address responds by
pulling SDA low during the ninth clock pulse (this is called
the acknowledge bit, or ACK). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to or read from its input shift register.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
Transitions on the SDA line must occur during the low period
of SCL; SDA must remain stable during the high period of SCL.
After all data bits are read or written, a stop condition is
established. In write mode, the master pulls the SDA line high
during the 10th clock pulse to establish a stop condition. In
read mode, the master issues a no acknowledge (NACK)
for the ninth clock pulse (that is, the SDA line remains
high). The master then brings the SDA line low before the
10th clock pulse, and then high again during the 10th clock
pulse to establish a stop condition.
1
9
SCL
0
SDA
0
0
1
1
A1
A0
DB23
R/W
DB22 DB21 DB20 DB19 DB18
ACK BY
AD5671R/AD5675R
START BY
MASTER
DB17
DB16
ACK BY
AD5671R/AD5675R
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
DB15 DB14
DB13 DB12
DB11 DB10
FRAME 3
MOST SIGNIFICANT
DATA BYTE
DB9
DB8
DB7
DB6
ACK BY
AD5671R/AD5675R
Figure 59. I2C Write Operation
Rev. C | Page 25 of 33
DB5
DB4
DB3
DB2
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
DB1
DB0
ACK BY
STOP BY
AD5671R/AD5675R MASTER
12664-303
SDA
(CONTINUED)
AD5671R/AD5675R
Data Sheet
READ OPERATION
MULTIPLE DAC READBACK SEQUENCE
When reading data back from the AD5671R/AD5675R, begin
with a start command followed by an address byte (R/W = 0),
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The address byte must be followed by
the command byte, which determines both the read command
that is to follow and the pointer address to read from; the
command byte is also acknowledged by the DAC. The user
configures the channel to read back the contents of one or more
DAC input registers and sets the read back command to active
using the command byte. The command byte must be followed
by two dummy bytes of data.
When reading data back from multiple AD5671R/AD5675R
DACs, the user begins with an address byte (R/W = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The address byte must be followed by the
command byte, which is also acknowledged by the DAC. The
user selects the first channel to read back using the command
byte.
Following this sequence, the master establishes a repeated start
condition, and the address is resent with R/W = 1. This byte is
acknowledged by the DAC, indicating that it is prepared to
transmit data. The first two bytes of data are then read from
DAC Input Register n (selected using the command byte), MSB
first, as shown in Figure 60. The next two bytes read back are the
contents of DAC Input Register n + 1, and the next bytes read
back are the contents of DAC Input Register n + 2. Data is read
from the DAC input registers in this autoincremented fashion
until a NACK followed by a stop condition follows. If the contents
of DAC Input Register 7 are read out, the next two bytes of data
read are the contents of DAC Input Register 0.
Then, the master establishes a repeated start condition, and the
address is resent with R/W = 1. This byte is acknowledged by the
DAC, indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC, as shown in Figure 60. A
NACK condition from the master, followed by a stop condition,
completes the read sequence. If more than one DAC is selected,
DAC 0 is read back by default.
1
9
1
9
SCL
0
SDA
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK BY
AD5671R/AD5675R
START BY
MASTER
ACK BY
AD5671R/AD5675R
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
0
SDA
0
0
REPEATED START BY
MASTER
1
1
A1
A0
R/W
DB15 DB14 DB13 DB12 DB11 DB10
ACK BY
AD5671R/AD5675R
FRAME 3
SLAVE ADDRESS
1
9
DB9
DB8
ACK BY
MASTER
FRAME 4
MOST SIGNIFICANT
DATA BYTE n
1
9
SCL
(CONTINUED)
DB7
DB6
DB5
DB4
DB3
DB2
FRAME 5
LEAST SIGNIFICANT
DATA BYTE n
DB1
DB0
DB15
DB14 DB13 DB12
ACK BY
MASTER
Figure 60. I2C Read Operation
Rev. C | Page 26 of 33
DB11 DB10
FRAME 6
MOST SIGNIFICANT
DATA BYTE n + 1
DB9
DB8
NACK BY
MASTER
STOP BY
MASTER
12664-304
SDA
(CONTINUED)
Data Sheet
AD5671R/AD5675R
POWER-DOWN OPERATION
The AD5671R/AD5675R contain two separate power-down
modes. Command 0100 is designated for the power-down
function (see Table 9). These power-down modes are software
programmable by setting 16 bits, Bit DB15 to Bit DB0, in the
input shift register. There are two bits associated with each DAC
channel. Table 12 shows how the state of the two bits corresponds
to the mode of operation of the device.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when power-down
mode is activated. However, the contents of the DAC registers
are unaffected in power-down mode, and the DAC registers can
be updated while the device is in power-down mode. The time
required to exit power-down is typically 2.5 µs for VDD = 5 V.
LOAD DAC (HARDWARE LDAC PIN)
Any or all DACs (DAC 0 to DAC 7) power down to the selected
mode by setting the corresponding bits. See Table 13 for the
contents of the input shift register during the power-down/
power-up operation.
The AD5671R/AD5675R DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The user can write to any combination of the input
registers. Updates to the DAC registers are controlled by
the LDAC pin.
Table 12. Modes of Operation
Instantaneous DAC Updating (LDAC Held Low)
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
Tristate
PD1
0
PD0
0
0
1
1
1
For instantaneous updating of the DACs, LDAC is held low while
data is clocked into the input register using Command 0001. Both
the addressed input register and the DAC register are updated on
the 24th clock, and the output changes immediately.
When both Bit PD1 and Bit PD0 in the input shift register are set
to 0, the device works normally with its normal power consumption of typically 1 mA at 5 V. However, for the two power-down
modes, the supply current falls to typically 1 µA. In addition to
this fall, the output stage switches internally from the amplifier
output to a resistor network of known values. Therefore the DAC
channel output impedance is defined when the channel is
powered down. There are two different power-down options.
The output is connected internally to GND through either a
1 kΩ resistor, or it is left open circuited (tristate). The output
stage is shown in Figure 61.
Deferred DAC Updating (LDAC is Pulsed Low)
For deferred updating of the DACs, LDAC is held high while data
is clocked into the input register using Command 0001. All DAC
outputs are asynchronously updated by pulling LDAC low after the
24th clock. The update occurs on the falling edge of LDAC.
AMPLIFIER
VREF
12-/16-BIT
DAC
LDAC
DAC
REGISTER
VOUTX
INPUT
REGISTER
AMPLIFIER
VOUT
SCL
SDA
RESISTOR
NETWORK
INTERFACE
LOGIC
Figure 62. Simplified Diagram of Input Loading Circuitry for a Single DAC
12664-071
POWER-DOWN
CIRCUITRY
12664-072
DAC
Figure 61. Output Stage During Power-Down
Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation
[DB23:DB20]
0100
1
DB19
0
[DB18:DB16]
XXX1
DAC 7
[DB15: B14]
[PD1:PD0]
DAC 6
[DB13: B12]
[PD1:PD0]
DAC 5
[DB11: B10]
[PD1:PD0]
DAC 4
[DB9:DB8]
[PD1:PD0]
X means don’t care.
Rev. C | Page 27 of 33
DAC 3
[DB7:DB6]
[PD1:PD0]
DAC 2
[DB5:DB4]
[PD1:PD0]
DAC 1
[DB3:DB2]
[PD1:PD0]
DAC 0
[DB1:DB0]
[PD1:PD0]
AD5671R/AD5675R
Data Sheet
LDAC MASK REGISTER
Command 0101 is reserved for this software LDAC function.
The address bits are ignored. Writing to the DAC using
Command 0101 loads the 8-bit LDAC register (DB7 to DB0).
The default for each channel is 0, that is, the LDAC pin works
normally. Setting the bits to 1 forces this DAC channel to ignore
transitions on the LDAC pin, regardless of the state of the
hardware LDAC pin. This flexibility is useful in applications
where the user wants to select which channels respond to
the LDAC pin.
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 15). Setting the LDAC
bits (DB0 to DB7) to 0 for a DAC channel means that this
channel update is controlled by the hardware LDAC pin.
Table 14. LDAC Overwrite Definition
Load LDAC Register
LDAC Bits (DB7 to DB0)
00000000
11111111
1
LDAC Pin
1 or 0
X1
LDAC Operation
Determined by the LDAC pin.
DAC channels update and override the LDAC pin. DAC channels see LDAC as 1.
X means don’t care.
Table 15. Write Commands and LDAC Pin Truth Table 1
Command
0001
Description
Write to Input Register n
(dependent on LDAC)
0010
Update DAC Register n
with contents of Input
Register n
Write to and update DAC
Channel n
0011
Hardware LDAC Pin State
VLOGIC
GND 2
VLOGIC
GND
Input Register Contents
Data update
Data update
No change
No change
DAC Register Contents
No change (no update)
Data update
Updated with input register contents
Updated with input register contents
VLOGIC
GND
Data update
Data update
Data update
Data update
A high to low hardware LDAC pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that
are not masked (blocked) by the LDAC mask register.
2
When LDAC is permanently tied low, the LDAC mask bits are ignored.
1
Rev. C | Page 28 of 33
Data Sheet
AD5671R/AD5675R
HARDWARE RESET (RESET)
SOLDER HEAT REFLOW
The RESET pin is an active low reset that allows the outputs to
be cleared to either zero scale or midscale. The clear code value
is user selectable via the RSTSEL pin. Keep RESET low for a
minimum time (see Table 5) to complete the operation. When
the RESET signal is returned high, the output remains at the
cleared value until a new value is programmed. While
the RESET pin is low, the outputs cannot be updated with a new
value. Any events on LDAC or RESET during power-on reset
are ignored. If the RESET pin is pulled low at power-up, the
device does not initialize correctly until the pin is released.
As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc., performs a reliability test called precondition to
mimic the effect of soldering a device to a board. The output
voltage specification quoted previously includes the effect of
this reliability test.
Figure 63 shows the effect of solder heat reflow (SHR) as
measured through the reliability test (precondition).
35
30
POSTSOLDER
HEAT REFLOW
25
PRESOLDER
HEAT REFLOW
RESET SELECT PIN (RSTSEL)
HITS
The AD5671R/AD5675R contain a power-on reset circuit that
controls the output voltage during power-up. By connecting the
RSTSEL pin low, the output powers up to zero scale. Note that
this power-up is outside the linear region of the DAC; by
connecting the RSTSEL pin high, VOUT powers up to midscale.
The output remains powered up at this level until a valid write
sequence is made to the DAC.
15
10
INTERNAL REFERENCE AND AMPLIFIER GAIN
SELECTION
0
2.497
2.498
2.499
2.500
2.501
12664-073
5
SOFTWARE RESET
A software executable reset function is also available, which
resets the DAC to the power-on reset code. Command 0110 is
designated for this software reset function. The DAC address
bits must be set to 0x0 and the data bits set to 0x1234 for the
software reset command to execute.
20
2.502
VREF (V)
Figure 63. Solder Heat Reflow Reference Voltage Shift
LONG-TERM TEMPERATURE DRIFT
Figure 64 shows the change in VREF value after 1000 hours in the
life test at 150°C.
70
The on-chip reference is on at power-up by default. To reduce
the supply current, turn off this reference by setting the software
programmable bit, DB0, in the internal reference and gain setup
register.
50
40
HITS
The state of Bit DB2 in the internal reference and gain setup
register determines the output amplifier gain setting for the
LFCSP package (see Table 16 and Table 17). Ignore Bit DB2 for
the TSSOP package. Command 0111 is reserved for setting up the
internal reference and amplifier gain.
0 HOURS
168 HOURS
500 HOURS
1000 HOURS
60
30
20
10
Bit
DB2
DB1
DB0
0
Description
Amplifier gain setting
DB2 = 0; amplifier gain = 1 (default)
DB2 = 1; amplifier gain = 2
Reserved; set to 0
Internal reference
DB0 = 0; reference is on (default)
DB1 = 1; reference is off
2.498
2.499
2.500
VREF (V)
2.501
Figure 64. Reference Drift Through to 1000 Hours
Rev. C | Page 29 of 33
2.502
12664-074
Table 16. Internal Reference and Gain Setup Register
AD5671R/AD5675R
Data Sheet
THERMAL HYSTERESIS
3
FIRST TEMPERATURE SWEEP
SUBSEQUENT TEMPERATURE SWEEPS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient to
cold, to hot, and then back to ambient.
2
HITS
Thermal hysteresis data is shown in Figure 65. It is measured by
sweeping the temperature from ambient to −40°C, then to +125°C,
and returning to ambient. The VREF delta is then measured
between the two ambient measurements and shown in blue in
Figure 65. The same temperature sweep and measurements
were immediately repeated, and the results are shown in red in
Figure 65.
0
–130 –110
–90
–70
–50
–30
–10
10
30
50
DISTORTION (ppm)
70
12664-075
1
Figure 65. Thermal Hysteresis
Table 17. 24-Bit Input Shift Register Contents for Internal Reference and Amplifier Gain Setup Command 1
DB23 (MSB)
0
DB22
1
DB21
1
Command bits (C3 to C0)
1
DB20
1
DB19
X
DB18
X
DB17
X
DB16
X
Address bits (A3 to A0)
DB1 to DB3
X
DB2
1/0
DB1
0
DB0 (LSB)
1/0
Don’t care
Amplifier
gain
Reserved
Reference setup
register
X means don’t care.
Rev. C | Page 30 of 33
Data Sheet
AD5671R/AD5675R
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
The AD5671R/AD5675R is typically powered by the following
supplies: VDD = 3.3 V and VLOGIC = 1.8 V.
The ADP7118 can be used to power the VDD pin. The ADP160
can be used to power the VLOGIC pin. This setup is shown in
Figure 66. The ADP7118 can operate from input voltages up to
20 V. The ADP160 can operate from input voltages up to 5.5 V.
ADP7118
3.3V: VDD
LDO
ADP160
1.8V: VLOGIC
LDO
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
The GND plane on the device can be increased (as shown in
Figure 68) to provide a natural heat sinking effect.
12664-176
5V
INPUT
series inductance (ESI), such as the common ceramic types,
which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
AD5671R/
AD5675R
Figure 66. Low Noise Power Solution for the AD5671R/AD5675R
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5671R/AD5675R is done
via a serial bus that uses a standard protocol that is compatible
with DSP processors and microcontrollers. The communications
channel requires a 2-wire interface consisting of a clock signal
and a data signal.
BOARD
AD5671R/AD5675R TO ADSP-BF531 INTERFACE
The I2C interface of the AD5671R/AD5675R is designed for
easy connection to industry-standard DSPs and microcontrollers.
Figure 67 shows the AD5671R/AD5675R connected to the Analog
Devices, Inc., Blackfin® processor. The Blackfin processor has
an integrated I2C port that can be connected directly to the I2C
pins of the AD5671R/AD5675R.
AD5671R/
AD5675R
ADSP-BF531
PF9
PF8
SCL
SDA
LDAC
RESET
12664-077
GPIO1
GPIO2
12664-078
GND
PLANE
Figure 68. Pad Connection to Board
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. iCoupler®
products from Analog Devices provide voltage isolation in excess
of 2.5 kV. The serial loading structure of the AD5671R/AD5675R
makes the devices ideal for isolated interfaces because the number
of interface lines is kept to a minimum. Figure 69 shows a
2-channel isolated interface to the AD5671R/AD5675R
using an ADuM1251. For further information, visit
www.analog.com/icoupler.
CONTROLLER
ADuM12511
DECODE
ENCODE
TO
SCL
SDA
ENCODE
DECODE
TO
SDA
SCL
ENCODE
DECODE
Figure 67. AD5671R/AD5675R to ADSP-BF531 Interface
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. Design the PCB on which the AD5671R/
AD5675R are mounted so that the devices lie on the analog
plane.
1ADDITIONAL
The AD5671R/AD5675R must have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply, located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are tantalum bead type. The 0.1 µF capacitor
must have low effective series resistance (ESR) and low effective
Rev. C | Page 31 of 33
PINS OMITTED FOR CLARITY.
Figure 69. Isolated Interface
12664-079
LAYOUT GUIDELINES
AD5671R/AD5675R
Data Sheet
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 70. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
16
0.50
BSC
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
20
1
15
2.75
2.60 SQ
2.35
EXPOSED
PAD
5
11
TOP VIEW
0.80
0.75
0.70
PKG-003502
SEATING
PLANE
SIDE VIEW
0.50
0.40
0.30
10
6
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11.
Figure 71. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
Rev. C | Page 32 of 33
0.20 MIN
10-12-2017-C
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Data Sheet
AD5671R/AD5675R
ORDERING GUIDE
Model1, 2
AD5671RBRUZ
AD5671RBRUZ-REEL7
AD5671RBCPZ-REEL7
AD5671RBCPZ-RL
AD5675RARUZ
AD5675RARUZ-REEL7
AD5675RBRUZ
AD5675RBRUZ-REEL7
AD5675RACPZ-REEL7
AD5675RACPZ-RL
AD5675RBCPZ-REEL7
AD5675RBCPZ-RL
EVAL-AD5675RSDZ
1
2
Resolution
12 Bits
12 Bits
12 Bits
12 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Accuracy
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±8 LSB INL
±8 LSB INL
±3 LSB INL
±3 LSB INL
±8 LSB INL
±8 LSB INL
±3 LSB INL
±3 LSB INL
Reference Temperature
Coefficient (ppm/°C)
2 (typical)
2 (typical)
2 (typical)
2 (typical)
5 (typical)
5 (typical)
2 (typical)
2 (typical)
5 (typical)
5 (typical)
5 (typical)
5 (typical)
Z = RoHS Compliant Part.
The EVAL-AD5675RSDZ is used to evaluate the AD5671R and AD5675R.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12664-0-4/18(C)
Rev. C | Page 33 of 33
Package
Description
20-Lead TSSOP
20-Lead TSSOP
20-Lead LFCSP
20-Lead LFCSP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead LFCSP
20-Lead LFCSP
20-Lead LFCSP
20-Lead LFCSP
AD5675R Evaluation Board
Package
Option
RU-20
RU-20
CP-20-8
CP-20-8
RU-20
RU-20
RU-20
RU-20
CP-20-8
CP-20-8
CP-20-8
CP-20-8
工商网监
湘ICP备2023018690号
