Data Sheet
AD5672R/AD5676R
Octal, 12-/16-Bit nanoDAC+ with 2 ppm/°C Reference, SPI Interface
FEATURES
►
GENERAL DESCRIPTION
High performance
High relative accuracy (INL): ±3 LSB maximum at 16 bits
► Total unadjusted error (TUE): ±0.14% of FSR maximum
► Offset error: ±1.5 mV maximum
► Gain error: ±0.06% of FSR maximum
► Low drift 2.5 V reference: 2 ppm/°C typical
Wide operating ranges
► −40°C to +125°C temperature range
► 2.7 V to 5.5 V power supply range
Simplified implementation
► User selectable gain of 1 or 2 (GAIN pin/gain bit)
► 1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
20-lead, RoHS compliant TSSOP and LFCSP
16-ball, RoHS compliant WLCSP (AD5676R)
The AD5672R/AD5676R are low power, octal, 12-/16-bit buffered
voltage output digital-to-analog converters (DACs). They include a
2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain
select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain
= 2). The devices operate from a single 2.7 V to 5.5 V supply
and are guaranteed monotonic by design. The AD5672R/AD5676R
are available in a 20-lead TSSOP and in a 20-lead LFCSP and
incorporate a power-on reset circuit and a RSTSEL pin that ensures
that the DAC outputs power up to zero scale or midscale and
remains there until a valid write. The AD5672R/AD5676R contain
a power-down mode, reducing the current consumption to 1 µA
typical while in power-down mode. The AD5676R is also available
in a 16-ball WLCSP.
►
►
►
►
►
►
Table 1. Octal nanoDAC+® Devices
►
►
►
►
Reference
16-Bit
12-Bit
SPI
Internal
External
Internal
AD5676R
AD5676
AD5675R
AD5672R
Not applicable
AD5671R
I2C
APPLICATIONS
►
Interface
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Data acquisition systems
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5672R (12-bit): ±1 LSB maximum.
AD5676R (16-bit): ±3 LSB maximum.
2. Low Drift, 2.5 V On-Chip Reference.
3. High Channel Density.
Eight channels in 2.5 mm × 2.4 mm WLCSP (AD5676R).
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Rev. E
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
AD5672R/AD5676R
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
General Description...............................................1
Product Highlights................................................. 1
Functional Block Diagram......................................1
Specifications........................................................ 4
AD5672R Specifications.....................................4
AD5676R Specifications.....................................6
AC Characteristics..............................................9
Timing Characteristics........................................9
Daisy-Chain and Readback Timing
Characteristics................................................10
Absolute Maximum Ratings.................................12
Thermal Resistance......................................... 12
ESD Caution.....................................................12
Pin Configurations and Function Descriptions.....13
Typical Performance Characteristics................... 15
Terminology......................................................... 24
Theory of Operation.............................................26
Digital-to-Analog Converter.............................. 26
Transfer Function............................................. 26
DAC Architecture..............................................26
Serial Interface................................................. 26
Standalone Operation...................................... 28
Write and Update Commands.......................... 28
Daisy-Chain Operation..................................... 28
Readback Operation........................................ 28
Power-Down Operation.................................... 29
Load DAC (Hardware LDAC Pin)..................... 30
LDAC Mask Register........................................30
Hardware Reset (RESET)................................ 31
Reset Select Pin (RSTSEL)............................. 31
Software Reset.................................................31
Amplifier Gain Selection on LFCSP and
WLCSP...........................................................31
Internal Reference Setup................................. 31
Solder Heat Reflow.......................................... 31
Long-Term Temperature Drift........................... 31
Thermal Hysteresis.......................................... 32
Applications Information...................................... 33
Power Supply Recommendations.................... 33
Microprocessor Interfacing............................... 33
AD5672R/AD5676R to ADSP-BF531
Interface......................................................... 33
AD5672R/AD5676R to SPORT Interface.........33
Layout Guidelines.............................................33
Galvanically Isolated Interface......................... 33
Outline Dimensions............................................. 35
Ordering Guide.................................................36
Evaluation Boards............................................ 36
REVISION HISTORY
12/2021—Rev. D to Rev. E
Added 16-Ball WLCSP.....................................................................................................................................1
Changed VREFOUT Pin to VREF Pin...................................................................................................................1
Changes to Features Section.......................................................................................................................... 1
Changes to Product Highlights Section........................................................................................................... 1
Changes to All Power-Down Modes Parameter, Table 2................................................................................. 4
Deleted Output Current Drive (IOUT) Parameter and Resistive Load Parameter, Table 2................................4
Deleted Note 2, Table 2; Renumbered Sequentially........................................................................................ 4
Changes to Static Performance Parameter, Reference Temperature Coefficient Parameter, Input
Current Parameter, and All Power-Down Modes Parameter, Table 3............................................................6
Deleted Output Current Drive (IOUT) Parameter and Resistive Load Parameter, Table 3................................6
Deleted Note 2, Table 3; Renumbered Sequentially........................................................................................ 6
Changes to Output Noise Spectral Density Parameter, Table 4...................................................................... 9
Changes to Table 8........................................................................................................................................ 12
Added Figure 8; Renumbered Sequentially................................................................................................... 13
Changes to Table 9........................................................................................................................................ 13
Changes to Figure 9 to Figure 28, Figure 28 Caption, Figure 35, Figure 36, Figure 42 Caption, Figure
43, Figure 50, and Figure 52........................................................................................................................15
Deleted Figure 29; Renumbered Sequentially............................................................................................... 15
Changes to Transfer Function Section...........................................................................................................26
Added Note 1, Table 10; Renumbered Sequentially...................................................................................... 27
analog.com
Rev. E | 2 of 36
Data Sheet
AD5672R/AD5676R
TABLE OF CONTENTS
Changes to Figure 60 and Figure 61............................................................................................................. 27
Changes to Write to Input Register n (Dependent on LDAC) Section........................................................... 28
Changes to Power-Down Operation Section and Table 14............................................................................29
Change to Figure 64...................................................................................................................................... 30
Changes to Reset Select Pin (RSTSEL) Section...........................................................................................31
Changes to Amplifier Gain Selection on LFCSP and WLCSP Section..........................................................31
Changes to Internal Reference Setup Section...............................................................................................31
Changes to Power Supply Recommendations Section................................................................................. 33
Updated Outline Dimensions......................................................................................................................... 35
Changes to Ordering Guide........................................................................................................................... 36
Changes to Evaluation Boards...................................................................................................................... 36
analog.com
Rev. E | 3 of 36
Data Sheet
AD5672R/AD5676R
SPECIFICATIONS
AD5672R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, resistive load (RL) = 2 kΩ, capacitive load (CL) = 200 pF, all specifications TA = −40°C to +125°C,
unless otherwise noted.
Table 2.
Parameter
Min
STATIC PERFORMANCE1
Resolution
Relative Accuracy (INL)
12
Differential Nonlinearity (DNL)
Zero Code Error
Offset Error
Full-Scale Error
Gain Error
TUE
Offset Error Drift
DC Power Supply Rejection Ratio (PSRR)
DC Crosstalk
OUTPUT CHARACTERISTICS
Output Voltage Range
Typ
Max
±0.12
±0.12
±0.01
±0.01
0.8
−0.75
−0.1
−0.018
±1
±1
±0.1
±0.1
1.6
±2
±1.5
±0.14
−0.013
+0.04
−0.02
±0.03
±0.006
±1
0.25
±2
±3
±2
±0.07
±0.12
±0.06
±0.18
±0.14
0
0
2.5
5
Unit
Bits
LSB
LSB
LSB
LSB
mV
mV
mV
% of fullscale range
(FSR)
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
mV/V
µV
µV/mA
µV
Test Conditions/Comments
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
DAC code = midscale, VDD = 5 V ± 10%
Due to single channel, full-scale output change
Due to load current change
Due to powering down (per channel)
V
V
Gain = 1
Gain = 2
Capacitive Load Stability
2
10
nF
nF
RL = ∞
RL = 1 kΩ
Load Regulation
183
µV/mA
177
µV/mA
VDD = 5 V ± 10%, DAC code = midscale, −30 mA ≤ IOUT ≤
+30 mA
VDD = 3 V ± 10%, DAC code = midscale, −20 mA ≤ IOUT ≤
+20 mA
40
25
2.5
mA
Ω
µs
Short-Circuit Current2
Load Impedance at Rails3
Power-Up Time
REFERENCE OUTPUT
Output Voltage4
Reference Temperature Coefficient5, 6
Output Impedance
Output Voltage Noise
Output Voltage Noise Density
Load Regulation Sourcing
Load Regulation Sinking
Output Current Load Capability
Line Regulation
analog.com
2.4975
2
0.04
13
240
29
74
±20
43
2.5025
5
V
ppm/°C
Ω
µV p-p
nV/√Hz
µV/mA
µV/mA
mA
µV/V
Exiting power-down mode, VDD = 5 V
See the Terminology section
0.1 Hz to 10 Hz
At ambient temperature, frequency (f) = 10 kHz, CL = 10 nF,
gain = 1 or 2
At ambient temperature
At ambient temperature
VDD ≥ 3 V
At ambient temperature
Rev. E | 4 of 36
Data Sheet
AD5672R/AD5676R
SPECIFICATIONS
Table 2.
Parameter
Min
Long-Term Stability/Drift
Thermal Hysteresis
LOGIC INPUTS
Input Current
Input Voltage
Low, VIL
High, VIH
Pin Capacitance
LOGIC OUTPUTS (SDO)
Output Voltage
Low, VOL
High, VOH
Floating State Output Capacitance
POWER REQUIREMENTS
VLOGIC
VLOGIC Supply Current (ILOGIC)
VDD
Typ
Max
Unit
Test Conditions/Comments
ppm
ppm
ppm
After 1000 hours at 125°C
First cycle
Additional cycles
±1
µA
Per pin
0.3 × VLOGIC
V
V
pF
0.4
V
V
pF
5.5
1
1.3
0.5
1.3
5.5
5.5
V
µA
µA
µA
µA
V
V
1.26
2.0
1.3
2.1
1.7
2.5
5.5
mA
mA
mA
mA
µA
µA
µA
12
125
25
0.7 × VLOGIC
3
VLOGIC − 0.4
4
1.62
2.7
VREF + 1.5
VDD Supply Current (IDD)
Normal Mode7
All Power-Down Modes8
1.1
1.8
1.1
1.8
1
1
1
IOL = 200 μA
IOH = −200 μA
Power-on, −40°C to +105°C
Power-on, −40°C to +125°C
Power-down, −40°C to +105°C
Power-down, −40°C to +125°C
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off, −40°C to +85°C
Internal reference on, −40°C to +85°C
Internal reference off
Internal reference on
−40°C to +85°C
−40°C to +105°C
−40°C to +125°C
1
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when the internal reference voltage (VREF) = VDD with
gain = 1, or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 12 to 4080.
2
VDD = 5 V. The devices include current limiting intended to protect the devices during temporary overload conditions. Junction temperature can be exceeded during current
limit. Operation above the specified maximum operation junction temperature can impair device reliability.
3
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For
example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
4
Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
5
Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.
6
Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
7
Interface inactive. All DACs active. DAC outputs unloaded.
8
All DACs powered down.
analog.com
Rev. E | 5 of 36
Data Sheet
AD5672R/AD5676R
SPECIFICATIONS
AD5676R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications TA = −40°C to +125°C, unless otherwise noted.
Table 3.
A Grade
Parameter
Min
B Grade
Typ
Max
±1.8
±1.7
±8
±8
±0.7
±0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
±0.03
±0.006
±1
±1
±1
3
±6
±4
±0.28
±0.14
±0.24
±0.12
±0.3
±0.25
Min
Typ
Max
±3
±3
±4
±1
±1
1.6
±2
±1.5
±0.14
±0.07
±0.12
±0.06
±0.18
±0.14
0.25
±1.8
±1.7
±1.7
±0.7
±0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
±0.03
±0.006
±1
±3
0.25
±2
±3
±2
±2
±3
±2
Unit
Test Conditions/Comments
STATIC PERFORMANCE1
Resolution
Relative Accuracy (INL)
16
Differential Nonlinearity (DNL)
Zero Code Error
Offset Error
Full-Scale Error
Gain Error
TUE
Offset Error Drift
DC Power Supply Rejection
Ratio (PSRR)
DC Crosstalk
OUTPUT CHARACTERISTICS
Output Voltage Range
16
0
0
2.5
5
0
0
2.5
5
Bits
LSB
LSB
LSB
LSB
LSB
mV
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
µV/°C
mV/V
µV
µV/mA
µV
Gain = 1, TSSOP and LFCSP
Gain = 2, TSSOP and LFCSP
Gain = 1 or gain = 2, WLCSP
Gain = 1
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
TSSOP and LFCSP
WLCSP
DAC code = midscale, VDD =
5 V ± 10%
Due to single channel, full-scale output change
Due to load current change
Due to powering down (per channel)
V
V
Gain = 1
Gain = 2
Capacitive Load Stability
2
10
2
10
nF
nF
RL = ∞
RL = 1 kΩ
Load Regulation
183
183
µV/mA
177
177
µV/mA
VDD = 5 V ± 10%, DAC code = midscale, −30 mA
≤ IOUT ≤ +30 mA
VDD = 3 V ± 10%, DAC code = midscale, −20 mA
≤ IOUT ≤ +20 mA
40
25
2.5
40
25
2.5
mA
Ω
µs
Exiting power-down mode, VDD = 5 V
2.5025
5
V
ppm/°C
TSSOP and LFCSP; see the Terminology section
20
ppm/°C
Ω
µV p-p
nV/√Hz
Short-Circuit Current2
Load Impedance at Rails3
Power-Up Time
REFERENCE OUTPUT
Output Voltage4
Reference Temperature
Coefficient5, 6
Output Impedance
Output Voltage Noise
Output Voltage Noise Density
analog.com
2.4975
5
0.04
13
240
2.5025
20
2.4975
2
5
0.04
13
240
WLCSP
0.1 Hz to 10 Hz
At ambient temperature, f = 10 kHz, CL = 10 nF,
gain = 1 or 2
Rev. E | 6 of 36
Data Sheet
AD5672R/AD5676R
SPECIFICATIONS
Table 3.
A Grade
Parameter
Min
Load Regulation Sourcing
Load Regulation Sinking
Output Current Load Capability
Line Regulation
Long-Term Stability/Drift
Thermal Hysteresis
Typ
Input Voltage
Low, VINL
Pin Capacitance
LOGIC OUTPUTS (SDO)
Output Voltage
Low, VOL
High, VOH
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
IDD
Normal Mode7
All Power-Down Modes8
Min
29
74
±20
43
12
125
25
LOGIC INPUTS
Input Current
High, VINH
B Grade
Max
Typ
Max
29
74
±20
43
12
125
25
µV/mA
µV/mA
mA
µV/V
ppm
ppm
ppm
At ambient temperature
At ambient temperature
VDD ≥ 3 V
At ambient temperature
After 1000 hours at 125°C
First cycle
Additional cycles
Per pin, TSSOP and LFCSP
Per pin, WLCSP
±1
±2
µA
µA
0.3 ×
VLOGIC
0.3 ×
VLOGIC
V
0.7 ×
VLOGIC
3
V
3
0.4
VLOGIC −
0.4
pF
0.4
VLOGIC −
0.4
4
4
5.5
1
1.3
0.5
1.3
5.5
5.5
2.7
VREF + 1.5
Test Conditions/Comments
±1
0.7 ×
VLOGIC
1.62
Unit
1.1
1.8
1.1
1.8
1
1
1.26
2.0
1.3
2.1
1.7
2.5
1
5.5
1.62
2.7
VREF + 1.5
1.1
1.8
1.1
1.8
1
1
1
1
1
V
V
ISINK = 200 μA
ISOURCE = 200 μA
pF
5.5
1
1.3
0.5
1.3
5.5
5.5
V
µA
µA
µA
µA
V
V
1.26
2.0
1.3
2.1
1.7
2.5
3.3
5.5
6.3
mA
mA
mA
mA
µA
µA
µA
µA
µA
Power-on, −40°C to +105°C
Power-on, −40°C to +125°C
Power-down, −40°C to +105°C
Power-down, −40°C to +125°C
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off, −40°C to +85°C
Internal reference on, −40°C to +85°C
Internal reference off
Internal reference on
−40°C to +85°C, TSSOP and LFCSP
−40°C to +105°C, TSSOP and LFCSP
−40°C to +105°C, WLCSP
−40°C to +125°C, TSSOP and LFCSP
−40°C to +125°C, WLCSP
1
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 = VDD
with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
2
VDD = 5 V. The devices include current limiting intended to protect the devices during temporary overload conditions. Junction temperature can be exceeded during current
limit. Operation above the specified maximum operation junction temperature can impair device reliability.
3
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For
example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
analog.com
Rev. E | 7 of 36
Data Sheet
AD5672R/AD5676R
SPECIFICATIONS
Table 3.
A Grade
Parameter
Min
Typ
B Grade
Max
Min
Typ
Max
Unit
Test Conditions/Comments
4
Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
5
Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.
6
Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
7
Interface inactive. All DACs active. DAC outputs unloaded.
8
All DACs powered down.
analog.com
Rev. E | 8 of 36
Data Sheet
AD5672R/AD5676R
SPECIFICATIONS
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX unless otherwise noted.
The operating temperature range is −40°C to +125°C; TA = 25°C.
Table 4.
Parameter
OUTPUT VOLTAGE SETTLING TIME1
AD5672R
AD5676R
SLEW RATE
DIGITAL-TO-ANALOG GLITCH IMPULSE1
DIGITAL FEEDTHROUGH1
CROSSTALK NOTEREF1
Digital
Analog
DAC-to-DAC
TOTAL HARMONIC DISTORTION2
OUTPUT NOISE SPECTRAL DENSITY1
OUTPUT NOISE1
SIGNAL-TO-NOISE RATIO (SNR)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
SIGNAL-TO-NOISE-AND-DISTORTION RATIO
(SINAD)
Min
Typ
Max
Unit
Test Conditions/Comments
5
5
0.8
1.4
0.13
8
8
µs
µs
V/µs
nV-sec
nV-sec
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
0.1
−0.25
−1.3
−2.0
−80
80
300
6
90
83
80
nV-sec
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
nV/√Hz
µV p-p
dB
dB
dB
1 LSB change around major carry (internal reference, gain = 1)
Internal reference, gain = 2
Internal reference, gain = 2
At TA, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz, gain = 2, external reference
DAC code = midscale, 10 kHz, gain = 2
0.1 Hz to 10 Hz, gain = 1
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
1
See the Terminology section. Measured using internal reference and gain = 1, unless otherwise noted.
2
Digitally generated sine wave (fOUT) at 1 kHz.
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREFIN = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 5.
1.62 V ≤ VLOGIC < 2.7 V
Parameter
Symbol
Min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates)
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SYNC Rising Edge to LDAC Rising Edge
SYNC Rising Edge to LDAC Falling Edge
LDAC Falling Edge to SYNC Rising Edge
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
20
8
10
15
2
2
4
15
870
4
8
25
25
840
analog.com
Max
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
20
8
12
11
3
2
4
12
830
4
8
25
25
800
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. E | 9 of 36
Data Sheet
AD5672R/AD5676R
SPECIFICATIONS
Table 5.
1.62 V ≤ VLOGIC < 2.7 V
Parameter
Symbol
Min
Minimum Pulse Width Low
RESET Activation Time
Power-Up Time1
t15
t16
8
90
5.5
1
Max
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Unit
Max
10
90
5.5
ns
ns
µs
Time to exit power-down to normal mode of AD5672R/AD5676R operation, SYNC rising edge to 90% of DAC midscale value, with output unloaded.
Figure 2. Serial Write Operation
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD =
2.7 V to 5.5 V.
Table 6.
1.62 V ≤ VLOGIC < 2.7 V
Parameter
Symbol
Min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SDO Data Valid from SCLK Rising Edge
SYNC Rising Edge to SCLK Falling Edge
SYNC Rising Edge to SDO Disable
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
130
33
12
80
2
2
35
55
60
2
40
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Max
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
110
23
7
80
2
2
10
30
50
6
35
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. E | 10 of 36
Data Sheet
AD5672R/AD5676R
SPECIFICATIONS
Circuit and Timing Diagrams
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
Figure 4. Daisy Chain Timing Diagram
Figure 5. Readback Timing Diagram
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Rev. E | 11 of 36
Data Sheet
AD5672R/AD5676R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 7.
Parameter
Rating
VDD to GND
VLOGIC to GND
VOUTx to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak Temperature,
Pb-Free (J-STD-020)
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +125°C
−65°C to +150°C
125°C
260°C
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to PCB
thermal design is required.
Table 8. Thermal Resistance
Package Type
θJA
θJB
θJC
ΨJT
ΨJB
Unit
20-Lead TSSOP
(RU-20)1
20-Lead LFCSP
(CP-20-8)2
16-Ball WLCSP
(CB-16-24)3
98.65
44.39
17.58
1.77
43.9
°C/W
82
16.67
32.5
0.43
22
°C/W
46.8
12.7
2.4
2.2
12.6
°C/W
1
Thermal impedance simulated values are based on a JEDEC 2S2P thermal test
board. See JEDEC JESD51.
2
Thermal impedance simulated values are based on a JEDEC 2S2P thermal test
board with nine thermal vias. See JEDEC JESD51.
3
Thermal impedance simulated values are based on a JEDEC 2S2P thermal test
board with four thermal vias. See JEDEC JESD51.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
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Rev. E | 12 of 36
Data Sheet
AD5672R/AD5676R
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. TSSOP Pin Configuration
Figure 8. WLCSP Pin Configuration
Figure 7. LFCSP Pin Configuration
Table 9. Pin Function Descriptions
Pin No.1
TSSOP
LFCSP
WLCSP
Mnemonic
Description
1
2
3
19
20
1
B2
A3
A4
VOUT1
VOUT0
VDD
4
5
2
3
B4
B3
VLOGIC
SYNC
6
4
C4
SCLK
7
5
C3
SDI
8
N/A
N/A
GAIN
9
10
11
12
N/A
13
14
6
7
8
9
10
11
N/A
D4
D3
D2
C2
N/A
D1
N/A
VOUT7
VOUT6
VOUT5
VOUT4
NIC
GND
RSTSEL
15
12
N/A
LDAC
16
13
C1
SDO
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
Power Supply Input. These devices operate from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 µF capacitor in
parallel with a 0.1 µF capacitor to GND.
Digital Power Supply. The voltage on this pin ranges from 1.62 V to 5.5 V.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data
transfers in on the falling edges of the next 24 clocks.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
transfers at rates of up to 50 MHz.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of
the serial clock input.
Span Set Pin. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is tied to
VLOGIC, all eight DACs output a span of 0 V to 2 × VREF.
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
No Internal Connection.
Ground Reference Point for All Circuitry on the Device.
Power-On Reset Pin. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to power
up all eight DACs to midscale.
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any
or all DAC registers to be updated if the input registers have new data, which allows all DAC outputs to update
simultaneously. This pin can also be tied permanently low. In the WLCSP, LDAC signal is tied low internally.
Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for
readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge.
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Rev. E | 13 of 36
Data Sheet
AD5672R/AD5676R
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 9. Pin Function Descriptions
Pin No.1
TSSOP
LFCSP
WLCSP
Mnemonic
Description
17
14
N/A
RESET
18
15
A1
VREF
N/A
19
20
N/A
16
17
18
0
N/A
B1
A2
N/A
NIC
VOUT3
VOUT2
EPAD
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses
are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or
midscale, depending on the state of the RSTSEL pin.
Reference Voltage Input/Output. When using the internal reference, this is the reference output pin. Disable the
internal reference to use this pin as an external reference input. This pin is the reference output by default.
No Internal Connection.
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
1
N/A means not applicable.
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Rev. E | 14 of 36
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
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Figure 9. AD5676R INL Error vs. Code
Figure 12. AD5672R DNL Error vs. Code
Figure 10. AD5672R INL Error vs. Code
Figure 13. AD5676R TUE vs. Code
Figure 11. AD5676R DNL Error vs. Code
Figure 14. AD5672R TUE vs. Code
Rev. E | 15 of 36
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 15. AD5676R INL Error vs. Temperature
Figure 18. AD5672R DNL Error vs. Temperature
Figure 16. AD5672R INL Error vs. Supply Voltage
Figure 19. AD5676R TUE vs. Temperature
Figure 17. AD5676R DNL Error vs. Temperature
Figure 20. AD5672R TUE vs. Temperature
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Rev. E | 16 of 36
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 21. AD5676R INL Error vs. Supply Voltage
Figure 24. AD5676R TUE vs. Supply Voltage
Figure 22. AD5676R DNL Error vs. Supply Voltage
Figure 25. AD5672R TUE vs. Supply Voltage
Figure 23. AD5672R DNL Error vs. Supply Voltage
Figure 26. AD5676R Gain Error and Full-Scale Error vs. Temperature
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Rev. E | 17 of 36
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 27. AD5672R Gain Error and Full-Scale Error vs. Temperature
Figure 30. AD5672R Zero Code Error and Offset Error vs. Temperature
Figure 28. AD5676R and AD5672R Gain Error and Full-Scale Error vs. Supply
Voltage
Figure 31. AD5676R Zero Code Error and Offset Error vs. Supply Voltage
Figure 32. AD5672R Zero Code Error and Offset Error vs. Supply Voltage
Figure 29. AD5676R Zero Code Error and Offset Error vs. Temperature
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Rev. E | 18 of 36
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 33. Supply Current (IDD) Histogram with Internal Reference
Figure 36. Source and Sink Capability at 3 V
Figure 34. Headroom/Footroom (ΔVOUT) vs. Load Current
Figure 37. IDD vs. Code
Figure 35. Source and Sink Capability at 5 V
Figure 38. IDD vs. Temperature
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Rev. E | 19 of 36
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 42. Power-On Reset to 0 V
Figure 39. IDD vs. Supply Voltage
Figure 43. Exiting Power-Down to Midscale
Figure 40. IDD vs. Zero Code and Full-Scale
Figure 44. Digital-to-Analog Glitch Impulse
Figure 41. Full-Scale Settling Time
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Rev. E | 20 of 36
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
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Figure 45. Analog Crosstalk
Figure 48. Noise Spectral Density (NSD)
Figure 46. DAC-to-DAC Crosstalk
Figure 49. Total Harmonic Distortion (THD) at 1 kHz
Figure 47. 0.1 Hz to 10 Hz Output Noise
Figure 50. Settling Time at Various Capacitive Loads
Rev. E | 21 of 36
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 51. Settling Time, 5.5 V
Figure 52. Hardware Reset
Figure 53. Internal Reference NSD vs. Frequency
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Figure 54. Internal Reference Voltage (VREF) vs. Temperature (A Grade)
Figure 55. Internal Reference Voltage (VREF) vs. Temperature (B Grade)
Figure 56. Internal Reference Voltage (VREF) vs. Load Current and Supply
Voltage (VDD)
Rev. E | 22 of 36
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 57. Internal Reference Voltage (VREF) vs. Supply Voltage (VDD)
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Rev. E | 23 of 36
Data Sheet
AD5672R/AD5676R
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
Digital-to-Analog Glitch Impulse
For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line
passing through the endpoints of the DAC transfer function.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec, and
is measured when the digital input code is changed by 1 LSB at the
major carry transition (0x7FFF to 0x8000).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. These DACs are guaranteed monotonic by
design.
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. The ideal output is
0 V. The zero code error is always positive because the output
of the DAC cannot go below 0 V due to a combination of the
offset errors in the DAC and the output amplifier. Zero code error is
expressed in mV.
Full-Scale Error
Full-scale error is a measurement of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. The ideal output is
VDD − 1 LSB. Full-scale error is expressed in percent of full-scale
range (% of FSR).
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the ideal
expressed as % of FSR.
Offset Error Drift
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. It is specified in
nV-sec, and measured with a full-scale code change on the data
bus, that is, from all 0s to all 1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal at
the DAC output to the reference input when the DAC output is not
being updated. It is expressed in dB.
Noise Spectral Density
Noise spectral density is a measurement of the internally generated
random noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale. It is
expressed in μV.
Offset error drift is a measurement of the change in offset error with
a change in temperature. It is expressed in µV/°C.
DC crosstalk due to load current change is a measure of the impact
that a change in load current on one DAC has on another DAC kept
at midscale. It is expressed in μV/mA.
Offset Error
Digital Crosstalk
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the transfer
function. Offset error is measured with Code 256 loaded in the DAC
register. It can be negative or positive.
Digital crosstalk is the glitch impulse transferred to the output of one
DAC at midscale in response to a full-scale code change (all 0s
to all 1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-sec.
DC Power Supply Rejection Ratio (PSRR)
Analog Crosstalk
The dc power supply rejection ratio indicates how the output of the
DAC is affected by changes in the supply voltage. PSRR is the ratio
of the change in VOUT to a change in VDD for full-scale output of the
DAC. It is measured in mV/V. VREF is held at 2 V, and VDD is varied
by ±10%.
Analog crosstalk is the glitch impulse transferred to the output of
one DAC due to a change in the output of another DAC. It is
measured by first loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa). Then, execute a
software LDAC and monitor the output of the DAC whose digital
code was not changed. The area of the glitch is expressed in
nV-sec.
Output Voltage Settling Time
The output voltage settling time is the amount of time it takes for the
output of a DAC to settle to a specified level for a ¼ to ¾ full-scale
input change and is measured from the rising edge of SYNC.
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Rev. E | 24 of 36
Data Sheet
AD5672R/AD5676R
TERMINOLOGY
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the output
of one DAC due to a digital code change and subsequent analog
output change of another DAC. It is measured by loading the attack
channel with a full-scale code change (all 0s to all 1s and vice
versa), using the write to and update commands while monitoring
the output of the victim channel that is at midscale. The energy of
the glitch is expressed in nV-sec.
Multiplying Bandwidth
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measurement of the harmonics
present on the DAC output. It is measured in dB.
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Voltage Reference Temperature Coefficient
(TC)
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given temperature
range expressed in ppm/°C, as follows:
TC =
VREF MAX − VREF MIN
VREF NOM × Temp Range
× 106
where:
VREF (MAX) is the maximum reference output measured over the
total temperature range.
VREF (MIN) is the minimum reference output measured over the total
temperature range.
VREF (NOM) is the nominal reference output voltage, 2.5 V.
Temp Range is the specified temperature range of −40°C to
+125°C.
Rev. E | 25 of 36
Data Sheet
AD5672R/AD5676R
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5672R/AD5676R are octal, 12-/16-bit, serial input, voltage
output DACs with an internal reference. The devices operate from
supply voltages of 2.7 V to 5.5 V. Data is written to the AD5672R/
AD5676R in a 24-bit word format via a 3-wire serial interface. The
AD5672R/AD5676R incorporate a power-on reset circuit to ensure
that the DAC output powers up to a known output state. The
devices also have a software power-down mode that reduces the
typical current consumption to 1 µA.
TRANSFER FUNCTION
The internal reference is on by default.
The gain of the output amplifier can be set to ×1 or ×2 using the
gain select pin (GAIN) on the TSSOP or the gain bit on the LFCSP
and WLCSP. When the GAIN pin is tied to GND, all eight DAC
outputs have a span from 0 V to VREF. When the GAIN pin is
tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF.
When using the LFCSP or WLCSP, the gain bit in the internal
reference and gain setup register is used to set the gain of the
output amplifier. The gain bit is 0 by default. When the gain bit is 0,
the output span of all eight DACs is 0 V to VREF. When the gain bit
is 1, the output span of all eight DACs is 0 V to 2 × VREF. The gain
bit is ignored on the TSSOP.
DAC ARCHITECTURE
The AD5672R/AD5676R implement a segmented string DAC architecture with an internal output buffer. Figure 59 shows the internal
block diagram.
Figure 59. Resistor String Structure
Internal Reference
The AD5672R/AD5676R on-chip reference is enabled at power-up,
but can be disabled via a write to the control register. See the
Internal Reference Setup section for details.
The AD5672R/AD5676R have a 2.5 V, 2 ppm/°C reference, giving a
full-scale output of 2.5 V or 5 V, depending on the state of the GAIN
pin or gain bit. The internal reference associated with the device
is available at the VREF pin. This buffered reference is capable of
driving external loads of up to 15 mA.
Output Amplifiers
The output buffer amplifier generates rail-to-rail voltages on its
output. The actual range depends on the value of VREF, the gain
setting, the offset error, and the gain error.
The output amplifiers can drive a load of 1 kΩ in parallel with 10
nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to ¾ scale
settling time of 5 µs.
SERIAL INTERFACE
Figure 58. Single DAC Channel Architecture Block Diagram
Figure 60 shows the resistor string structure. The code loaded to
the DAC register determines the node on the string where the
voltage is tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches and connecting the string
to the amplifier. Because each resistance in the string has same
value, R, the string DAC is guaranteed monotonic.
The AD5672R/AD5676R use a 3-wire serial interface (SYNC,
SCLK, and SDI) that is compatible with SPI, QSPI™, and MICROWIRE interface standards, as well as most DSPs. See Figure 2
for a timing diagram of a typical write sequence. The AD5672R/
AD5676R contain an SDO pin to allow the user to daisy-chain
multiple devices together (see the Daisy-Chain Operation section)
or for readback.
Input Shift Register
The input shift register of the AD5672R/AD5676R is 24 bits wide.
Data is loaded MSB first (DB23), and the first four bits are the
command bits, C3 to C0 (see Table 10), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 11), and finally, the 16-bit
data-word.
The data-word comprises 12-bit or 16-bit input code, followed
by zero or four don't care bits for the AD5672R and AD5676R,
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Rev. E | 26 of 36
Data Sheet
AD5672R/AD5676R
THEORY OF OPERATION
respectively (see Figure 60 and Figure 61). These data bits are
transferred to the input register on the 24 falling edges of SCLK and
are updated on the rising edge of SYNC.
Table 10. Command Definitions
C3
C2
C1
C0
Description
Commands execute on individual DAC channels, combined DAC
channels, or on all DACs, depending on the address bits selected.
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
…
1
1
…
1
0
…
1
0
…
1
No operation
Write to Input Register n where n = 1 to 8, depending
on the DAC selected from the address bits in Table 11
(dependent on LDAC)1
Update DAC Register n with contents of Input Register
n
Write to and update DAC Channel n
Power down/power up the DAC
Hardware LDAC mask register
Software reset (power-on reset)
Internal reference and gain setup register
Set up the DCEN register (daisy-chain enable)
Set up the readback register (readback enable)
Update all channels of the input register
simultaneously with the input data1
Update all channels of the DAC register and input
register simultaneously with the input data
Reserved
Command
1
No operation, daisy-chain mode
On WLCSP, data written using this command is transparent to the DAC output.
Table 11. Address Commands
Channel Address[3:0]
A3
A2
A1
A0
Selected Channel
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
Figure 60. AD5672R Input Shift Register Content
Figure 61. AD5676R Input Shift Register Content
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Rev. E | 27 of 36
Data Sheet
AD5672R/AD5676R
THEORY OF OPERATION
STANDALONE OPERATION
Bring the SYNC line low to begin the write sequence. Data from
the SDI line is clocked into the 24-bit input shift register on the
falling edge of SCLK. After the last of 24 data bits is clocked in,
bring SYNC high. The programmed function is then executed, that
is, an LDAC-dependent change in DAC register contents and/or a
change in the mode of operation. If SYNC is taken high at a clock
before the 24th clock, it is considered a valid frame, and invalid data
is loaded to the DAC. Bring SYNC high for a minimum of 20 ns
(single channel, see t8 in Figure 2) before the next write sequence
so that a falling edge of SYNC can initiate the next write sequence.
Idle SYNC at rails between write sequences for even lower power
operation. The SYNC line is kept low for 24 falling edges of SCLK,
and the DAC is updated on the rising edge of SYNC.
Table 12. Daisy-Chain Enable (DCEN) Register
DB0
Description
0
1
Standalone mode (default)
DCEN mode
When data is transferred into the input register of the addressed
DAC, all DAC registers and outputs update by taking LDAC low
while the SYNC line is high.
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on LDAC)
Command 0001 allows the user to write the dedicated input register
of each DAC individually. When LDAC is low, the input register
is transparent, if not controlled by the LDAC mask register. On
WLCSP, data written using this command is transparent to the DAC
output.
Update DAC Register n with Contents of Input
Register n
Command 0010 loads the DAC registers and outputs with the contents of the input registers selected and updates the DAC outputs
directly. Data Bit D7 to Bit D0 determine which DACs have data
from the input register transferred to the DAC register. Setting a bit
to 1 transfers data from the input register to the appropriate DAC
register.
Write to and Update DAC Channel n
(Independent of LDAC
Command 0011 allows the user to write to the DAC registers and
updates the DAC outputs directly. The address bits are used to
select the DAC channel.
DAISY-CHAIN OPERATION
For systems that contain several DACs, the SDO pin can daisychain several devices together and is enabled through a software
executable daisy-chain enable (DCEN) command. Command 1000
is reserved for this DCEN function (see Table 10). The daisy-chain
mode is enabled by setting Bit DB0 in the DCEN register. The
default setting is standalone mode, where DB0 = 0. Table 12 shows
how the state of the bit corresponds to the mode of operation of the
device.
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Figure 62. Daisy-Chaining the AD5672R/AD5676R
The SCLK pin is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the SDI input on
the next DAC in the chain, a daisy-chain interface is constructed.
Each DAC in the system requires 24 clock pulses. Therefore, the
total number of clock cycles must equal 24 × N, where N is the
total number of devices updated. If SYNC is taken high at a clock
that is not a multiple of 24, it is considered a valid frame, and
invalid data may be loaded to the DAC. When the serial transfer to
all devices is complete, SYNC goes high, which latches the input
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift register. The serial clock
can be continuous or a gated clock. If SYNC is held low for the
correct number of clock cycles, a continuous SCLK source is used.
In gated clock mode, use a burst clock containing the exact number
of clock cycles, and take SYNC high after the final clock to latch the
data.
READBACK OPERATION
Readback mode is invoked through a software executable readback command. If the SDO output is disabled via the daisy-chain
mode disable bit in the control register, it is automatically enabled
for the duration of the read operation, after which it is disabled
again. Command 1001 is reserved for the readback function. This
command, in association with the address bits A3 to A0, selects
the DAC input register to read (see Table 10 and Table 11). Note
Rev. E | 28 of 36
Data Sheet
AD5672R/AD5676R
THEORY OF OPERATION
that, during readback, only one input register can be selected. The
remaining data bits in the write sequence are don’t care bits. During
the next SPI write, the data appearing on the SDO output contains
the data from the previously addressed register.
Table 13. Modes of Operation
For example, to read back the DAC register for Channel 0, implement the following sequence:
1. Write 0x900000 to the AD5672R/AD5676R input register. This
configures the device for read mode with the DAC register of
Channel 0 selected. Note that all data bits, DB15 to DB0, are
don’t care bits.
2. Follow this with a second write, a no operation (NOP) condition,
0x000000 or 0xF00000 when in daisy-chain mode. During this
write, the data from the register is clocked out on the SDO
line. DB23 to DB20 contain undefined data, and the last 16 bits
contain the DB19 to DB4 DAC register contents.
Operating Mode
PD1
PD0
Normal Operation
Power-Down Modes
1 kΩ to GND
Tristate
0
0
0
1
1
1
When both Bit PD1 and Bit PD0 in the input shift register are set
to 0, the device works normally with a typical power consumption of
1 mA at 5 V. However, for the two power-down modes, the supply
current typically falls to 1 µA. In addition to this fall, the output stage
switches internally from the amplifier output to a resistor network
of known values. Therefore the DAC channel output impedance is
defined when the channel is powered down. There are two different
power-down options. The output is either connected internally to
GND through a 1 kΩ resistor or it is left open circuited (tristate).
Figure 63 shows the output stage.
When SYNC is high, the SDO pin is driven by a weak latch, which
holds the last data bit. The SDO pin can be overdriven by the SDO
pin of another device, thus allowing multiple devices to be read
using the same SPI interface.
POWER-DOWN OPERATION
The AD5672R/AD5676R contain two separate power-down modes.
Command 0100 is designated for the power-down function (see
Table 10). These power-down modes are software programmable
by setting 16 bits, Bit DB15 to Bit DB0, in the input shift register.
There are two bits associated with each DAC channel. Table 13
shows how the state of the two bits corresponds to the mode of
operation of the device.
Figure 63. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry shut down when power-down mode is
activated. However, the contents of the DAC register are unaffected
when in power-down. The DAC register updates while the device
is in power-down mode. The time required to exit power-down is
typically 2.5 µs for VDD = 5 V.
Any or all DACs (DAC 0 to DAC 7) power down to the selected
mode by setting the corresponding bits. See Table 14 for the
contents of the input shift register during the power-down/power-up
operation.
To reduce the current consumption further, power off the on-chip
reference. See the Internal Reference Setup section.
Table 14. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation
[DB23:DB20]
0100
1
DAC 7
DAC 6
DAC 5
DAC 4
DAC 3
DAC 2
DAC 1
DAC 0
DB19
[DB18:DB16]
[DB15: B14]
[DB13:DB12] [DB11:DB10] [DB9:DB8]
[DB7:DB6]
[DB5:DB4]
[DB3:DB2]
[DB1:DB0]
0
XXX1
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
X means don’t care.
analog.com
Rev. E | 29 of 36
Data Sheet
AD5672R/AD5676R
THEORY OF OPERATION
LOAD DAC (HARDWARE LDAC PIN)
Deferred DAC Updating (LDAC is Pulsed Low)
The AD5672R/AD5676R DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers.
Updates to the DAC register are controlled by the LDAC pin.
LDAC is held high while data is clocked into the input register using
Command 0001. All DAC outputs are asynchronously updated by
taking LDAC low after SYNC is taken high. The update now occurs
on the falling edge of LDAC.
Instantaneous DAC Updating (LDAC Held Low)
LDAC MASK REGISTER
LDAC is held low while data is clocked into the input register using
Command 0001. Both the addressed input register and the DAC
register are updated on the rising edge of SYNC and the output
begins to change (see Table 16).
Command 0101 is reserved for this software LDAC function. Address bits are ignored. Writing to the DAC, using Command 0101,
loads the 8-bit LDAC register (DB7 to DB0). The default for each
channel is 0; that is, the LDAC pin works normally. Setting the bits
to 1 forces this DAC channel to ignore transitions on the LDAC pin,
regardless of the state of the hardware LDAC pin. This flexibility
is useful in applications where the user wishes to select which
channels respond to the LDAC pin.
The LDAC register gives the user extra flexibility and control over
the hardware LDAC pin (see Table 15). Setting the LDAC bits (DB0
to DB7) to 0 for a DAC channel means that this channel update is
controlled by the hardware LDAC pin.
Figure 64. Simplified Diagram of Input Loading Circuitry for a Single DAC
Table 15. LDAC Overwrite Definition
Load LDAC Register
LDAC Bits (DB7 to DB0)
LDAC Pin
LDAC Operation
00000000
11111111
1 or 0
X1
Determined by the LDAC pin.
DAC channels update and override the LDAC pin. DAC channels see LDAC as 1.
1
X means don’t care.
Table 16. Write Commands and LDAC Pin Truth Table1
Command
Description
Hardware LDAC Pin State
Input Register Contents
DAC Register Contents
0001
Write to Input Register n
(dependent on LDAC)
0010
Update DAC Register n with
contents of Input Register n
0011
Write to and update DAC
Channel n
VLOGIC
GND2
VLOGIC
GND
VLOGIC
GND
Data update
Data update
No change
No change
Data update
Data update
No change (no update)
Data update
Updated with input register contents
Updated with input register contents
Data update
Data update
1
A high to low hardware LDAC pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that are not
masked (blocked) by the LDAC mask register.
2
When LDAC is permanently tied low, the LDAC mask bits are ignored.
analog.com
Rev. E | 30 of 36
Data Sheet
AD5672R/AD5676R
THEORY OF OPERATION
HARDWARE RESET (RESET)
The RESET pin is an active low reset that allows the outputs to be
cleared to either zero scale or midscale. The clear code value is
user selectable via the RESET select pin. It is necessary to keep
the RESET pin low for a minimum time (see Table 5) to complete
the operation. When the RESET signal is returned high, the output
remains at the cleared value until a new value is programmed.
While the RESET pin is low, the outputs cannot be updated with
a new value. Any events on the LDAC or RESET pins during
power-on reset are ignored. If the RESET pin is pulled low at
power-up, the device does not initialize correctly until the pin is
released.
RESET SELECT PIN (RSTSEL)
The AD5672R/AD5676R contain a power-on reset circuit that
controls the output voltage during power-up. By connecting the
RSTSEL pin low, the output powers up to zero scale. Note that
this is outside the linear region of the DAC; by connecting the
RSTSEL pin high, VOUTx power up to midscale. The output remains
powered up at this level until a valid write sequence is made to
the DAC. The RSTSEL pin is only available on the TSSOP. When
the AD5672R/AD5676R LFCSP or AD5676R WLCSP is used, the
outputs power up to 0 V.
Table 17. Internal Reference and Gain Setup Register
Bit
Description
DB0
Reference enable
DB0 = 0: internal reference enabled (default)
DB0 = 1: internal reference disabled
SOLDER HEAT REFLOW
As with all IC reference voltage circuits, the reference value experiences a shift induced by the soldering process. Analog Devices,
Inc., performs a reliability test called precondition to mimic the effect
of soldering a device to a board. The output voltage specification
quoted previously includes the effect of this reliability test.
Figure 65 shows the effect of solder heat reflow (SHR) as measured through the reliability test (precondition).
SOFTWARE RESET
A software executable reset function is also available that resets
the DAC to the power-on reset code. Command 0110 is designated
for this software reset function. The DAC address bits must be
set to 0x0 and the data bits set to 0x1234 for the software reset
command to execute.
AMPLIFIER GAIN SELECTION ON LFCSP AND
WLCSP
The output amplifier gain setting for the LFCSP and WLCSP is
determined by the state of the DB2 bit in the internal reference and
gain setup register (see Table 17 and Table 18).
Figure 65. Solder Heat Reflow Reference Voltage Shift
LONG-TERM TEMPERATURE DRIFT
Figure 66 shows the change in VREF value after 1000 hours in the
life test at 150°C.
INTERNAL REFERENCE SETUP
The on-chip reference is on at power-up by default. To reduce
the supply current, turn off this reference by setting the software
programmable bit, DB0, in the Internal reference and gain setup
register. Table 17 shows how the state of the bit corresponds to the
mode of operation. Command 0111 is reserved for setting up the
internal reference and the gain setting on the LFCSP and WLCSP
(see Table 10).
Table 17. Internal Reference and Gain Setup Register
Bit
Description
DB2
Amplifier gain setting
DB2 = 0: amplifier gain = 1 (default)
DB2 = 1: amplifier gain = 2
analog.com
Figure 66. Reference Drift Through to 1000 Hours
Rev. E | 31 of 36
Data Sheet
AD5672R/AD5676R
THEORY OF OPERATION
Table 18. 24-Bit Input Shift Register Contents for Internal Reference and Gain Setup Command
DB23 (MSB)
DB22
DB21
DB20
DB19 to DB3
DB2
DB1
DB0 (LSB)
0
1
1
1
Don’t care
Gain
Reserved. Set to 0
Reference enable
THERMAL HYSTERESIS
Thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, to
hot, and then back to ambient.
Figure 67 shows thermal hysteresis data. It is measured by sweeping the temperature from ambient to −40°C, then to +125°C, and
returning to ambient. The VREF delta, shown in blue in Figure 67, is
then measured between the two ambient measurements. The same
temperature sweep and measurements were immediately repeated
and the results are shown in red in Figure 67.
Figure 67. Thermal Hysteresis
analog.com
Rev. E | 32 of 36
Data Sheet
AD5672R/AD5676R
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
LAYOUT GUIDELINES
The following supplies typically power the AD5672R/AD5676R: VDD
= 3.3 V and VLOGIC = 1.8 V.
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. Design the PCB on which the AD5672R/
AD5676R are mounted so that the devices lie on the analog plane.
The ADP7118 can be used to power the VDD pin. The ADP160 can
be used to power the VLOGIC pin. Figure 68 shows this setup. The
ADP7118 can operate from input voltages up to 20 V. The ADP160
can operate from input voltages up to 5.5 V.
Figure 68. Low Noise Power Solution for the AD5672R/AD5676R
The ideal power-up sequence is GND, VLOGIC, VDD, followed by the
digital inputs.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5672R/AD5676R is performed
via a serial bus that uses a standard protocol compatible with DSP
processors and microcontrollers. The communications channel requires a 3-wire or 4-wire interface consisting of a clock signal, a
data signal, and a synchronization signal. The devices require a
24-bit data-word with data valid on the rising edge of SYNC.
The AD5672R/AD5676R must have ample supply bypassing of 10
µF in parallel with 0.1 µF on each supply, located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are tantalum bead type. The 0.1 µF capacitors
must have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
In systems where there are many devices on one board, it is often
useful to provide some heat sinking capability to allow the power to
dissipate easily.
The GND plane on the device can be increased (as shown in
Figure 71) to provide a natural heat sinking effect.
AD5672R/AD5676R TO ADSP-BF531
INTERFACE
The SPI interface of the AD5672R/AD5676R can easily connect
to industry-standard DSPs and microcontrollers. Figure 69 shows
the AD5672R/AD5676R connected to the Analog Devices Blackfin®
DSP. The Blackfin has an integrated SPI port that can connect
directly to the SPI pins of the AD5672R/AD5676R.
Figure 69. ADSP-BF531 Interface
AD5672R/AD5676R TO SPORT INTERFACE
Figure 71. Pad Connection to the Board
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide an
isolation barrier between the controller and the unit being controlled
to protect and isolate the controlling circuitry from any hazardous
common-mode voltages that may occur. iCoupler® products from
Analog Devices provide voltage isolation in excess of 2.5 kV. The
serial loading structure of the AD5672R/AD5676R makes the devices ideal for isolated interfaces because the number of interface
lines is kept to a minimum. Figure 72 shows a 4-channel isolated interface to the AD5672R/AD5676R using an ADuM1400. For further
information, visit www.analog.com/icoupler.
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 70 shows how a SPORT interface is used to control the
AD5672R/AD5676R.
Figure 70. SPORT Interface
analog.com
Rev. E | 33 of 36
Data Sheet
AD5672R/AD5676R
APPLICATIONS INFORMATION
Figure 72. Isolated Interface
analog.com
Rev. E | 34 of 36
Data Sheet
AD5672R/AD5676R
OUTLINE DIMENSIONS
Figure 73. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Figure 74. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
Figure 75. 16-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-16-24)
Dimensions shown in millimeters
analog.com
Rev. E | 35 of 36
Data Sheet
AD5672R/AD5676R
OUTLINE DIMENSIONS
Updated: December 15, 2021
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package
Option
AD5672RBCPZ-REEL7
AD5672RBCPZ-RL
AD5672RBRUZ
AD5672RBRUZ-REEL7
AD5676RACPZ-REEL7
AD5676RACPZ-RL
AD5676RARUZ
AD5676RARUZ-REEL7
AD5676RBCBZ-RL
AD5676RBCPZ-REEL7
AD5676RBCPZ-RL
AD5676RBRUZ
AD5676RBRUZ-REEL7
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
20-Lead LFCSP (4mm x 4mm w/ EP)
20-Lead LFCSP (4mm x 4mm w/ EP)
20-Lead TSSOP
20-Lead TSSOP
20-Lead LFCSP (4mm x 4mm w/ EP)
20-Lead LFCSP (4mm x 4mm w/ EP)
20-Lead TSSOP
20-Lead TSSOP
CHIPS W/SOLDER BUMPS/WLCSP
20-Lead LFCSP (4mm x 4mm w/ EP)
20-Lead LFCSP (4mm x 4mm w/ EP)
20-Lead TSSOP
20-Lead TSSOP
Reel, 1500
Reel, 5000
Tube, 75
Reel, 1000
Reel, 1500
Reel, 5000
Tube, 75
Reel, 1000
Reel, 10000
Reel, 1500
Reel, 5000
Tube, 75
Reel, 1000
CP-20-8
CP-20-8
RU-20
RU-20
CP-20-8
CP-20-8
RU-20
RU-20
CB-16-24
CP-20-8
CP-20-8
RU-20
RU-20
1
Marking Code
DN4
DN4
DN2
DN2
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model1, 2, 3
Description
EVAL-AD5676RSDZ
EVAL-AD5676RARDZ
Evaluation Board
Evaluation Board
1
Z = RoHS Compliant Part.
2
The EVAL-AD5676RSDZ is used to evaluate the AD5672R and AD5676R TSSOP.
3
The EVAL-AD5676RARDZ is used to evaluate the AD5676R WLCSP only.
©2014-2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. E | 36 of 36
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