5 V 18-Bit nanoDAC®
in a SOT-23
AD5680
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VREF
Single 18-bit nanoDAC
18-bit monotonic
12-bit accuracy guaranteed
Tiny 8-lead SOT-23 package
Power-on reset to zero scale/midscale
4.5 V to 5.5 V power supply
Serial interface
Rail-to-rail operation
SYNC interrupt facility
Temperature range: −40°C to +105°C
GND
VDD
VFB
POWER-ON
RESET
OUTPUT
BUFFER
REF(+)
DAC
REGISTER
VOUT
18-BIT DAC
APPLICATIONS
AD5680
Closed-loop process control
Low bandwidth data acquisition systems
Portable battery-powered instruments
Gain and offset adjustment
Precision setpoint control
SYNC
SCLK
DIN
05854-001
INPUT
CONTROL
LOGIC
Figure 1.
GENERAL DESCRIPTION
The AD5680, a member of the nanoDAC family, is a single,
18-bit buffered voltage-out digital-to-analog converter (DAC)
that operates from a single 4.5 V to 5.5 V supply and is 18-bit
monotonic.
The AD5680 uses a versatile 3-wire serial interface that operates
at clock rates up to 30 MHz, and is compatible with standard
SPI®, QSPI™, MICROWIRE™, and DSP interface standards.
The AD5680 requires an external reference voltage to set the
output range of the DAC. The part incorporates a power-on
reset circuit that ensures the DAC output powers up to 0 V
(AD5680-1) or to midscale (AD5680-2) and remains there until
a valid write takes place.
1.
18 bits of resolution.
2.
12-bit accuracy guaranteed for 18-bit DAC.
3.
Available in an 8-lead SOT-23.
4.
Low power; typically consumes 1.6 mW at 5 V.
5.
Power-on reset to zero scale or to midscale.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The power consumption is 1.6 mW at 5 V.
The AD5680 on-chip precision output amplifier allows rail-torail output swing to be achieved. For remote sensing applications,
the output amplifier’s inverting input is available to the user.
Rev. B
PRODUCT HIGHLIGHTS
RELATED DEVICES
AD5662—16-bit DAC in SOT-23.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5680* Product Page Quick Links
Last Content Update: 08/30/2016
Comparable Parts
Design Resources
View a parametric search of comparable parts
• AD5680 Evaluation Board
•
•
•
•
Documentation
Discussions
Data Sheet
• AD5680: 5 V 18-Bit nanoDAC® in a SOT-23 Data Sheet
View all AD5680 EngineerZone Discussions
Evaluation Kits
AD5680 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
Sample and Buy
Software and Systems Requirements
Visit the product page to see pricing options
• AD5680 Software Evaluation, (zip)
Technical Support
Reference Materials
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
AD5680
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier ........................................................................ 11
Applications ....................................................................................... 1
Interpolator Architecture .......................................................... 11
Functional Block Diagram .............................................................. 1
Serial Interface ............................................................................ 12
General Description ......................................................................... 1
Input Shift Register .................................................................... 12
Product Highlights ........................................................................... 1
SYNC Interrupt .......................................................................... 12
Related Devices ................................................................................. 1
Power-On Reset .......................................................................... 12
Revision History ............................................................................... 2
Microprocessor Interfacing ....................................................... 13
Specifications..................................................................................... 3
Applications Information .............................................................. 14
Timing Characteristics ................................................................ 4
Closed-Loop Applications......................................................... 14
Absolute Maximum Ratings ............................................................ 5
Filter ............................................................................................. 14
ESD Caution .................................................................................. 5
Choosing a Reference for the AD5680 .................................... 15
Pin Configurations and Function Descriptions ........................... 6
Using a Reference as a Power Supply for the AD5680 .......... 16
Typical Performance Characteristics ............................................. 7
Using the AD5680 with a Galvanically Isolated Interface .... 16
Terminology .................................................................................... 10
Power Supply Bypassing and Grounding ................................ 16
Theory of Operation ...................................................................... 11
Outline Dimensions ....................................................................... 17
DAC Section ................................................................................ 11
Ordering Guide .......................................................................... 17
Resistor String ............................................................................. 11
REVISION HISTORY
2/14—Rev. A to Rev. B
Added 8-Lead LFCSP ......................................................... Universal
Changes to Figure 3 Caption and Table 4 Caption ...................... 6
Added Figure 4; Renumbered Sequentially .................................. 6
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
3/07—Rev. 0 to Rev. A
Changes to Input Shift Register Section ...................................... 12
Changes to Figure 25 ...................................................................... 12
6/06—Revision 0: Initial Version
Rev. B | Page 2 of 20
Data Sheet
AD5680
SPECIFICATIONS
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE 2
Resolution
Relative Accuracy
Differential Nonlinearity 3
Zero-Code Error
Full-Scale Error
Offset Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
OUTPUT CHARACTERISTICS3
Output Voltage Range
Output Voltage Settling Time
Min
18
±32
2
−0.2
±64
±1
±2
10
−1
±10
±1.5
±2
±2.5
−100
0
80
Slew Rate
Capacitive Load Stability
Output Noise Spectral Density 4
Output Noise (0.1 Hz to 10 Hz)4
Total Harmonic Distortion (THD)4
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short-Circuit Current4
REFERENCE INPUT
Reference Current
Reference Input Range 5
Reference Input Impedance
LOGIC INPUTS3
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
POWER EFFICIENCY
IOUT/IDD
B Grade 1
Typ
Max
VDD
85
1.5
2
10
80
25
−80
5
0.2
0.5
30
40
0.75
85
V
µs
Conditions/Comments
Measured in 50 Hz system bandwidth
Measured in 300 Hz system bandwidth
All 0s loaded to DAC register
All 1s loaded to DAC register
Of FSR/°C
DAC code = midscale; VDD = 5 V ± 10%
¼ to ¾ scale change settling to ±8 LSB,
RL = 2 kΩ; 0 pF < CL < 200 pF
¼ to ¾ scale
RL = ∞
RL = 2 kΩ
DAC code = midscale, 10 kHz
DAC code = midscale
VREF = 2 V ± 300 mV p-p, f = 200 Hz
1 LSB change around major carry
VDD = 5 V
75
VDD
µA
V
kΩ
VREF = VDD = 5 V
±2
0.8
µA
V
V
pF
All digital inputs
VDD = 5 V
VDD = 5 V
5.5
V
450
μA
All digital inputs at 0 V or VDD
DAC active and excluding load current
VIH = VDD and VIL = GND
%
ILOAD = 2 mA, VDD = 5 V
2
3
325
Bits
LSB
LSB
LSB
mV
% FSR
mV
% FSR
µV/°C
ppm
dB
V/µs
nF
nF
nV/√Hz
µV p-p
dB
nV-s
nV-s
Ω
mA
125
4.5
Unit
1
Temperature range for B version is −40°C to +105°C, typical at +25°C.
DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 2048 to 260,096.
Guaranteed by design and characterization; not production tested.
4
Output unloaded.
5
Reference input range at ambient where maximum DNL specification is achievable.
2
3
Rev. B | Page 3 of 20
AD5680
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 4.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Limit at TMIN, TMAX
VDD = 4.5 V to 5.5 V
33
13
13
13
5
4.5
0
33
13
0
Parameter
t1 1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
Maximum SCLK frequency is 30 MHz at VDD = 4.5 V to 5.5 V.
t10
t1
t9
SCLK
t8
t3
t4
t2
t7
SYNC
t5
DIN
DB23
t6
DB0
Figure 2. Serial Write Operation
Rev. B | Page 4 of 20
05854-002
1
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Data Sheet
AD5680
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VOUT to GND
VFB to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
θJA Thermal Impedance
SOT-23 Package (4-Layer Board)
Reflow Soldering Peak Temperature
Pb-free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
119°C/W
260°C
Rev. B | Page 5 of 20
AD5680
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
8
GND
2
AD5680
7
DIN
VFB
3
TOP VIEW
(Not to Scale)
6
SCLK
VOUT
4
5
SYNC
VDD 1
VREF 2
VFB 3
VOUT 4
8 GND
AD5680
TOP VIEW
(Not to Scale)
7 DIN
6 SCLK
5 SYNC
05854-104
1
05854-003
VDD
VREF
Figure 4. 8-Lead LFCSP Pin Configuration
Figure 3. 8-Lead SOT-23 Pin Configuration
Table 4. 8-Lead SOT-23 and 8-Lead LFSCP Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
VDD
VREF
VFB
VOUT
SYNC
6
SCLK
7
DIN
8
GND
Description
Power Supply Input. The part can be operated from 4.5 V to 5.5 V. VDD should be decoupled to GND.
Reference Voltage Input.
Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation.
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. SYNC
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Ground. Ground reference point for all circuitry on the part.
Rev. B | Page 6 of 20
Data Sheet
AD5680
TYPICAL PERFORMANCE CHARACTERISTICS
40
0
VDD = VREF = 5V
32 TA = 25°C
–0.02
24
–0.04
16
–0.06
VDD = 5V
8
0
–8
–0.08
–0.10
–0.12
–0.14
–24
–0.16
05854-028
–16
–32
–40
80k
40k
0
160k
120k
CODE
200k
FULL-SCALE ERROR
05854-044
ERROR (% FSR)
INL ERROR (LSB)
GAIN ERROR
–0.18
–0.20
–40
240k
0
–20
20
40
60
TEMPERATURE (°C)
80
100
Figure 8. Gain Error and Full-Scale Error vs. Temperature
Figure 5. Typical INL Plot
1.5
1.0
VDD = VREF = 5V
TA = 25°C
0.8
1.0
ZERO-SCALE ERROR
0.6
ERROR (mV)
DNL ERROR (LSB)
0.5
0.4
0.2
0
–0.2
0
–0.5
–1.0
–0.4
–1.5
OFFSET ERROR
–0.6
–1.0
0
25k
50k
–2.5
–40
75k 100k 125k 150k 175k 200k 225k 250k
CODE
Figure 6. Typical DNL Plot in 50 Hz System Bandwidth
05854-043
–2.0
05854-029
–0.8
–20
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 9. Zero-Scale Error and Offset Error vs. Temperature
0.20
±4
VDD = 4.5V TO 5.5V
T = –40°C TO +105°C
0.15
DAC LOADED WITH
ZERO SCALE –
SINKING CURRENT
VDD = VREF = 5V, 3V
TA = 25°C
ERROR VOLTAGE (V)
0.10
DNL (LSB)
±2
±1
0.05
0
–0.05
–0.10
–0.15
0
300
50
SYSTEM BANDWIDTH (Hz)
>300
05854-042
0
Figure 7. DNL Performance vs. System Bandwidth
–0.25
–5
–4
–3
–2
–1
0
I (mA)
05854-014
DAC LOADED WITH
FULL SCALE –
SOURCING CURRENT
–0.20
1
2
3
4
Figure 10. Headroom at Rails vs. Source and Sink Current
Rev. B | Page 7 of 20
5
AD5680
450
Data Sheet
VDD = VREF = 5V
TA = 25°C
400
SCLK
1
350
DIN
IDD (µA)
300
250
2
200
Δ: 1.52V
Δ: 64.8µs
@: 1.20V
150
VOUT
05854-015
100
50
3
4000
0
8000
12000
16000
20000
CH1 2.00V
CH3 1.00V
05854-007
0
24000
CODE
CH2 2.00V
M 20.0µs
CH4
1.30V
Figure 14. Full-Scale Settling Time, 5 V
Figure 11. Supply Current vs. Code
350
VDD = VREF = 5V
300
1
VDD
IDD (µA)
250
200
VREF
VOUT
C3 MAX
284mV
2
150
VOUT
C3 MIN
–52mV
100
05854-016
VOUT
50
3
–20
0
20
40
60
80
100
TEMPERATURE (°C)
CH1 3.00V CH2 3.00V
CH3 100mV
05854-006
0
–40
CH1
2.40V
Figure 15. Power-On Reset to 0 V
Figure 12. Supply Current vs. Temperature
700
M 100µs
TA = 25°C
600
VDD = 5V
1
VDD
500
VREF
VOUT
C3 MAX
2.5V
300
VOUT
C3 MIN
–40mV
200
VOUT
100
0
0
1
2
3
4
VLOGIC (V)
5
05854-017
3
CH1 3.00V CH2 3.00V
CH3 500mV
05854-004
IDD (µA)
2
400
M 100µs
CH1
Figure 16. Power-On Reset to Midscale
Figure 13. Supply Current vs. Logic Input Voltage
Rev. B | Page 8 of 20
2.40V
Data Sheet
AD5680
2.502500
16
VDD = VREF = 5V
TA = 25°C
13ns/SAMPLE NUMBER
1 LSB CHANGE AROUND
MIDSCALE (0x20000 TO 0x1FFFF)
GLITCH IMPULSE = 2.723nV-s
2.502250
2.502000
2.501750
2.501500
VREF = VDD
TA = 25°C
14
VDD = 3V
12
2.501000
TIME (µs)
AMPLITUDE
2.501250
2.500750
2.500500
2.500250
10
VDD = 5V
8
2.500000
2.499750
2.499500
05854-005
2.499000
2.498750
0
50
100
4
450 500 550
400
150 200 250 300 350
SAMPLE NUMBER
05854-027
6
2.499250
0
Figure 17. Digital-to-Analog Glitch Impulse (Negative)
2.5010
2.5006
2.5004
2
3
4
5
6
7
CAPACITANCE (nF)
8
9
10
Figure 20. Settling Time vs. Capacitive Load
VDD = VREF = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
DIGITAL FEEDTHROUGH
= 0.201nV
2.5008
1
VDD = VREF = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
2.5000
5µV/DIV
AMPLITUDE
2.5002
2.4998
VREF
1
2.4996
2.4994
2.4992
05854-020
05854-019
2.4990
2.4988
2.4986
0
50
100
150
200 250 300 350
SAMPLES × 6.5ns
400
450
5s/DIV
500
Figure 21. 0.1 Hz to 10 Hz Output Noise Plot
Figure 18. Digital Feedthrough
–20
1000
VDD = 5V
TA = 25°C
FULL SCALE LOADED
VREF = 2V ±300mV p-p
–30
VDD = VREF = 5V
TA = 25°C
MIDSCALE LOADED
900
800
–40
NOISE (nV/ Hz)
700
–60
–70
600
500
400
300
–80
–100
0
1
2
3
4
5
6
FREQUENCY (kHz)
7
8
9
05854-013
200
–90
05854-018
(dB)
–50
100
0
100
10
1k
10k
FREQUENCY (Hz)
100k
Figure 22. Noise Spectral Density
Figure 19. Total Harmonic Distortion
Rev. B | Page 9 of 20
1M
AD5680
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. Figure 5 shows a typical INL vs. code plot.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V, and VDD is varied by ±10%.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. Figure 6 shows a typical DNL vs. code
plot.
Output Voltage Settling Time
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change
and is measured from the 24th falling edge of SCLK.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x00000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5680 because the output of the DAC cannot go below
0 V. It is due to a combination of the offset errors in the DAC
and the output amplifier. Zero-code error is expressed in mV. A
plot of zero-code error vs. temperature can be seen in Figure 9.
Full-Scale Error
Full-scale error is a measurement of the output error when fullscale code (0x3FFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range.
Gain Error
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from ideal, expressed
as a percent of the full-scale range.
Zero-Code Error Drift
This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with a change
in temperature. It is expressed in (ppm of full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is injected into the analog
output when the input code in the DAC register changes state.
It is normally specified as the area of the glitch in nV-s, and is
measured when the digital input code is changed by 1 LSB at
the major carry transition (0x1FFFF to 0x20000). See Figure 17.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Total Harmonic Distortion (THD)
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC. The THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Noise Spectral Density
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(voltage per √Hz). It is measured by loading the DAC to
midscale and measuring noise at the output. It is measured in
nV/√Hz. Figure 22 shows a plot of noise spectral density.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal), expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5680 with
Code 2048 loaded in the DAC register. It can be negative or
positive.
Rev. B | Page 10 of 20
Data Sheet
AD5680
THEORY OF OPERATION
DAC SECTION
OUTPUT AMPLIFIER
The AD5680 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 23 shows a block diagram of the DAC
architecture.
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. This output
buffer amplifier has a gain of 2 derived from a 50 kΩ resistor
divider network in the feedback path. The output amplifier’s
inverting input is available to the user, allowing for remote
sensing. This VFB pin must be connected to VOUT for normal
operation. It can drive a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier can
be seen in Figure 10. The slew rate is 1.5 V/μs with a ¼ to ¾
full-scale settling time of 10 μs.
VDD
R
VFB
R
REF (+)
RESISTOR
STRING
VOUT
REF (–)
OUTPUT
AMPLIFIER
GND
05854-030
DAC REGISTER
Figure 23. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
D
VOUT VREF
262,144
where D is the decimal equivalent of the binary code that is
loaded to the DAC register. It can range from 0 to 262,143.
RESISTOR STRING
The resistor string section is shown in Figure 24. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
R
INTERPOLATOR ARCHITECTURE
The AD5680 contains a 16-bit DAC with an internal clock
generator and interpolator. The voltage levels generated by the
16-bit, 1 LSB step can be subdivided using the interpolator to
increase the resolution to 18 bits.
The 18-bit input code can be divided into two segments:
16-bit DAC code (DB19 to DB4) and 2-bit interpolator code
(DB3 and DB2). The input to the DAC is switched between a
16-bit code (for example, Code 1023) and a 16-bit code + 1 LSB
(for example, Code 1024). The 2-bit interpolator code determines the duty cycle of the switching and hence the 18-bit
code level. See Table 5 for an example.
Table 5.
18-Bit Code
DB19 to DB2
4092
4093
4094
4095
4096
16-Bit
DAC Code
DB19 to DB4
1023
1023
1023
1023
1024
2-Bit
Interpolator Code
DB3
DB2
0
0
0
1
1
0
1
1
0
0
Duty
Cycle
0
25%
50%
75%
0
R
R
TO OUTPUT
AMPLIFIER
The DAC output voltage is given by the average value of
the waveform switching between 16-bit code (C) and 16-bit
code + 1 (C + 1). The output voltage is a function of the duty
cycle of the switching.
FILTER
PLANT
18-BIT INPUT CODE
18
16 C + 1
DAC
MUX
16
+1
R
2
INTERPOLATOR
05854-031
R
VOUT
C+1
C
C+1
C
C+1
C
CLK
Figure 25. Interpolation Architecture
Figure 24. Resistor String
Rev. B | Page 11 of 20
75% DUTY CYCLE
50% DUTY CYCLE
25% DUTY CYCLE
05854-032
C
AD5680
Data Sheet
SERIAL INTERFACE
INPUT SHIFT REGISTER
The AD5680 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as with most DSPs. See Figure 2 for
a timing diagram of a typical write sequence.
The input shift register is 24 bits wide (see Figure 26). The first
two bits are don’t care bits. Bit DB21 and Bit DB20 are reserved
bits and should be set to 0. The next 18 bits are the data bits
followed by two don’t care bits. These are transferred to the
DAC register on the 24th falling edge of SCLK.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5680 compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change
in DAC register contents occurs. At this stage, the SYNC line
can be kept low or brought high. In either case, it must be
brought high for a minimum of 33 ns before the next write
sequence so that a falling edge of SYNC can initiate the next
write sequence. Because the SYNC buffer draws more current
when VIN = 2 V than it does when VIN = 0.8 V, SYNC should be
idled low between write sequences for even lower power
operation. As mentioned previously, it must, however, be
brought high again just before the next write sequence.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However, if SYNC is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as invalid.
Neither an update of the DAC register contents nor a change in
the operating mode occurs (see Figure 27).
POWER-ON RESET
The AD5680 family contains a power-on reset circuit that
controls the output voltage during power-up. The AD5680-1
DAC output powers up to 0 V, and the AD5680-2 DAC output
powers up to midscale. The output remains there until a valid
write sequence is made to the DAC. This is useful in applications
where it is important to know the output state of the DAC while
it is in the process of powering up.
DB23 (MSB)
0
0
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
05854-033
X
DATA BITS
RESERVED BITS
Figure 26. Input Register Contents
SCLK
SYNC
DIN
DB23
DB23
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24TH FALLING EDGE
DB0
VALID WRITE SEQUENCE:
OUTPUT UPDATES ON THE 24TH FALLING EDGE
Figure 27. SYNC Interrupt Facility
Rev. B | Page 12 of 20
05854-034
X
DB0 (LSB)
Data Sheet
AD5680
MICROPROCESSOR INTERFACING
AD5680 to 80C51/80L51 Interface
AD5680 to Blackfin® ADSP-BF53x Interface
Figure 30 shows a serial interface between the AD5680 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows. TxD of the 80C51/80L51 drives SCLK of the AD5680,
while RxD drives the serial data line of the part. The SYNC
signal is again derived from a bit-programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmitted
to the AD5680, P3.3 is taken low. The 80C51/80L51 transmits
data in 8-bit bytes only; thus, only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5680 must receive data with the MSB first. The 80C51/80L51
transmit routine should take this into account.
Figure 28 shows a serial interface between the AD5680 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5680, the
setup for the interface is as follows. DT0PRI drives the DIN pin
of the AD5680, while TSCLK0 drives the SCLK of the part. The
SYNC is driven from TFS0.
AD5680*
ADSP-BF53x*
SYNC
DIN
TSCLK0
SCLK
05854-035
TFS0
DTOPRI
AD5680*
80C51/80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5680 to 68HC11/68L11 Interface
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0 and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured this way, data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11/68L11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first. To
load data to the AD5680, PC7 is left low after the first eight bits
are transferred, and a second serial write operation is performed
to the DAC; PC7 is taken high at the end of this procedure.
SYNC
TxD
SCLK
RxD
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 30. AD5680 to 80C51/80L51 Interface
AD5680 to MICROWIRE Interface
Figure 31 shows an interface between the AD5680 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the AD5680
on the rising edge of the SK.
AD5680*
MICROWIRE*
CS
SYNC
SK
SCLK
SO
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5680*
PC7
SYNC
SCK
SCLK
MOSI
DIN
Figure 31. AD5680 to MICROWIRE Interface
05854-036
68HC11/68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 29. AD5680 to 68HC11/68L11 Interface
Rev. B | Page 13 of 20
05854-038
Figure 29 shows a serial interface between the AD5680 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5680, while the MOSI output drives
the serial data line of the DAC.
P3.3
05854-037
Figure 28. AD5680 to Blackfin ADSP-BF53x Interface
AD5680
Data Sheet
APPLICATIONS INFORMATION
CLOSED-LOOP APPLICATIONS
The AD5680 is suitable for closed-loop low bandwidth applications. Ideally, the system bandwidth acts as a filter on the DAC
output. (See the Filter section for details of the DAC output
prefiltering and postfiltering.) The DAC updates at the
interpolation frequency of 10 kHz.
Δ: 2.09ms
@: 1.28ms
2
1
PLANT
CONTROLLER
DAC
CODE 4092
05854-025
CODE 4094
CH1 20.0µV CH2 5V
05854-039
ADC
M 500µs
CH2
1.4V
Figure 34. DAC Output with 50 Hz Filter on Output
Figure 32. Typical Closed-Loop Application
FILTER
Δ: 2.09ms
@: 1.28ms
1
CODE 4092
CODE 4094
05854-026
The DAC output voltage for code transition 4092 to 4094 can be
seen in Figure 33. This is the DAC output unfiltered. Code 4092
does not have any interpolation but Code 4094 has interpolation
with a 50% duty cycle (see Table 5). Figure 34 shows the DAC
output with a 50 Hz passive RC filter and Figure 35 shows the
output with a 300 Hz passive RC filter. An RC combination of
320 kΩ and 10 nF has been used to achieve the 50 Hz cutoff
frequency, and an RC combination of 81 kΩ and 10 nF has
been used to achieve the 300 Hz cutoff frequency.
2
CH1 20.0µV CH2 5V
M 500µs
CH2
1.4V
Figure 35. DAC Output with 300 Hz Filter on Output
CODE 4092
05854-024
CODE 4094
1
CH1 20.0µV
M 500µs
CH4
0V
Figure 33. DAC Output Unfiltered
Rev. B | Page 14 of 20
Data Sheet
AD5680
CHOOSING A REFERENCE FOR THE AD5680
To achieve the optimum performance from the AD5680, choose
a precision voltage reference carefully. The AD5680 has only
one reference input, VREF. The voltage on the reference input is
used to supply the positive input to the DAC. Therefore, any
error in the reference is reflected in the DAC.
When choosing a voltage reference for high accuracy applications, the sources of error are initial accuracy, ppm drift, longterm drift, and output voltage noise. Initial accuracy on the
output voltage of the DAC leads to a full-scale error in the DAC.
To minimize these errors, a reference with high initial accuracy
is preferred. In addition, choosing a reference with an output
trim adjustment, such as the ADR425, allows a system designer
to trim out system errors by setting a reference voltage to a
voltage other than the nominal. The trim adjustment can also
be used at temperature to trim out any error.
Long-term drift is a measurement of how much the reference
drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable
during its entire lifetime.
The temperature coefficient of a reference’s output voltage
affects INL, DNL, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce temperature
dependence of the DAC output voltage in ambient conditions.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as is practical for the system noise resolution required.
Precision voltage references such as the ADR425 produce low
output noise in the 0.1 Hz to 10 Hz range. Examples of recommended precision references for use as supply to the AD5680
are shown in the Table 6.
Table 6. Partial List of Precision References for Use with the AD5680
Part No.
ADR425
ADR395
REF195
Initial Accuracy (mV max)
±2
±6
±2
Temperature Drift (ppm/°C max)
3
25
5
Rev. B | Page 15 of 20
0.1 Hz to 10 Hz Noise (µV p-p typ)
3.4
5
50
VOUT (V)
5
5
5
AD5680
Data Sheet
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD5680
5V
REGULATOR
10µF
POWER
SCLK
VIA
VOA
SCLK
VDD
AD5680
ADuM130x
SDI
VIB
VOB
SYNC
DATA
VIC
VOC
DIN
VOUT
GND
325 µA + (5 V/5 kΩ) = 1.33 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 2.7 ppm (13.5 µV) error for the 1.33 mA
current drawn from it. This corresponds to a 0.177 LSB error.
15V
REF195
5V
250µA
SYNC
SCLK
VDD VREF
AD5680
VOUT = 0V TO 5V
DIN
05854-040
3-WIRE
SERIAL
INTERFACE
Figure 36. REF195 as Power Supply to the AD5680
USING THE AD5680 WITH A GALVANICALLY
ISOLATED INTERFACE
In process-control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous commonmode voltages that might occur in the area where the DAC is
functioning. Isocouplers provide isolation in excess of 3 kV. The
AD5680 uses a 3-wire serial logic interface, so the ADuM130x
3-channel digital isolator provides the required isolation (see
Figure 37). The power supply to the part also needs to be isolated,
which is done by using a transformer. On the DAC side of the
transformer, a 5 V regulator provides the 5 V supply required
for the AD5680.
05854-041
Because the supply current required by the AD5680 is extremely
low, an alternative option is to use a voltage reference to supply
the required voltage to the part (see Figure 36). This is especially
useful if the power supply is quite noisy, or if the system supply
voltages are at some value other than 5 V, for example, 15 V.
The voltage reference outputs a steady supply voltage for the
AD5680; see Table 6 for a suitable reference. If the low dropout
REF195 is used, it must supply 325 µA of current to the AD5680,
with no load on the output of the DAC. When the DAC output
is loaded, the REF195 also needs to supply the current to the
load. The total current required (with a 5 kΩ load on the DAC
output) is
0.1µF
Figure 37. AD5680 with a Galvanically Isolated Interface
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5680 should have
separate analog and digital sections, each having its own area of
the board. If the AD5680 is in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5680.
The power supply to the AD5680 should be bypassed with 10 µF
and 0.1 µF capacitors. The capacitors should be located as close
as possible to the device, with the 0.1 µF capacitor ideally right
up against the device. The 10 µF capacitors should be the tantalum bead type. It is important that the 0.1 µF capacitor has low
effective series resistance (ESR) and effective series inductance
(ESI), for example, common ceramic types of capacitors. This
0.1 µF capacitor provides a low impedance path to ground for
high frequencies caused by transient currents due to internal
logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching digital
signals should be shielded from other parts of the board by
digital ground. Avoid crossover of digital and analog signals if
possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects on the board. The best board layout technique is the microstrip technique where the component side of
the board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a 2-layer board.
Rev. B | Page 16 of 20
Data Sheet
AD5680
OUTLINE DIMENSIONS
3.00
2.90
2.80
1.70
1.60
1.50
8
7
6
5
1
2
3
4
3.00
2.80
2.60
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.22 MAX
0.08 MIN
8°
4°
0°
SEATING
PLANE
0.38 MAX
0.22 MIN
0.60
0.45
0.30
0.60
BSC
12-16-2008-A
1.30
1.15
0.90
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 38. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
3.10
3.00 SQ
2.90
1.95 REF
0.65 BSC
8
5
PIN 1 INDEX
AREA
0.50
0.40
0.30
PIN 1 CORNER
C 0.130× 45°
BOTTOM VIEW
0.80
0.75
0.70
0.05 MAX
0.00 MIN
COPLANARITY
0.08
0.203 REF
0.35
0.30
0.25
02-23-2011-A
SEATING
PLANE
1
4
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-229-WEEC-2
Figure 39. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5680BRJZ-1500RL7
AD5680BRJZ-1REEL7
AD5680BRJZ-2500RL7
AD5680BRJZ-2REEL7
AD5680BCPZ-1500RL7
AD5680BCPZ-1RL7
AD5680BCPZ-2500RL7
AD5680BCPZ-2RL7
1
Power-On
Reset to Code
Zero
Zero
Midscale
Midscale
Zero
Zero
Midscale
Midscale
Accuracy
±64 LSB INL
±64 LSB INL
±64 LSB INL
±64 LSB INL
±64 LSB INL
±64 LSB INL
±64 LSB INL
±64 LSB INL
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Z = RoHS Compliant Part.
Rev. B | Page 17 of 20
Package
Description
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
Package
Option
RJ-8
RJ-8
RJ-8
RJ-8
CP-8-15
CP-8-15
CP-8-15
CP-8-15
Branding
D3C
D3C
D3D
D3D
DLN
DLN
DLP
DLP
AD5680
Data Sheet
NOTES
Rev. B | Page 18 of 20
Data Sheet
AD5680
NOTES
Rev. B | Page 19 of 20
AD5680
Data Sheet
NOTES
©2006–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05854-0-2/14(B)
Rev. B | Page 20 of 20
工商网监
湘ICP备2023018690号
