AD5754AREZ

Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs AD5724/AD5734/AD5754 Data Sheet FEATURES GENERAL DESCRIPTION Complete, quad, 12-/14-/16-bit digital-to-analog converter (DAC) Operates from single/dual supplies Software programmable output range +5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum Total unadjusted error (TUE): 0.1% FSR maximum Settling time: 10 µs typical Integrated reference buffers Output control during power-up/brownout Simultaneous updating via LDAC Asynchronous CLR to zero scale or midscale DSP-/microcontroller-compatible serial interface 24-lead TSSOP Operating temperature range: −40°C to +85°C iCMOS process technology1 The AD5724/AD5734/AD5754 are quad, 12-/14-/16-bit, serial input, voltage output DACs. The devices operate from singlesupply voltages from +4.5 V up to +16.5 V or dual-supply voltages from ±4.5 V up to ±16.5 V. Nominal full-scale output range is software-selectable from +5 V, +10 V, +10.8 V, ±5 V, ±10 V, or ±10.8 V. Integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry are also provided. The devices offer guaranteed monotonicity, integral nonlinearity (INL) of ±16 LSB maximum, low noise, and 10 µs maximum settling time. The AD5724/AD5734/AD5754 use a serial interface that operates at clock rates up to 30 MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is user-selectable twos complement or offset binary for a bipolar output (depending on the state of Pin BIN/2sComp), and straight binary for a unipolar output. The asynchronous clear function clears all DAC registers to a user-selectable zero-scale or midscale output. The devices are available in a 24-lead TSSOP and offer guaranteed specifications over the −40°C to +85°C industrial temperature range. APPLICATIONS Industrial automation Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers FUNCTIONAL BLOCK DIAGRAM DVCC AVDD AD5724/AD5734/AD5754 n SDIN SCLK SYNC REFIN INPUT SHIFT REGISTER AND CONTROL LOGIC REFERENCE BUFFERS INPUT REGISTER A DAC REGISTER A INPUT REGISTER B DAC REGISTER B INPUT REGISTER C DAC REGISTER C INPUT REGISTER D DAC REGISTER D n DAC A VOUTA DAC B VOUTB DAC C VOUTC DAC D VOUTD n SDO CLR BIN/2sCOMP AD5724: n = 12-BIT AD5734: n = 14-BIT AD5754: n = 16-BIT GND LDAC n n DAC_GND (2) SIG_GND (2) 06468-001 AVSS Figure 1. 1 For analog systems designers within industrial/instrumentation equipment OEMs that need high performance ICs at higher-voltage levels, iCMOS® is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, as well as increased ac and dc performance. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5724/AD5734/AD5754 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Transfer Function ....................................................................... 20 Applications ....................................................................................... 1 Input Shift Register .................................................................... 24 General Description ......................................................................... 1 DAC Register .............................................................................. 24 Functional Block Diagram .............................................................. 1 Output Range Select Register ................................................... 25 Revision History ............................................................................... 2 Control Register ......................................................................... 25 Specifications..................................................................................... 3 Power Control Register.............................................................. 26 AC Performance Characteristics ................................................ 5 Features ............................................................................................ 27 Timing Characteristics ................................................................ 5 Analog Output Control ............................................................. 27 Timing Diagrams.......................................................................... 6 Power-Down Mode .................................................................... 27 Absolute Maximum Ratings ............................................................ 8 Overcurrent Protection ............................................................. 27 ESD Caution .................................................................................. 8 Thermal Shutdown .................................................................... 27 Pin Configuration and Function Descriptions ............................. 9 Applications Information .............................................................. 28 Typical Performance Characteristics ........................................... 10 +5 V/±5 V Operation ................................................................ 28 Terminology .................................................................................... 16 Alternative Power-Up Sequence Support ............................... 28 Theory of Operation ...................................................................... 18 Layout Guidelines....................................................................... 28 Architecture ................................................................................. 18 Galvanically Isolated Interface ................................................. 29 Power-Up Sequence ................................................................... 18 Voltage Reference Selection ...................................................... 29 Serial Interface ............................................................................ 18 Microprocessor Interfacing ....................................................... 29 Load DAC (LDAC)..................................................................... 20 Outline Dimensions ....................................................................... 31 Asynchronous Clear (CLR) ....................................................... 20 Ordering Guide .......................................................................... 31 Configuring the AD5724/AD5734/AD5754 .......................... 20 REVISION HISTORY 2/2017—Rev. E to Rev. F Added Power-Up Sequence Section ............................................. 18 Changes to Table 7 and Table 8 ..................................................... 21 Changes to Table 10 and Table 11 ................................................ 22 Changes to Table 13 and Table 14 ................................................ 23 Changes to Analog Output Control Section ............................... 27 Added Alternative Power-Up Sequence Support Section, Figure 43, and Figure 44; Renumbered Sequentially ................. 28 2/2016—Rev. D to Rev. E Changes to Table 1...................................................................................... 3 Change to Table 5 ......................................................................................... 9 7/2011—Rev. C to Rev. D Changes to Table 3: t7, t8, t10 Limits ....................................................... 5 3/2011—Rev. B to Rev. C Changes to Configuring the AD5724/AD5734/AD5754 Section .............................................................................................. 20 8/2010—Rev. A to Rev. B Changes to Table 27 ....................................................................... 26 4/2010—Rev. 0 to Rev. A Changes to Junction Temperature, TJ max Parameter, Table 4 ...8 Changes to Exposed Pad Description, Table 5 ..............................9 Added Exposed Paddle Notation to Outline Dimensions ........ 30 8/2008—Revision 0: Initial Version Rev. F | Page 2 of 31 Data Sheet AD5724/AD5734/AD5754 SPECIFICATIONS AVDD = 4.5 V 1 to 16.5 V; AVSS = −4.5 V1 to −16.5 V, or 0 V; GND = 0 V; REFIN= 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD = 200 pF; all specifications TMIN to TMAX. Table 1. Parameter ACCURACY Resolution AD5754 AD5734 AD5724 Total Unadjusted Error (TUE) A Version B Version Relative Accuracy (INL) 2 AD5754 AD5734 AD5724 Differential Nonlinearity (DNL) Bipolar Zero Error Min Typ Max 16 14 12 Unit Test Conditions/Comments Outputs unloaded Bits Bits Bits −0.3 −0.1 +0.3 +0.1 % FSR % FSR ±10 V range ±10 V range −16 −4 −1 −1 −6 +16 +4 +1 +1 +6 LSB LSB LSB LSB mV ±10 V range, TA = 25°C, error at other temp- +6 ppm FSR/°C mV +6 ppm FSR/°C mV All models, all versions, guaranteed monotonic eratures obtained using bipolar zero error TC Bipolar Zero Error TC 3 Zero-Scale Error ±4 −6 ±10 V range, TA = 25°C, error at other temp- eratures obtained using zero-scale error TC Zero-Scale Error TC3 Offset Error −6 Offset Error TC3 Gain Error −0.025 +0.025 ppm FSR/°C % FSR Gain Error3 −0.065 0 % FSR Gain Error3 0 +0.08 % FSR 120 ppm FSR/°C µV ±1% for specified performance +2 3 V MΩ µA V V V V ppm FSR/°C mA kΩ pF Ω AVDD/AVSS = ±11.7 V min, REFIN = +2.5 V AVDD/AVSS = ±12.9 V min, REFIN = +3 V Gain Error TC3 DC Crosstalk3 REFERENCE INPUT3 Reference Input Voltage DC Input Impedance Input Current Reference Range OUTPUT CHARACTERISTICS3 Output Voltage Range Headroom Required Output Voltage TC Short-Circuit Current Load Capacitive Load Stability DC Output Impedance ±4 ±4 ±8 1 −2 2 2.5 5 ±0.5 −10.8 −12 0.5 ±4 20 +10.8 +12 0.9 2 4000 0.5 Rev. F | Page 3 of 31 +10 V range, TA = 25°C, error at other temperatures obtained using offset error TC ±10 V range, TA = 25°C, error at other temperatures obtained using gain error TC +10 V and +5 V ranges, TA = 25°C, error at other temperatures obtained using gain error TC ±5 V range, TA = 25°C, error at other temperatures obtained using gain error TC For specified performance AD5724/AD5734/AD5754 Parameter DIGITAL INPUTS3 Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance DIGITAL OUTPUTS (SDO)3 Output Low Voltage, VOL Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS AVDD AVSS DVCC Power Supply Sensitivity3 ∆VOUT/∆ΑVDD AIDD AISS DICC Power Dissipation Power-Down Currents AIDD AISS DICC Data Sheet Min Typ Max Unit 0.8 ±1 V V µA pF 2 5 0.4 DVCC − 1 0.4 DVCC − 0.5 −1 +1 5 4.5 −4.5 2.7 16.5 −16.5 5.5 −65 0.5 310 115 40 40 300 2.5 1.75 2.2 3 V V V V µA pF Test Conditions/Comments DVCC = 2.7 V to 5.5 V, JEDEC compliant Per pin Per pin DVCC = 5 V ± 10%, sinking 200 µA DVCC = 5 V ± 10%, sourcing 200 µA DVCC = 2.7 V to 3.6 V, sinking 200 µA DVCC = 2.7 V to 3.6 V, sourcing 200 µA V V V dB mA/channel mA/channel mA/channel µA mW mW Outputs unloaded AVSS = 0 V, outputs unloaded Outputs unloaded VIH = DVCC, VIL = GND ±16.5 V operation, outputs unloaded 16.5 V operation, AVSS = 0 V, outputs unloaded µA µA nA For specified performance, maximum headroom requirement is 0.9 V. INL is measured from Code 512, Code 128, and Code 32 for the AD5754, the AD5734, and the AD5724, respectively. 3 Guaranteed by characterization; not production tested. 1 2 Rev. F | Page 4 of 31 Data Sheet AD5724/AD5734/AD5754 AC PERFORMANCE CHARACTERISTICS AVDD = 4.5 V 1 to 16.5 V; AVSS = −4.5 V1 to −16.5 V, or 0 V; GND = 0 V; REFIN= 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD = 200 pF; all specifications TMIN to TMAX. Table 2. Parameter 2 DYNAMIC PERFORMANCE Output Voltage Settling Time Min 2 Unit Test Conditions/Comments 20 V step to ±0.03% FSR 10 V step to ±0.03% FSR 512 LSB step settling (16-bit resolution) 3.5 13 35 10 10 0.6 µs µs µs V/µs nV-sec mV nV-sec nV-sec nV-sec 15 80 320 µV p-p µV rms nV/√Hz 0x8000 DAC code 10 7.5 Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Digital Crosstalk DAC to DAC Crosstalk Digital Feedthrough Output Noise 0.1 Hz to 10 Hz Bandwidth 100 kHz Bandwidth Output Noise Spectral Density 1 A, B Version Typ Max 12 8.5 5 Measured at 10 kHz, 0x8000 DAC code For specified performance, maximum headroom requirement is 0.9 V. Guaranteed by design and characterization. Not production tested. TIMING CHARACTERISTICS AVDD = 4.5 V to 16.5 V; AVSS = −4.5 V to −16.5 V, or 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 4 t164 t17 Limit at tMIN, tMAX 33 13 13 13 13 100 7 2 20 130 20 10 20 2.5 13 40 200 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min µs typ ns min µs max ns min ns max ns min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time SCLK falling edge to SYNC rising edge Minimum SYNC high time (write mode) Data setup time Data hold time LDAC falling edge to SYNC falling edge SYNC rising edge to LDAC falling edge LDAC pulse width low DAC output settling time CLR pulse width low CLR pulse activation time SYNC rising edge to SCLK rising edge SCLK rising edge to SDO valid (CL SDO 5 = 15 pF) Minimum SYNC high time (readback/daisy-chain mode) Guaranteed by characterization; not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 Daisy-chain and readback mode. 5 CL SDO = capacitive load on SDO output. 1 2 Rev. F | Page 5 of 31 AD5724/AD5734/AD5754 Data Sheet TIMING DIAGRAMS t1 SCLK 1 2 24 t2 t3 t6 t5 t4 SYNC t8 t7 SDIN DB23 DB0 t9 t11 t10 LDAC t12 VOUTx t12 VOUTx t13 CLR t14 06468-002 VOUTx Figure 2. Serial Interface Timing Diagram t1 SCLK 24 t3 t17 48 t2 t5 t15 t4 SYNC t7 SDIN t8 D32B D0B INPUT WORD FOR DAC N D32B D0B t16 INPUT WORD FOR DAC N – 1 DB23 SDO UNDEFINED DB0 INPUT WORD FOR DAC N t11 06468-003 LDAC t10 Figure 3. Daisy-Chain Timing Diagram Rev. F | Page 6 of 31 Data Sheet SCLK AD5724/AD5734/AD5754 1 24 1 24 t17 SYNC DB23 DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ SDO DB23 DB0 NOP CONDITION DB0 DB23 UNDEFINED DB0 SELECTED REGISTER DATA CLOCKED OUT Figure 4. Readback Timing Diagram Rev. F | Page 7 of 31 06468-004 SDIN AD5724/AD5734/AD5754 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter AVDD to GND AVSS to GND DVCC to GND Digital Inputs to GND Digital Outputs to GND REFIN to GND VOUTA, VOUTB, VOUTC, VOUTD to GND DAC_GND to GND SIG_GND to GND Operating Temperature Range, TA Industrial Storage Temperature Range Junction Temperature, TJ max 24-Lead TSSOP Package θJA Thermal Impedance θJC Thermal Impedance Power Dissipation Lead Temperature Soldering ESD (Human Body Model) Rating −0.3 V to +17 V +0.3 V to −17 V −0.3 V to +7 V −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to +5 V AVSS to AVDD −0.3 V to +0.3 V −0.3 V to +0.3 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 42°C/W 9°C/W (TJ max − TA)/ θJA JEDEC industry standard J-STD-020 3.5 kV Rev. F | Page 8 of 31 Data Sheet AD5724/AD5734/AD5754 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 AVDD AVSS 1 NC 2 VOUTA 3 VOUTB 4 BIN/2sCOMP 5 NC 6 SYNC 7 18 DAC_GND SCLK 8 17 REFIN SDIN 9 16 SDO LDAC 10 15 GND NC 12 22 VOUTD 21 SIG_GND 20 SIG_GND TOP VIEW (Not to Scale) 19 DAC_GND 14 DVCC 13 NC NOTES 1. NC = NO CONNECT. 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. 06468-005 CLR 11 23 VOUTC AD5724/ AD5734/ AD5754 Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic AVSS 2, 6, 12, 13 3 4 5 NC VOUTA VOUTB BIN/2sCOMP 7 SYNC 8 SCLK 9 10 SDIN LDAC 11 14 15 16 CLR DVCC GND SDO 17 18, 19 20, 21 22 23 24 Exposed Paddle REFIN DAC_GND SIG_GND VOUTD VOUTC AVDD AVSS Description Negative Analog Supply. Voltage ranges from −4.5 V to −16.5 V. This pin can connect to 0 V if output ranges are unipolar. No connect. Do not connect to these pins. Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. Determines the DAC coding for a bipolar output range. This pin must be hardwired to either DVCC or GND. When hardwired to DVCC, input coding is offset binary. When hardwired to GND, input coding is twos complement. (For unipolar output ranges, coding is always straight binary). Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC. Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Load DAC, Logic Input. This is used to update the DAC registers and consequently, the analog outputs. When this pin is tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected. Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user-selectable). Digital Supply. Voltage ranges from 2.7 V to 5.5 V. Ground Reference. Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. External Reference Voltage Input. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance. Ground Reference for the Four Digital-to-Analog Converters. Ground Reference for the Four Output Amplifiers. Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V. This exposed paddle can be connected to the potential of the AVSS pin, or alternatively, it can be left electrically unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. F | Page 9 of 31 AD5724/AD5734/AD5754 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.6 6 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS 4 = +12V/0V, RANGE = +10V = ±12V, RANGE = ±10V = ±6.5V, RANGE = ±5V = +6.5V/0V, RANGE = +5V 0.4 0 –2 0 –0.2 –4 –0.4 –6 –0.6 –8 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS –0.8 0 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS 1.0 40000 50,000 60,000 0.15 = +12V/0V, RANGE = +10V = ±12V, RANGE = ±10V = ±6.5V, RANGE = ±5V = +6.5V/0V, RANGE = +5V 0.10 0 –0.5 0 –0.05 –1.0 –0.10 –1.5 –0.15 –2.0 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 CODE AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS –0.20 0 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS 0.2 +12V/0V, RANGE = +10V ±12V, RANGE = ±10V ±6.5V, RANGE = ±5V +6.5V/0V, RANGE = +5V 4000 6000 8000 10000 12000 14000 16000 CODE Figure 7. AD5734 INL Error vs. Code 0.3 2000 = = = = 06468-017 DNL ERROR (LSB) 0.05 06468-014 Figure 10. AD5734 DNL Error vs. Code 0.04 = +12V/0V, RANGE = +10V = ±12V, RANGE = ±10V = ±6.5V, RANGE = ±5V = +6.5V/0V, RANGE = +5V AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS 0.03 = +12V/0V, RANGE = +10V = ±12V, RANGE = ±10V = ±6.5V, RANGE = ±5V = +6.5V/0V, RANGE = +5V 0.02 DNL ERROR (LSB) 0.1 0 –0.1 –0.2 0.01 0 –0.01 –0.02 –0.3 –0.03 –0.4 0 500 1000 1500 2000 2500 3000 CODE 3500 4000 06468-015 –0.04 –0.5 Figure 8. AD5724 INL Error vs. Code –0.05 0 500 1000 1500 2000 2500 3000 CODE Figure 11. AD5724 DNL Error vs. Code Rev. F | Page 10 of 31 3500 4000 06468-018 INL ERROR (LSB) 30,000 Figure 9. AD5754 DNL Error vs. Code 0.5 INL ERROR (LSB) 20,000 CODE Figure 6. AD5754 INL Error vs. Code 1.5 10,000 = +12V/0V, RANGE = +10V = ±12V, RANGE = ±10V = ±6.5V, RANGE = ±5V = +6.5V/0V, RANGE = +5V 06468-016 DNL ERROR (LSB) 0.2 06468-013 INL ERROR (LSB) 2 Data Sheet AD5724/AD5734/AD5754 8 10 8 6 6 4 MAX INL ±10V MAX INL ±5V MIN INL ±10V MIN INL ±5V MAX INL +10V MIN INL +10V MAX INL +5V MIN INL +5V 2 0 –2 INL ERROR (LSB) INL ERROR (LSB) 4 2 BIPOLAR 5V MIN UNIPOLAR 5V MIN BIPOLAR 5V MAX UNIPOLAR 5V MAX 0 –2 –4 –4 –6 –6 –20 0 20 40 60 80 TEMPERATURE (°C) 06468-044 –8 –40 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 SUPPLY VOLTAGE (V) Figure 12. AD5754 INL Error vs. Temperature Figure 15. AD5754 INL Error vs. Supply Voltage 0.1 1.0 BIPOLAR 10V MIN UNIPOLAR 10V MIN BIPOLAR 10V MAX UNIPOLAR 10V MAX 0.8 0 0.6 MAX DNL ±10V MAX DNL ±5V MIN DNL ±10V MIN DNL ±5V MAX DNL +10V MIN DNL +10V MAX DNL +5V MIN DNL +5V –0.2 –0.3 DNL ERROR (LSB) DNL ERROR (LSB) –0.1 06468-035 –8 –10 5.5 –0.4 0.4 0.2 0 –0.2 –0.4 –0.6 –0.5 20 40 60 80 TEMPERATURE (°C) –1.0 11.5 0.8 6 0.6 4 0.4 DNL ERROR (LSB) 8 2 BIPOLAR 10V MIN UNIPOLAR 10V MIN BIPOLAR 10V MAX UNIPOLAR 10V MAX –4 13.5 14.0 14.5 15.0 15.5 15.0 15.5 16.0 16.5 16.0 SUPPLY (V) 16.5 BIPOLAR 5V MIN UNIPOLAR 5V MIN BIPOLAR 5V MAX UNIPOLAR 5V MAX –0.4 –0.8 13.0 14.5 –0.2 –0.6 12.5 14.0 0 –8 12.0 13.5 0.2 –6 –10 11.5 13.0 Figure 16. AD5754 DNL Error vs. Supply Voltage 1.0 06468-034 INL ERROR (LSB) Figure 13. AD5754 DNL Error vs. Temperature –2 12.5 SUPPLY VOLTAGE (V) 10 0 12.0 –1.0 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 SUPPLY VOLTAGE (V) Figure 17. AD5754 DNL Error vs. Supply Voltage Figure 14. AD5754 INL Error vs. Supply Voltage Rev. F | Page 11 of 31 06468-033 0 06468-045 –20 06468-032 –0.8 –0.6 –40 AD5724/AD5734/AD5754 Data Sheet 0.02 10 0.01 9 BIPOLAR 10V MIN UNIPOLAR 10V MIN BIPOLAR 10V MAX UNIPOLAR 10V MAX 8 AIDD (mA) –0.01 –0.02 6 –0.03 5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 SUPPLY VOLTAGE (V) 06468-036 –0.04 11.5 7 4 4.5 6.5 8.5 10.5 12.5 14.5 06468-042 TUE (%) 0 16.5 AVDD (V) Figure 18. AD5754 TUE vs. Supply Voltage Figure 21. Supply Current vs. Supply Voltage (Single Supply) 0.04 4 0.03 +10V 3 TUE (%) 0.01 ZERO-SCALE ERROR (mV) 0.02 BIPOLAR 5V MIN UNIPOLAR 5V MIN BIPOLAR 5V MAX UNIPOLAR 5V MAX 0 –0.01 –0.02 –0.03 –0.04 2 1 ±10V 0 –1 –2 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 SUPPLY VOLTAGE (V) –3 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 19. AD5754 TUE vs. Supply Voltage 06468-046 6.5 06468-037 ±5V –0.05 5.5 Figure 22. Zero-Scale Error vs. Temperature 8 0.8 6 0.6 IDD (mA) BIPOLAR ZERO ERROR (mV) 2 0 –2 ISS (mA) –4 –6 ±5V RANGE 0.2 0 ±10V RANGE –0.2 –0.4 –0.6 6.5 8.5 10.5 12.5 14.5 16.5 AVDD/AVSS (V) Figure 20. Supply Current vs. Supply Voltage (Dual Supply) –1.0 –40 –20 0 20 40 60 TEMPERATURE (°C) Figure 23. Bipolar Zero Error vs. Temperature Rev. F | Page 12 of 31 80 06468-047 –8 4.5 0.4 –0.8 06468-038 AIDD/AISS (mA) 4 Data Sheet AD5724/AD5734/AD5754 0.06 15 ±5V 10 OUTPUT VOLTAGE (V) GAIN ERROR (% FSR) 0.04 0.02 0 ±10V –0.02 5 0 –5 +10V –0.04 –10 40 60 80 –15 TEMPERATURE (°C) –3 –1 1 3 5 7 9 11 06468-022 20 11 06468-023 0 11 06468-024 –20 06468-048 –0.06 –40 TIME (µs) Figure 24. Gain Error vs. Temperature Figure 27. Full-Scale Settling Time, ±10 V Range 7 1000 900 5 800 OUTPUT VOLTAGE (V) 700 DICC (µA) 600 500 400 DVCC = 5V 300 3 1 –1 –3 200 100 –5 DVCC = 3V 0 –7 0 1 2 3 4 5 6 VLOGIC (V) –3 06468-043 –100 –1 1 3 5 7 9 TIME (µs) Figure 28. Full-Scale Settling Time, ±5 V Range Figure 25. Digital Current vs. Logic Input Voltage 12 10 0 –0.005 –0.010 8 6 4 2 –0.015 0 –0.020 –25 –3 –20 –15 –10 –5 0 5 10 15 OUTPUT CURRENT (mA) 20 25 06468-040 OUTPUT VOLTAGE DELTA (V) 0.005 ±5V RANGE, CODE = 0xFFFF ±10V RANGE, CODE = 0xFFFF +10V RANGE, CODE = 0xFFFF +5V RANGE, CODE = 0xFFFF ±5V RANGE, CODE = 0x0000 ±10V RANGE, CODE = 0x0000 OUTPUT VOLTAGE (V) 0.010 Figure 26. Output Source and Sink Capability Rev. F | Page 13 of 31 –1 1 3 5 7 9 TIME (µs) Figure 29. Full-Scale Settling Time, 10 V Range AD5724/AD5734/AD5754 Data Sheet 6 OUTPUT VOLTAGE (V) 5 4 1 3 2 RANGE = ±5V RANGE = +5V –3 –1 1 3 5 7 9 06468-025 0 11 TIME (µs) CH1 5µV M5s LINE 0.10 0.020 ± ±10V RANGE, 0x7FFF TO 0x8000 ±10V RANGE, 0x8000 TO 0x7FFF ±5V RANGE, 0x7FFF± TO 0x8000 ±5V RANGE, 0x8000 TO 0x7FFF +10V RANGE, 0x7FFF TO 0x8000 +10V RANGE, 0x8000 TO 0x7FFF +5V RANGE, 0x7FFF TO 0x8000 +5V RANGE, 0x8000 TO 0x7FFF 0.010 AVDD/AVSS = ±16.5V AVDD = +16.5V, AVSS = 0V 0.08 0.06 OUTPUT VOLTAGE (V) 0.015 73.8V Figure 33. Peak-to-Peak Noise, 100 kHz Bandwidth Figure 30. Full-Scale Settling Time, +5 V Range 0.005 0 –0.005 0.04 0.02 0 –0.02 –0.010 1 2 3 4 5 TIME (µs) –0.06 –50 –30 –10 10 30 50 70 90 06468-041 0 06468-039 –0.015 –1 6000 06468-019 –0.04 TIME (µs) Figure 34. Output Glitch on Power-Up Figure 31. Digital-to-Analog Glitch Energy 15 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS 10 5 = +12V/0V, RANGE = +10V = ±12V, RANGE = ±10V = ±6.5V, RANGE = ±5V = +6.5V/0V, RANGE = +5V TUE (LSB) 0 1 –5 –10 –15 –20 –25 RANGE = ±5V RANGE = +5V CH1 5µV RANGE = +10V RANGE = ±10V M 5s LINE 73.8V –30 06468-026 OUTPUT VOLTAGE (V) RANGE = +10V RANGE = ±10V 06468-027 1 –35 0 1000 2000 3000 4000 5000 CODE Figure 35. AD5754 TUE vs. Code Figure 32. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth Rev. F | Page 14 of 31 Data Sheet 4 AD5724/AD5734/AD5754 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS 2 1.0 = +12V/0V, RANGE = +10V = ±12V, RANGE = ±10V = ±6.5V, RANGE = ±5V = +6.5V/0V, RANGE = +5V 0.5 0 = +12V/0V, RANGE = +10V = ±12V, RANGE = ±10V = ±6.5V, RANGE = ±5V = +6.5V/0V, RANGE = +5V –2 –4 –0.5 –1.0 –6 –1.5 –8 –2.0 –10 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 CODE –2.5 0 500 1000 1500 2000 2500 3000 CODE Figure 37. AD5724 TUE vs. Code Figure 36. AD5734 TUE vs. Code Rev. F | Page 15 of 31 3500 4000 06468-021 TUE (LSB) 0 06468-020 TUE (LSB) AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS AD5724/AD5734/AD5754 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5724/AD5734/ AD5754 are monotonic over the full operating temperature range of the devices. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Figure 23. Bipolar Zero Temperature Coefficient (TC) Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Zero-Scale Error or Negative Full-Scale Error Zero-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage must be negative full-scale −1 LSB. A plot of zero-scale error vs. temperature can be seen in Figure 22. Zero-Scale TC Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale TC is expressed in ppm FSR/°C. Output Voltage Settling Time Output voltage settling time is the amount of time required for the output to settle to a specified level for a full-scale input change. A plot for full-scale settling time can be seen in Figure 27. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage output DAC is usually limited by the slew rate of the amplifier used at the output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal and is expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure 24. Gain TC Gain TC is a measure of the change in gain error with changes in temperature. Gain TC is expressed in ppm FSR/°C. Total Unadjusted Error (TUE) Total unadjusted error is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31. Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. It is measured by superimposing a 50 Hz/60 Hz, 200 mV p-p sine wave on the supply voltages and measuring the proportion of the sine wave that transfers to the outputs. Rev. F | Page 16 of 31 Data Sheet AD5724/AD5734/AD5754 DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in LSBs. Digital Crosstalk Digital crosstalk is a measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and a subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec. Rev. F | Page 17 of 31 AD5724/AD5734/AD5754 Data Sheet THEORY OF OPERATION The AD5724/AD5734/AD5754 are quad, 12-/14-/16-bit, serial input, unipolar/bipolar, voltage output DACs. They operate from unipolar supply voltages of +4.5 V to +16.5 V or bipolar supply voltages of ±4.5 V to ±16.5 V. In addition, the devices have software-selectable output ranges of +5 V, +10 V, +10.8 V, ±5 V, ±10 V, and ±10.8 V. Data is written to the AD5724/AD5734/ AD5754 in a 24-bit word format via a 3-wire serial interface. The devices also offer an SDO pin to facilitate daisy-chaining or readback. The resistor string structure is shown in Figure 39. It is a string of resistors, each of value R. The code loaded to the DAC register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Output Amplifiers The AD5724/AD5734/AD5754 incorporate a power-on reset circuit to ensure that the DAC registers power up loaded with 0x0000. When powered on, the outputs are clamped to 0 V via a low impedance path. The output amplifiers are capable of generating both unipolar and bipolar output voltages. They are capable of driving a load of 2 kΩ in parallel with 4000 pF to GND. The source and sink capabilities of the output amplifiers can be seen in Figure 26. The slew rate is 3.5 V/µs with a full-scale settling time of 10 µs. ARCHITECTURE Reference Buffers The DAC architecture consists of a string DAC followed by an output amplifier. Figure 38 shows a block diagram of the DAC architecture. The reference input is buffered before being applied to the DAC. The AD5724/AD5734/AD5754 require an external reference source. The reference input has an input range of 2 V to 3 V, with 2.5 V for specified performance. This input voltage is then buffered before it is applied to the DAC cores. REFIN POWER-UP SEQUENCE REF (+) RESISTOR STRING VOUTx CONFIGURABLE OUTPUT AMPLIFIER REF (–) GND OUTPUT RANGE CONTROL Figure 38. DAC Architecture Block Diagram REFIN 06468-006 DAC REGISTER Because the DAC output voltage is controlled by the voltage monitor and control block (see Figure 42), it is important to power the DVCC pin before applying any voltage to the AVDD and AVSS pins; otherwise, the G1 and G2 transmission gates are at an undefined state. The ideal power-up sequence is in the following order: GND, SIG_GND, DAC_GND, DVCC, AVDD, AVSS, and then the digital inputs. The relative order of powering AVDD and AVSS is not important, provided that they are powered up after DVCC. SERIAL INTERFACE The AD5724/AD5734/AD5754 are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards. R R TO OUTPUT AMPLIFIER R Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits, and 16 data bits. The timing diagram for this operation is shown in Figure 2. R 06468-007 R Figure 39. Resistor String Structure Rev. F | Page 18 of 31 Data Sheet AD5724/AD5734/AD5754 Standalone Operation Daisy-Chain Operation The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought high again. If SYNC is brought high before the 24th falling SCLK edge, the data written is invalid. If more than 24 falling SCLK edges are applied before SYNC is brought high, the input data is also invalid. The input register addressed is updated on the rising edge of SYNC. For another serial transfer to take place, SYNC must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. Daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the write cycle. SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of AD5724/AD5734/AD5754 devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. When the data has been transferred into the chosen register of the addressed DAC, all DAC registers and outputs can be updated by taking LDAC low while SYNC is high. AD5724/ AD5734/ AD5754* 68HC11* MOSI SDIN SCK SCLK PC7 SYNC PC6 LDAC Readback Operation Readback mode is invoked by setting the R/W bit = 1 in the serial input shift register write. (If the SDO output is disabled via the SDO disable bit in the control register, it is automatically enabled for the duration of the read operation, after which it is disabled again). With R/W = 1, Bit A2 to Bit A0 in association with Bit REG2 to Bit REG0, select the register to be read. The remaining data bits in the write sequence are don’t care bits. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. For a read of a single register, the NOP command can clock out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the DAC register of Channel A, the following sequence must be implemented: SDO MISO A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. SDIN AD5724/ AD5734/ AD5754* SCLK SYNC LDAC SDO SDIN AD5724/ AD5734/ AD5754* 1. SCLK SYNC LDAC *ADDITIONAL PINS OMITTED FOR CLARITY. 06468-008 SDO 2. Figure 40. Daisy Chaining the AD5724/AD5734/AD5754 Rev. F | Page 19 of 31 Write 0x800000 to the AD5724/AD5734/AD5754 input register. This configures the device for read mode with the DAC register of Channel A selected. Note that all the data bits, DB15 to DB0, are don’t care bits. Follow this with a second write, a NOP condition, 0x180000. During this write, the data from the register is clocked out on the SDO line. AD5724/AD5734/AD5754 Data Sheet LOAD DAC (LDAC) After data has been transferred into the input register of the DACs, there are two ways to update the DAC registers and DAC outputs. Depending on the status of both SYNC and LDAC, one of two update modes is selected: individual DAC updating or simultaneous updating of all DACs. OUTPUT AMPLIFIER REFIN 12-/14-/16-BIT DAC LDAC DAC REGISTER VOUT TRANSFER FUNCTION INTERFACE LOGIC SDO 06468-009 INPUT REGISTER SCLK SYNC SDIN The DVCC must be brought high before any of the interface lines are powered. If this is not done, the first write to the device may be ignored. The first communication to the AD5724/AD5734/ AD5754 must be to set the required output range on all channels (the default range is the 5 V unipolar range) by writing to the output range select register. The user must then write to the power control register to power on the required channels. To program an output value on a channel, that channel must first be powered up; any writes to a channel while it is in power-down mode are ignored. The AD5724/AD5734/AD5754 operate with a wide power supply range. It is important that the power supply applied to the devices provides adequate headroom to support the chosen output ranges. Figure 41. Simplified Diagram of Input Loading Circuitry for One DAC Individual DAC Updating In this mode, LDAC is held low while data is being clocked into the input shift register. The addressed DAC output is updated on the rising edge of SYNC. Table 7 to Table 15 show the relationships of the ideal input code to output voltage for the AD5754, AD5734, and AD5724, respectively, for all output voltage ranges. For unipolar output ranges, the data coding is straight binary. For bipolar output ranges, the data coding is user-selectable via the BIN/2sCOMP pin and can be either offset binary or twos complement. For a unipolar output range, the output voltage expression is given by D VOUT = VREFIN × Gain  N  2   Simultaneous Updating of All DACs In this mode, LDAC is held high while data is being clocked into the input shift register. All DAC outputs are asynchronously updated by taking LDAC low after SYNC has been taken high. The update now occurs on the falling edge of LDAC. ASYNCHRONOUS CLEAR (CLR) CLR is an active low clear that allows the outputs to clear to either zero-scale code or midscale code. The clear code value is user-selectable via the CLR select bit of the control register (see the Control Register section). It is necessary to maintain CLR low for a minimum amount of time to complete the operation (see Figure 2). When the CLR signal is returned high, the output remains at the cleared value until a new value is programmed. The outputs cannot update with a new value while the CLR pin is low. A clear operation can also be performed via the clear command in the control register. CONFIGURING THE AD5724/AD5734/AD5754 When the power supplies are applied to the AD5724/AD5734/ AD5754, the power-on reset circuit ensures that all registers default to 0. This places all channels in power-down mode. For a bipolar output range, the output voltage expression is given by Gain × VREFIN D VOUT = VREFIN × Gain  N  − 2 2  where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. VREFIN is the reference voltage applied at the REFIN pin. Gain is an internal gain with a value that depends on the output range selected by the user, as shown in Table 6. Table 6. Internal Gain Values Output Range (V) +5 +10 +10.8 ±5 ±10 ±10.8 Rev. F | Page 20 of 31 Gain Value 2 4 4.32 4 8 8.64 Data Sheet AD5724/AD5734/AD5754 Ideal Output Voltage to Input Code Relationship—AD5754 Table 7. Bipolar Output, Offset Binary Coding Digital Input MSB 1111 1111 … 1000 1000 0111 … 0000 0000 1111 1111 … 0000 0000 1111 … 0000 0000 1111 1111 … 0000 0000 1111 … 0000 0000 LSB 1111 1110 … 0001 0000 1111 … 0001 0000 ±5 V Output Range +2 × REFIN × (32,767/32,768) +2 × REFIN × (32,766/32,768) … +2 × REFIN × (1/32,768) 0V −2 × REFIN × (1/32,768) … −2 × REFIN × (32,767/32,768) −2 × REFIN × (32,768/32,768) Analog Output ±10 V Output Range +4 × REFIN × (32,767/32,768) +4 × REFIN × (32,766/32,768) … +4 × REFIN × (1/32,768) 0V −4 × REFIN × (1/32,768) … −4 × REFIN × (32,767/32,768) −4 × REFIN × (32,768/32,768) ±10.8 V Output Range +4.32 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,766/32,768) … +4.32 × REFIN × (1/32,768) 0V −4.32 × REFIN × (32,766/32,768) … −4.32 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,768/32,768) Analog Output ±10 V Output Range +4 × REFIN × (32,767/32,768) +4 × REFIN × (32,766/32,768) … +4 × REFIN × (1/32,768) 0V −4 × REFIN × (1/32,768) … −4 × REFIN × (32,767/32,768) −4 × REFIN × (32,768/32,768) ±10.8 V Output Range +4.32 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,766/32,768) … +4.32 × REFIN × (1/32,768) 0V −4.32 × REFIN × (1/32,768) … −4.32 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,768/32,768) Analog Output +10 V Output Range +4 × REFIN × (65,535/65,536) +4 × REFIN × (65,534/65,536) … +4 × REFIN × (32,769/65,536) +4 × REFIN × (32,768/65,536) +4 × REFIN × (32,767/65,536) … +4 × REFIN × (1/65,536) 0V +10.8 V Output Range +4.32 × REFIN × (65,535/65,536) +4.32 × REFIN × (65,534/65,536) … +4.32 × REFIN × (32,769/65,536) +4.32 × REFIN × (32,768/65,536) +4.32 × REFIN × (32,767/65,536) … +4.32 × REFIN × (1/65,536) 0V Table 8. Bipolar Output, Twos Complement Coding Digital Input MSB 0111 0111 … 0000 0000 1111 … 1000 1000 1111 1111 … 0000 0000 1111 … 0000 0000 1111 1111 … 0000 0000 1111 … 0000 0000 LSB 1111 1110 … 0001 0000 1111 … 0001 0000 ±5 V Output Range +2 × REFIN × (32,767/32,768) +2 × REFIN × (32,766/32,768) … +2 × REFIN × (1/32,768) 0V −2 × REFIN × (1/32,768) … −2 × REFIN × (32,767/32,768) −2 × REFIN × (32,768/32,768) Table 9. Unipolar Output, Straight Binary Coding Digital Input MSB 1111 1111 … 1000 1000 0111 … 0000 0000 1111 1111 … 0000 0000 1111 … 0000 0000 1111 1111 … 0000 0000 1111 … 0000 0000 LSB 1111 1110 … 0001 0000 1111 … 0001 0000 +5 V Output Range +2 × REFIN × (65,535/65,536) +2 × REFIN × (65,534/65,536) … +2 × REFIN × (32,769/65,536) +2 × REFIN × (32,768/65,536) +2 × REFIN × (32,767/65,536) … +2 × REFIN × (1/65,536) 0V Rev. F | Page 21 of 31 AD5724/AD5734/AD5754 Data Sheet Ideal Output Voltage to Input Code Relationship—AD5734 Table 10. Bipolar Output, Offset Binary Coding Digital Input MSB 11 11 … 10 10 01 … 00 00 1111 1111 … 0000 0000 1111 … 0000 0000 1111 1111 … 0000 0000 1111 … 0000 0000 LSB 1111 1110 … 0001 0000 1111 … 0001 0000 ±5 V Output Range +2 × REFIN × (8191/8192) +2 × REFIN × (8190/8192) … +2 × REFIN × (1/8192) 0V −2 × REFIN × (1/8192) … −2 × REFIN × (8191/8192) −2 × REFIN × (8192/8192) Analog Output ±10 V Output Range +4 × REFIN × (8191/8192) +4 × REFIN × (8190/8192) … +4 × REFIN × (1/8192) 0V −4 × REFIN × (1/8192) … −4 × REFIN × (8191/8192) −4 × REFIN × (8192/8192) ±10.8 V Output Range +4.32 × REFIN × (8191/8192) +4.32 × REFIN × (8190/8192) … +4.32 × REFIN × (1/8192) 0V −4.32 × REFIN × (1/8192) … −4.32 × REFIN × (8191/8192) −4.32 × REFIN × (8192/8192) Analog Output ±10 V Output Range +4 × REFIN × (8191/8192) +4 × REFIN × (8190/8192) … +4 × REFIN × (1/8192) 0V −4 × REFIN × (1/8192) … −4 × REFIN × (8191/8192) −4 × REFIN × (8192/8192) ±10.8 V Output Range +4.32 × REFIN × (8191/8192) +4.32 × REFIN × (8190/8192) … +4.32 × REFIN × (1/8192) 0V −4.32 × REFIN × (1/8192) … −4.32 × REFIN × (8191/8192) −4.32 × REFIN × (8192/8192) Analog Output +10 V Output Range +4 × REFIN × (16,383/16,384) +4 × REFIN × (16,382/16,384) … +4 × REFIN × (8193/16,384) +4 × REFIN × (8192/16,384) +4 × REFIN × (8191/16,384) … +4 × REFIN × (1/16,384) 0V +10.8 V Output Range +4.32 × REFIN × (16,383/16,384) +4.32 × REFIN × (16,382/16,384) … +4.32 × REFIN × (8193/16,384) +4.32 × REFIN × (8192/16,384) +4.32 × REFIN × (8191/16,384) … +4.32 × REFIN × (1/16,384) 0V Table 11. Bipolar Output, Twos Complement Coding Digital Input MSB 01 01 … 00 00 11 … 10 10 1111 1111 … 0000 0000 1111 … 0000 0000 1111 1111 … 0000 0000 1111 … 0000 0000 LSB 1111 1110 … 0001 0000 1111 … 0001 0000 ±5 V Output Range +2 × REFIN × (8191/8192) +2 × REFIN × (8190/8192) … +2 × REFIN × (1/8192) 0V −2 × REFIN × (1/8192) … −2 × REFIN × (8191/8192) −2 × REFIN × (8192/8192) Table 12. Unipolar Output, Straight Binary Coding Digital Input MSB 11 11 … 10 10 01 … 00 00 1111 1111 … 0000 0000 1111 … 0000 0000 1111 1111 … 0000 0000 1111 … 0000 0000 LSB 1111 1110 … 0001 0000 1111 … 0001 0000 +5 V Output Range +2 × REFIN × (16,383/16,384) +2 × REFIN × (16,382/16,384) … +2 × REFIN × (8193/16,384) +2 × REFIN × (8192/16,384) +2 × REFIN × (8191/16,384) … +2 × REFIN × (1/16,384) 0V Rev. F | Page 22 of 31 Data Sheet AD5724/AD5734/AD5754 Ideal Output Voltage to Input Code Relationship—AD5724 Table 13. Bipolar Output, Offset Binary Coding Digital Input MSB 1111 1111 … 1000 1000 0111 … 0000 0000 1111 1111 … 0000 0000 1111 … 0000 0000 LSB 1111 1110 … 0001 0000 1111 … 0001 0000 ±5 V Output Range +2 × REFIN × (2047/2048) +2 × REFIN × (2046/2048) … +2 × REFIN × (1/2048) 0V −2 × REFIN × (1/2048) … −2 × REFIN × (2047/2048) −2 × REFIN × (2048/2048) Analog Output ±10 V Output Range +4 × REFIN × (2047/2048) +4 × REFIN × (2046/2048) … +4 × REFIN × (1/2048) 0V −4 × REFIN × (1/2048) … −4 × REFIN × (2047/2048) −4 × REFIN × (2048/2048) ±10.8 V Output Range +4.32 × REFIN × (2047/2048) +4.32 × REFIN × (2046/2048) … +4.32 × REFIN × (1/2048) 0V −4.32 × REFIN × (1/2048) … −4.32 × REFIN × (2047/2048) −4.32 × REFIN × (2048/2048) Analog Output ±10 V Output Range +4 × REFIN × (2047/2048) +4 × REFIN × (2046/2048) … +4 × REFIN × (1/2048) 0V −4 × REFIN × (1/2048) … −4 × REFIN × (2047/2048) −4 × REFIN × (2048/2048) ±10.8 V Output Range +4.32 × REFIN × (2047/2048) +4.32 × REFIN × (2046/2048) … +4.32 × REFIN × (1/2048) 0V −4.32 × REFIN × (1/2048) … −4.32 × REFIN × (2047/2048) −4.32 × REFIN × (2048/2048) Analog Output +10 V Output Range +4 × REFIN × (4095/4096) +4 × REFIN × (4094/4096) … +4 × REFIN × (2049/4096) +4 × REFIN × (2048/4096) +4 × REFIN × (2047/4096) … +4 × REFIN × (1/4096) 0V +10.8 V Output Range +4.32 × REFIN × (4095/4096) +4.32 × REFIN × (4094/4096) … +4.32 × REFIN × (2049/4096) +4.32 × REFIN × (2048/4096) +4.32 × REFIN × (2047/4096) … +4.32 × REFIN × (1/4096) 0V Table 14. Bipolar Output, Twos Complement Coding Digital Input MSB 0111 0111 … 0000 0000 1111 … 1000 1000 1111 1111 … 0000 0000 1111 … 0000 0000 LSB 1111 1110 … 0001 0000 1111 … 0001 0000 ±5 V Output Range +2 × REFIN × (2047/2048) +2 × REFIN × (2046/2048) … +2 × REFIN × (1/2048) 0V −2 × REFIN × (1/2048) … −2 × REFIN × (2047/2048) −2 × REFIN × (2048/2048) Table 15. Unipolar Output, Straight Binary Coding Digital Input MSB 1111 1111 … 1000 1000 0111 … 0000 0000 1111 1111 … 0000 0000 1111 … 0000 0000 LSB 1111 1110 … 0001 0000 1111 … 0001 0000 +5 V Output Range +2 × REFIN × (4095/4096) +2 × REFIN × (4094/4096) … +2 × REFIN × (2049/4096) +2 × REFIN × (2048/4096) +2 × REFIN × (2047/4096) … +2 × REFIN × (1/4096) 0V Rev. F | Page 23 of 31 AD5724/AD5734/AD5754 Data Sheet INPUT SHIFT REGISTER The input shift register is 24 bits wide and consists of a read/write bit (R/W), a reserved bit (zero) that must always be set to 0, three register select bits (REG0, REG1, REG2), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB first on the SDIN pin. Table 16 shows the register format and Table 17 describes the function of each bit in the register. All registers are read/write registers. Table 16. Input Register Format MSB DB23 R/W DB22 Zero DB21 REG2 DB20 REG1 DB19 REG0 DB18 A2 DB17 A1 LSB DB15 to DB0 Data DB16 A0 Table 17. Input Register Bit Functions Bit Mnemonic R/W Description Indicates a read from or a write to the addressed register. REG2, REG1, REG0 Used in association with the address bits to determine if a write operation is to the DAC register, the output range select register, the power control register, or the control register. REG2 REG1 REG0 Function 0 0 0 DAC register 0 0 1 Output range select register 0 1 0 Power control register 0 1 1 Control register These DAC address bits are used to decode the DAC channels. A2 A1 A0 Channel Address 0 0 0 DAC A 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 0 0 All four DACs Data bits. A2, A1, A0 DB15 to DB0 DAC REGISTER The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer is to take place (see Table 17). The data bits are in positions DB15 to DB0 for the AD5754 (see Table 18), DB15 to DB2 for the AD5734 (see Table 19), and DB15 to DB4 for the AD5724 (see Table 20). Table 18. Programming the AD5754 DAC Register MSB R/W Zero REG2 REG1 REG0 0 0 0 0 0 A2 A1 LSB DB15 to DB0 A0 DAC address 16-bit DAC data Table 19. Programming the AD5734 DAC Register MSB R/W Zero REG2 REG1 REG0 A2 0 0 0 0 0 DAC address A1 A0 DB15 to DB2 DB1 LSB DB0 14-bit DAC data X X Table 20. Programming the AD5724 DAC Register MSB R/W Zero REG2 REG1 REG0 A2 0 0 0 0 0 DAC address A1 A0 Rev. F | Page 24 of 31 DB15 to DB4 DB3 DB2 DB1 LSB DB0 12-bit DAC data X X X X Data Sheet AD5724/AD5734/AD5754 OUTPUT RANGE SELECT REGISTER The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel and the range bits (R2, R1, R0) select the required output range (see Table 21 and Table 22). Table 21. Programming the Required Output Range MSB R/W Zero REG2 REG1 REG0 A2 0 0 0 0 1 DAC address A1 A0 DB15 to DB3 DB2 DB1 LSB DB0 Don’t care R2 R1 R0 Table 22. Output Range Options R2 0 0 0 0 1 1 R1 0 0 1 1 0 0 R0 0 1 0 1 0 1 Output Range (V) +5 +10 +10.8 ±5 ±10 ±10.8 CONTROL REGISTER The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the control function selected. The control register options are shown in Table 23 and Table 24. Table 23. Programming the Control Register MSB R/W Zero REG2 REG1 REG0 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 1 DB15 to DB4 DB3 Don’t care TSD enable DB2 DB1 NOP, data = don’t care Clamp enable CLR select Clear, data = don’t care Load, data = don’t care LSB DB0 SDO disable Table 24. Explanation of Control Register Options Option NOP Clear Load SDO Disable CLR Select Clamp Enable TSD Enable Description No operation instruction used in readback operations. Addressing this function sets the DAC registers to the clear code and updates the outputs. Addressing this function updates the DAC registers and, consequently, the DAC outputs. Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). See Table 25 for a description of the CLR select operation. Set by the user to enable the current-limit clamp. The channel does not power down upon detection of an overcurrent; the current is clamped at 20 mA (default). Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent. Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown feature (default). Table 25. CLR Select Options CLR Select Setting 0 1 Unipolar Output Range 0V Midscale Output CLR Value Bipolar Output Range 0V Negative full scale Rev. F | Page 25 of 31 AD5724/AD5734/AD5754 Data Sheet POWER CONTROL REGISTER The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5724/AD5734/AD5754. The power control register options are shown in Table 26 and Table 27. Table 26. Programming the Power Control Register MSB R/W 0 LSB Zero 0 REG2 0 REG1 1 REG0 0 A2 0 A1 0 A0 0 DB15 to DB11 X DB10 OCD DB9 OCC DB8 OCB DB7 OCA DB6 0 DB5 TSD DB4 0 DB3 PUD DB2 PUC DB1 PUB DB0 PUA Table 27. Power Control Register Functions Option PUA PUB PUC PUD TSD OCA OCB OCC OCD Description DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down mode (default). After setting this bit to power DAC A, a power up time of 10 µs is required. During this power-up time, the DAC register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is cleared, DAC A powers down automatically upon detection of an overcurrent, and PUA is cleared to reflect this. DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down mode (default). After setting this bit to power DAC B, a power up time of 10 µs is required. During this power-up time, the DAC register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is cleared, DAC B powers down automatically upon detection of an overcurrent, and PUB is cleared to reflect this. DAC C power-up. When set, this bit places DAC C in normal operating mode. When cleared, this bit places DAC C in power-down mode (default). After setting this bit to power DAC C, a power up time of 10 µs is required. During this power-up time, the DAC register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is cleared, DAC C powers down automatically upon detection of an overcurrent, and PUC is cleared to reflect this. DAC D power-up. When set, this bit places DAC D in normal operating mode. When cleared, this bit places DAC D in power-down mode (default). After setting this bit to power DAC D, a power up time of 10 µs is required. During this power-up time, the DAC register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is cleared, DAC D powers down automatically upon detection of an overcurrent, and PUD is cleared to reflect this. Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, the four DACs are powered down and this bit is set. DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set. DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set. DAC C overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC C, this bit is set. DAC D overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC D, this bit is set. Rev. F | Page 26 of 31 Data Sheet AD5724/AD5734/AD5754 FEATURES ANALOG OUTPUT CONTROL OVERCURRENT PROTECTION In many industrial process control applications, it is vital to control the output voltage during power-up. When the supply voltages change during power-up, the VOUTx pins are clamped to 0 V via a low impedance path (approximately 4 kΩ). To prevent the output amplifiers from being shorted to 0 V during this time, Transmission Gate G1 is also opened (see Figure 42). These conditions are maintained until the analog power supplies have stabilized and a valid word is written to a DAC register. At this time, G2 opens and G1 closes. Each DAC channel of the AD5724/AD5734/AD5754 incorporates individual overcurrent protection. The user has two options for the configuration of the overcurrent protection: constant current clamp or automatic channel power-down. The configuration of the overcurrent protection is selected via the clamp enable bit in the control register. VOLTAGE MONITOR AND CONTROL G1 Constant Current Clamp (Clamp Enable = 1) If a short circuit occurs in this configuration, the current is clamped at 20 mA. This event is signaled to the user by the setting of the appropriate overcurrent (OCX) bit in the power control register. Upon removal of the short-circuit fault, the OCX bit is cleared. Automatic Channel Power-Down (Clamp Enable = 0) VOUTA 06468-010 G2 Figure 42. Analog Output Control Circuitry POWER-DOWN MODE Each DAC channel of the AD5724/AD5734/AD5754 can be individually powered down. By default, all channels are in powerdown mode. The power status is controlled by the power control register (see Table 26 and Table 27 for details). When a channel is in power-down mode, the output pin is clamped to ground through a resistance of approximately 4 kΩ and the output of the amplifier is disconnected from the output pin. If a short circuit occurs in this configuration, the shorted channel powers down and the output is clamped to ground via a resistance of approximately 4 kΩ. At this time, the output of the amplifier is disconnected from the output pin. The short-circuit event is signaled to the user via the overcurrent (OCX) bits, and the power-up (PUX) bits indicate which DACs have powered down. After the fault is rectified, the channels can be powered up again by setting the PUX bits. THERMAL SHUTDOWN The AD5724/AD5734/AD5754 incorporate a thermal shutdown feature that automatically shuts down the device if the core temperature exceeds approximately 150°C. The thermal shutdown feature is disabled by default and can be enabled via the TSD enable bit of the control register. In the event of a thermal shutdown, the TSD bit of the power control register is set. Rev. F | Page 27 of 31 AD5724/AD5734/AD5754 Data Sheet APPLICATIONS INFORMATION +5 V/±5 V OPERATION When operating from a single +5 V supply or a dual ±5 V supply, an output range of +5 V or ±5 V is not achievable because sufficient headroom for the output amplifier is not available. In this situation, a reduced reference voltage can be used. For example, a 2 V reference voltage produces an output range of +4 V or ±4 V, and the 1 V of headroom is more than enough for full operation. A standard value voltage reference of 2.048 V can be used to produce output ranges of +4.096 V and ±4.096 V. Figure 44 shows an example of the analog supplies powering up before the digital supply. The circuit delays the AVDD power up until after DVCC, as shown by the AVDD (delayed) line. AVDD AVSS t (sec) ALTERNATIVE POWER-UP SEQUENCE SUPPORT There may be cases where it is not possible to use the recommended power-up sequence, and in those instances an external circuit shown in Figure 43 is recommended to be used. The circuit shown in Figure 43 ensures that the digital block is powered up first, prior to the analog block, by using a load switch circuit. This circuit targets applications for which either AVDD or AVSS or both supplies power up before DVCC.  R1 ensures that the Q1 gate to source voltage is zero when DVCC is in an open state. R1 also prevents false turn on of Q1. However, if DVCC is permanently connected to the source, R1 can be removed to conserve power. Select Q1 (N-channel MOSFET) with a VGS threshold that is much lower than the minimum operating DVCC and a VDS rating much lower than the maximum operating AVDD. C1, R2, and R3 are the main components that dictates the delay from DVCC enable to AVDD. Adjust the values according for the desired delay. Choose R2 and R3 values that ensure Q2 turn on.  V t DELAY (sec)   C1 (R3 || R2 )  ln 1   GS   VEQ  R3 where VEQ  AVDD   R 3  R2           Q2 (P-channel MOSFET) acts as a switch that allows the flow of current from VIN to AVDD; therefore, choosing a MOSFET with very low RDSON is necessary to minimize losses during operation. Other parameters such as maximum VDS rating, maximum drain to source current rating, VGS threshold voltage, and maximum gate to source voltage rating must also be taken into consideration when choosing Q2. VIN + C1 R3 LOAD SWITCH SECTION R2 DVCC CONTROL SECTION AVDD Q2 R1 Q1 Figure 43. Load Switch Control Circuit 06468-143  06468-144 AVDD (DELAYED) Figure 44. Delayed Power Supplies Sequence Example LAYOUT GUIDELINES Consider the following design rules when choosing the component values for the AVDD delay circuit.  DVCC In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5724/AD5734/AD5754 are mounted must be designed so the analog and digital sections are separated and confined to certain areas of the board. If the AD5724/AD5734/AD5754 are in a system where multiple devices require an AGND to DGND connection, the connection must be made at one point only. The star ground point must be established as close as possible to the device. The AD5724/AD5734/AD5754 must have ample supply bypassing of a 10 μF capacitor in parallel with a 0.1 μF capacitor on each supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitor is the tantalum bead type. The 0.1 μF capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5724/AD5734/AD5754 must use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as a data clock, must be shielded with digital ground to avoid radiating noise to other devices of the board, and must never run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (this is not required on a multilayer board that has a separate ground plane, but separating the lines does help). It is essential to minimize noise on the REFIN line because any unwanted signals couple through to the DAC outputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board must run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip Rev. F | Page 28 of 31 Data Sheet AD5724/AD5734/AD5754 technique is by far the best method, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to a ground plane and signal traces are placed on the solder side. GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The iCoupler® family of products from Analog Devices, Inc., provides voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5724/AD5734/AD5754 makes them ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 45 shows a 4-channel isolated interface to the AD5724/AD5734/AD5754 using an ADuM1400. For further information, visit http://www.analog.com/icouplers. CONTROL OUT V IB V IC V ID ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE V OA V OB V OC V OD TO SCLK TO SDIN TO SYNC TO LDAC *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 45. Isolated Interface VOLTAGE REFERENCE SELECTION To achieve optimum performance from the AD5724/AD5734/ AD5754 over the full operating temperature range of the devices, a precision voltage reference must be used. Thought must be given to the selection of a precision voltage reference. The voltage applied to the reference inputs are used to provide a buffered positive and negative reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the device. There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long-term drift, and output voltage noise.   The temperature coefficient of a reference output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification must be chosen to reduce the dependence of the DAC output voltage on ambient conditions. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over the entire lifetime. Consider reference output voltage noise in high accuracy applications that have relatively low noise budgets. It is important to choose a reference with as low an output noise voltage as practical for the required system resolution. Precision voltage references such as the ADR431 (XFET® design) produce low output noise in the 0.1 Hz to 10 Hz range. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5724/AD5734/AD5754 is via a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5724/AD5734/ AD5754 require a 24-bit data-word with data valid on the falling edge of SCLK. For all interfaces, the DAC output update can be initiated automatically when all the data is clocked in, or it can be performed under the control of LDAC. The contents of the registers can be read using the readback function. AD5724/AD5734/AD5754 to Blackfin® DSP Interface Figure 46 shows how the AD5724/AD5734/AD5754 can be interfaced to the Analog Devices Blackfin DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5724/AD5734/AD5754 and the programmable I/O pins that can be used to set the state of a digital input such as the LDAC pin. Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR421, allows a system designer to trim out system errors by setting the reference voltage to a voltage other than the nominal. The trim adjustment can also trim out temperature-induced errors. SPISELx SYNC SCK MOSI SCLK SDIN ADSP-BF531 PF10 AD5724/ AD5734/ AD5754 LDAC 06468-012 SYNC OUT V IA 06468-011 SERIAL DATA OUT  ADuM1400* MICROCONTROLLER SERIAL CLOCK OUT  Figure 46. AD5724/AD5734/AD5754 to Blackfin Interface Rev. F | Page 29 of 31 AD5724/AD5734/AD5754 Data Sheet Table 28. Some Precision References Recommended for Use with the AD5724/AD5734/AD5754 Part No. ADR431 ADR421 ADR03 ADR291 AD780 Initial Accuracy (mV Max) ±1 ±1 ±2.5 ±2 ±1 Long-Term Drift (ppm Typ) 40 50 50 50 20 Temp Drift (ppm/°C Max) 3 3 3 8 3 Rev. F | Page 30 of 31 0.1 Hz to 10 Hz Noise (µV p-p Typ) 3.5 1.75 6 8 4 Data Sheet AD5724/AD5734/AD5754 OUTLINE DIMENSIONS 5.02 5.00 4.95 7.90 7.80 7.70 24 13 4.50 4.40 4.30 3.25 3.20 3.15 EXPOSED PAD (Pins Up) 6.40 BSC 12 BOTTOM VIEW TOP VIEW 1.05 1.00 0.80 1.20 MAX 0.15 0.05 SEATING PLANE 0.10 COPLANARITY 0.65 BSC 8° 0° 0.20 0.09 0.30 0.19 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.75 0.60 0.45 061708-A 1 COMPLIANT TO JEDEC STANDARDS MO-153-ADT Figure 47. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5724AREZ AD5724AREZ-REEL7 AD5734AREZ AD5734AREZ-REEL7 AD5754AREZ AD5754AREZ-REEL7 AD5754BREZ AD5754BREZ-REEL7 1 Resolution (Bits) 12 12 14 14 16 16 16 16 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C TUE 0.3% FSR 0.3% FSR 0.3% FSR 0.3% FSR 0.3% FSR 0.3% FSR 0.1% FSR 0.1% FSR Z = RoHS Compliant Part. ©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06468-0-2/17(F) Rev. F | Page 31 of 31 INL ±1 LSB ±1 LSB ±4 LSB ±4 LSB ±16 LSB ±16 LSB ±16 LSB ±16 LSB Package Description 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP Package Option RE-24 RE-24 RE-24 RE-24 RE-24 RE-24 RE-24 RE-24