Multiple Range, 16-Bit, Bipolar/Unipolar
Voltage Output DAC with 7 ppm/°C Reference
AD5761R-EP
Enhanced Product
FEATURES
GENERAL DESCRIPTION
8 software-programmable output ranges: 0 V to 5 V, 0 V to
10 V, 0 V to 16 V, 0 V to 20 V, −2.5 V to +7.5 V, ±3 V, ±5 V, and
±10 V; 5% overrange
Low drift 2.5 V reference: ±7 ppm/°C typical
TUE: ±0.1% FSR maximum
16-bit relative accuracy (INL): ±8 LSB maximum
Guaranteed monotonicity (DNL): ±1 LSB maximum
Single channel, 16-bit DAC
Output voltage settling time
7.5 μs typical, 10 V step to 1 LSB at 16-bit resolution
Integrated reference buffers
Low noise: 35 nV/√Hz (±3 V range)
Low glitch: 1 nV-sec (0 V to 5 V range)
1.7 V to 5.5 V digital supply range (DVCC)
Asynchronous updating via LDAC
Asynchronous RESET to zero scale/midscale
DSP-/microcontroller-compatible serial interface
Robust 4 kV HBM ESD rating
16-lead TSSOP package
Operating temperature range: −55°C to +125°C
The AD5761R-EP is a single-channel, 16-bit serial input, voltage
output, digital-to-analog converter (DAC). It operates from
single-supply voltages from 4.75 V to 30 V VDD or dual supply
voltages from −16.5 V to 0 V VSS and 4.75 V to 16.5 V VDD. The
integrated output amplifier, reference buffer, and reference
provide an easy to use, universal solution.
The device offers guaranteed monotonicity, integral nonlinearity
(INL) of ±8 LSB maximum, 35 nV/√Hz noise, and a 7.5 μs settling
time on selected ranges.
The AD5761R-EP uses a serial interface that operates at clock
rates of up to 50 MHz and is compatible with digital signal
processor (DSP) and microcontroller interface standards. Double
buffering allows the asynchronous updating of the DAC output.
The input coding is user selectable, twos complement or straight
binary. The asynchronous reset function resets all registers to
their default state. The output range is user selectable via the
RA[2:0] bits in the control register.
The device is available in a 16-lead TSSOP package, and it offers
guaranteed specifications over the −55°C to +125°C military
temperature range.
ENHANCED PRODUCT FEATURES
Additional application and technical information can be found in
the AD5761R data sheet.
Supports defense and aerospace applications (AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Industrial automation
Instrumentation, data acquisition
Open-/closed-loop servo control, process control
Programmable logic controllers
FUNCTIONAL BLOCK DIAGRAM
VREFIN/VREFOUT
DD
2.5V
REFERENCE
CC
ALERT
SDI
SCLK
SYNC
SDO
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
16
INPUT
REG
DAC
REG
REFERENCE
BUFFERS
16
16-BIT
DAC
RESET
V OUT
0V TO 5V
0V TO 10V
0V TO 16V
0V TO 20V
±3V
±5V
±10V
−2.5V TO +7.5V
DNC
DGND
VSS
AGND
LDAC
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
15433-001
CLEAR
Figure 1.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5761R-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................7
Enhanced Product Features ............................................................ 1
ESD Caution...................................................................................7
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................8
General Description ......................................................................... 1
Typical Performance Characterstics ...............................................9
Functional Block Diagram .............................................................. 1
Outline Dimensions ....................................................................... 11
Revision History ............................................................................... 2
Ordering Guide .......................................................................... 11
Specifications..................................................................................... 3
AC Performance Characteristics ................................................ 6
REVISION HISTORY
3/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 11
Enhanced Product
AD5761R-EP
SPECIFICATIONS
VDD 1 = 4.75 V to 30 V, VSS1 = −16.5 V to 0 V, AGND = DGND = 0 V, VREFIN/VREFOUT = 2.5 V external, DVCC = 1.7 V to 5.5 V, RLOAD = 1 kΩ for
all ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, and all specifications TMIN to TMAX, unless otherwise
noted. Temperature range: −55°C to +125°C, typical at +25°C.
Table 1.
Parameter
STATIC PERFORMANCE
Programmable Output Ranges
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Min
Max
Unit
0
0
0
0
−2.5
−3
−5
−10
16
−8
−1
−6
5
10
16
20
+7.5
+3
+5
+10
+8
+1
+6
V
V
V
V
V
V
V
V
Bits
LSB
LSB
mV
−10
−6
+10
+6
mV
mV
−8
−9
−13
+8
+9
+13
±5
mV
mV
mV
µV/°C
±15
µV/°C
Zero-Scale Temperature
Coefficient (TC) 3
Bipolar Zero Error
−5
−7
Bipolar Zero TC3
Offset Error
Gain Error TC3
Total Unadjusted Error (TUE)
+5
+7
±2
mV
mV
µV/°C
±5
µV/°C
−6
+6
mV
−10
−6
+10
+6
mV
mV
−8
−9
−18
+8
+9
+18
±5
mV
mV
mV
µV/°C
±15
µV/°C
Offset Error TC3
Gain Error
Typ
−0.1
−0.15
+0.1
+0.15
±1.5
−0.1
−0.15
+0.1
+0.15
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
Rev. 0 | Page 3 of 11
Test Conditions/Comments
External reference 2 and internal reference,
outputs unloaded
External reference2 and internal reference
All ranges except ±10 V and 0 V to 20 V, external
reference2
0 V to 20 V, ±10 V ranges, external reference2
All ranges except ±5 V, ±10 V, and 0 V to 20 V,
internal reference
±5 V range, internal reference
0 V to 20 V range, internal reference
±10 V range, internal reference
Unipolar ranges, external reference2 and internal
reference
Bipolar ranges, external reference2 and internal
reference
All bipolar ranges except ±10 V
±10 V output range
±3 V range, external reference2 and internal
reference
All bipolar ranges except ±3 V range, external
reference2 and internal reference
All ranges except ±10 V and 0 V to 20 V, external
reference2
0 V to 20 V, ±10 V ranges, external reference2
All ranges except ±5 V, ±10 V, and 0 V to 20 V;
internal reference
±5 V range, internal reference
0 V to 20 V range, internal reference
±10 V range, internal reference
Unipolar ranges, external reference2 and internal
reference
Bipolar ranges, external reference2 and internal
reference
External reference2
Internal reference
External reference2 and internal reference
External reference2
Internal reference
AD5761R-EP
Parameter
REFERENCE INPUT (EXTERNAL)3
Reference Input Voltage (VREF)
Input Current
Reference Range
REFERENCE OUTPUT (INTERNAL)3
Output Voltage
Voltage Reference TC
Output Impedance
Output Voltage Noise
Noise Spectral Density
Line Regulation
Thermal Hysteresis
Start-Up Time
OUTPUT CHARACTERISTICS3
Output Voltage Range
Enhanced Product
Min
−2
2
Typ
2.5
±0.5
2.5
7
25
6
10
6
±80
3.5
Unit
Test Conditions/Comments
V
µA
V
±1% for specified performance
+2
3
V
ppm/°C
kΩ
µV p-p
nV/√Hz
µV/V
ppm
ms
±3 mV, at ambient temperature
25
−VOUT
+VOUT
−10
−10.5
+10
+10.5
V
V
1
1
nF
V
1
2
ppm FSR/°C
mA
kΩ
kΩ
mV/mA
Ω
Capacitive Load Stability
Headroom
0.5
Output Voltage TC
Short-Circuit Current
Resistive Load
±3
25
Load Regulation
DC Output Impedance
LOGIC INPUTS3
Input Voltage
High (VIH)
Low (VIL)
Input Current
Leakage Current
0.3
0.5
Pin Capacitance
LOGIC OUTPUTS (SDO, ALERT)3
Output Voltage
Low (VOL)
High (VOH)
High Impedance, SDO Pin
Leakage Current
Pin Capacitance
POWER REQUIREMENTS
Single Supply
VDD
VSS
Dual Supply
VDD
VSS
Max
0.7 × DVCC
0.3 × DVCC
−1
−1
−55
V
V
SDI, SCLK, SYNC
LDAC, CLEAR, RESET pins held high
LDAC, CLEAR, RESET pins held low
Per pin, outputs unloaded
0.4
V
V
DVCC = 1.7 V to 5.5 V, sinking 200 µA
DVCC = 1.7 V to 5.5 V, sourcing 200 µA
+1
µA
pF
30
V
V
16.5
0
V
V
5
0
4.75
−16.5
RLOAD = 1 kΩ for all ranges except 0 V to16 V and 0 V
to 20 V ranges (RLOAD = 2 kΩ)
±10 V range, external reference
Short on the VOUT pin
All ranges except 0 V to16 V and 0 V to 20 V
0 V to 16 V, 0 V to 20 V ranges
Outputs unloaded
Outputs unloaded
DVCC = 1.7 V to 5.5 V, JEDEC compliant
µA
µA
µA
pF
DVCC − 0.5
4.75
Seethe AD5761R data sheet for the different
output voltage ranges available
VDD/VSS = ±11 V, ±10 V output range
VDD/VSS = ±11 V, ±10 V output range with 5%
overrange
+1
+1
5
−1
0.1 Hz to 10 Hz
At ambient; f = 10 kHz
At ambient
First temperature cycle
Coming out of power-down mode with a 10 nF
capacitor on the VREFIN/VREFOUT pin improves noise
performance; outputs unloaded
Rev. 0 | Page 4 of 11
Enhanced Product
Parameter
DVCC
IDD
ISS
DICC
Power Dissipation
DC Power Supply Rejection
Ratio (PSRR)3
AC PSRR3
AD5761R-EP
Min
1.7
Typ
5.1
1
0.005
67.1
0.1
Max
5.5
6.5
3
1
Unit
V
mA
mA
µA
mW
mV/V
0.1
65
mV/V
dB
65
dB
80
dB
80
dB
Test Conditions/Comments
Outputs unloaded, external reference
Outputs unloaded
VIH = DVCC, VIL = DGND
±11 V operation, outputs unloaded
VDD ± 10%, VSS = −15 V
VSS ±10%, VDD = +15 V
VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V, internal
reference, CLOAD = 100 nF
VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V, internal
reference, CLOAD = 100 nF
VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V, external
reference, CLOAD = unloaded
VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V, external
reference, CLOAD = unloaded
For specified performance, headroom requirement is 1 V. VDD = 4.75 V to 30 V and VSS = 0 V for single-supply operation, and VDD = 4.75 V to 16.5 V and VSS = −16.5 V to 0 V for dualsupply operation.
External reference is 2 V to 2.85 V with overrange and 2 V to 3 V without overrange.
3
Guaranteed by design and characterization, not production tested.
1
2
Rev. 0 | Page 5 of 11
AD5761R-EP
Enhanced Product
AC PERFORMANCE CHARACTERISTICS
VDD 1 = 4.75 V to 30 V, VSS1 = −16.5 V to 0 V, AGND = DGND = 0 V, VREFIN/VREFOUT = 2.5 V external, DVCC = 1.7 V to 5.5 V, RLOAD = 1 kΩ for
all ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted.
Temperature range: −55°C to +125°C, typical at +25°C. Guaranteed by design and characterization, not production tested.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
Digital-to-Analog Glitch Impulse
Glitch Impulse Peak Amplitude
Power-On Glitch
Digital Feedthrough
Output Noise
0.1 Hz to 10 Hz Bandwidth
100 kHz Bandwidth
Output Noise Spectral Density,
at 10 kHz
Total Harmonic Distortion (THD) 2
Signal-to-Noise Ratio (SNR)
Peak Harmonic or Spurious
Noise (SFDR)
Signal-to-Noise-and-Distortion
(SINAD) Ratio
Min
Typ
Max
Unit
Test Conditions/Comments
9
7.5
12.5
8.5
5
8
1
15
10
100
0.6
µs
µs
µs
nV-sec
nV-sec
mV
mV
mV p-p
nV-sec
20 V step to 1 LSB at 16-bit resolution
10 V step to 1 LSB at 16-bit resolution
512 LSB step to 1 LSB at 16-bit resolution
±10 V range
0 V to 5 V range
±10 V range
0 V to 5 V range
15
45
35
25
15
80
µV p-p
µV rms
µV rms
µV rms
µV rms
nV/√Hz
35
70
110
90
45
−87
92
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
dB
dB
92
dB
±3 V range, 2.5 V external reference
±5 V, 0 V to 10 V, and −2.5 V to +7.5 V ranges, 2.5 V external reference
0 V to 20 V range, 2.5 V external reference
0 V to 16 V range, 2.5 V external reference
0 V to 5 V range, 2.5 V external reference
2.5 V external reference, 1 kHz tone
At ambient, 2.5 V external reference, bandwidth (BW) = 20 kHz,
fOUT = 1 kHz
At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
85
dB
At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
0 V to 20 V and 0 V to 16 V ranges, 2.5 V external reference
0 V to 10 V, ±10 V, and −2.5 V to +7.5 V ranges, 2.5 V external reference
±5 V range, 2.5 V external reference
0 V to 5 V and ±3 V ranges, 2.5 V external reference
±10 V range, 2.5 V external reference
For specified performance, headroom requirement is 1 V. VDD = 4.75 V to 30 V and VSS = 0 V for single-supply operation, and VDD = 4.75 V to 16.5 V and VSS = −16.5 V to 0 V for
dual-supply operation.
2
Digitally generated sine wave at 1 kHz.
1
Rev. 0 | Page 6 of 11
Enhanced Product
AD5761R-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
200 mA do not cause silicon controlled rectifier (SCR) latch-up.
1.2
MAXIMUM POWER DISSIPATION (W)
1.1
Table 3.
Digital Outputs to DGND
VREFIN/VREFOUT to DGND
VOUT to AGND
AGND to DGND
Military Temperature Range
Storage Temperature Range
Junction Temperature, TJ MAX
θJA Thermal Impedance
Power Dissipation
Lead Temperature
Soldering
ESD (Human Body Model)
1
Rating
−0.3 V to +34 V
+0.3 V to −17 V
−0.3 V to +34 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to +7 V
VSS to VDD
−0.3 V to +0.3 V
−55°C to +125°C
−65°C to +150°C
150°C
113°C/W1
See Figure 2
JEDEC industry standard
J-STD-020
4 kV
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–60
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
JEDEC 2S2P test board, still air (0 m/sec airflow).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 7 of 11
15433-002
Parameter
VDD to AGND
VSS to AGND
VDD to VSS
DVCC to DGND
Digital Inputs to DGND
1.0
AD5761R-EP
Enhanced Product
ALERT
1
16
DGND
CLEAR
2
15
DVCC
14
SCLK
RESET
3
VREFIN/VREFOUT
4
AD5761R-EP
13
SYNC
AGND
5
TOP VIEW
(Not to Scale)
12
SDI
VSS
6
11
LDAC
VOUT
7
10
SDO
VDD
8
9
DNC
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT
TO THIS PIN.
12355-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
ALERT
2
CLEAR
3
RESET
4
VREFIN/VREFOUT
5
6
AGND
VSS
7
8
VOUT
VDD
9
10
DNC
SDO
11
LDAC
12
13
SDI
SYNC
14
SCLK
15
DVCC
16
DGND
Description
Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or when an
output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full software reset, or
a hardware reset for which a write to the control register asserts the pin high.
Falling Edge Clear Input. Asserting this pin sets the DAC register to zero-scale, midscale, or full-scale code (user
selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor.
Active Low Reset Input. Asserting this pin returns the AD5761R-EP to its default power-on status where the
output is clamped to ground, and the output buffer is powered down. This pin can be left floating because
there is an internal pull-up resistor.
Internal Reference Voltage Output and External Reference Voltage Input. For specified performance,
VREFIN/VREFOUT = 2.5 V. Connect a 10 nF capacitor with the internal reference to minimize the noise.
Ground Reference Pin for Analog Circuitry.
Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin. For
unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND.
Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load.
Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin for
unipolar output ranges. Bipolar output ranges accept a voltage in the range of 4.75 V to 16.5 V. VDD must be
decoupled to AGND.
Do Not Connect. Do not connect to this pin.
Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is clocked
out on the rising edge of SCLK and is valid on the falling edge of SCLK.
Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied
permanently low, the DAC register is updated when the input register is updated. If LDAC is held high during
the write to the input register, the DAC output register is not updated, and the DAC output update is held off
until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While
SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at
clock speeds of up to 50 MHz.
Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the digital
interface operates.
Digital Ground.
Rev. 0 | Page 8 of 11
Enhanced Product
AD5761R-EP
TYPICAL PERFORMANCE CHARACTERSTICS
0.006
1.5
0.004
MIDSCALE ERROR (V)
0
–0.5
–1.0
–2
–55
+5V U2 EXTERNAL REFERENCE MINIMUM
+5V U1 INTERNAL REFERENCE MINIMUM
+5V U2 EXTERNAL REFERENCE MAXIMUM
+5V U1 INTERNAL REFERENCE MAXIMUM
–40
–20
0
25
50
85
0
–0.002
–0.004
105
125
TEMPERATURE (°C)
–0.006
–55
15433-308
–1.5
0.002
DNL ERROR (LSB)
0.6
0.4
0.008
0.006
0
–0.2
–0.4
105
125
105
125
105
125
0
–0.004
–0.008
–20
0
25
50
85
105
125
–0.010
–55
15433-309
–40
+5V U1 EXTERNAL REFERENCE
+5V U2 INTERNAL REFERENCE
±10V U1 EXTERNAL REFERENCE
±10V U2 INTERNAL REFERENCE
–0.002
–0.8
TEMPERATURE (°C)
–40
–20
0
25
50
85
TEMPERATURE (°C)
Figure 5. DNL Error vs. Temperature
Figure 8. Full-Scale Error vs. Temperature
0.15
+5V U1 EXTERNAL REFERENCE
+5V U2 INTERNAL REFERENCE
±10V U1 EXTERNAL REFERENCE
±10V U2 INTERNAL REFERENCE
0.10
0.006
GAIN ERROR (%FSR)
0.004
0.002
0
–0.002
–0.004
–0.006
+5V U1 EXTERNAL REFERENCE
+5V U2 INTERNAL REFERENCE
±10V U1 EXTERNAL REFERENCE
±10V U2 INTERNAL REFERENCE
0.05
0
–0.05
–0.10
–0.010
–55
–40
–20
0
25
50
85
TEMPERATURE (°C)
105
125
Figure 6. Zero-Scale Error vs. Temperature
–0.15
–55
–40
–20
0
25
50
85
TEMPERATURE (°C)
Figure 9. Gain Error vs. Temperature
Rev. 0 | Page 9 of 11
15433-317
–0.008
15433-314
ZERO-SCALE ERROR (V)
85
0.002
–0.006
0.008
50
0.004
–0.6
0.010
25
0.010
+5V U2 EXTERNAL REFERENCE MAXIMUM
+5V U1 INTERNAL REFERENCE MAXIMUM
+5V U2 EXTERNAL REFERENCE MINIMUM
+5V U1 INTERNAL REFERENCE MINIMUM
±10V U2 EXTERNAL REFERENCE MAXIMUM
±10V U1 INTERNAL REFERENCE MAXIMUM
±10V U2 EXTERNAL REFERENCE MINIMUM
±10V U1 INTERNAL REFERENCE MINIMUM
0.2
–1.0
–55
0
Figure 7. Midscale Error vs. Temperature
FULL-SCALE ERROR (V)
0.8
–20
TEMPERATURE (°C)
Figure 4. INL Error vs. Temperature
1.0
–40
15433-315
INL ERROR (LSB)
0.5
+5V U1 EXTERNAL REFERENCE
+5V U2 INTERNAL REFERENCE
±10V U1 EXTERNAL REFERENCE
±10V U2 INTERNAL REFERENCE
15433-316
1.0
±10V U2 EXTERNAL REFERENCE MAXIMUM
±10V U1 INTERNAL REFERENCE MAXIMUM
±10V U2 EXTERNAL REFERENCE MINIMUM
±10V U1 INTERNAL REFERENCE MINIMUM
AD5761R-EP
12
0.10
+5V U1 EXTERNAL REFERENCE
+5V U2 INTERNAL REFERENCE
+5V U3 INTERNAL REFERENCE
±10V U1 EXTERNAL REFERENCE
±10V U2 INTERNAL REFERENCE
±10V U3 INTERNAL REFERENCE
10
NUMBER OF HITS
0.08
0.06
0.04
0.02
8
6
4
2
0
25
50
85
105
TEMPERATURE (°C)
125
0
TEMPERATURE DRIFT (ppm/°C)
Figure 12. Reference Output TC
Figure 10. Total Unadjusted Error (TUE) vs. Temperature
Figure 11. Reference Output Voltage vs. Temperature
Rev. 0 | Page 10 of 11
15433-539
–20
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
MORE
–40
15433-328
0
–55
15433-041
TOTAL UNADJUSTED ERROR (%FSR)
Enhanced Product
Enhanced Product
AD5761R-EP
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 13. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5761RTRUZ-EP
AD5761RTRUZ-EP-RL7
1
Resolution (Bits)
16
16
Internal
Reference (V)
2.5
2.5
Temperature Range
−55°C to +125°C
−55°C to +125°C
Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15433-0-3/17(0)
Rev. 0 | Page 11 of 11
INL (LSB)
±8
±8
Package Description
16-Lead TSSOP
16-Lead TSSOP
Package
Option
RU-16
RU-16
