AD5770RBCBZ-RL7

6-Channel, 14-Bit, Current Output DAC with On-Chip Reference, SPI Interface AD5770R Data Sheet FEATURES APPLICATIONS 6-channel, current output DAC 14-bit resolution Programmable output current ranges Channel 0: 0 mA to 300 mA, −60 mA to +300 mA, −60 mA to 0 mA Channel 1: 0 mA to 140 mA, 0 mA to 250 mA Channel 2: 0 mA to 55 mA, 0 mA to 150 mA Channel 3, Channel 4, Channel 5: 0 mA to 45 mA, 0 mA to 100 mA All current sourcing output ranges scale back by up to 0.5× 1.25 V, on-chip voltage reference Integrated precision reference resistor SPI interface Reset function Output current monitor Compliance voltage monitor Die temperature monitor Integrated thermal shutdown 49-ball, 4 mm × 4 mm WLCSP package Operating temperature: −40°C to +105°C Photonics control LED driver programmable current source Current mode biasing GENERAL DESCRIPTION The AD5770R is a 6-channel, 14-bit resolution, low noise, programmable current output, digital-to-analog converter (DAC) for photonics control applications. The device incorporates a 1.25 V, on-chip voltage reference, a 2.5 kΩ precision resistor for reference current generation, die temperature, output monitoring functions, fault alarm, and reset functions. The AD5770R contains five 14-bit resolution current sourcing DAC channels and one 14-bit resolution current sourcing and sinking DAC channel. Channel 0 can be configured to sink up to 60 mA and source up to 300 mA. Channel 1 to Channel 5 have multiple programmable output current sourcing ranges set by register access. Each DAC operates with a wide power supply rail from 0.8 V to AVDD − 0.4 V for optimizing power efficiency and thermal power dissipation. The AD5770R operates from a 2.9 V to 5.5 V AVDD supply and is specified over the −40°C to +105°C temperature range. FUNCTIONAL BLOCK DIAGRAM IOVDD DVDD AVDD CREG CDAMP_IDACx PVDDx AD5770R CS SCLK INPUT REGISTER DAC REGISTER DAC IDAC0 INPUT REGISTER DAC REGISTER DAC IDAC1 INPUT REGISTER DAC REGISTER DAC IDAC5 SDI SDO INTERFACE LOGIC ALARM LDAC RESET 1.25V REFERENCE CREF IREF TEMPERATURE SENSOR 2.5kΩ INTERNAL RESISTOR REFGND AVEE DGND AGND PVEE0 MUX_OUT 16128-001 MUX VREF_IO Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5770R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Load DAC .................................................................................... 28  Applications ....................................................................................... 1  Input Page Mask Register .......................................................... 28  General Description ......................................................................... 1  DAC Page Mask Register ........................................................... 28  Functional Block Diagram .............................................................. 1  Output Stages .............................................................................. 28  Revision History ............................................................................... 2  Output Filter ............................................................................... 30  Specifications..................................................................................... 3  Output Current Scaling ............................................................. 30  AC Performance Characteristics ................................................ 6  ALARM ....................................................................................... 30  Timing Specifications .................................................................. 7  Applications Information .............................................................. 33  Timing Diagrams.......................................................................... 8  Microprocessor Interfacing ....................................................... 33  Absolute Maximum Ratings............................................................ 9  AD5770R to SPI Interface ......................................................... 33  Thermal Resistance ...................................................................... 9  Thermal Considerations............................................................ 33  ESD Caution .................................................................................. 9  Combining Channels to Increase Current Range .................. 33  Pin Configuration and Function Descriptions ........................... 10  Layout Guidelines....................................................................... 33  Typical Performance Characteristics ........................................... 12  Register Summary .......................................................................... 35  Terminology .................................................................................... 24  SPI Configuration Registers...................................................... 35  Theory of Operation ...................................................................... 25  AD5770R Configuration Registers .......................................... 35  Digital to Analog Converter ..................................................... 25  Register Details ............................................................................... 38  Precision Reference Current Generation ................................ 25  Outline Dimensions ....................................................................... 59  Diagnostic Monitoring .............................................................. 25  Ordering Guide .......................................................................... 59  Serial Interface ............................................................................ 26  Reset Function ............................................................................ 28  REVISION HISTORY 11/2019—Rev. 0 to Rev. A Changes to AVEE Supply Current Parameter, Table 1 ................ 5 Changes to Figure 2 .......................................................................... 8 Changes to Figure 41 Caption, Figure 42 Caption, Figure 43 Caption, Figure 44 Caption, Figure 45 Caption, and Figure 46 Caption.................................................................... 18 Changes to Figure 47 Caption....................................................... 19 Changes to Output Current Scaling Section ............................... 30 Changes to Table 10 ........................................................................ 31 Changes to Table 11 ........................................................................ 34 2/2019—Revision 0: Initial Version Rev. A | Page 2 of 59 Data Sheet AD5770R SPECIFICATIONS AVDD = DVDD = 2.9 V to 5.5 V, PVDD = 0.8 V to AVDD − 0.4 V, AVEE = −3.0 V to 0 V, 2.5 V ≤ PVDD − AVEE ≤ 5.5 V, IOVDD = 1.65 V to 5.5 V, AVEE ≤ PVEE0 ≤ 0 V, AVDD − PVEE0 ≤ 5.5 V, VREF = 1.25 V external voltage reference, ambient temperature (TA) = −40°C to +105°C, unless otherwise noted. Table 1. Parameter1 STATIC PERFORMANCE, EXTERNAL RSET2 Min Typ Max Unit Bits LSB LSB Resolution Relative Accuracy (INL) Differential Nonlinearity (DNL) 14 −6.5 −1 +6.5 +1 Total Unadjusted Error −1 −1.3 +1.2 +1.3 Zero-Scale Error Zero-Scale Error Drift −600 Full-Scale Error Full-Scale Error Drift −1.3 Gain Error Gain Temperature Coefficient −1.3 μA/V +600 1 0.5 +1.3 20 50 DC Crosstalk DC Power Supply Rejection Ratio (PSRR) STATIC PERFORMANCE, INTERNAL RSET Total Unadjusted Error (TUE) Zero-Scale Error Zero-Scale Error Drift 17 +600 500 300 170 Offset Error Offset Error Drift Resolution Relative Accuracy (INL) Differential Nonlinearity (DNL) 30 80 2 LSB % full-scale range (FSR) μA nA/°C nA/°C nA/°C μA μA/°C μA/°C % FSR ppm/°C ppm/°C % FSR ppm/°C ppm/°C LSB +1.3 14 −6.5 −1 +6.5 +1 −1 −1.3 +1.2 +1.3 +600 500 300 170 Offset Error Offset Error Drift −600 Full-Scale Error Full-Scale Error Drift −1.3 Gain Error Gain Temperature Coefficient −1.3 +600 1 0.5 +1.3 20 50 +1.3 30 80 Rev. A | Page 3 of 59 Bits LSB LSB LSB % FSR μA nA/°C nA/°C nA/°C μA μA/°C μA/°C % FSR ppm/°C ppm/°C % FSR ppm/°C ppm/°C Test Conditions/Comments VREF = 1.25 V external voltage reference, assumes ideal 2.5 kΩ external RSET resistor, all channels and all output current ranges TA = −20°C to +105°C, guaranteed monotonic Guaranteed monotonic All 0s loaded into the DAC register Channel 0, Channel 1 Channel 2 Channel 3, Channel 4, Channel 5 Channel 0, Channel 1 Channel 2, Channel 3, Channel 4, Channel 5 All 1s loaded into the DAC register Channel 0, Channel 1 Channel 2, Channel 3, Channel 4, Channel 5 Channel 0, Channel 1 Channel 2, Channel 3, Channel 4, Channel 5 TA = 25°C, due to full-scale change in output current on a single adjacent channel TA = 25°C, DAC register loaded to full scale VREF = 1.25 V internal voltage reference, all channels and all output current ranges TA = −20°C to +105°C, guaranteed monotonic Guaranteed monotonic All 0s loaded into the DAC register Channel 0, Channel 1 Channel 2 Channel 3, Channel 4, Channel 5 Channel 0, Channel 1 Channel 2, Channel 3, Channel 4, Channel 5 All 1s loaded into the DAC register Channel 0, Channel 1 Channel 2, Channel 3, Channel 4, Channel 5 Channel 0, Channel 1 Channel 2, Channel 3, Channel 4, Channel 5 AD5770R Parameter1 DC Crosstalk DC PSRR OUTPUT CHARACTERISTICS Output Current Ranges Channel 0 Data Sheet Min Typ 2 Max 17 Unit LSB μA/V −60 −60 0 0 0 0 0 0 0 0 +300 300 140 250 55 150 45 100 mA mA mA mA mA mA mA mA mA Output Compliance Voltage3 Channel 0 0 PVDD0 − 0.45 V PVEE0 + 0.5 0 PVDD1 − 0.275 V 0 PVDD1 − 0.45 V 0 PVDDx − 0.275 V Channel 1 Channel 2 Channel 3, Channel 4, Channel 5 Channel 1 Channel 2, Channel 3, Channel 4, Channel 5 DC Output Impedance VOLTAGE REFERENCE INPUT Reference Input Impedance Reference Input Range VOLTAGE REFERENCE OUTPUT Output Voltage Reference Temperature Coefficient Output Impedance Output Current Load Capability Maximum Capacitive Load Load Regulation Sourcing Load Regulation Sinking Output Voltage Noise Output Voltage Noise Spectral Density Line Regulation INTEGRATED MULTIPLEXER Buffer Output Current Buffer Output Impedance Buffer Offset Buffer Maximum Capacitive Load 1.245 600 kΩ 60 115 1.25 GΩ kΩ V 2.5 V 1.25 15 0.01 ±5 10 250 250 920 70 70 35 1.255 ±8 0.5 0.3 100 Rev. A | Page 4 of 59 V ppm/°C Ω mA μF μV/mA μV/mA nV rms nV/√Hz nV/√Hz μV/V mA Ω mV pF Test Conditions/Comments TA = 25°C, due to 200 mW change in output power on a single channel TA = 25°C, DAC register loaded to midscale When sourcing in the 0 mA to 300 mA range, DAC register is loaded to full scale When sinking current on the −60 mA to 0 mA and the −60 mA to +300 mA ranges, DAC register is loaded to zero scale When configured to the 140 mA range with low headroom, DAC register is loaded to full scale When configured to the 250 mA range or to the 140 mA range with low noise, DAC register is loaded to full scale All output ranges, DAC register loaded to full scale TA = 25°C TA = 25°C, external 1.25 V reference option TA = 25°C, external 2.5 V reference option For specified performance, external 1.25 V reference option External 2.5 V reference option TA = 25°C, reference output on Internal RSET resistor TA = 25°C, 0.1 Hz to 10 Hz TA = 25°C , 1 kHz TA = 25°C, 10 kHz TA = 25°C, due to change in AVDD Data Sheet Parameter1 LOGIC INPUTS Input Current Input Voltage Input Low Voltage (VINL) Input High Voltage (VINH) Pin Capacitance LOGIC OUTPUTS SDO Pin Output Low Voltage (VOL) Output High Voltage (VOH) AD5770R Min −3.5 +3.5 μA 0.3 × IOVDD V pF 0.4 4 V V V V IOVDD – 0.4 700 880 1.04 −1.8 −1.3 −0.9 Open-drain enabled4, 10 kΩ pull-up resistor to IOVDD Open-drain enabled4, 10 kΩ pull-up resistor to IOVDD mV mV V mV/°C mV/°C mV/°C μA TA = 25°C, internal bias current TA = 25°C, 100 μA external bias current TA = 25°C, 200 μA external bias current Internal bias current 100 μA external bias current 200 μA external bias current Temperature diode bias current is supplied externally 125 °C 150 4 20 °C °C °C Junction temperature, warning flag activated Junction temperature, thermal shutdown 100 200 2.9 −3.0 0.8 AVEE 5.5 0 AVDD − 0.4 0 32 −16 125 2.9 1.65 Per pin pF 0.4 THERMAL ALARMS Overheat Warning Temperature Test Conditions/Comments CS, SCLK, SDI, LDAC, RESET Per pin V IOVDD − 0.4 Temperature Coefficient Overheat Shutdown Temperature Overheat Warning Hysteresis Overheat Shutdown Hysteresis POWER REQUIREMENTS Analog Power Supply Voltage AVDD AVEE PVDD0 to PVDD5 PVEE0 Analog Power Supply Current AVDD Supply Current AVEE Supply Current PVDD0 to PVDD5 Supply Current Digital Power Supply Voltage DVDD IOVDD Unit 4.5 TEMPERATURE MEASUREMENT DIODE Diode Output Voltage External Bias Current5 Max 0.7 × IOVDD Floating State Output Capacitance ALARM Pin Output Low Voltage (VOL) Output High Voltage (VOH) Typ 5.5 5.5 Rev. A | Page 5 of 59 V V V V AVDD must be equal to DVDD 2.5 V ≤ PVDD − AVEE ≤ 5.5 V AVDD − PVEE0 ≤ 5.5 V mA mA μA Internal voltage reference option selected V V AVDD must be equal to DVDD AD5770R Parameter1 Digital Power Supply Current DVDD Supply Current IODVDD Supply Current Power Consumption Data Sheet Min Typ Max 1.1 200 110 Unit Test Conditions/Comments mA nA mW All outputs at 0 A, nominal supplies 1 See the Terminology section. See the Precision RSET Resistor section for more information about the internal and external RSET resistors. When sourcing current, the output compliance voltage is the maximum voltage at the IDACx pin, for which the output current is within 0.1% of the measured fullscale range. When sinking current on Channel 0, the output compliance voltage is the minimum voltage at the IDAC0 pin, for which the output current is within 0.1% of the measured zero-scale current. 4 The active low ALARM pin can be configured as an open drain. Refer to the ALARM section. 5 The internal temperature sensing diode can be biased with an internal or external current. Refer to the Internal Die Temperature Monitoring section. 2 3 AC PERFORMANCE CHARACTERISTICS AVDD = DVDD = 2.9 V to 5.5 V, PVDD = 0.8 V to AVDD − 0.4 V, AVEE = −3.0 V to 0 V, 2.5 V ≤ PVDD − AVEE ≤ 5.5 V, IOVDD = 1.65 V to 5.5 V, AVEE ≤ PVEE0 ≤ 0 V, AVDD − PVEE0 ≤ 5.5 V, VREF = 1.25 V external voltage reference, TA = 25°C, unless otherwise noted. Table 2. Parameter1 DYNAMIC PERFORMANCE Output Current Settling Time Unit Test Conditions/Comments2 13 μs 10 μs Slew Rate 50 10 mA/μs mA/μs Digital-to-Analog Glitch Impulse Multiplexer Switching Glitch Digital Feedthrough Digital Crosstalk DAC-to-DAC Crosstalk 0.057 14 0.03 0.03 0.8 nA-sec pA-sec nA-sec nA-sec nA-sec Zero-scale to full-scale step settling to ±4 LSB, 0 mA to 300 mA range Zero-scale to full-scale step settling to ±4 LSB, 0 mA to 45 mA range, Channel 3, Channel 4, and Channel 5 Channel 0 , 0 mA to 300 mA range Channel 3, Channel 4, Channel 5, 0 mA to 45 mA range 1 LSB change around major carry Switching monitored channel Output Noise Spectral Density (NSD) 35 nA/√Hz 18 nA/√Hz 19 nA/√Hz 13 nA/√Hz 16 nA/√Hz 9 nA/√Hz 9 nA/√Hz 6 nA/√Hz Min Typ Max Rev. A | Page 6 of 59 Victim Channel 4, due to a 300 mA step change on Channel 0 Channel 0, 0 mA to 300 mA range, at 1 kHz, DAC register loaded to midscale Channel 1, 0 mA to 140 mA low noise range, at 1 kHz, DAC register loaded to midscale Channel 2, 0 mA to 150 mA range, at 1 kHz, DAC register loaded to midscale Channel 3, Channel 4, Channel 5, 0 mA to 100 mA range, at 1 kHz, DAC register loaded to midscale Channel 0, 0 mA to 300 mA range, at 10 kHz, DAC register loaded to midscale Channel 1, 0 mA to 140 mA low noise range, at 10 kHz, DAC register loaded to midscale Channel 2, 0 mA to 150 mA range, at 10 kHz, DAC register loaded to midscale Channel 3, Channel 4, Channel 5, 0 mA to 100 mA range, at 10 kHz, DAC register loaded to midscale Data Sheet AD5770R Parameter1 Output Noise Min PVDDx AC PSRR 1 2 Typ 900 Max Unit nA rms 180 nA rms 400 nA rms 300 nA rms −98 −87 −67 −23 −8 dB dB dB dB dB Test Conditions/Comments2 0.1 Hz to 10 Hz, Channel 0, 0 mA to 300 mA range, DAC register loaded to full scale 0.1 Hz to 10 Hz, Channel 1, 0 mA to 140 mA low noise range, DAC register loaded to full scale 0.1 Hz to 10 Hz, Channel 2, 0 mA to 150 mA range, DAC register loaded to full scale 0.1 Hz to 10 Hz, Channel 3, Channel 4, Channel 5, 0 mA to 100 mA range, DAC register loaded to full scale 100 Hz 1 kHz 10 kHz 1000 kHz 3000 kHz See the Terminology section. Temperature range is −40°C to +105°C, typically at 25°C. TIMING SPECIFICATIONS Table 3. Parameter t1 1.65 V ≤ IOVDD ≤ 5.5 V 50 100 20 20 25 10 10 0 250 30 40 5 90 40 100 10 100 10 100 t2 t3 t4 t5 t6 t7 t71 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 1 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min ns min ns min ns max Test Conditions/Comments SCLK cycle time, write operation. SCLK cycle time, read operation. SCLK high time. SCLK low time. CS to SCLK rising edge setup time. Data setup time. Data hold time. SCLK rising edge to CS rising edge. LDAC idle high mode. SCLK rising edge to CS rising edge. LDAC idle low mode. CS high time. CS rising edge to SCLK rising edge. SCLK rising edge to CS falling edge. SDO data valid from SCLK falling edge. CS rising edge to SDO disabled. LDAC pulse width low. LDAC falling edge to CS rising edge. SCLK rising edge to LDACfalling edge. RESET minimum pulse width low. RESET pulse activation time. t7 ≥ 250 ns only applies to the first SCLK rising edge to CS rising edge after LDAC (IDLEL LOW) falling edge. t7 ≥ 0 ns applies for all other SCLK rising edge to CS rising edge. Refer to Figure 3. Table 4. LDAC Idle Low Timing Parameter t1 1.65 V ≤ IOVDD ≤ 5.5 V 250 Unit ns min t2 t3 0 10 ns min ns min Test Conditions/Comments SCLK rising edge to CS rising edge. The first SCLK rising edge to CS rising edge after LDAC idle low falling edge. SCLK rising edge to CS rising edge. LDAC falling edge to CS rising edge. Rev. A | Page 7 of 59 AD5770R Data Sheet TIMING DIAGRAMS t1 SCLK t4 t2 t10 t7 t3 t9 t8 CS t5 t6 SDI R/W A6 A5 A1 A0 Dn Dn – 1 D1 Dn – 1 D1 D0 t11 Dn SDO t12 D0 t15 t13 LDAC (IDLE HIGH) t14 LDAC (IDLE LOW) RESET t16 16128-002 IDACx t17 Figure 2. Timing Diagram (Not to Scale) SCLK t1 t2 t3 LDAC (IDLE LOW) Figure 3. LDAC Idle Low Timing Diagram Rev. A | Page 8 of 59 16128-003 CS Data Sheet AD5770R ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted THERMAL RESISTANCE Table 5. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Parameter AVDD to DVDD AVDD to AGND AVDD to PVDDx AVDD to AVEE AVEE to AGND PVEE0 to AGND AVEE to PVEE0 PVDDx to AGND PVDDx to AVEE AVDD to PVEE0 VREF_IO to AGND IDAC0 to PVEE0 IDAC1 through IDAC5 to AGND DVDD to DGND IOVDD to DGND REFGND to AGND AGND to DGND Digital Inputs to DGND1 Digital Outputs to DGND2 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature, TJMAX Power Dissipation Lead Temperature, Soldering Reflow 1 2 Rating −0.3 V to +0.3 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +10 V +0.3 V to −3.5 V +0.3 V to −3.5 V −3 .0 V to +0.3 V −0.3 V to +6.5 V −0.3 V to +8.5 V −0.3 V to +6.5 V −0.3 V to AVDD + 0.3 V −0.3 V to +6.5 V −0.3 V to PVDDx + 0.3 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to IOVDD + 0.3 V −40°C to +105°C −65°C to +150°C 150°C (TJMAX – TA)/θJA 260°C, as per JEDEC J-STD-020 θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. Table 6. Thermal Resistance Package Type CB-49-5 1 θJA 301 Unit °C/W Thermal impedance simulated values are based on JEDEC 2S2P thermal test board with 16 thermal vias. See JEDEC JESD51. ESD CAUTION Digital inputs include SCLK, SDI, RESET, and LDAC. Digital outputs include SDO and ALARM Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional soperation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 9 of 59 AD5770R Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 2 3 4 5 6 7 A IDAC0 PVDD0 IDAC2 PVDD2 CDAMP_ IDAC1 PVDD1 IDAC1 B IDAC0 PVDD0 PVDD5 CDAMP_ IDAC2 PVDD4 PVDD1 IDAC1 C PVEE0 CDAMP_ IDAC0 IDAC5 AGND IDAC4 PVDD3 IDAC3 D DNC AVEE CDAMP_ IDAC5 AVEE CDAMP_ IDAC4 DNC CDAMP_ IDAC3 E IREF REFGND DNC AGND AVDD DNC CS F VREF_IO ALARM DGND DGND DVDD LDAC SDI G CREF SDO IOVDD SCLK RESET MUX_OUT CREG TOP VIEW (BALL SIDE DOWN) Not to Scale NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS. 16128-004 AD5770R 1 Figure 4. Pin Configuration Table 7. Pin Function Descriptions Pin No. A1, B1 Mnemonic IDAC0 Type1 AO A2, B2 A3 A4 A5 A6, B6 A7, B7 B3 B4 B5 C1 PVDD0 IDAC2 PVDD2 CDAMP_IDAC1 PVDD1 IDAC1 PVDD5 CDAMP_IDAC2 PVDD4 PVEE0 S AO S AI S AO S AI S S C2 C3 C4, E4 C5 C6 C7 D1, D6, E3, E6 D2, D4 CDAMP_IDAC0 IDAC5 AGND IDAC4 PVDD3 IDAC3 DNC AVEE AI AO S AO S AO DNC S D3 D5 D7 CDAMP_IDAC5 CDAMP_IDAC4 CDAMP_IDAC3 AI AI AI Description Current Output of Channel 0 is Available on this Pin. Channel 0 sinks up to 60 mA and sources up to 300 mA. Power Supply for IDAC0. Current Output of Channel 2 is Available on this Pin. Channel 2 sources up to 150 mA. Power Supply for IDAC2. Damping Capacitor for IDAC1. Connect a 10 nF capacitor between this pin and the PVDD1 supply. Power Supply for IDAC1. Current Output of Channel 1 is Available on this Pin. Channel 1 sources up to 250 mA. Power Supply for IDAC5. Damping Capacitor for IDAC2. Connect a 10 nF capacitor between this pin and the PVDD2 supply. Power Supply for IDAC4. Power Supply Return for IDAC0 Sink. When sinking this current on Channel 0, up to 60 mA flows out of PVEE0. Damping Capacitor for IDAC0. Connect a 10 nF capacitor between this pin and the PVDD0 supply. Current Output of Channel 5 is Available on this Pin. Channel 5 sources up to 100 mA. Analog Supply Ground Pin. Current Output of Channel 4 is Available on this Pin. Channel 4 sources up to 100 mA. Power Supply for IDAC3. Current Output of Channel 3 is Available on this Pin. Channel 3 sources up to 100 mA. Do Not Connect. Do not connect to this pin. Negative Power Supply. AVEE must be between −3 V and 0 V. This pin supplies the low side voltage for biasing some analog circuit blocks. Damping Capacitor for IDAC5. Connect a 10 nF capacitor between this pin and the PVDD5 supply. Damping Capacitor for IDAC4. Connect a 10 nF capacitor between this pin and the PVDD4 supply. Damping Capacitor for IDAC3. Connect a 10 nF capacitor between this pin and the PVDD3 supply. Rev. A | Page 10 of 59 Data Sheet AD5770R Pin No. E1 Mnemonic IREF Type1 AI/O E2 REFGND S E5 AVDD S E7 CS DI F1 VREF_IO AI/O F2 ALARM DO F3, F4 F5 DGND DVDD S S F6 LDAC DI F7 SDI DI G1 CREF AI/O G2 RESET DI G3 MUX_OUT AI/O G4 CREG AI/O G5 SDO DO G6 IOVDD S G7 SCLK DI 1 Description External Resistor Pin for Reference Current Generation (Optional). When using an external RSET resistor, connect this pin directly to REFGND via a low drift, 2.5 kΩ external resistor. Reference Supply Ground Pin. Connect this pin with a low impedance path to AGND. If using an external resistor, the low side of the RSET resistor must be connected to REFGND before the connection to AGND. Analog Power Supply. AVDD must be between 2.9 V and 5.5 V. This pin supplies power to the analog circuit blocks on the device. This pin must be at the same potential as DVDD. Active Low Control Input. CS is used to frame data during a SPI transaction. When CS is low, data is transferred on the rising edges of SCLK. Voltage Reference Input/Output. When the internal reference is enabled, the buffered 1.25 V reference voltage can be made available on this pin. When the internal reference is disabled, an external reference must be applied to this pin. The external reference voltage must be 1.25 V or 2.5 V. Active Low Output. When ALARM goes low, this alerts the user of a change in the status register. User must read the status register to deassert this pin. Digital Power Supply Ground. Digital Power Supply. DVDD must be between 2.9 V and 5.5 V. This pin supplies power to the digital core and internal oscillator blocks on the device. This pin must be at the same potential as AVDD. Logic Input. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, allowing any or all DAC outputs to update synchronously. Alternatively, this pin can be tied low. Serial Data Input. Data to be written to the device is provided on this input and is clocked into the register on the rising edge of SCLK. Filter Capacitor for Voltage Reference. A 0.1 μF capacitor connected from the CREF pin to AGND is recommended to achieve the specified performance from the AD5770R. Active Low Reset Input. Tie this pin high for normal operation. Asserting this pin low resets the AD5770R to the default configuration. Analog Output. An external analog-to-digital converter (ADC) reads voltages on this pin for diagnostic purposes. Use external excitation current for the temperature sensing diode and force the current on this pin. Filter Capacitor for Internal Regulator. A 1 μF capacitor connected from the CREG pin to AGND is recommended to achieve the specified performance from the AD5770R. Serial Data Output. A read back operation provides data on this output pin as a serial data stream. Data is clocked out on the falling edge of SCLK and is valid on the rising edge of SCLK. Logic Power Supply. IOVDD must be between 1.65 V and 5.5 V. This pin supplies power to the serial interface circuit blocks on the device. Serial Clock Input. Data is clocked into the input shift register on the rising edge of the serial clock input. Data can be transferred at rates up to 20 MHz when writing to the AD5770R. This pin has a maximum speed of 10 MHz when performing a read operation from the AD5770R. AO is analog output, S is power, AI is analog input, DNC is do not connect, AI/O is analog input and output, DI is digital input, and DO is digital output. Rev. A | Page 11 of 59 AD5770R Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.6 1.0 0.4 0.8 0.6 0.2 0.4 0.2 INL (LSB) INL (LSB) 0 –0.2 –0.4 0 –0.2 –0.4 –0.6 –0.6 –0.8 –1.2 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE 0.2 0.2 0 0 –0.2 –0.2 INL (LSB) 0.4 –0.4 –0.6 –0.8 –1.0 –1.0 –1.2 –1.2 6000 8000 10000 12000 14000 16000 18000 CODE –1.4 2000 4000 6000 8000 10000 12000 14000 16000 18000 Figure 9. INL Error vs. DAC Code (Channel 4, 0 mA to 100 mA Range) 0.8 0.8 0.6 0.6 0.4 0.4 0.2 INL (LSB) 0.2 0 –0.2 –0.4 0 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE Figure 7. INL Error vs. DAC Code (Channel 2, 0 mA to 150 mA Range) –1.2 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE Figure 10. INL Error vs. DAC Code (Channel 5, 0 mA to 100 mA Range) Rev. A | Page 12 of 59 16128-105 –1.0 16128-102 INL (LSB) 0 CODE Figure 6. INL Error vs. DAC Code (Channel 1, 0 mA to 250 mA Range) –1.0 8000 10000 12000 14000 16000 18000 –0.6 –0.8 4000 6000 –0.4 16128-101 INL (LSB) 0.6 0.4 2000 4000 Figure 8. INL Error vs. DAC Code (Channel 3, 0 mA to 100 mA Range) 0.6 0 2000 CODE Figure 5. INL Error vs. DAC Code (Channel 0, 0 mA to 300 mA Range) –1.4 0 16128-104 0 16128-100 –1.0 –1.2 16128-103 –0.8 –1.0 AD5770R 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 Figure 11. DNL Error vs. DAC Code (Channel 0, 0 mA to 300 mA Range) 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE 1.0 0.8 0.8 0.6 0.6 0.4 DNL (LSB) 0.4 0.2 0 –0.2 0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE Figure 12. DNL Error vs. DAC Code (Channel 1, 0 mA to 250 mA Range) 0.8 0.6 0.6 0.4 0.4 0.2 0.2 DNL (LSB) 0.8 –0.4 –0.6 –0.8 –1.0 6000 8000 10000 12000 14000 16000 18000 CODE 16128-108 –0.8 –1.0 4000 Figure 13. DNL Error vs. DAC Code (Channel 2, 0 mA to 150 mA Range) 8000 10000 12000 14000 16000 18000 –0.2 –0.6 2000 6000 0 –0.4 0 4000 Figure 15. DNL Error vs. DAC Code (Channel 4, 0 mA to 100 mA Range) 1.0 –0.2 2000 CODE 1.0 0 0 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE 16128-111 0 16128-107 –1.0 16128-110 –0.8 –0.8 –1.0 0 Figure 14. DNL Error vs. DAC Code (Channel 3, 0 mA to 100 mA Range) 1.0 DNL (LSB) –0.2 –0.4 CODE DNL (LSB) 0 16128-109 DNL (LSB) 1.0 16128-106 DNL (LSB) Data Sheet Figure 16. DNL Error vs. DAC Code (Channel 5, 0 mA to 100 mA Range) Rev. A | Page 13 of 59 AD5770R Data Sheet 1.0 1.0 +105°C +85°C +25°C –40°C 1.5 1.0 0.5 0.5 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE –2.0 Figure 17. INL Error vs. DAC Code for Various Temperatures (Channel 0, 0 mA to 300 mA Range) 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE Figure 20. INL Error vs. DAC Code for Various Temperatures (Channel 3, 0 mA to 100 mA Range) 1.0 2.0 +105°C +85°C +25°C –40°C 1.5 1.5 1.0 0.5 0.5 INL (LSB) 1.0 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE –2.0 16128-113 –2.0 +105°C +85°C +25°C –40°C Figure 18. INL Error vs. DAC Code for Various Temperatures (Channel 1, 0 mA to 250 mA Range) +105°C +85°C +25°C –40°C 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE 16128-116 –2.0 INL (LSB) 0 16128-115 INL (LSB) 1.0 16128-112 INL (LSB) 1.5 Figure 21. INL Error vs. DAC Code for Various Temperatures (Channel 4, 0 mA to 100 mA Range) 2.0 2.0 1.5 1.5 1.0 1.0 INL (LSB) INL (LSB) 0.5 0.5 0 0 –0.5 –1.0 –0.5 –1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE –2.5 16128-114 –1.5 +105°C +85°C +25°C –40°C –2.0 Figure 19. INL Error vs. DAC Code for Various Temperatures (Channel 2, 0 mA to 150 mA Range) 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE 16128-117 +105°C +85°C +25°C –40°C –1.0 Figure 22. INL Error vs. DAC Code for Various Temperatures (Channel 5, 0 mA to 100 mA Range) Rev. A | Page 14 of 59 AD5770R 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 DNL (LSB) 0 –0.2 –0.4 4000 6000 8000 10000 12000 14000 16000 18000 Figure 23. DNL Error vs. DAC Code for Various Temperatures (Channel 0, 0 mA to 300 mA Range) 4000 6000 8000 10000 12000 14000 16000 18000 CODE 1.0 +105°C +85°C +25°C –40°C 0.6 0.8 0.6 0.4 0.2 0.2 DNL (LSB) 0.4 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE –1.0 16128-119 0 Figure 24. DNL Error vs. DAC Code for Various Temperatures (Channel 1, 0 mA to 250 mA Range) +105°C +85°C +25°C –40°C 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE 16128-122 0.8 Figure 27. DNL Error vs. DAC Code for Various Temperatures (Channel 4, 0 mA to 100 mA Range) 1.0 1.0 +105°C +85°C +25°C –40°C 0.8 0.6 0.8 0.6 0.4 0.2 0.2 DNL (LSB) 0.4 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE –1.0 16128-120 –1.0 2000 Figure 26. DNL Error vs. DAC Code for Various Temperatures (Channel 3, 0 mA to 100 mA Range) 1.0 –1.0 0 16128-121 2000 –0.8 –1.0 16128-118 0 CODE DNL (LSB) –0.2 –0.6 +105°C +85°C +25°C –40°C –0.8 DNL (LSB) 0 –0.4 –0.6 –1.0 +105°C +85°C +25°C –40°C Figure 25. DNL Error vs. DAC Code for Various Temperatures (Channel 2, 0 mA to 150 mA Range) +105°C +85°C +25°C –40°C 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE 16128-123 DNL (LSB) Data Sheet Figure 28. DNL Error vs. DAC Code for Various Temperatures (Channel 5, 0 mA to 100 mA Range) Rev. A | Page 15 of 59 AD5770R Data Sheet 70 50 40 30 20 0.40 0.35 0.30 0 20 40 60 80 100 TEMPERATURE (°C) 0.20 –40 16128-124 –20 0.035 TOTAL UNADJUSTED ERROR (% FSR) FULL-SCALE ERROR (% FSR) 20 40 60 80 100 Figure 32. Gain Error vs. Temperature CH0 CH1 CH2 CH3 CH4 CH5 0.45 0 TEMPERATURE (°C) Figure 29. Zero-Scale Error vs. Temperature 0.50 –20 16128-127 0.25 10 0 –40 CH0 CH1 CH2 CH3 CH4 CH5 0.45 GAIN ERROR (% FSR) 60 ZERO-SCALE ERROR (µA) 0.50 CH0 CH1 CH2 CH3 CH4 CH5 0.40 0.35 0.30 +105°C +85°C 0.030 +25°C –40°C 0.025 0.020 0.015 0.010 0.005 0 –0.005 0.25 20 40 60 80 100 TEMPERATURE (°C) Figure 30. Full-Scale Error vs. Temperature TOTAL UNADJUSTED ERROR (% FSR) –40 0 20 40 60 TEMPERATURE (°C) 80 4000 6000 8000 10000 12000 14000 16000 CODE 100 16128-126 OFFSET ERROR (µA) 10 –20 2000 0.05 60 –90 –40 0 Figure 33. Total Unadjusted Error vs. DAC Code for Various Temperatures (Channel 0, 0 mA to 300 mA Range) CH0 CH1 CH2 CH3 CH4 CH5 110 –0.015 +105°C +85°C +25°C 0.03 0.01 –0.01 –0.03 –0.05 0 2000 4000 6000 8000 CODE Figure 31. Offset Error vs. Temperature 10000 12000 14000 16000 16128-149 0 16128-125 –20 16128-148 –0.010 0.20 –40 Figure 34. Total Unadjusted Error vs. DAC Code for Various Temperatures (Channel 1, 0 mA to 250 mA Range) Rev. A | Page 16 of 59 Data Sheet AD5770R 0 –0.005 –0.010 –0.015 +105°C +85°C +25°C –40°C –0.020 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE 0 –0.01 –0.02 –0.03 0 1.6 0.02 1.4 4000 6000 8000 10000 12000 14000 16000 1.2 OUTPUT (V) 0.01 0 –0.01 –0.02 1.0 0.8 0.6 CH1 (0mA TO 250mA) CH0 (0mA TO 300mA) CH0 (–60mA TO +300mA) 0.4 +105°C +85°C +25°C –40°C 0 2000 4000 6000 8000 10000 12000 14000 16000 0.2 WITH 5Ω LOAD 0 –10 0 10 20 30 40 Figure 36. Total Unadjusted Error vs. DAC Code for Various Temperatures (Channel 3, 0 mA to 100 mA Range) Figure 39. Full-Scale Settling Time (Rising Step) 1.6 0.005 1.4 CH1 (0mA TO 250mA) CH0 (0mA TO 300mA) CH0 (–60mA TO +300mA) 0 1.2 WITH 5Ω LOAD –0.005 1.0 OUTPUT (V) 0.010 –0.010 –0.015 0.8 0.6 0.4 –0.020 0.2 –0.025 +105°C +85°C 0 2000 4000 6000 8000 CODE +25°C –40°C 10000 12000 14000 16000 16128-152 –0.030 50 TIME (µs) 16128-178 –0.03 CODE TOTAL UNADJUSTED ERROR (% FSR) 2000 +25°C –40°C Figure 38. Total Unadjusted Error vs. DAC Code for Various Temperatures (Channel 5, 0 mA to 100 mA Range) 0.03 –0.04 +105°C +85°C CODE 16128-151 TOTAL UNADJUSTED ERROR (% FSR) Figure 35. Total Unadjusted Error vs. DAC Code for Various Temperatures (Channel 2, 0 mA to 150 mA Range) 0.01 Figure 37. Total Unadjusted Error vs. DAC Code for Various Temperatures (Channel 4, 0 mA to 100 mA Range) Rev. A | Page 17 of 59 0 –10 0 10 20 30 TIME (µs) Figure 40. Full-Scale Settling Time (Falling Step) 40 16128-179 –0.025 0.02 16128-153 TOTAL UNADJUSTED ERROR (% FSR) 0.03 16128-150 TOTAL UNADJUSTED ERROR (% FSR) 0.005 AD5770R Data Sheet 0.35 0.050 0.045 0.30 0.15 0.10 +105°C +85°C +25°C –40°C 0.05 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 PVDD0 HEADROOM (V) 0.035 0.030 0.025 0.020 0.015 0.010 +105°C +85°C +25°C –40°C 0.005 0 Figure 41. CH0 Output Current vs. PVDD0 Headroom for Various Temperatures 0 0.05 0.10 0.15 0.20 0.25 PVDD3 HEADROOM (V) 16128-184 CH3 OUTPUT CURRENT (A) 0.20 16128-181 CH0 OUTPUT CURRENT (A) 0.040 0.25 Figure 44. CH3 Output Current vs. PVDD3 Headroom for Various Temperatures 0.16 0.050 0.045 0.14 0.08 0.06 0.04 +105°C +85°C +25°C –40°C 0.02 0 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 PVDD1 HEADROOM (V) 0.035 0.030 0.025 0.020 0.015 0.010 +105°C +85°C +25°C –40°C 0.005 0 Figure 42. CH1 Output Current vs. PVDD1 Headroom for Various Temperatures 0 0.05 0.10 0.15 0.20 0.25 PVDD4 HEADROOM (V) 16128-185 CH4 OUTPUT CURRENT (A) 0.10 16128-182 CH1 OUTPUT CURRENT (A) 0.040 0.12 Figure 45. CH4 Output Current vs. PVDD4 Headroom for Various Temperatures 0.06 0.050 0.045 0.04 0.03 0.02 +105°C +85°C +25°C –40°C 0.01 0 0 0.05 0.10 0.15 PVDD2 HEADROOM (V) 0.20 0.25 0.035 0.030 0.025 0.020 0.015 0.010 +105°C +85°C +25°C –40°C 0.005 0 Figure 43. CH2 Output Current vs. PVDD2 Headroom for Various Temperatures 0 0.05 0.10 0.15 PVDD5 HEADROOM (V) 0.20 0.25 16128-186 CH5 OUTPUT CURRENT (A) 0.040 16128-183 CH2 OUTPUT CURRENT (A) 0.05 Figure 46. CH5 Output Current vs. PVDD5 Footroom for Various Temperatures Rev. A | Page 18 of 59 AD5770R 900k +105°C +85°C +25°C –40°C 0.30 700k 0.25 600k 500k 0.20 400k 0.15 300k 0.10 200k 0.05 100k 0.05 0.10 0.15 0.20 0.25 0.30 0.35 PVEE0 HEADROOM (V) Figure 47. CH0 Output Current vs. PVEE0 Footroom for Various Temperatures CH0 (0mA TO 300mA) CH0 (–60mA TO +300mA) CH1 (0mA TO 140mA, LOW HEADROOM) CH1 (0mA TO 140mA, LOW NOISE) CH1 (0mA TO 250mA) CH2 (0mA TO 55mA) CH2 (0mA TO 150mA) –20 CH5 (0mA TO 45mA) CH5 (0mA TO 100mA) CH4 (0mA TO 45mA) CH4 (0mA TO 100mA) CH3 (0mA TO 45mA) CH3 (0mA TO 100mA) CH2 (0mA TO 55mA) 3 2 OUTPUT CURRENT (µA) 0 –40 –60 –80 CH3 (0mA TO CH3 (0mA TO CH4 (0mA TO CH4 (0mA TO CH5 (0mA TO CH5 (0mA TO –100 –120 45mA) 100mA) 45mA) 100mA) 45mA) 100mA) 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 0 –1 –2 –4 0dB = 1A/V 1 1 –3 –5 16128-188 AC PSRR (dB) Figure 49. DC Output Impedance vs. Full-Scale Output Current (All Ranges) 4 20 –140 16128-190 0 0 20 40 60 80 100 TIME (Seconds) Figure 50. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth, (CH0 0 mA to 300 mA Range) Figure 48. AC PSRR vs. Frequency (All Ranges) Rev. A | Page 19 of 59 16128-191 –0.07 16128-187 –0.06 CH2 (0mA TO 150mA) –0.05 0 CH1 (0mA TO 250mA) CH0 (0mA TO 300mA) –0.04 CH0 (–60mA TO +300mA) –0.03 CH1 (0mA TO 140mA, LOW HEADROOM) 0 –0.02 CH1 (0mA TO 140mA, LOW NOISE) –0.01 CH0 OUTPUT CURRENT (A) DC OUTPUT IMPEDANCE (Ω) 800k 0 0.35 DC OUTPUT IMPEDANCE FULL-SCALE OUTPUT CURRENT FULL-SCALE OUTPUT CURRENT (A) Data Sheet AD5770R Data Sheet CH3 (0mA TO CH3 (0mA TO CH4 (0mA TO CH4 (0mA TO CH5 (0mA TO CH5 (0mA TO 1n 1 10 100 1k 3.5 3.0 200 2.5 100 2.0 0 CS 20MHz SCLK 0x0000 TO 0x3FFF 20MHz SCLK 0x3FFF TO 0x0000 20MHz SCLK 0x0000 TO 0x2AAA –100 –200 –300 10k 100k FREQUENCY (Hz) –400 1.5 2.0 3.5 IDAC0 OUTPUT CURRENT, AC COUPLED (µA) 450 1µ 100n 10 100 1k 10k 100k FREQUENCY (Hz) 350 250 150 –50 –150 191.2 196.2 201.2 206.2 211.2 TIME (µs) Figure 55. DAC to DAC Crosstalk (Victim Channel Zero) 1.2530 4.0 0.007 3.5 1.2525 3.0 0.005 1.2520 1.2515 1.2510 1.2505 VDD = 5.5V VDD = 3.3V VDD = 2.9V –0.003 –0.001 0.001 0.003 LOAD CURRENT (I) 2.0 0.003 RLOAD IDAC0 = 5Ω RLOAD IDAC1 = 5Ω RLOAD IDAC2 = 5Ω RLOAD IDAC3 = 5Ω 0.001 –0.003 220 Figure 53. VREF_IO Voltage vs. Load Current RLOAD IDAC4 = 5Ω RLOAD IDAC5 = 5Ω CS 221 222 223 224 225 TIME (µs) Figure 56. Analog Crosstalk Rev. A | Page 20 of 59 1.0 0.5 –0.001 0.005 1.5 CS (V) VOLTAGE (V) 2.5 16128-194 VREF_IO (V) FS ZS FS ZS FS ZS FS ZS FS ZS 50 Figure 52. VREF_IO Output NSD vs. Frequency 1.2500 –0.005 0 –0.5 4.5 4.0 ATTACK CH1 ZS TO ATTACK CH1 FS TO ATTACK CH2 ZS TO ATTACK CH2 FS TO ATTACK CH3 ZS TO ATTACK CH3 FS TO ATTACK CH4 ZS TO ATTACK CH4 FS TO ATTACK CH5 ZS TO ATTACK CH5 FS TO –250 186.2 16128-193 1 0.5 Figure 54. Digital Feedthrough 10µ NOISE SPECTRAL DENSITY (V/√Hz) 3.0 1.0 TIME (µs) Figure 51. Output NSD vs. Frequency (All Ranges) 10n 0.1 2.5 1.5 226 0 –0.5 227 16128-197 100p 45mA) 100mA) 45mA) 100mA) 45mA) 100mA) 300 16128-195 10n 4.0 CS (V) 100n 400 16128-196 1µ OUTPUT CURRENT (µA) CH0 (0mA TO 300mA) CH0 (–60mA TO +300mA) CH1 (0mA TO 140mA, LOW HEADROOM) CH1 (0mA TO 140mA, LOW NOISE) CH1 (0mA TO 250mA) CH2 (0mA TO 55mA) CH2 (0mA TO 150mA) 16128-192 NOISE SPECTRAL DENSITY (A/√Hz) 10µ AD5770R 600 4.0 1.2 500 3.5 1.1 1.5 200 –100 1.0 1.0 –200 –500 2.0 2.5 3.0 3.5 0.7 EXTERNAL BIAS (100µA) EXTERNAL BIAS (200µA) INTERNAL BIAS (10µA) 0.5 0.4 –50 16128-198 –400 0.8 0.6 0.5 ATTACK CH4 ZS TO FS ATTACK CH4 FS TO ZS ATTACK CH5 ZS TO FS 0 ATTACK CH5 FS TO ZS CS –0.5 4.0 4.5 5.0 –300 0.9 TIME (µs) –30 –10 10 30 50 70 90 110 TEMPERATURE (°C) 16128-202 0 300 DIODE VOLTAGE (V) 100 ATTACK CH0 ZS TO FS 3.0 ATTACK CH0 FS TO ZS ATTACK CH1 ZS TO FS ATTACK CH1 FS TO ZS 2.5 ATTACK CH2 ZS TO FS ATTACK CH2 FS TO ZS 2.0 CS (V) 400 Figure 60. Diode Voltage vs. Temperature Figure 57. Digital Crosstalk 4.5 3.5 VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –200 0 200 400 600 800 1000 TIME (ns) COOLING DOWN HEATING UP 0 110 16128-200 RESET RLOAD IOUT3 = 10Ω 1 120 130 140 150 170 160 DIE TEMPERATURE (°C) Figure 58. Reset Glitch 16128-203 OVERTEMPERATURE DETECTION FLAG 4.0 Figure 61. Overheat Warning 1.2535 COOLING DOWN HEATING UP 1.2525 1.2520 1.2510 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) 110 16128-201 1.2515 Figure 59. VREF vs. Temperature for Devices for Five AD5770R Devices 1 0 110 115 120 125 130 135 140 DIE TEMPERATURE (°C) Figure 62. Overheat Shutdown Rev. A | Page 21 of 59 145 150 155 16128-204 THERMAL SHUTDOWN FLAG 1.2530 VREF (V) IDAC OUTPUT, AC COUPLED (µA) Data Sheet Data Sheet 4.0 33.4 3.5 33.2 3.0 33.0 2.5 32.6 1.0 32.2 0.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) 0 2.0 1.15 33.0 1.14 32.5 IAVDD (mA) 33.5 1.11 31.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) 16128-206 31.5 2.5 Figure 64. DVDD Supply Current (IDVDD) vs. Supply Voltage for Five AD5770R Devices 4.0 3.5 3.0 2.5 2.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) 16128-207 1.5 1.0 1.0 3.5 4.0 4.5 5.0 5.5 6.0 32.0 1.12 1.10 2.0 3.0 Figure 66. IOVDD Supply Current vs. IOVDD Supply Voltage for Five AD5770R Devices 1.16 1.13 2.5 SUPPLY VOLTAGE (V) Figure 63. AVDD Supply Current (IAVDD) vs. Supply Voltage for Five AD5770R Devices IDVDD (mA) 1.5 32.4 32.0 2.0 IOVDD (µA) 2.0 Figure 65. IOVDD Supply Current vs. IOVDD Supply Voltage for Five AD5770R Devices Rev. A | Page 22 of 59 30.5 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) Figure 67. IAVDD vs. Temperature for Ten AD5770R Devices 110 16128-209 32.8 16128-208 IOVDD (µA) 33.6 16128-205 IAVDD (mA) AD5770R Data Sheet AD5770R 1.24 1.75 1.22 1.20 1.73 IDVDD (µA) 1.16 1.14 1.12 1.71 1.69 1.10 1.08 1.67 1.04 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) 110 Figure 68. IDVDD vs. Temperature for Ten AD5770R Devices 1.65 –40 –20 0 20 40 60 TEMPERATURE (°C) Figure 69. IDVDD vs. Temperature Rev. A | Page 23 of 59 80 100 16128-211 1.06 16128-210 IDVDD (mA) 1.18 AD5770R Data Sheet TERMINOLOGY TUE Total unadjusted error is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Typical INL error vs. DAC code plots are shown in Figure 5 to Figure 10. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL error vs. DAC code plots are shown in Figure 11 to Figure 16. Zero-Scale Error Zero-scale error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Zero code error is expressed in μA. Zero-Scale Error Temperature Coefficient Zero code error drift is a measure of the change in zero code error with a change in temperature. It is expressed in nA/°C. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % FSR. Gain Error Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/°C. Offset Error Offset error is a measurement of the difference between IOUTx (actual) and IOUTx (ideal), expressed in μA, in the linear region of the transfer function. Offset error can be negative or positive. Offset Error Drift Offset error drift is a measurement of the change in offset error with a change in temperature. It is expressed in μA/°C. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in IOUTx to a change in AVDD for a full-scale output of the DAC. It is measured in μA/V. Output Settling Time Output settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a zero-scale to full-scale input change and is measured from the falling edge of LDAC. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nA-sec, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x1FFF to 0x2000 for the AD5770R). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nA-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC when monitoring another DAC maintained at midscale. It is expressed in nA-sec. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nA-sec. DAC to DAC Crosstalk DAC to DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa), using the write to and update commands when monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nA-sec. Output Noise Spectral Density Output noise spectral density is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nA/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nA/√Hz. Multiplexer Switching Glitch The multiplexer switching glitch is a measure of the impulse injected into the analog output of the DAC when the monitor mux is changed to monitor a different channel. AC Power Supply Rejection Ratio (AC PSRR) AC power supply rejection ratio is a measure of the rejection of the output current to ac changes in the power supplies applied to the DAC. AC PSRR is measured for a given amplitude and frequency change in power supply voltage and is expressed in decibels. Rev. A | Page 24 of 59 Data Sheet AD5770R THEORY OF OPERATION DIGITAL TO ANALOG CONVERTER The AD5770R is a 6-channel, 14-bit, serial input, current output DAC capable of multiple low noise output current ranges with high power efficiency. Each of the six DACs has a segmented current steering architecture, chosen to achieve low glitch performance when changing codes. When the external 1.25 V reference option is selected, switch SWA1 is closed, switch SWA2 is open, and switch SWA3 is connected to switch SWA2. When the external 2.5 V option is selected, switch SWA1 and switch SWA2 are open and switch SWA3 is connected to the resistor divider shown in Figure 70. PRECISION REFERENCE CURRENT GENERATION Precision RSET Resistor The AD5770R requires a 500 μA precision reference current for all four DAC cores, which is generated using a 1.25 V voltage reference and a 2.5 kΩ precision RSET resistor. The AD5770R integrates an internal 1.25 V voltage reference and 2.5 kΩ internal precision RSET resistor for this function. The AD5770R can also use an external voltage reference and external precision RSET resistor for the reference current generation. Ensure that the voltage reference and the precision RSET resistor have low noise, high accuracy, and low temperature drift to help minimize the overall IDACx gain error and gain error drift. Table 1 outlines the performance specifications of the AD5770R with both the internal reference and internal RSET resistor, and an external 1.25 V reference and external precision RSET resistor. The AD5770R integrates an on-chip 2.5 kΩ (10 ppm/°C, 0.1%) precision RSET resistor that can be used for the reference current generation. If required, an external precision RSET resistor can be used for reference current generation. The user selects an internal or an external reference resistor by writing to the REFERENCE_ RESISTOR_SEL bit in the reference register. The AD5770R powers up with the internal precision RSET resistor selected. The AD5770R integrates fault protection circuitry when using an external resistor. The AD5770R automatically switches from an external to an internal resistor if the external resistor option is selected, and if the external resistance is below the minimum specification. A simplified diagram of the how the reference resistor is configured by changing switch SWB1 is shown in Figure 70. Voltage Reference SWA1 The AD5770R can use an external voltage reference for the precision reference current generation. The external reference voltage can be either 1.25 V or 2.5 V, configured by writing to the REFERENCE_VOLTAGE_SEL bits in the reference register. When the user selects the 2.5 V external voltage reference option, an internal voltage divider attenuates to achieve the 1.25 V required. VREF_IO 1.25V INTERNAL REFERENCE SWA2 SWA3 PRECISION REFERENCE CURRENT The device powers up with the external 2.5 V reference voltage option selected. CREF 100nF The AD5770R integrates a low noise, on-chip, 15 ppm/°C, 1.25 V voltage reference that can be used as the voltage reference. The on-chip reference is powered down by default and is enabled when the REFERENCE_VOLTAGE_SEL bits in the reference register select the internal reference. IREF SWB1 RSET_EXT 2.5kΩ 16128-048 RSET_INT 2.5kΩ The buffered 1.25 V internal reference voltage can be made available at the VREF_IO pin for use as a system reference. Figure 70. AD5770R Reference Options Regardless of the voltage reference scheme used, it is recommended that a 100 nF capacitor is placed between the CREF pin and AGND to achieve specified performance. A simplified diagram of the voltage reference configuration is shown in Figure 70. DIAGNOSTIC MONITORING When the internal 1.25 V reference is selected and made available on the VREF_IO pin, switch SWA1 and switch SWA2 are closed, and switch SWA3 is connected to switch SWA2. The AD5770R diagnostic feature allows the user to monitor output compliance voltages, output currents, and the internal die temperature of the device. The output compliance voltages, which are voltages representative of output current and internal die temperature, are multiplexed on-chip and are available on the MUX_OUT pin and can be measured using an external ADC. When the internal 1.25 V reference is selected but not made available on the VREF_IO pin, switch SWA1 is open, switch SWA2 is closed, and switch SWA3 is connected to switch SWA2. Diagnostics monitoring is disabled on power up and can be enabled by writing to the MON_FUNCTION bits in the MONITOR_SETUP register. Rev. A | Page 25 of 59 AD5770R Data Sheet Compliance Voltage Monitoring When the MON_FUNCTION bits in the MONITOR_ SETUP register are set to select output voltage monitoring, the output compliance voltage of the selected DAC channel is multiplexed onto the MUX_OUT pin. The IDACx channel to be monitored is selected using the MON_CH bits in the MONITOR_SETUP register. Output Current Monitoring When the MON_FUNCTION bits in the MONITOR_SETUP register select output current monitoring, a voltage representation of the output current of the selected DAC channel is multiplexed onto the MUX_OUT pin. The output current can only be monitored in current sourcing mode. The IDACx channel to be monitored is selected using the MON_CH bits in the MONITOR_ SETUP register. The output current is calculated by I SOURCE  I FULLSCALE  VMUX  VOS  400 mV (1) where: ISOURCE is the output current being sourced. IFULLSCALE is the full-scale output current. VMUX is the measured voltage at the MUX_OUT pin. VOS is the monitor offset voltage, nominally 28 mV. Uncalibrated, the current monitoring feature is accurate to within 10% of the full-scale output range. To improve the accuracy of the current monitor feature, calibrate VOS by measuring the voltage at the MUX_OUT pin at zero scale. To calibrate the 400 mV term, measure the voltage at the MUX_OUT pin at full scale. For 0 mA to 140 mA low headroom mode on Channel 1, use a value of 250 mA for IFULLSCALE. Internal Die Temperature Monitoring When temperature monitoring is selected in the MONITOR_ SETUP register, a voltage representation of the internal die temperature is multiplexed onto the MUX_OUT pin. To monitor the internal die temperature, a precision current is forced through a diode on the chip, and the voltage across the diode is multiplexed onto the MUX_OUT pin. Choose to use an external bias current for the temperature monitoring function by setting the IB_EXT_EN bit high in the MONITOR_SETUP register. The external bias current must be forced into the MUX_OUT pin. The multiplexer buffer must be bypassed when using an external bias current for temperature monitoring. Using the internal bias current with the IB_EXT_EN bit set low, calculate the internal die temperature as follows: T 700 mV  VD  25 1.8 mV (2) where: T is the die temperature (°C). VD is the diode voltage. Using an external bias current of 100 μA, with the IB_EXT_EN bit set high, the internal die temperature can be calculated as follows: T 880 mV  VD  25 1.3 mV (3) When using an external bias current of 200 μA, with the IB_EXT_EN bit set high, the die temperature can be calculated as follows: T 1.04 V  VD  25 0.9 mV (4) SERIAL INTERFACE The AD5770R has a 4-wire (CS, SCLK, SDI, and SDO) interface that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most digital signal processors (DSPs). For both read and write SPI transactions, data must be valid on the rising edge of SCLK (SCLK clock polarity = 0, SCLK clock phase = 0). For all SPI transactions, data is shifted MSB first. Communication with the device is separated into two distinct phases of operation. The first phase is the instruction phase and is used to initiate some action of the device. The second phase is the data phase where data is either passed to the device to operate on or received from the device in response to the instruction phase. Figure 71 illustrates the SPI transaction phases. CS SDI R/W 7-BIT ADDRESS DATA BYTE DATA BYTE DATA BYTE DATA BYTE Z SDO INSTRUCTION PHASE DATA PHASE 16128-049 The AD5770R integrates a voltage buffer on the multiplexer output to ease system design. The multiplexer buffer is disabled and bypassed on power up. The multiplexer buffer is enabled by setting the MUX_BUFFER bit in the MONITOR_SETUP register. Figure 71. SPI Transaction Phases Instruction Phase The instruction phase immediately follows the falling edge of CS that initiates the SPI transaction. The instruction phase consists of a read/write bit (R/W) followed by a register address word. Setting R/W high selects a read instruction. Setting R/W low selects a write instruction. The address word is 7 bits long. The register address sent in the instruction phase is used as the starting address to start writing or reading from. Refer to Table 12 and Table 13 for a full list of registers and the associated addresses. Data Phase The data phase immediately follows the instruction phase. When a write instruction is sent to the device, data is written to the register location selected. When a read instruction is sent to the device, data stored in the register location selected is shifted out on the SDO pin. Rev. A | Page 26 of 59 Data Sheet AD5770R SPI Frame Synchronization The CS pin is used to frame data during an SPI transaction. A falling edge on CS initiates a SPI transaction. Deasserting CS during a SPI transaction terminates part or all of the data transfer. If CS is deasserted (returned high) before the instruction phase is complete, the transaction aborts and the AD5770R returns to the ready state. If CS is deasserted before the first data word is written, the transaction aborts and the AD5770R returns to the ready state. If CS is deasserted after one or more data words have been written, those completed data words are written or read, but any partial written data words are aborted. Streaming Mode The CS pin can be held low, and multiple data bytes can be shifted during the data phase, which reduces the amount of overhead associated with data transfer. This mode of operation is known as streaming mode. When in streaming mode, the register address sent in the instruction phase is automatically incremented or decremented after each byte of data is processed. The ADDR_ASCENSION_MSB bit and ADDR_ASCENSION_ LSB bit in the INTERFACE_CONFIG_A register selects the address increment or decrement. The default operation is to decrement addresses when streaming data. Figure 72 illustrates a streaming mode SPI write transaction in which the six input registers are accessed using only a single instruction byte. The register address is automatically decremented after each data byte is processed. Figure 73 illustrates a streaming mode SPI read transaction in which the six DAC registers are accessed using a decrementing address. be preceded with a new instruction phase even though the CS line has not been deasserted by the SPI master. Single instruction mode allows the user to access one or more registers in a single synchronization frame without having to deassert the CS line after each data bye. The default for this bit is cleared, resulting in streaming mode being enabled. Figure 74 illustrates an SPI transaction in single instruction mode in which the following sequence of events occur: 1. 2. 3. 4. Sets the output range of Channel 1. Enables the output of Channel 1. Writes to the Channel 1 DAC register. Reads the status register. Multibyte Registers If writing to a multibyte register, CS must be held low for the whole transaction for the write to be valid. The address used must be the address of the most significant byte. The ADDR_ ASCENSION_MSB bit and the ADDR_ASCENSION_LSB bit in the INTERFACE_CONFIG_A register must be cleared. This applies when reading or writing to any multibyte register in both single instruction mode and streaming mode. Figure 75 illustrates a multibyte register access. The AD5770R contains 14 multibyte registers, as follows:     Six input registers. Six DAC registers. One input page mask register. One DAC page mask register. Single Instruction Mode When the single instruction bit is set in the INTERFACE_ CONFIG_B register, streaming mode is disabled, and the AD5770R is placed in single instruction mode. In single instruction mode, the internal SPI state machine resets after the data phase as if CS was deasserted, and awaits the next instruction. Single instruction mode forces each data phase to W CH5_INPUT_MSB ADDRESS CH5_INPUT_MSB CH5_INPUT_LSB INSTRUCTION PHASE CH0_INPUT_MSB CH0_INPUT_LSB DATA PHASE Figure 72. Streaming Mode SPI Write Transaction with Decrementing Address CS SDI R CH5_DAC_LSB ADDRESS SDO DON’T CARE DON’T CARE DON’T CARE DON’T CARE CH5_DAC_MSB CH5_DAC_LSB CH0_DAC_MSB CH0_DAC_MSB INSTRUCTION PHASE DATA PHASE Figure 73. Streaming Mode SPI Read Transaction with Decrementing Address Rev. A | Page 27 of 59 16128-051 SDI 16128-050 CS AD5770R Data Sheet CS OUTPUT_RANGE_CH1 CH1_MODE W W CH_CONFIG CH1 OUTPUT EN W CH1_DAC_MSB MSB BYTE LSB BYTE R STATUS DON’T CARE STATUS SDO INSTRUCTION PHASE DATA PHASE 16128-052 SDI Figure 74. SPI Transaction in Single Instruction Mode SDI W CH3_DAC_MSB ADDRESS INSTRUCTION PHASE CH3_DAC_MSB CH3_DAC_LSB DATA PHASE 16128-053 CS Figure 75. Multibyte Register Write RESET FUNCTION The AD5770R has an asynchronous RESET pin. For normal operation, RESET is tied high. Asserting the RESET pin to logic low for at least 10 ns resets all registers to their default values. The reset function takes 100 ns, maximum. Data must not be written to the device during this time. The AD5770R has a software reset function that performs the same function as the RESET pin, with the exception of not resetting the INTERFACE_CONFIG_A register. The reset function is activated by setting the SW_RESET_MSB and SW_RESET_LSB bits in the INTERFACE_CONFIG_A register. The SW_RESET_MSB and SW_RESET_LSB bits clear automatically during a software reset. A reset function must not be performed when the TEMP_ WARNING bit in the status register is high. Ensure that the device reads the correct trim values from the internal memory. Software LDAC It is possible to transfer data from any or all input registers to the corresponding DAC registers with a write to the SW_LDAC register, which is useful in cases where only a selection of channels are required to update synchronously. Setting the SW_LDAC register for any channel updates the selected channels DAC register with the input register contents. The contents of the SW_LDAC register clear to 0x00 after a software LDAC operation. INPUT PAGE MASK REGISTER Following a write to the input page mask register, the code loaded into this register is copied into the input register of any channels selected in the CH_SELECT register. DAC PAGE MASK REGISTER LOAD DAC The AD5770R DAC consists of double buffered registers for the DAC code. Data for one or many channels can be written to the input register without changing the DAC outputs. A load DAC command issued to the device transfers input register content into the DAC register, updating the DAC output. Hardware LDAC Pin The AD5770R has an active low LDAC pin that can synchronize updates to the outputs of the DACs. When LDAC is held high, DAC codes can be written to the input registers of the DAC without affecting the output. When LDAC is taken low, the contents of the input register are transferred to the DAC register of the corresponding channel, and the output updates. The LDAC idle high behavior is shown in Figure 2. When the LDAC pin is held low before the last rising edge of CS prior to the beginning of a new SPI transaction and the input registers contents are modified, the update to the DAC output happens when the LSB of the DAC input register is written. The LDAC idle low behavior is shown in Figure 2 and Figure 3. The LDAC pin functionality can be masked for any or all channels by configuring the corresponding HW_LDAC_ MASK_CHx bits high in the HW_LDAC register, which is useful in cases where only a selection of channels are required to update synchronously. Following a write to the DAC page mask register, the DAC code loaded into this register is copied into the DAC register of any channels selected in the CH_SELECT register. OUTPUT STAGES Each of the six AD5770R channels has a programmable current output stage that sets the required output current. Channel 0 Sink Current Generator To sink current on Channel 0, the sink current generator must be enabled by setting the CH0_SINK_EN bit in the CHANNEL_ CONFIG register to one. On power-up, the sink current generator is enabled. Output Shutdown On power-up, the outputs of each channel are in shutdown mode. When a DAC output is in shutdown mode, the output current is set to 0 mA. However, the bias circuitry for each IDACx channel remains powered up, and only the output is shut down. The shutdown bits for each register are located in the CHANNEL_ CONFIG register. When changing between output modes on a DAC channel, the output stage of the channel must be shut down to prevent glitches on the output. Rev. A | Page 28 of 59 Data Sheet AD5770R Channel 0 Channel 0 of the AD5770R sinks up to 60 mA and sources up to 300 mA of current. This channel has three different modes of operation. The CH0_MODE bits in the OUTPUT_RANGE_CH0 register configure the different modes. The configuration options for Channel 0 are listed in Table 8. On power-up, Channel 0 defaults to the 0 mA to 300 mA range. Channel 0 has a sinking only mode of −60 mA to 0 mA. In this mode, the DAC has a zero-scale output of −60 mA and a full-scale output of 0 mA. To enter this mode safely without output glitches, the output must be shut down first by setting CH0_SHUTDOWN_B high in the CHANNEL_CONFIG register. Channel 0 has a sourcing and sinking mode where the DAC has a zero-scale output of −60 mA and a full-scale output of +300 mA. To reduce glitches on the output of Channel 0, CH0_MODE must be configured before taking the output out of shutdown. Channel 1 Channel 1 can be set up to source 0 mA to 140 mA or 0 mA to 250 mA. The full-scale output range for Channel 1 must be set by writing to the CH1_MODE bits of the OUTPUT_RANGE_ CH1 register. In addition to the 0 mA to 250 mA range, Channel 1 has two 0 mA to 140 mA ranges; the channel can be set up to optimize for better noise and PSRR or for reduced headroom. The configuration options for Channel 1 are listed in Table 8. Channel 2 Channel 2 can be set up to source 0 mA to 55 mA or 0 mA to 150 mA. The full-scale output range for Channel 2 must be set by writing to the CH2_MODE bits of the OUTPUT_RANGE_ CH2 register. Table 8 lists configuration options for Channel 2. Channel 3 to Channel 5 Channel 3, Channel 4, and Channel 5 of the AD5770R can be set up to source 0 mA to 45 mA or 0 mA to 100 mA. The full-scale output rages for Channel 3, Channel 4, and Channel 5 must be set by writing to the CH3_MODE, CH4_MODE, and CH5_MODE bits of the OUTPUT_RANGE_CH3, OUTPUT_ RANGE_CH4, and OUTPUT_RANGE_CH5 registers. The configuration options for Channel 3, Channel 4, and Channel 5 are listed in Table 8. Table 8. Output Range Mode Register Setup Channel Channel 0 Mode Bit Name CH0_MODE Channel 1 CH1_MODE Channel 2 CH2_MODE Channel 3 CH3_MODE Channel 4 CH4_MODE Channel 5 CH5_MODE 1 2 Mode 0x0 0x1 0x2 0x1 0x2 0x3 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 Zero-Scale Output (mA) 0 −60 −60 0 0 0 0 0 0 0 0 0 0 0 Full-Scale Output (mA)1 300 0 300 140 140 250 55 150 45 100 45 100 45 100 Output current scaling feature disabled. See the Output Current Scaling section for more information. 500 mV footroom from PVEE0 supply required when sinking current. Rev. A | Page 29 of 59 Minimum Headroom (mV) 450 02 4502 275 450 450 275 275 275 275 275 275 275 275 Comments Low headroom Low noise and PSRR AD5770R Data Sheet OUTPUT FILTER Background CRC Failure Each channel of the AD5770R has a user programmable variable resistor in the output stage used for filtering. The output filter resistor creates a low-pass RC filter with the 10 nF external capacitor connected to the CDAMP_IDACx pin. The value loaded into the OUTPUT_FILTER_CH0x register configures the value of the variable resistor. Table 9 shows the cutoff frequency of each resistor setting. The AD5770R periodically performs a background cyclic redundancy check (CRC) on the status of the on-chip registers to ensure that the memory bits are not corrupted. In the unlikely event that the background CRC fails, the ALARM pin activates and the BACKGROUND_CRC_STATUS bit in the status register is set high. Reading the status register deasserts the ALARM pin. A hardware or software reset is required to clear the BACKGROUND _CRC_STATUS bit. The ALARM pin can be set to ignore background CRC failures by setting the BACKGROUND_ CRC_ALARM_MASK bit of the ALARM_CONFIG register. Table 9. IDACx Filter Bandwidth Control Settings OUTPUT_FIILTER_CHx Setting 0x0 0x5 0x6 0x7 0x8 0x9 Resistor Value 60 Ω 5.6 kΩ 11.2 kΩ 22.2 kΩ 44.4 kΩ 104 kΩ Cutoff Frequency 262 kHz 2.8 kHz 1.4 kHz 715 Hz 357 Hz 153 Hz Overtemperature Warning and Shutdown To protect the device from damage from overtemperature occurrences during operation, the AD5770R has an overtemperature warning alert and an overtemperature shutdown alert. OUTPUT CURRENT SCALING When in current sourcing mode only, the full-scale output current of each channel of the AD5770R can be scaled by up to ½ of the nominal full-scale current and maintain 14-bit monotonicity. The full-scale output current of any channel can be scaled by writing to the CHx_OUTPUT_SCALING bits of the OUTPUT_ RANGE_CHx register. The value loaded into the CHx_OUTPUT_ SCALING bits determines the multiplier, which scales the fullscale current. The adjusted full-scale current of an IDACx channel is calculated by, x   I ADJ  I NOM   1    128  (5) where: IADJ is the adjusted full-scale output current. INOM is the nominal full-scale output current. x is the code loaded into output scaling register, 0 ≤ x ≤ 63. For the range scaling feature to take effect on the output current for a particular channel, write to the DAC register for that channel after writing to the OUTPUT_RANGE_CHx register. Refer to Table 10 for a list of output current ranges achievable using the scaling feature. ALARM The AD5770R provides a number of fault alerts that are signaled via the ALARM pin and the status register. The active low ALARM pin can be configured as an open-drain output by setting the OPEN_DRAIN_EN bit in the ALARM_CONFIG register, allowing several devices to be connected together to one pull-up resistor for global fault detection. Open drain mode on the ALARM pin is disabled on power up. When the internal die temperature reaches approximately 125°C, the ALARM pin activates, and the TEMP_WARNING bit in the status register is set high. The user must read the status register to deassert the ALARM pin. When the internal die temperature reaches approximately 145°C, the ALARM pin activates (if not already activated) and the OVER_TEMP bit in the status register is set. The user must read the status register to deassert the ALARM pin. If the THERMAL_SHUTDOWN_EN bit in the ALARM_ CONFIG register is set to high, the device shuts down the output stages to protect from over temperature, and the outputs remain shut down until the user initiates a software or hardware reset to the device. The TEMP_WARNING and OVER_TEMP flags in the status register clear when the device temperature returns below approximately 120°C. To guarantee proper data downloads from the internal memory, a reset function must not be performed when the TEMP_WARNING bit in the status register is high. The ALARM pin can be set to ignore over temperature faults and over temperature warnings by setting the OVER_TEMP_ ALARM_MASK and TEMP_WARNING_ALARM_MASK bits of the ALARM_CONFIG register. Negative Compliance Voltage The compliance voltage on IDAC0 pin of the AD5770R can be a negative value when sinking current. The AD5770R has a negative compliance voltage alert feature to protect an external unipolar ADC connected to the MUX_OUT pin. The following sequence of events occurs if the user enables voltage monitoring of Channel 0 when the voltage on IDAC0 is negative: 1. 2. 3. Rev. A | Page 30 of 59 The ALARM pin activates. The MUX_OUT pin is disabled. The NEGATIVE_CHANNEL0 bit in the status register is set. Data Sheet AD5770R The status register must be read to dessert the ALARM pin. current that is too high and can damage the device. The AD5770R incorporates an internal protection circuit that protects the device if the reference current is too high. The following sequence of events occurs if the voltage on IDAC0 goes negative after the user enables voltage monitoring of Channel 0: 1. 2. 3. When the protection circuit detects a reference current that is too high, the following events occur: The ALARM pin activates. The MUX_OUT pin is set to the same voltage as PVDD0. The NEGATIVE_CHANNEL0 bit in the status register is set. 1. 2. 3. The status register must be read to dessert the ALARM pin. This circuit switches to the internal RSET resistor. The ALARM pin activates. The IREF_FAULT bit in the status register is set. The user must then read the status register to deassert the ALARM pin. The ALARM pin can be set to ignore IREF faults by setting the IREF_FAULT_ALARM_MASK bit of the ALARM_CONFIG register. The ALARM pin can be set to ignore the negative compliance voltage warning by setting the NEGATIVE_CHANNEL0_ ALARM_MASK bit of the ALARM_CONFIG register. IREF Fault When the external RSET resistor option is selected, it is important that the value of this external RSET resistor cannot create a reference Table 10. Full-Scale Output Current Per Channels, for All Scaling Code Values Scaling Code 0 (Default) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Channel 0, 0 mA to 300 mA Range (mA) 300 Channel 1, 0 mA to 140 mA Range (mA) 140 Channel 1, 0 mA to 250 mA Range (mA) 250 Channel 2, 0 mA to 55 mA Range (mA) 55 Channel 2, 0 mA to 150 mA Range (mA) 150 Channel 3 to Channel 5, 0 mA to 45 mA Range (mA) 45 Channel 3 to Channel 5, 0 mA to 100 mA Range (mA) 100 298 295 293 291 288 286 284 281 279 277 274 272 270 267 265 263 260 258 255 253 251 248 246 244 241 239 237 234 232 230 227 139 138 137 136 135 133 132 131 130 129 128 127 126 125 124 123 121 120 119 118 117 116 115 114 113 112 110 109 108 107 106 248 246 244 242 240 238 236 234 232 230 229 227 225 223 221 219 217 215 213 211 209 207 205 203 201 199 197 195 193 191 189 55 54 54 53 53 52 52 52 51 51 50 50 49 49 49 48 48 47 47 46 46 46 45 45 44 44 43 43 43 42 42 149 148 146 145 144 143 142 141 139 138 137 136 135 134 132 131 130 129 128 127 125 124 123 122 121 120 118 117 116 115 114 45 44 44 44 43 43 43 42 42 41 41 41 40 40 40 39 39 39 38 38 38 37 37 37 36 36 36 35 35 34 34 99 98 98 97 96 95 95 94 93 92 91 91 90 89 88 88 87 86 85 84 84 83 82 81 80 80 79 78 77 77 76 Rev. A | Page 31 of 59 AD5770R Scaling Code 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Channel 0, 0 mA to 300 mA Range (mA) 225 223 220 218 216 213 211 209 206 204 202 199 197 195 192 190 188 185 183 180 178 176 173 171 169 166 164 162 159 157 155 152 Data Sheet Channel 1, 0 mA to 140 mA Range (mA) 105 104 103 102 101 100 98 97 96 95 94 93 92 91 90 89 88 86 85 84 83 82 81 80 79 78 77 75 74 73 72 71 Channel 1, 0 mA to 250 mA Range (mA) 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 145 143 141 139 137 135 133 131 129 127 Channel 2, 0 mA to 55 mA Range (mA) 41 41 40 40 40 39 39 38 38 37 37 37 36 36 35 35 34 34 34 33 33 32 32 31 31 31 30 30 29 29 28 28 Rev. A | Page 32 of 59 Channel 2, 0 mA to 150 mA Range (mA) 113 111 110 109 108 107 105 104 103 102 101 100 98 97 96 95 94 93 91 90 89 88 87 86 84 83 82 81 80 79 77 76 Channel 3 to Channel 5, 0 mA to 45 mA Range (mA) 34 33 33 33 32 32 32 31 31 31 30 30 30 29 29 28 28 28 27 27 27 26 26 26 25 25 25 24 24 24 23 23 Channel 3 to Channel 5, 0 mA to 100 mA Range (mA) 75 74 73 73 72 71 70 70 69 68 67 66 66 65 64 63 63 62 61 60 59 59 58 57 56 55 55 54 53 52 52 51 Data Sheet AD5770R APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5770R is via a serial bus that uses a standard protocol compatible with DSPs and microcontrollers. The communications channel requires a 4-wire serial interface consisting of a clock signal, a data input signal, a data output signal, and a synchronization signal. AD5770R TO SPI INTERFACE The SPI interface of the AD5770R is designed to be easily connected to industry-standard DSPs and microcontrollers. Figure 76 shows the AD5770R connected to the ADuCM320. The ADuCM320 has an integrated SPI port that can be connected directly to the SPI pins of the AD5770R. COMBINING CHANNELS TO INCREASE CURRENT RANGE The maximum current that can be sourced from IDAC0 is 300 mA. It is possible to increase the current source capability by connecting two channels directly together. Figure 77 shows IDAC1 combined with IDAC2 to create a full-scale output current of 400 mA. When channels are combined, care must be taken to ensure the following:   The output compliance voltage stays within the range specified in Table 1. The output voltage stays within the absolute maximum ratings specified in Table 5. PVDDx AD5770R CS P0.0/SCLK0/PLAI[0] SCLK P0.2/MOSI0/PLAI[2] SDI P0.1/MISO0/PLAI[1] SDO P1.4/PWM2/SCLK1/PLAO[10] RESET P1.5/PWM3/MISO1/PLAO[11] LDAC P1.6/PWM4/MOSI1/PLAO[12] ALARM IDAC2 250mA 150mA 400mA RLOAD 16128-057 P0.3/IRQ0/CS0/PLACLK0/PLAI[3] IDAC1 AD5770R 16128-054 ADuCM320 Figure 76. ADuCM320 SPI Interface LAYOUT GUIDELINES THERMAL CONSIDERATIONS The AD5770R has a maximum junction temperature of 150°C (see Table 5). To ensure reliable and specified operation over the lifetime of the device, it is important that the AD5770R is not operated under conditions that cause the junction temperature to exceed 150°C. The junction temperature is directly affected by the power dissipated across the AD5770R and the ambient temperature. Table 1 specifies the output current ranges for each AD5770R channel and the maximum power supply voltages. Therefore, it is important to understand the effects of power dissipation on the package and the effects the package has on the junction temperature. The AD5770R is packaged in a 49-ball, 4 mm × 4 mm, wafer level chip scale packaging (WLCSP) package. The thermal impedance, θJA, is specified in Table 6. Table 11 provides examples of the maximum allowed power dissipation and the maximum allowed ambient temperature under certain conditions. Figure 77. Increasing the Current Range by Summing Channels Take careful consideration of the power supply and ground return layout in order to ensure the rated performance. Design the PCB on which the AD5770R is mounted so that the AD5770R lies on the analog plane. The AD5770R must have an ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply, located as close to the package as possible (ideally directly against the device). The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI). Common ceramic capacitors provide a low impedance path to ground at high frequencies to handle transient currents, due to internal logic switching. Ensure that the power supply line has as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Shield clocks and other fast switching digital signals from other parts of the board by using a digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only, and the signal traces are placed on the solder side. However, this technique is not always possible with a 2-layer board. Rev. A | Page 33 of 59 AD5770R Data Sheet Because the AD5770R can dissipate a large amount of power, it is recommended to provide some heat sinking capability to allow power to dissipate easily. For the WLCSP package, heat is transferred through the solder balls to the PCB board. θJA thermal impedance is dependent on board construction. More copper layers enable heat to be removed more effectively. If using an external RSET resistor, the low side of the RSET resistor must be connected to REFGND before the connection to AGND. Ensure that the width of the trace connecting RSET to the IREF pin is as wide as possible to reduce the resistance and the temperature coefficient of the trace. Table 11. Thermal Considerations for 49-Ball WLCSP Package Parameter Maximum Power Dissipation1 Description Maximum allowed AD5770R power dissipation (PDISS) when operating at an ambient temperature of 105°C, TJMAX  TA 150C  105C   1.5 W JA 30C / W Recommended Power Dissipation1 Maximum recommended AD5770R PDISS when operating at an ambient temperature of 85°C and a junction temperature of 115°C, TJ  TA 115C  85C  1 W JA 30C / W Ambient Temperature1 Maximum recommended ambient temperature when dissipating 980.4 mW across the AD5770R while maintaining a junction temperature of 115°C. TJ – PDISS × θJA = 115°C – (980.4mW × 30°C/W) = 85.58°C Power dissipation calculation example: AVDD = DVDD = IOVDD = 3.3 V, PVDDx = 2.5 V AVEE = PVEE0 = 0 V, RLOAD = 6 Ω per channel, AD5770R quiescent power dissipation = 110 mW IDAC0 = 300 mA, power dissipation = 210 mW IDAC1 = 150 mA, power dissipation = 240 mW IDAC2 = 55 mA, power dissipation = 119.35 mW IDAC3, IDAC4, IDAC5 = 45 mA, power dissipation = 301.05 mW Total power dissipation = 110 mW + 870.4 mW = 980.4 W 1 TJMAX in Table 5 is the junction temperature that the AD5770R can tolerate, but not operate at. It is recommended that the junction temperature does not exceed 115°C. Rev. A | Page 34 of 59 Data Sheet AD5770R REGISTER SUMMARY SPI CONFIGURATION REGISTERS Table 12. AD5770R SPI Configuration Register Summary Reg 0x00 Name INTERFACE_ CONFIG_A Bits [7:0] Bit 7 SW_RESET_ MSB 0x01 INTERFACE_ CONFIG_B CHIP_TYPE PRODUCT_ID_L PRODUCT_ID_H CHIP_GRADE SCRATCH_PAD SPI_REVISION VENDOR_L VENDOR_H STREAM_MODE INTERFACE_ CONFIG_C [7:0] SINGLE_INST 0x03 0x04 0x05 0x06 0x0A 0x0B 0x0C 0x0D 0x0E 0x10 0x11 INTERFACE_ STATUS_A [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit 6 Reserved Bit 5 ADDR_ ASCENSION_ MSB Reserved Bit 4 SDO_ ACTIVE_MSB Bit 3 SDO_ ACTIVE_LSB Bit 2 ADDR_ ASCENSION_ LSB SHORT_ INSTRUCTION Bit 1 Reserved Bit 0 SW_ RESET_ LSB Reserved Reserved CHIP_TYPE PRODUCT_ID[7:0] PRODUCT_ID[15:8] GRADE DEVICE_REVISION VALUE VERSION VID[7:0] VID[15:8] LENGTH Reserved STRICT_ REGISTER_ ACCESS Reserved INTERFACE_ NOT_READY Reserved Reset 0x18 R/W R/W 0x08 R/W 0x08 0x04 0x40 0x00 0x00 0x82 0x56 0x04 0x00 0x20 R R R R R/W R R R R/W R 0x00 R AD5770R CONFIGURATION REGISTERS Table 13. AD5770R Configuration Register Summary Reg Name 0x14 CHANNEL_ CONFIG Bits [7:0] Bit 7 CH0_SINK_EN 0x15 OUTPUT_ RANGE_ CH0 0x16 OUTPUT_ RANGE_ CH1 0x17 OUTPUT_ RANGE_ CH2 0x18 OUTPUT_ RANGE_ CH3 0x19 OUTPUT_ RANGE_ CH4 0x1A OUTPUT_ RANGE_ CH5 0x1B REFERENCE [7:0] CH0_OUTPUT_SCALING CH0_MODE 0x00 R/W [7:0] CH1_OUTPUT_SCALING CH1_MODE 0x02 R/W [7:0] CH2_OUTPUT_SCALING Reserved CH2_ MODE 0x00 R/W [7:0] CH3_OUTPUT_SCALING Reserved CH3_ MODE 0x00 R/W [7:0] CH4_OUTPUT_SCALING Reserved CH4_ MODE 0x00 R/W [7:0] CH5_OUTPUT_SCALING Reserved CH5_ MODE 0x00 R/W REFERENCE_VOLTAGE_SEL 0x00 R/W 0x1C ALARM_ CONFIG [7:0] THERMAL_ SHUTDOWN_ EN 0x06 R/W 0x1D OUTPUT_ FILTER_ CH0 0x1E OUTPUT_ FILTER_ CH1 0x1F OUTPUT_ FILTER_ CH2 0x20 OUTPUT_ FILTER_ CH3 [7:0] IREF_ NEGATIVE_ FAULT_ CHANNEL0_ ALARM_ ALARM_ MASK MASK Reserved OUTPUT_FILTER_RESISTOR0 0x00 R/W [7:0] Reserved OUTPUT_FILTER_RESISTOR1 0x00 R/W [7:0] Reserved OUTPUT_FILTER_RESISTOR2 0x00 R/W [7:0] Reserved OUTPUT_FILTER_RESISTOR3 0x00 R/W [7:0] Bit 6 Reserved Bit 5 CH5_ SHUTDOWN_B Bit 4 CH4_ SHUTDOWN_B Bit 3 CH3_ SHUTDOWN_B Reserved BACKGROUND_ CRC_ALARM_ MASK OVER_TEMP_ ALARM_MASK TEMP_ WARNING_ ALARM_ MASK Rev. A | Page 35 of 59 Bit 2 CH2_ SHUTDOWN_B REFERENCE_ RESISTOR_ SEL BACKGROUND_ CRC_EN Bit 1 CH1_ SHUTDOWN_B Bit 0 CH0_ SHUTDOWN_B OPEN_ DRAIN_ EN Reset R/W 0x80 R/W AD5770R Data Sheet Reg Name 0x21 OUTPUT_ FILTER_ CH4 0x22 OUTPUT_ FILTER_ CH5 0x23 MONITOR_ SETUP 0x24 STATUS Bits [7:0] 0x25 HW_LDAC [7:0] 0x26 CH0_DAC_ LSB 0x27 CH0_DAC_ MSB 0x28 CH1_DAC_ LSB 0x29 CH1_DAC_ MSB 0x2A CH2_DAC_ LSB 0x2B CH2_DAC_ MSB 0x2C CH3_DAC_ LSB 0x2D CH3_DAC_ MSB 0x2E CH4_DAC_ LSB 0x2F CH4_DAC_ MSB 0x30 CH5_DAC_ LSB 0x31 CH5_DAC_ MSB 0x32 DAC_PAGE _ MASK_LSB 0x33 DAC_PAGE _ MASK_MSB 0x34 CH_SELECT [7:0] Bit 6 [7:0] [7:0] [7:0] Bit 5 Reserved Bit 4 Bit 3 Reserved MON_FUNCTION BACKGROUND_ CRC_STATUS Reserved MUX_ BUFFER Reserved IB_EXT_EN HW_LDAC_ MASK_CH5 HW_LDAC_ MASK_CH4 TEMP_ WARNING 0x00 R HW_LDAC_ MASK_CH3 HW_LDAC_ MASK_CH2 HW_LDAC_ MASK_CH1 HW_LDAC_ MASK_CH0 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W DAC_DATA3[13:6] DAC_DATA4[5:0] Reserved DAC_DATA4[13:6] DAC_DATA5[5:0] Reserved DAC_DATA5[13:6] [7:0] DAC_PAGE_MASK[5:0] [7:0] [7:0] OVER_TEMP Reserved [7:0] [7:0] NEGATIVE_ CHANNEL0 DAC_DATA3[5:0] [7:0] [7:0] IREF_FAULT Reserved [7:0] [7:0] R/W DAC_DATA2[13:6] [7:0] [7:0] 0x00 DAC_DATA2[5:0] [7:0] [7:0] MON_CH DAC_DATA1[13:6] [7:0] [7:0] R/W Reserved [7:0] [7:0] 0x00 DAC_DATA1[5:0] [7:0] Reserved DAC_PAGE_MASK[13:6] Reserved SEL_CH5 SEL_CH4 SEL_CH3 SEL_CH2 SEL_CH1 INPUT_PAGE_MASK[5:0] SEL_CH0 Reserved INPUT_PAGE_MASK[13:6] Reserved SW_LDAC_ SW_LDAC_ CH5 CH4 INPUT_DATA0[5:0] Reset R/W 0x00 R/W OUTPUT_FILTER_RESISTOR5 Reserved [7:0] [7:0] Bit 0 DAC_DATA0[13:6] [7:0] [7:0] Bit 2 Bit 1 OUTPUT_FILTER_RESISTOR4 DAC_DATA0[5:0] [7:0] 0x35 INPUT_ [7:0] PAGE_ MASK_LSB 0x36 INPUT_ [7:0] PAGE_ MASK_MSB 0x37 SW_LDAC [7:0] 0x38 CH0_INPUT _LSB 0x39 CH0_INPUT _MSB 0x3A CH1_INPUT _LSB 0x3B CH1_INPUT _MSB 0x3C CH2_INPUT _LSB 0x3D CH2_INPUT _MSB 0x3E CH3_INPUT _LSB 0x3F CH3_INPUT _MSB 0x40 CH4_INPUT _LSB Bit 7 SW_LDAC_ CH3 SW_LDAC_ CH2 SW_LDAC_ CH1 SW_LDAC_ CH0 Reserved INPUT_DATA0[13:6] INPUT_DATA1[5:0] Reserved INPUT_DATA1[13:6] INPUT_DATA2[5:0] Reserved INPUT_DATA2[13:6] INPUT_DATA3[5:0] Reserved INPUT_DATA3[13:6] INPUT_DATA4[5:0] Rev. A | Page 36 of 59 Reserved Data Sheet Reg Name 0x41 CH4_INPUT _MSB 0x42 CH5_INPUT _LSB 0x43 CH5_INPUT _MSB 0x44 RESERVED Bits [7:0] AD5770R Bit 7 Bit 6 [7:0] Bit 4 Bit 3 INPUT_DATA4[13:6] Bit 2 INPUT_DATA5[5:0] [7:0] [7:0] Bit 5 RESERVED1 Rev. A | Page 37 of 59 Bit 0 Reserved INPUT_DATA5[13:6] RESERVED0 Bit 1 Reset R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x3F R AD5770R Data Sheet REGISTER DETAILS Address: 0x00, Reset: 0x18, Name: INTERFACE_CONFIG_A 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 0 [7] SW_RESET_MSB (R/W) Software Reset 0: Do Nothing. 1: Initiates a Software Reset. [0] SW_RESET_LSB (R/W) Software Reset 0: Do Nothing. 1: Initiates a Software Reset. [6] RESERVED [1] RESERVED [5] ADDR_ASCENSION_MSB (R/W) Address Ascension 0: Address Decrem ent. 1: Address Increment. [2] ADDR_ASCENSION_LSB (R/W) Address Ascension 0: Address Decrem ent. 1: Address Increment. [4] SDO_ACTIVE_MSB (R) SDO Pin Active [3] SDO_ACTIVE_LSB (R) SDO Pin Active Table 14. Bit Descriptions for INTERFACE_CONFIG_A Bits 7 Bit Name SW_RESET_MSB 6 5 Reserved ADDR_ASCENSION_MSB 4 3 2 SDO_ACTIVE_MSB SDO_ACTIVE_LSB ADDR_ASCENSION_LSB 1 0 Reserved SW_RESET_LSB Description Software Reset. Setting both software reset bits in a single SPI write performs a software reset on the device, returning all registers except INTERFACE_CONFIG_A to the default power-up state. 0: do nothing. 1: initiates a software reset. Reserved. Address Ascension. When set, this bit causes incrementing streaming addresses; otherwise, decrementing addresses are generated. This must be a mirror of ADDR_ ASCENSION_LSB. 0: address decrement. 1: address increment. SDO Pin Active. SDO pin enabled. This bit is always set. SDO Pin Active. SDO pin enabled. This bit is always set. Address Ascension. When set, this bit causes incrementing streaming addresses; otherwise, decrementing addresses are generated. This must be a mirror of ADDR_ ASCENSION_MSB. 0: address decrement. 1: address increment. Reserved. Software Reset. Setting both software reset bits in a single SPI write performs a software reset on the device, returning all registers except INTERFACE_CONFIG_A to the default power up state. 0: do nothing. 1: initiates a software reset. Reset 0x0 Access R/W 0x0 0x0 R R/W 0x1 0x1 0x0 R R R/W 0x0 0x0 R R/W Reset 0x0 Access R/W 0x0 0x01 0x0 R R R Address: 0x01, Reset: 0x08, Name: INTERFACE_CONFIG_B 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 [7] SINGLE_INST (R/W) Single Instruction [2:0] RESERVED [3] SHORT_INSTRUCTION (R) Short Instruction [6:4] RESERVED Table 15. Bit Descriptions for INTERFACE_CONFIG_B Bits 7 Bit Name SINGLE_INST [6:4] 3 [2:0] Reserved SHORT_INSTRUCTION Reserved Description Single Instruction. When this bit is set, streaming mode is disable, and each SPI transaction must specify the register address to access. 0: streaming mode enabled. 1: streaming mode disabled. Reserved. Short Instruction. When this bit is set, the address word must be 7 bits long. Reserved. Rev. A | Page 38 of 59 Data Sheet AD5770R Address: 0x03, Reset: 0x08, Name: CHIP_TYPE 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 [7:4] RESERVED [3:0] CHIP_TYPE (R) Chip Type Table 16. Bit Descriptions for CHIP_TYPE Bits [7:4] [3:0] Bit Name Reserved CHIP_TYPE Description Reserved. Chip Type. Precision DAC chip type = 0x08. Reset 0x0 0x8 Access R R Address: 0x04, Reset: 0x04, Name: PRODUCT_ID_L 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 [7:0] PRODUCT_ID[7:0] (R) Product ID Table 17. Bit Descriptions for PRODUCT_ID_L Bits [7:0] Bit Name PRODUCT_ID[7:0] Description Product ID. AD5770R product ID = 0x4004. Reset 0x4 Access R Reset 0x40 Access R Address: 0x05, Reset: 0x40, Name: PRODUCT_ID_H 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] PRODUCT_ID[15:8] (R) Product ID Table 18. Bit Descriptions for PRODUCT_ID_H Bits [7:0] Bit Name PRODUCT_ID[15:8] Description Product ID. AD5770R product ID = 0x4004. Address: 0x06, Reset: 0x00, Name: CHIP_GRADE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] GRADE (R) Device Grade [3:0] DEVICE_REVISION (R) Device Revision Table 19. Bit Descriptions for CHIP_GRADE Bits [7:4] [3:0] Bit Name Grade DEVICE_REVISION Description Device Grade Device Revision Reset 0x0 0x0 Access R R Address: 0x0A, Reset: 0x00, Name: SCRATCH_PAD 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] VALUE (R/W) Scratch Pad Table 20. Bit Descriptions for SCRATCH_PAD Bits [7:0] Bit Name Value Description Scratch Pad. Use this is register to test communication with the device. Rev. A | Page 39 of 59 Reset 0x0 Access R/W AD5770R Data Sheet Address: 0x0B, Reset: 0x82, Name: SPI_REVISION 7 6 5 4 3 2 1 0 1 0 0 0 0 0 1 0 [7:0] VERSION (R) SPI Standard Version Table 21. Bit Descriptions for SPI_REVISION Bits [7:0] Bit Name Version Description SPI Standard Version. Analog Devices SPI standard used. Reset 0x82 Access R Address: 0x0C, Reset: 0x56, Name: VENDOR_L 7 6 5 4 3 2 1 0 0 1 0 1 0 1 1 0 [7:0] VID[7:0] (R) Manufacturer ID Table 22. Bit Descriptions for VENDOR_L Bits [7:0] Bit Name VID[7:0] Description Manufacturer ID. Analog Devices ID = 0x0456. Reset 0x56 Access R Reset 0x4 Access R Address: 0x0D, Reset: 0x04, Name: VENDOR_H 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 [7:0] VID[15:8] (R) Manufacturer ID Table 23. Bit Descriptions for VENDOR_H Bits [7:0] Bit Name VID[15:8] Description Manufacturer ID. Analog Devices ID = 0x0456. Address: 0x0E, Reset: 0x00, Name: STREAM_MODE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] LENGTH (R/W) Stream Length Table 24. Bit Descriptions for STREAM_MODE Bits [7:0] Bit Name LENGTH Description Stream Length. These bits set the length of registers addresses to increment/decrement when streaming multiple bytes of data before looping back to the first register address. When the contents of this register are cleared, register addresses increment/decrement when in streaming mode until the end of the address space before looping to the last/first address and continuing to increment/decrement. Reset 0x0 Access R/W Reset 0x0 0x1 Access R R 0x0 R Address: 0x10, Reset: 0x20, Name: INTERFACE_CONFIG_C 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 [7:6] RESERVED [4:0] RESERVED [5] STRICT_REGISTER_ACCESS (R) Strict Entity Access Table 25. Bit Descriptions for INTERFACE_CONFIG_C Bits [7:6] 5 Bit Name Reserved STRICT_REGISTER_ACCESS [4:0] Reserved Description Reserved. Strict Register Access. When this bit is set, all multibyte registers must be written to in a single SPI transaction. The address used must be the address of the most significant byte when address ascension is off or the address of the least significant byte when address accession is on. Reserved. Rev. A | Page 40 of 59 Data Sheet AD5770R Address: 0x11, Reset: 0x00, Name: INTERFACE_STATUS_A 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] INTERFACE_NOT_READY (R) Interface Not Ready [6:0] RESERVED Table 26. Bit Descriptions for INTERFACE_STATUS_A Bits 7 Bit Name INTERFACE_NOT_READY [6:0] Reserved Description Interface Not Ready. When this bit is set, the device is not ready to receive data on the SPI bus. Reserved. Reset 0x0 Access R 0x0 R Reset 0x1 Access R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Address: 0x14, Reset: 0x80, Name: CHANNEL_CONFIG 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7] CH0_SINK_EN (R/W) Channel 0 Sink Current Generator Enable 0: Disable. 1: Enable. [6] RESERVED [5] CH5_SHUTDOWN_B (R/W) Channel 5 Output Enable 0: Output Shutdown. 1: Normal Operation. [0] CH0_SHUTDOWN_B (R/W) Channel 0 Output Enable 0: Output Shutdown. 1: Normal Operation. [1] CH1_SHUTDOWN_B (R/W) Channel 1 Output Enable 0: Output Shutdown. 1: Normal Operation. [2] CH2_SHUTDOWN_B (R/W) Channel 2 Output Enable 0: Output Shutdown. 1: Normal Operation. [4] CH4_SHUTDOWN_B (R/W) Channel 4 Output Enable 0: Output Shutdown. 1: Normal Operation. [3] CH3_SHUTDOWN_B (R/W) Channel 3 Output Enable 0: Output Shutdown. 1: Normal Operation. Table 27. Bit Descriptions for CHANNEL_CONFIG Bits 7 Bit Name CH0_SINK_EN 6 5 Reserved CH5_SHUTDOWN_B 4 CH4_SHUTDOWN_B 3 CH3_SHUTDOWN_B 2 CH2_SHUTDOWN_B 1 CH1_SHUTDOWN_B Description Channel 0 Sink Current Generator Enable. When this bit is set, Channel 0 sink current is enabled. 0: disable. 1: enable. Reserved. Channel 5 Output Enable. This active low enable bit shuts down the output of IDAC5 when asserted. 0: output shutdown. 1: normal operation. Channel 4 Output Enable. This active low enable bit shuts down the output of IDAC4 when asserted. 0: output shutdown. 1: normal operation. Channel 3 Output Enable. This active low enable bit shuts down the output of IDAC3 when asserted. 0: output shutdown. 1: normal operation. Channel 2 Output Enable. This active low enable bit shuts down the output of IDAC2 when asserted. 0: output shutdown. 1: normal operation. Channel 1 Output Enable. This active low enable bit shuts down the output of IDAC1 when asserted. 0: output shutdown. 1: normal operation. Rev. A | Page 41 of 59 AD5770R Bits 0 Bit Name CH0_SHUTDOWN_B Data Sheet Description Channel 0 Output Enable. This active low enable bit shuts down the output of IDAC0 when asserted. 0: output shutdown. 1: normal operation. Reset 0x0 Access R/W Reset 0x0 Access R/W 0x0 R/W Reset 0x0 Access R/W 0x2 R/W Reset 0x0 Access R/W 0x0 0x0 R R/W Address: 0x15, Reset: 0x00, Name: OUTPUT_RANGE_CH0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] CH0_OUTPUT_SCALING (R/W) Channel 0 Output Range Scaling [1:0] CH0_MODE (R/W) Channel 0 Output Range Mode 00: 0mA to 300mA. 01: -60mA to 0mA. 10: -60mA to 300mA. Table 28. Bit Descriptions for OUTPUT_RANGE_CH0 Bits [7:2] Bit Name CH0_OUTPUT_SCALING [1:0] CH0_MODE Description Channel 0 Output Range Scaling. These bits set the output range scaling factor for Channel 0. Output scaling must only be used when in a sourcing current mode. Channel 0 Output Range Mode. These bits select the output range mode for Channel 0. 00: 0 mA to 300 mA. 01: −60 mA to 0 mA. 10: −60 mA to +300 mA. Address: 0x16, Reset: 0x02, Name: OUTPUT_RANGE_CH1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 [7:2] CH1_OUTPUT_SCALING (R/W) Channel 1 Output Range Scaling [1:0] CH1_MODE (R/W) Channel 1 Output Range Mode 01: 0mA to 140mA - Low Headroom. 10: 0mA to 140mA - Low Noise. 11: 0mA to 250mA. Table 29. Bit Descriptions for OUTPUT_RANGE_CH1 Bits [7:2] Bit Name CH1_OUTPUT_SCALING [1:0] CH1_MODE Description Channel 1 Output Range Scaling. These bits set the output range scaling factor for Channel 1. Channel 1 Output Range Mode. These bits select the output range mode for Channel 1. 01: 0 mA to 140 mA low headroom. 10: 0 mA to 140 mA low noise. 11: 0 mA to 250 mA. Address: 0x17, Reset: 0x00, Name: OUTPUT_RANGE_CH2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] CH2_OUTPUT_SCALING (R/W) Channel 2 Output Range Scaling [0] CH2_MODE (R/W) Channel 2 Output Range Mode 0: 0mA to 55mA. 1: 0mA to 150mA. [1] RESERVED Table 30. Bit Descriptions for OUTPUT_RANGE_CH2 Bits [7:2] Bit Name CH2_OUTPUT_SCALING 1 0 Reserved CH2_MODE Description Channel 2 Output Range Scaling. These bits set the output range scaling factor for Channel 2. Reserved. Channel 2 Output Range Mode. This bit selects the output range mode for Channel 2. 0: 0 mA to 55 mA. 1: 0 mA to 150 mA. Rev. A | Page 42 of 59 Data Sheet AD5770R Address: 0x18, Reset: 0x00, Name: OUTPUT_RANGE_CH3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] CH3_OUTPUT_SCALING (R/W) Channel 3 Output Range Scaling [0] CH3_MODE (R/W) Channel 3 Output Range Mode 0: 0mA to 45mA. 1: 0mA to 100mA. [1] RESERVED Table 31. Bit Descriptions for OUTPUT_RANGE_CH3 Bits [7:2] Bit Name CH3_OUTPUT_SCALING 1 0 Reserved CH3_MODE Description Channel 3 Output Range Scaling. These bits set the output range scaling factor for Channel 3. Reserved. Channel 3 Output Range Mode. This bit selects the output range mode for Channel 3. 0: 0 mA to 45 mA. 1: 0 mA to 100 mA. Reset 0x0 Access R/W 0x0 0x0 R R/W Reset 0x0 Access R/W 0x0 0x0 R R/W Reset 0x0 Access R/W 0x0 0x0 R R/W Address: 0x19, Reset: 0x00, Name: OUTPUT_RANGE_CH4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] CH4_OUTPUT_SCALING (R/W) Channel 4 Output Range Scaling [0] CH4_MODE (R/W) Channel 4 Output Range Mode 0: 0mA to 45mA. 1: 0mA to 100mA. [1] RESERVED Table 32. Bit Descriptions for OUTPUT_RANGE_CH4 Bits [7:2] Bit Name CH4_OUTPUT_SCALING 1 0 Reserved CH4_MODE Description Channel 4 Output Range Scaling. These bits set the output range scaling factor for Channel 4. Reserved. Channel 4 Output Range Mode. This bit selects the output range mode for Channel 4. 0: 0 mA to 45 mA. 1: 0 mA to 100 mA. Address: 0x1A, Reset: 0x00, Name: OUTPUT_RANGE_CH5 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] CH5_OUTPUT_SCALING (R/W) Channel 5 Output Range Scaling [0] CH5_MODE (R/W) Channel 5 Output Range Mode 0: 0mA to 45mA. 1: 0mA to 100mA. [1] RESERVED Table 33. Bit Descriptions for OUTPUT_RANGE_CH5 Bits [7:2] Bit Name CH5_OUTPUT_SCALING 1 0 Reserved CH5_MODE Description Channel 5 Output Range Scaling. These bits set the output range scaling factor for Channel 5. Reserved. Channel 5 Output Range Mode. This bit selects the output range mode for Channel 5. 0: 0 mA to 45 mA. 1: 0 mA to 100 mA. Rev. A | Page 43 of 59 AD5770R Data Sheet Address: 0x1B, Reset: 0x00, Name: REFERENCE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:3] RESERVED [1:0] REFERENCE_VOLTAGE_SEL (R/W) Voltage Reference Setup 00: External 2.5V. 01: Internal 1.25V (Reference Output On) 10: External 1.25V. 11: Internal 1.25V (Reference Output Off) [2] REFERENCE_RESISTOR_SEL (R/W) IREF Resistor Setup 0: Internal Resistor. 1: External Resistor. Table 34. Bit Descriptions for REFERENCE Bits [7:3] 2 Bit Name Reserved REFERENCE_RESISTOR_SEL [1:0] REFERENCE_VOLTAGE_SEL Description Reserved. IREF Resistor Setup. This bit selects whether an internal or external resistor is used for reference current generation. 0: internal resistor. 1: external resistor. Voltage Reference Setup. These bits select the voltage reference scheme used for reference current generation. 00: external 2.5 V. 01: internal 1.25 V (reference output on). 10: external 1.25 V. 11: internal 1.25 V (reference output off ). Reset 0x0 0x0 Access R R/W 0x0 R/W Reset 0x0 Access R/W 0x0 R/W Address: 0x1C, Reset: 0x06, Name: ALARM_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 [7] BACKGROUND_CRC_ALARM_MASK (R/W) Background CRC Alarm Mask 0: Normal Operation. 1: Mask Background CRC ALARM Activation. [0] OPEN_DRAIN_EN (R/W) Open Drain ALARM Enable 0: ALARM Open Drain Disable. 1: ALARM Open Drain Enable. [6] IREF_FAULT_ALARM_MASK (R/W) External IREF Resistor Fault Alarm Mask 0: Normal Operation. 1: Mask IREF Fault ALARM Activation. [1] THERMAL_SHUTDOWN_EN (R/W) Thermal Shutdown Enable 0: Disable Thermal Shutdown - Not Recommended. 1: Enable Thermal Shutdown. [5] NEGATIVE_CHANNEL0_ALARM_MASK (R/W) Negative Voltage Channel 0 Fault Alarm Mask 0: Normal Operation. 1: Mask Negative Channel 0 ALARM Activation. [2] BACKGROUND_CRC_EN (R/W) Background CRC Enable 0: Disable Background CRC. 1: Enable Background CRC. [4] OVER_TEMP_ALARM_MASK (R/W) Over-Temperature Fault Alarm Mask 0: Normal Operation. 1: Mask Over Temperature ALARM Activation. [3] TEMP_WARNING_ALARM_MASK (R/W) Over-Temperature Warning Alarm Mask 0: Normal Operation. 1: Mask Temperature Warning ALARM Activation. Table 35. Bit Descriptions for ALARM_CONFIG Bits 7 Bit Name BACKGROUND_CRC_ALARM_MASK 6 IREF_FAULT_ALARM_MASK Description Background CRC Alarm Mask. When this bit is set, the ALARM pin does not activate for background CRC errors. 0: normal operation. 1: mask background CRC ALARM activation. External IREF Resistor Fault Alarm Mask. When this bit is set, the ALARM pin does not activate for external reference current generation resistor faults. 0: normal operation. 1: mask IREF fault ALARM activation. Rev. A | Page 44 of 59 Data Sheet AD5770R Bits 5 Bit Name NEGATIVE_CHANNEL0_ALARM_MASK 4 OVER_TEMP_ALARM_MASK 3 TEMP_WARNING_ALARM_MASK 2 BACKGROUND_CRC_EN 1 THERMAL_SHUTDOWN_EN 0 OPEN_DRAIN_EN Description Negative Voltage Channel 0 Fault Alarm Mask. When this bit is set, the ALARM pin does not activate when a negative voltage is multiplexed to the MUX_OUT pin due to monitoring Channel 0. 0: normal operation. 1: mask negative Channel 0 ALARM activation. Overtemperature Fault Alarm Mask. When this bit is set, the ALARM pin does not activate for an overtemperature fault occurrence. 0: normal operation. 1: mask overtemperature ALARM activation. Overtemperature Warning Alarm Mask. When this bit is set, the ALARM pin does not activate for an overtemperature warning occurrence. 0: normal operation. 1: mask temperature warning ALARM activation. Background CRC Enable. When this bit is set, a CRC of the memory map contents is periodically computed by the device. 0: disable background CRC. 1: enable background CRC. Thermal Shutdown Enable. When this bit is set, the AD5770R goes into thermal shutdown in the event of an overtemperature fault. 0: disable thermal shutdown (not recommended). 1: enable thermal shutdown. Open-Drain ALARM Enable. When this bit is set, the ALARM pin is configured as an open-drain output. 0: ALARM open-drain disable. 1: ALARM open-drain enable. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x1 R/W 0x0 R/W Reset 0x0 0x0 Access R R/W Address: 0x1D, Reset: 0x00, Name: OUTPUT_FILTER_CH0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3:0] OUTPUT_FILTER_RESISTOR0 (R/W) Output Filter Resistor Setup Channel 0 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 KΩ. 1001: 104 KΩ. Table 36. Bit Descriptions for OUTPUT_FILTER_CH0 Bits [7:4] [3:0] Bit Name Reserved OUTPUT_FILTER_RESISTOR0 Description Reserved. Output Filter Resistor Setup Channel 0. These bits select the internal variable resistor to be used for the output filter on Channel 0. The output filter resistor creates a resistor capacitor filter with the external capacitor connected to the CDAMP_IDAC0 pin. 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Rev. A | Page 45 of 59 AD5770R Data Sheet Address: 0x1E, Reset: 0x00, Name: OUTPUT_FILTER_CH1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3:0] OUTPUT_FILTER_RESISTOR1 (R/W) Output Filter Resistor Setup Channel 1 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Table 37. Bit Descriptions for OUTPUT_FILTER_CH1 Bits [7:4] [3:0] Bit Name Reserved OUTPUT_FILTER_RESISTOR1 Description Reserved. Output Filter Resistor Setup Channel 1. These bits select the internal variable resistor to be used for the output filter on Channel 1. The output filter resistor creates a resistor capacitor filter with the external capacitor connected to the CDAMP_IDAC1 pin. 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Address: 0x1F, Reset: 0x00, Name: OUTPUT_FILTER_CH2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3:0] OUTPUT_FILTER_RESISTOR2 (R/W) Output Filter Resistor Setup Channel 2 0000: 60 Ω. 0101: 5.6 KΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Table 38. Bit Descriptions for OUTPUT_FILTER_CH2 Bits [7:4] [3:0] Bit Name Reserved OUTPUT_FILTER_RESISTOR2 Description Reserved. Output Filter Resistor Setup Channel 2. These bits select the internal variable resistor to be used for the output filter on Channel 2. The output filter resistor creates a resistor capacitor filter with the external capacitor connected to the CDAMP_IDAC2 pin. 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Rev. A | Page 46 of 59 Data Sheet AD5770R Address: 0x20, Reset: 0x00, Name: OUTPUT_FILTER_CH3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3:0] OUTPUT_FILTER_RESISTOR3 (R/W) Output Filter Resistor Setup Channel 3 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Table 39. Bit Descriptions for OUTPUT_FILTER_CH3 Bits [7:4] [3:0] Bit Name Reserved OUTPUT_FILTER_RESISTOR3 Description Reserved. Output Filter Resistor Setup Channel 3. These bits select the internal variable resistor to be used for the output filter on Channel 3. The output filter resistor creates a resistor capacitor filter with the external capacitor connected to the CDAMP_IDAC3 pin. 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Address: 0x21, Reset: 0x00, Name: OUTPUT_FILTER_CH4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3:0] OUTPUT_FILTER_RESISTOR4 (R/W) Output Filter Resistor Setup Channel 4 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Table 40. Bit Descriptions for OUTPUT_FILTER_CH4 Bits [7:4] [3:0] Bit Name Reserved OUTPUT_FILTER_RESISTOR4 Description Reserved. Output Filter Resistor Setup Channel 4. These bits select the internal variable resistor to be used for the output filter on Channel 4. The output filter resistor creates a resistor capacitor filter with the external capacitor connected to the CDAMP_IDAC4 pin. 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Rev. A | Page 47 of 59 AD5770R Data Sheet Address: 0x22, Reset: 0x00, Name: OUTPUT_FILTER_CH5 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3:0] OUTPUT_FILTER_RESISTOR5 (R/W) Output Filter Resistor Setup Channel 5 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Table 41. Bit Descriptions for OUTPUT_FILTER_CH5 Bits [7:4] [3:0] Bit Name Reserved OUTPUT_FILTER_RESISTOR5 Description Reserved. Output Filter Resistor Setup Channel 5. These bits select the internal variable resistor to be used for the output filter on Channel 5. The output filter resistor creates a resistor capacitor filter with the external capacitor connected to the CDAMP_IDAC5 pin. 0000: 60 Ω. 0101: 5.6 kΩ. 0110: 11.2 kΩ. 0111: 22.2 kΩ. 1000: 44.4 kΩ. 1001: 104 kΩ. Reset 0x0 0x0 Access R R/W Reset 0x0 Access R/W 0x0 R/W 0x0 R/W Address: 0x23, Reset: 0x00, Name: MONITOR_SETUP 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] MON_FUNCTION (R/W) Monitor Function Setup 0: Disable. 1: Voltage Monitoring. 10: Current Monitoring. 11: Temperature Monitoring. [3:0] MON_CH (R/W) Monitor Channel Setup 0: Channel 0. 1: Channel 1. 10: Channel 2. 11: Channel 3. 100: Channel 4. 101: Channel 5. [5] MUX_BUFFER (R/W) Multiplexer Buffer Setup 0: Bypass. 1: Enable. [4] IB_EXT_EN (R/W) Tem perature Diode External Bias Current Enable 0: Internal Bias Current. 1: External Bias Current. Table 42. Bit Descriptions for MONITOR_SETUP Bits [7:6] Bit Name MON_FUNCTION 5 MUX_BUFFER 4 IB_EXT_EN Description Monitor Function Setup. These bits configure which on-chip diagnostic function is selected. 0: disable. 1: voltage monitoring. 10: current monitoring. 11: temperature monitoring. Multiplexer Buffer Setup. When this bit is set, the multiplexer buffer is enabled and used to buffer the multiplexer output. Clearing this bit disables the buffer and bypasses it. 0: bypass. 1: enable. Temperature Diode External Bias Current Enable. When this bit is set, an internal bias current for the temperature monitoring diode is shut off. This bias current must then be supplied externally. 0: internal bias current. 1: external bias current. Rev. A | Page 48 of 59 Data Sheet Bits [3:0] Bit Name MON_CH AD5770R Description Monitor Channel Setup. These bits select the channel to be monitored when output voltage or output current diagnostics are enabled. 0: Channel 0. 1: Channel 1. 10: Channel 2. 11: Channel 3. 100: Channel 4. 101: Channel 5. Reset 0x0 Access R/W Reset 0x0 Access R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R Address: 0x24, Reset: 0x00, Name: STATUS 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] BACKGROUND_CRC_STATUS (R) Background CRC Status [0] TEMP_WARNING (R) Overtemperature Warning Status [6:4] RESERVED [1] OVER_TEMP (R) Overtemperature Fault Status [3] IREF_FAULT (R) External IREF Resistor Fault Status [2] NEGATIVE_CHANNEL0 (R) Negative Voltage Channel 0 Status Table 43. Bit Descriptions for STATUS Bits 7 Bit Name BACKGROUND_CRC_STATUS [6:4] 3 Reserved IREF_FAULT 2 NEGATIVE_CHANNEL0 1 OVER_TEMP 0 TEMP_WARNING Description Background CRC Status. Read Only Status Bit. When this bit is high, this signifies that a background CRC of the memory map has failed and a memory bit may have inadvertently flipped. 0: normal. 1: background CRC error activated. Reserved. External IREF Resistor Fault Status. Read only status bit. When this bit is set, a fault has been detected with the external reference current generation resistor, and the internal resistor has been switched to avoid damage to the device. 0: normal. 1: IREF fault activated. Negative Voltage Channel 0 Status. Read only status bit. When this bit is set, a fault has been detected due to a negative voltage being multiplexed to the MUX_OUT pin when monitoring Channel 0. 0: normal. 1: negative Channel 0 activated. Overtemperature Fault Status. Read only status bit. When this bit is set, an overtemperature fault occurrence has been detected. An overtemperature fault occurs when the internal die temperature reaches approximately 145°C. A reset command must be issued to the device to clear this bit. 0: normal. 1: overtemperature activated. Overtemperature Warning Status. Read only status bit. When this bit is set, an overtemperature warning occurrence has been detected. An overtemperature warning occurs when the internal die temperature reaches approximately 125°C. This bit is automatically cleared when the internal die temperature returns below 120°C. 0: normal. 1: temperature warning activated. Rev. A | Page 49 of 59 AD5770R Data Sheet Address: 0x25, Reset: 0x00, Name: HW_LDAC 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] HW_LDAC_MASK_CH0 (R/W) Hardware LDAC Mask Channel 0 0: No Operation. 1: Mask LDAC on Channel 0. [5] HW_LDAC_MASK_CH5 (R/W) Hardware LDAC Mask Channel 5 0: No Operation. 1: Mask LDAC on Channel 5. [1] HW_LDAC_MASK_CH1 (R/W) Hardware LDAC Mask Channel 1 0: No Operation. 1: Mask LDAC on Channel 1. [4] HW_LDAC_MASK_CH4 (R/W) Hardware LDAC Mask Channel 4 0: No Operation. 1: Mask LDAC on Channel 4. [2] HW_LDAC_MASK_CH2 (R/W) Hardware LDAC Mask Channel 2 0: No Operation. 1: Mask LDAC on Channel 2. [3] HW_LDAC_MASK_CH3 (R/W) Hardware LDAC Mask Channel 3 0: No Operation. 1: Mask LDAC on Channel 3. Table 44. Bit Descriptions for HW_LDAC Bits [7:6] 5 Bit Name RESERVED HW_LDAC_MASK_CH5 4 HW_LDAC_MASK_CH4 3 HW_LDAC_MASK_CH3 2 HW_LDAC_MASK_CH2 1 HW_LDAC_MASK_CH1 0 HW_LDAC_MASK_CH0 Description Reserved. Hardware LDAC Mask Channel 5. When this bit is set, activity on the LDAC pin is ignored for Channel 5. 0: no operation. 1: mask LDAC on Channel 5. Hardware LDAC Mask Channel 4. When this bit is set, activity on the LDAC pin is ignored for Channel 4. 0: no operation. 1: mask LDAC on Channel 4. Hardware LDAC Mask Channel 3. When this bit is set, activity on the LDAC pin is ignored for Channel 3. 0: no operation. 1: mask LDAC on Channel 3. Hardware LDAC Mask Channel 2. When this bit is set, activity on the LDAC pin is ignored for Channel 2. 0: no operation. 1: mask LDAC on Channel 2. Hardware LDAC Mask Channel 1. When this bit is set, activity on the LDAC pin is ignored for Channel 1. 0: no operation. 1: mask LDAC on Channel 1. Hardware LDAC Mask Channel 0. When this bit is set, activity on the LDAC pin is ignored for Channel 0. 0: no operation. 1: mask LDAC on Channel 0. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Reset 0x0 0x0 Access R/W R Address: 0x26, Reset: 0x00, Name: CH0_DAC_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] DAC_DATA0[5:0] (R/W) Channel 0 DAC Data [1:0] RESERVED Table 45. Bit Descriptions for CH0_DAC_LSB Bits [7:2] [1:0] Bit Name DAC_DATA0[5:0] RESERVED Description Channel 0 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC0. Reserved. Rev. A | Page 50 of 59 Data Sheet AD5770R Address: 0x27, Reset: 0x00, Name: CH0_DAC_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] DAC_DATA0[13:6] (R/W) Channel 0 DAC Data Table 46. Bit Descriptions for CH0_DAC_MSB Bits [7:0] Bit Name DAC_DATA0[13:6] Description Channel 0 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC0. Reset 0x0 Access R/W Reset 0x0 0x0 Access R/W R Reset 0x0 Access R/W Reset 0x0 0x0 Access R/W R Reset 0x0 Access R/W Address: 0x28, Reset: 0x00, Name: CH1_DAC_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] DAC_DATA1[5:0] (R/W) Channel 1 DAC Data [1:0] RESERVED Table 47. Bit Descriptions for CH1_DAC_LSB Bits [7:2] [1:0] Bit Name DAC_DATA1[5:0] Reserved Description Channel 1 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC1. Reserved. Address: 0x29, Reset: 0x00, Name: CH1_DAC_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] DAC_DATA1[13:6] (R/W) Channel 1 DAC Data Table 48. Bit Descriptions for CH1_DAC_MSB Bits [7:0] Bit Name DAC_DATA1[13:6] Description Channel 1 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC1. Address: 0x2A, Reset: 0x00, Name: CH2_DAC_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] DAC_DATA2[5:0] (R/W) Channel 2 DAC Data [1:0] RESERVED Table 49. Bit Descriptions for CH2_DAC_LSB Bits [7:2] [1:0] Bit Name DAC_DATA2[5:0] Reserved Description Channel 2 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC2. Reserved. Address: 0x2B, Reset: 0x00, Name: CH2_DAC_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] DAC_DATA2[13:6] (R/W) Channel 2 DAC Data Table 50. Bit Descriptions for CH2_DAC_MSB Bits [7:0] Bit Name DAC_DATA2[13:6] Description Channel 2 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC2. Rev. A | Page 51 of 59 AD5770R Data Sheet Address: 0x2C, Reset: 0x00, Name: CH3_DAC_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] DAC_DATA3[5:0] (R/W) Channel 3 DAC Data [1:0] RESERVED Table 51. Bit Descriptions for CH3_DAC_LSB Bits [7:2] [1:0] Bit Name DAC_DATA3[5:0] Reserved Description Channel 3 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC3. Reserved. Reset 0x0 0x0 Access R/W R Reset 0x0 Access R/W Reset 0x0 0x0 Access R/W R Reset 0x0 Access R/W Reset 0x0 0x0 Access R/W R Address: 0x2D, Reset: 0x00, Name: CH3_DAC_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] DAC_DATA3[13:6] (R/W) Channel 3 DAC Data Table 52. Bit Descriptions for CH3_DAC_MSB Bits [7:0] Bit Name DAC_DATA3[13:6] Description Channel 3 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC3. Address: 0x2E, Reset: 0x00, Name: CH4_DAC_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] DAC_DATA4[5:0] (R/W) Channel 4 DAC Data [1:0] RESERVED Table 53. Bit Descriptions for CH4_DAC_LSB Bits [7:2] [1:0] Bit Name DAC_DATA4[5:0] Reserved Description Channel 4 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC4. Reserved. Address: 0x2F, Reset: 0x00, Name: CH4_DAC_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] DAC_DATA4[13:6] (R/W) Channel 4 DAC Data Table 54. Bit Descriptions for CH4_DAC_MSB Bits [7:0] Bit Name DAC_DATA4[13:6] Description Channel 4 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC4. Address: 0x30, Reset: 0x00, Name: CH5_DAC_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] DAC_DATA5[5:0] (R/W) Channel 5 DAC Data [1:0] RESERVED Table 55. Bit Descriptions for CH5_DAC_LSB Bits [7:2] [1:0] Bit Name DAC_DATA5[5:0] Reserved Description Channel 5 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC5. Reserved. Rev. A | Page 52 of 59 Data Sheet AD5770R Address: 0x31, Reset: 0x00, Name: CH5_DAC_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] DAC_DATA5[13:6] (R/W) Channel 5 DAC Data Table 56. Bit Descriptions for CH5_DAC_MSB Bits [7:0] Bit Name DAC_DATA5[13:6] Description Channel 5 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC5. Reset 0x0 Access R/W Address: 0x32, Reset: 0x00, Name: DAC_PAGE_MASK_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] DAC_PAGE_MASK[5:0] (R/W) Page Mas k DAC Data [1:0] RESERVED Table 57. Bit Descriptions for DAC_PAGE_MASK_LSB Bits [7:2] Bit Name DAC_PAGE_MASK[5:0] [1:0] Reserved Description Page Mask DAC Data. Following a write to this register, the DAC code loaded into this register is copied into the DAC register of any channels selected in the CH_SELECT register. Reserved. Reset 0x0 Access R/W 0x0 R Reset 0x0 Access R/W Reset 0x0 0x0 Access R R/W 0x0 R/W Address: 0x33, Reset: 0x00, Name: DAC_PAGE_MASK_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] DAC_PAGE_MASK[13:6] (R/W) Page Mas k DAC Data Table 58. Bit Descriptions for DAC_PAGE_MASK_MSB Bits [7:0] Bit Name DAC_PAGE_MASK[13:6] Description Page Mask DAC Data. Following a write to this register, the DAC code loaded into this register is copied into the DAC register of any channels selected in the CH_SELECT register. Address: 0x34, Reset: 0x00, Name: CH_SELECT 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] SEL_CH5 (R/W) Select Channel 5 0: No Operation. 1: Copy to Channel 5. [4] SEL_CH4 (R/W) Select Channel 4 0: No Operation. 1: Copy to Channel 4. [3] SEL_CH3 (R/W) Select Channel 3 0: No Operation. 1: Copy to Channel 3. [0] SEL_CH0 (R/W) Select Channel 0 0: No Operation. 1: Copy to Channel 0. [1] SEL_CH1 (R/W) Select Channel 1 0: No Operation. 1: Copy to Channel 1. [2] SEL_CH2 (R/W) Select Channel 2 0: No Operation. 1: Copy to Channel 2. Table 59. Bit Descriptions for CH_SELECT Bits [7:6] 5 Bit Name Reserved SEL_CH5 4 SEL_CH4 Description Reserved. Select Channel 5. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to the INPUT_DATA5 bits and data written to the DAC_PAGE_MASK register is copied to the DAC_DATA5 bits. 0: no operation. 1: copy to Channel 5. Select Channel 4. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to the INPUT_DATA4 bits and data written to the DAC_PAGE_MASK register is copied to the DAC_DATA4 bits. 0: no operation. 1: copy to Channel 4. Rev. A | Page 53 of 59 AD5770R Bits 3 Bit Name SEL_CH3 2 SEL_CH2 1 SEL_CH1 0 SEL_CH0 Data Sheet Description Select Channel 3. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to the INPUT_DATA3 bits and data written to the DAC_PAGE_MASK register is copied to the DAC_DATA3 bits. 0: no operation. 1: copy to Channel 3. Select Channel 2. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to the INPUT_DATA2 bits and data written to the DAC_PAGE_MASK register is copied to the DAC_DATA2 bits. 0: no operation. 1: copy to Channel 2. Select Channel 1. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to the INPUT_DATA1 bits and data written to the DAC_PAGE_MASK register is copied to the DAC_DATA1 bits. 0: no operation. 1: copy to Channel 1. Select Channel 0. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to the INPUT_DATA0 bits and data written to the DAC_PAGE_MASK register is copied to the DAC_DATA0 bits. 0: no operation. 1: copy to Channel 0. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W Reset 0x0 Access R/W 0x0 R Reset 0x0 Access R/W Address: 0x35, Reset: 0x00, Name: INPUT_PAGE_MASK_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] INPUT_PAGE_MASK[5:0] (R/W) Input Data Page Mask [1:0] RESERVED Table 60. Bit Descriptions for INPUT_PAGE_MASK_LSB Bits [7:2] Bit Name INPUT_PAGE_MASK[5:0] [1:0] Reserved Description Input Data Page Mask. Following a write to this register, the DAC code loaded into this register is copied into the input register of any channels selected in the CH_SELECT register. Reserved. Address: 0x36, Reset: 0x00, Name: INPUT_PAGE_MASK_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] INPUT_PAGE_MASK[13:6] (R/W) Input Data Page Mas k Table 61. Bit Descriptions for INPUT_PAGE_MASK_MSB Bits [7:0] Bit Name INPUT_PAGE_MASK[13:6] Description Input Data Page Mask. Following a write to this register, the DAC code loaded into this register is copied into the input register of any channels selected in the CH_SELECT register. Rev. A | Page 54 of 59 Data Sheet AD5770R Address: 0x37, Reset: 0x00, Name: SW_LDAC 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] SW_LDAC_CH0 (W) Software LDAC Channel 0 0: No Operation. 1: Load DAC 0. [5] SW_LDAC_CH5 (W) Software LDAC Channel 5 0: No Operation. 1: Load DAC 5. [1] SW_LDAC_CH1 (W) Software LDAC Channel 1 0: No Operation. 1: Load DAC 1. [4] SW_LDAC_CH4 (W) Software LDAC Channel 4 0: No Operation. 1: Load DAC 4. [2] SW_LDAC_CH2 (W) Software LDAC Channel 2 0: No Operation. 1: Load DAC 2. [3] SW_LDAC_CH3 (W) Software LDAC Channel 3 0: No Operation. 1: Load DAC 3. Table 62. Bit Descriptions for SW_LDAC Bits [7:6] 5 Bit Name Reserved SW_LDAC_CH5 4 SW_LDAC_CH4 3 SW_LDAC_CH3 2 SW_LDAC_CH2 1 SW_LDAC_CH1 0 SW_LDAC_CH0 Description Reserved. Software LDAC Channel 5. Setting this bit transfers content from the INPUT_DATA5 bits to the DAC_DATA5 bits. This bit automatically resets after a write to the SW_LDAC register. 0: no operation. 1: load DAC_DATA5. Software LDAC Channel 4. Setting this bit transfers content from the INPUT_DATA4 bits to the DAC_DATA4 bits. This bit automatically resets after a write to the SW_LDAC register. 0: no operation. 1: load DAC_DATA4. Software LDAC Channel 3. Setting this bit transfers content from the INPUT_DATA3 bits to the DAC_DATA3 bits. This bit automatically resets after a write to the SW_LDAC register. 0: no operation. 1: load DAC_DATA3. Software LDAC Channel 2. Setting this bit transfers content from the INPUT_DATA2 bits to the DAC_DATA2 bits. This bit automatically resets after a write to the SW_LDAC register. 0: no operation. 1: load DAC_DATA2. Software LDAC Channel 1. Setting this bit transfers content from the INPUT_DATA1 bits to the DAC_DATA1 bits. This bit automatically resets after a write to the SW_LDAC register. 0: no operation. 1: load DAC_DATA1. Software LDAC Channel 0. Setting this bit transfers content from the INPUT_DATA0 bits to the DAC_DATA0 bits. This bit automatically resets after a write to the SW_LDAC register. 0: no operation. 1: load DAC_DATA0. Reset 0x0 0x0 Access R W 0x0 W 0x0 W 0x0 W 0x0 W 0x0 W Address: 0x38, Reset: 0x00, Name: CH0_INPUT_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] INPUT_DATA0[5:0] (R/W) Input Data Channel 0 [1:0] RESERVED Table 63. Bit Descriptions for CH0_INPUT_LSB Bits [7:2] [1:0] Bit Name INPUT_DATA0[5:0] Reserved Description Input Data Channel 0. These bits are the DAC code loaded into the input register for IDAC0. Reserved. Rev. A | Page 55 of 59 Reset 0x0 0x0 Access R/W R AD5770R Data Sheet Address: 0x39, Reset: 0x00, Name: CH0_INPUT_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] INPUT_DATA0[13:6] (R/W) Input Data Channel 0 Table 64. Bit Descriptions for CH0_INPUT_MSB Bits [7:0] Bit Name INPUT_DATA0[13:6] Description Input Data Channel 0. These bits are the DAC code loaded into the input register for IDAC0. Reset 0x0 Access R/W Reset 0x0 0x0 Access R/W R Reset 0x0 Access R/W Reset 0x0 0x0 Access R/W R Reset 0x0 Access R/W Address: 0x3A, Reset: 0x00, Name: CH1_INPUT_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] INPUT_DATA1[5:0] (R/W) Input Data Channel 1 [1:0] RESERVED Table 65. Bit Descriptions for CH1_INPUT_LSB Bits [7:2] [1:0] Bit Name INPUT_DATA1[5:0] Reserved Description Input Data Channel 1. These bits are the DAC code loaded into the input register for IDAC1. Reserved. Address: 0x3B, Reset: 0x00, Name: CH1_INPUT_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] INPUT_DATA1[13:6] (R/W) Input Data Channel 1 Table 66. Bit Descriptions for CH1_INPUT_MSB Bits [7:0] Bit Name INPUT_DATA1[13:6] Description Input Data Channel 1. These bits are the DAC code loaded into the input register for IDAC1. Address: 0x3C, Reset: 0x00, Name: CH2_INPUT_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] INPUT_DATA2[5:0] (R/W) Input Data Channel 2 [1:0] RESERVED Table 67. Bit Descriptions for CH2_INPUT_LSB Bits [7:2] [1:0] Bit Name INPUT_DATA2[5:0] Reserved Description Input Data Channel 2. These bits are the DAC code loaded into the input register for IDAC2. Reserved. Address: 0x3D, Reset: 0x00, Name: CH2_INPUT_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] INPUT_DATA2[13:6] (R/W) Input Data Channel 2 Table 68. Bit Descriptions for CH2_INPUT_MSB Bits [7:0] Bit Name INPUT_DATA2[13:6] Description Input Data Channel 2. These bits are the DAC code loaded into the input register for IDAC2. Rev. A | Page 56 of 59 Data Sheet AD5770R Address: 0x3E, Reset: 0x00, Name: CH3_INPUT_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] INPUT_DATA3[5:0] (R/W) Input Data Channel 3 MSB [1:0] RESERVED Table 69. Bit Descriptions for CH3_INPUT_LSB Bits [7:2] [1:0] Bit Name INPUT_DATA3[5:0] Reserved Description Input Data Channel 3. These bits are the DAC code loaded into the input register for IDAC3. Reserved. Reset 0x0 0x0 Access R/W R Reset 0x0 Access R/W Address: 0x3F, Reset: 0x00, Name: CH3_INPUT_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] INPUT_DATA3[13:6] (R/W) Input Data Channel 3 MSB Table 70. Bit Descriptions for CH3_INPUT_MSB Bits [7:0] Bit Name INPUT_DATA3[13:6] Description Input Data Channel 3. These bits are the DAC code loaded into the input register for IDAC3. Address: 0x40, Reset: 0x00, Name: CH4_INPUT_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] INPUT_DATA4[5:0] (R/W) Input Data Channel 4 [1:0] RESERVED Table 71. Bit Descriptions for CH4_INPUT_LSB Bits [7:2] [1:0] Bit Name INPUT_DATA4[5:0] Reserved Description Input Data Channel 4. These bits are the DAC code loaded into the input register for IDAC4. Reserved. Reset 0x0 0x0 Access R/W R Reset 0x0 Access R/W Reset 0x0 0x0 Access R/W R Address: 0x41, Reset: 0x00, Name: CH4_INPUT_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] INPUT_DATA4[13:6] (R/W) Input Data Channel 4 Table 72. Bit Descriptions for CH4_INPUT_MSB Bits [7:0] Bit Name INPUT_DATA4[13:6] Description Input Data Channel 4. These bits are the DAC code loaded into the input register for IDAC4. Address: 0x42, Reset: 0x00, Name: CH5_INPUT_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] INPUT_DATA5[5:0] (R/W) Input Data Channel 5 [1:0] RESERVED Table 73. Bit Descriptions for CH5_INPUT_LSB Bits [7:2] [1:0] Bit Name INPUT_DATA5[5:0] Reserved Description Input Data Channel 5. These bits are the DAC code loaded into the input register for IDAC5. Reserved. Rev. A | Page 57 of 59 AD5770R Data Sheet Address: 0x43, Reset: 0x00, Name: CH5_INPUT_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] INPUT_DATA5[13:6] (R/W) Input Data Channel 5 Table 74. Bit Descriptions for CH5_INPUT_MSB Bits [7:0] Bit Name INPUT_DATA5[13:6] Description Input Data Channel 5. These bits are the DAC code loaded into the input register for IDAC5. Reset 0x0 Address: 0x44, Reset: 0x3F, Name: RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7:6] RESERVED0[7:6] (R) RESERVED [5:0] RESERVED1 (R) RESERVED Table 75. Bit Descriptions for RESERVED Bits [7:6] [0:5] Bit Name RESERVED0 RESERVED1 Description Reserved Reserved Rev. A | Page 58 of 59 Reset 0x0 0x1 Access R R Access R/W Data Sheet AD5770R OUTLINE DIMENSIONS 4.080 4.040 SQ 4.000 7 6 5 4 3 2 1 A BALL A1 IDENTIFIER B C 3.00 REF SQ D E F 0.50 BSC TOP VIEW (BALL SIDE DOWN) SEATING PLANE END VIEW BOTTOM VIEW (BALL SIDE UP) 0.390 0.360 0.330 COPLANARITY 0.05 0.360 0.320 0.280 0.270 0.240 0.210 01-09-2018-A PKG-003790 0.660 0.600 0.540 G Figure 78. 49-Ball Wafer Level Chip Scale Package [WLCSP] (CB-49-5) Dimensions shown in millimeters ORDERING GUIDE Model1 AD5770RBCBZ-RL7 EVAL-AD5770RSDZ 1 Temperature Range −40°C to +105°C Package Description 49-Ball Wafer Level Chip Scale Packaging [WLCSP] Evaluation Board Z = RoHS Compliant Part. ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16128-0-11/19(A) Rev. A | Page 59 of 59 Package Option CB-49-5