System Ready, 20-Bit, ±2 LSB INL,
Voltage Output DAC
AD5790
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VCC
VREFP
VDD
A1
IOVCC
6.8kΩ 6.8kΩ
R1
RFB
RFB
INV
SDIN
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
SCLK
SYNC
SDO
20
DAC
REG
20
20-BIT
DAC
VOUT
6kΩ
LDAC
CLR
POWER-ON-RESET
AND CLEAR LOGIC
RESET
DGND
VSS
AD5790
VREFN
AGND
10239-001
Single 20-bit voltage output DAC, ±2 LSB INL
8 nV/√Hz output noise spectral density
0.1 LSB long-term linearity error stability
±0.018 ppm/°C gain error temperature coefficient
2.5 µs output voltage settling time
3.5 nV-sec midscale glitch impulse
Integrated precision reference buffers
Operating temperature range: −40°C to +125°C
4 mm × 5 mm LFCSP package
Wide power supply range of up to ±16.5 V
35 MHz Schmitt-triggered digital interface
1.8 V compatible digital interface
Figure 1.
APPLICATIONS
Medical instrumentation
Test and measurement
Industrial control
Scientific and aerospace instrumentation
Data acquisition systems
Digital gain and offset adjustment
Power supply control
GENERAL DESCRIPTION
The AD5790 1 is a single, 20-bit, unbuffered voltage output digitalto-analog converter (DAC) that operates from a bipolar supply of
up to 33 V. The AD5790 accepts a positive reference input in the
range of 5 V to VDD − 2.5 V and a negative reference input in the
range of VSS + 2.5 V to 0 V. The AD5790 offers a relative
accuracy specification of ±2 LSB maximum range, and
operation is guaranteed monotonic with a −1 LSB to +3 LSB
differential nonlinearity (DNL) specification.
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 35 MHz and is compatible with standard
serial peripheral interface (SPI), QSPI™, MICROWIRE™, and
DSP interface standards. Reference buffers are also provided on
chip. The part incorporates a power-on reset circuit that ensures
the DAC output powers up to 0 V in a known output impedance
state and remains in this state until a valid write to the device
takes place. The part provides a disable feature that places the
output in a defined load state. The part provides an output
clamp feature that places the output in a defined load state.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
20-bit resolution.
Wide power supply range of up to ±16.5 V.
−40°C to +125°C operating temperature range.
Low 8 nV/√Hz noise.
Low ±0.018 ppm/°C gain error temperature coefficient.
COMPANION PRODUCTS
Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1
External Reference: ADR445, ADR4550
DC-to-DC Design Tool: ADIsimPower™
Additional companion products on the AD5790 product page.
Table 1. Related Devices
Part No.
AD5791
AD5780
AD5781
AD5760
AD5541A/AD5542A
1
Description
20-bit, 1 LSB accurate DAC
18-bit, ±1 LSB INL, voltage output DAC ,
buffered reference inputs
18-bit, ±1 LSB INL, voltage Output DAC ,
unbuffered reference inputs
16-bit, ±0.5 LSB INL, voltage Output DAC
16-bit, 1 LSB accurate 5 V DAC
Protected by U.S. Patent No. 7,884,747 and 8,089,380.
Rev. E
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Technical Support
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AD5790
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface ............................................................................ 18
Applications ....................................................................................... 1
Standalone Operation ................................................................ 19
Functional Block Diagram .............................................................. 1
Hardware Control Pins .............................................................. 19
General Description ......................................................................... 1
On-Chip Registers ...................................................................... 19
Product Highlights ........................................................................... 1
AD5790 Features ............................................................................ 23
Companion Products ....................................................................... 1
Power-On to 0 V......................................................................... 23
Revision History ............................................................................... 2
Power-Up Sequence ................................................................... 23
Specifications..................................................................................... 3
Configuring the AD5790 .......................................................... 23
Timing Characteristics ................................................................ 5
DAC Output State ...................................................................... 23
Absolute Maximum Ratings............................................................ 7
Output Amplifier Configuration.............................................. 23
ESD Caution .................................................................................. 7
Applications Information .............................................................. 25
Pin Configuration and Function Descriptions ............................. 8
Typical Operating Circuit ......................................................... 25
Typical Performance Characteristics ............................................. 9
Evaluation Board ........................................................................ 26
Terminology .................................................................................... 17
Outline Dimensions ....................................................................... 27
Theory of Operation ...................................................................... 18
Ordering Guide .......................................................................... 27
DAC Architecture ....................................................................... 18
REVISION HISTORY
4/2018—Rev. D to Rev. E
Added Power-Up Sequence Section and Figure 50; Renumbered
Sequentially ..................................................................................... 23
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
7/2013—Rev. C to Rev. D
Changes to t1 Test Conditions/Comments and Endnote 2 ......... 5
Deleted Figure 4 ................................................................................ 7
Changes to Pin 11 Description ....................................................... 8
Deleted Daisy-Chain Operation Section ..................................... 19
2/2012—Rev. A to Rev. B
Deleted Linearity Compensation Section ................................... 24
12/2011—Rev. 0 to Rev. A
Changes to Table 1.............................................................................1
Changes to Table 2.............................................................................4
Changes to Figure 48...................................................................... 17
Changes to DAC Register Section ................................................ 21
Changes to Table 11 ....................................................................... 22
Updated Outline Dimensions ....................................................... 28
11/2011—Revision 0: Initial Version
7/2012—Rev. B to Rev. C
Changes to Companion Products Section and to Endnote 1 ..... 1
Changes to Terminology Section.................................................. 18
Changes to Figure 53 ...................................................................... 24
Added Figure 55.............................................................................. 26
Rev. E | Page 2 of 27
Data Sheet
AD5790
SPECIFICATIONS
VDD = +12.5 V to +16.5 V, VSS = −16.5 V to −12.5 V, VREFP = +10 V, VREFN = −10 V, VCC = +2.7 V to +5.5 V, IOVCC = +1.71 V to +5.5 V,
RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 2
Resolution
Integral Nonlinearity Error (Relative
Accuracy)
Differential Nonlinearity Error
Long-Term Linearity Error Stability 3
Full-Scale Error
Full-Scale Error Temperature Coefficient
Zero-Scale Error
Zero-Scale Error Temperature Coefficient
Gain Error
Gain Error Temperature Coefficient
R1, RFB Matching
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Settling Time
Output Noise Spectral Density
Output Voltage Noise
Midscale Glitch Impulse4
MSB Segment Glitch Impulse4
Min
20
−2
−3
−4
−1
−1
−12
−22
−40
−9
−12
−22
−19
−40
−82
−8
−13
−22
−19
−35
−68
−9
−15
−22
B Version 1
Typ
Max
±1.2
+2
±1.2
±1.2
+3
+4
+2
+3
0.1
±3.8
±2.7
±1.8
±3.8
±2.7
±1.8
±0.026
±1.3
±0.7
±0.9
±1.3
±0.7
±0.9
±0.025
±2.3
±1.9
±0.9
±2.3
±2.9
±0.9
±0.018
0.015
VREFN
+12
+22
+40
+9
+12
+22
+19
+40
+82
+8
+13
+22
+19
+35
+68
+9
+15
+22
VREFP
Unit
Test Conditions/Comments
Bits
LSB
VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm FSR
ppm FSR
ppm FSR
ppm FSR
ppm FSR
ppm FSR
ppm/°C
%
2.5
V
µs
3.5
8
8
1.1
14
3.5
4
14
3.5
4
µs
nV/√Hz
nV/√Hz
µV p-p
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
Rev. E | Page 3 of 27
VREFP = +10 V, VREFN = −10 V, TA =−40°C to +105°C
VREFx = ±10 V, +10 V, and +5 V
VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C
VREFx = ±10 V, +10 V, and +5 V
After 750 hours at TA = 135°C
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
VREFP = 5 V, VREFN = 0 V
VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C
VREFP = 10 V, VREFN = 0 V, TA = 0°C to 105°C
VREFP = 5 V, VREFN = 0 V, TA = 0°C to 105°C
VREFP = +10 V, VREFN = −10 V
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
VREFP = 5 V, VREFN = 0 V
VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C
VREFP = 10 V, VREFN = 0 V, TA = 0°C to 105°C
VREFP = 5 V, VREFN = 0 V, TA = 0°C to 105°C
VREFP = +10 V, VREFN = −10 V
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
VREFP = 5 V, VREFN = 0 V
VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C
VREFP = 10 V, VREFN = 0 V, TA = 0°C to 105°C
VREFP = 5 V, VREFN = 0 V, TA = 0°C to 105°C
VREFP = +10 V, VREFN = −10 V
10 V step to 0.02%, using the ADA4898-1 buffer
in unity-gain mode
500 code step to ±1 LSB 4
At 1 kHz, DAC code = midscale
At 10 kHz, DAC code = midscale
DAC code = midscale, 0.1 Hz to 10 Hz bandwidth
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
VREFP = 5 V, VREFN = 0 V
VREFP = +10 V, VREFN = −10 V, see Figure 42
VREFP = 10 V, VREFN = 0 V, see Figure 43
VREFP = 5 V, VREFN = 0 V, see Figure 44
AD5790
Parameter
Output Enabled Glitch Impulse
Digital Feedthrough
DC Output Impedance (Normal Mode)
DC Output Impedance (Output
Clamped to Ground)
REFERENCE INPUTS
VREFP Input Range
VREFN Input Range
Input Bias Current
Input Capacitance
LOGIC INPUTS
Input Current 5
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
LOGIC OUTPUT (SDO)
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output Capacitance
POWER REQUIREMENTS
VDD
VSS
VCC
IOVCC
IDD
ISS
ICC
IOICC
DC Power Supply Rejection Ratio
AC Power Supply Rejection Ratio
Data Sheet
Min
5
VSS + 2.5
−20
−4
B Version 1
Typ
Max
57
0.27
3.4
6
−0.63
−0.63
1
−1
VDD − 2.5
0
+20
+4
Unit
nV-sec
nV-sec
kΩ
kΩ
V
V
nA
pF
+1
0.3 × IOVCC
µA
V
V
pF
0.4
V
V
µA
pF
0.7 × IOVCC
5
IOVCC − 0.5
±1
3
Test Conditions/Comments
On removal of output ground clamp
TA = 0°C to 105°C
VREFP, VREFN
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V, sinking 1 mA
IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
All digital inputs at DGND or IOVCC
7.5
VDD − 33
2.7
1.71
10.3
−10
600
52
±7.5
±1.5
90
90
VSS + 33
−2.5
5.5
5.5
14
−14
900
140
V
V
V
V
mA
mA
µA
µA
µV/V
µV/V
dB
dB
IOVCC ≤ VCC
SDO disabled
∆VDD ± 10%, VSS = −15 V
∆VSS ± 10%, VDD = 15 V
∆VDD ± 200 mV, 50 Hz/60 Hz, VSS = −15 V
∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V
Temperature range: −40°C to +125°C, typical conditions: TA = +25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.
Performance characterized with the AD8675ARZ output buffer.
3
Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified.
4
The AD5790 is configured in unity-gain mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead
capacitance, and so forth).
5
Current flowing in an individual logic pin.
1
2
Rev. E | Page 4 of 27
Data Sheet
AD5790
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
1
2
Limit 1
IOVCC = 1.71 V to 3.3 V
IOVCC = 3.3 V to 5.5 V
40
28
92
60
15
10
9
5
5
5
2
2
48
40
8
6
9
7
12
7
13
10
20
16
14
11
130
130
130
130
50
50
140
140
0
0
65
60
62
45
0
0
35
35
150
150
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns min
ns typ
ns min
ns max
ns max
ns min
ns typ
ns typ
Test Conditions/Comments
SCLK cycle time
SCLK cycle time (readback mode)
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge hold time
Minimum SYNC high time
SYNC rising edge to next SCLK falling edge ignore
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
LDAC falling edge to output response time
SYNC rising edge to output response time (LDAC tied low)
CLR pulse width low
CLR pulse activation time
SYNC falling edge to first SCLK rising edge
SYNC rising edge to SDO tristate (CL = 50 pF)
SCLK rising edge to SDO valid (CL = 50 pF)
SYNC rising edge to SCLK rising edge ignore
RESET pulse width low
RESET pulse activation time
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode.
Rev. E | Page 5 of 27
AD5790
Data Sheet
t7
t1
SCLK
1
2
24
t3
t6
t2
t4
t5
SYNC
t9
t8
SDIN
DB23
DB0
t10
t12
t11
LDAC
t13
VOUT
t14
VOUT
t15
CLR
t16
VOUT
t21
RESET
10239-002
t22
VOUT
Figure 2. Write Mode Timing Diagram
t1
t17
SCLK
1
2
24
t3
t6
t20
t7
1
2
24
t2
t5
t4
t5
t17
SYNC
SDIN
t9
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
t18
t19
DB23
SDO
REGISTER CONTENTS CLOCKED OUT
Figure 3. Readback Mode Timing Diagram
Rev. E | Page 6 of 27
DB0
10239-003
t8
Data Sheet
AD5790
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 4.
Parameter
VDD to AGND
VSS to AGND
VDD to VSS
VCC to DGND
IOVCC to DGND
Digital Inputs to DGND
VOUT to AGND
VREFP to AGND
VREFN to AGND
DGND to AGND
Operating Temperature Range, TA
Industrial
Storage Temperature Range
Maximum Junction Temperature,
TJ max
Power Dissipation
LFCSP Package
θJA Thermal Impedance
Lead Temperature
Soldering
ESD (Human Body Model)
Rating
−0.3 V to +34 V
−34 V to +0.3 V
−0.3 V to +34 V
−0.3 V to +7 V
−0.3 V to VCC + 3 V or +7 V
(whichever is less)
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
VSS − 0.3 V to + 0.3 V
−0.3 V to +0.3 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
This device is a high performance integrated circuit with an
ESD rating of
