AD586

Preliminary Technical Data FEATURES Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DACs AD5762R GENERAL DESCRIPTION The AD5762R is a dual, 16-bit, serial input, bipolar voltage output digital-to-analog converter that operates from supply voltages of ±11.4 V up to ±16.5 V. Nominal full-scale output range is ±10 V. The AD5762R provides integrated output amplifiers, reference buffers and proprietary power-up/powerdown control circuitry. The parts also feature a digital I/O port, which is programmed via the serial interface and an analog temperature sensor. The part incorporates digital offset and gain adjust registers per channel. The AD5762R is a high performance converter that offers guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB, low noise, and 10 µs settling time. The AD5762R includes an on-chip 5 V reference with a reference tempco of 10 ppm/°C maximum. During power-up (when the supply voltages are changing), VOUT is clamped to 0 V via a low impedance path. The AD5762R uses a serial interface that operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or offset binary formats. The asynchronous clear function clears all DAC registers to either bipolar zero or zero scale depending on the coding used. The AD5762R is ideal for both closed-loop servo control and open-loop control applications. The AD5762R is available in a 32-lead TQFP, and offers guaranteed specifications over the −40°C to +85°C industrial temperature range. See Figure 1, the functional block diagram. Complete dual, 16-bit digital-to-analog converters (DACs) Programmable output range: ±10 V, ±10.2564 V, or ±10.5263 V ±1 LSB max INL error, ±1 LSB max DNL error Low noise: 60 nV/√Hz Settling time: 10 µs max Integrated reference buffers Internal reference: 10 ppm/°C On-chip die temperature sensor Output control during power-up/brownout Programmable short-circuit protection Simultaneous updating via LDAC Asynchronous CLR to zero code Digital offset and gain adjust Logic output control pins DSP-/microcontroller-compatible serial interface Temperature range: −40°C to +85°C iCMOS™ process technology1 APPLICATIONS Industrial automation Open-/closed-loop servo control Process control Data acquisition systems Automatic test equipment Automotive test and measurement High accuracy instrumentation 1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, and increased AC and DC performance. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD5762R TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 AC Performance Characteristic...................................................... 6 Timing Characteristics..................................................................... 7 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Terminology .................................................................................... 13 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 21 DAC Architecture....................................................................... 21 Reference Buffers........................................................................ 21 Serial Interface ............................................................................ 21 Simultaneous Updating via LDAC ........................................... 22 Transfer Function ....................................................................... 23 Asynchronous Clear (CLR)....................................................... 23 Function Register ....................................................................... 24 Preliminary Technical Data Data Register............................................................................... 25 Coarse Gain Register ................................................................. 25 Fine Gain Register...................................................................... 25 Offset Register ............................................................................ 25 Offset and Gain Adjustment Worked Example...................... 27 AD5762R Features.......................................................................... 28 Analog Output Control ............................................................. 28 Digital Offset and Gain Control............................................... 28 Programmable Short-Circuit Protection ................................ 28 Digital I/O Port........................................................................... 28 die Temperature Sensor............................................................. 28 Local Ground Offset Adjust...................................................... 28 Applications Information .............................................................. 29 Typical Operating Circuit ......................................................... 29 Layout Guidelines........................................................................... 30 Galvanically Isolated Interface ................................................. 30 Microprocessor Interfacing....................................................... 30 Evaluation Board ........................................................................ 32 Outline Dimensions ....................................................................... 33 Ordering Guide .......................................................................... 33 REVISION HISTORY Preliminary Revision PrA December 10, 2007 Rev. PrA | Page 2 of 33 Preliminary Technical Data FUNCTIONAL BLOCK DIAGRAM PGND AVDD AVSS AVDD AVSS REFOUT REFGND REFA VOLTAGE MONITOR AND CONTROL RSTOUT AD5762R RSTIN DVCC DGND AD5762R 16 +5V REFERENCE REFERENCE BUFFERS ISCC SDIN SCLK SYNC SDO D0 D1 BIN/2SCOMP INPUT SHIFT REGISTER AND CONTROL LOGIC INPUT REG A GAIN REG A OFFSET REG A DAC REG A 16 G1 DAC A G2 AGNDA VOUTA INPUT REG B GAIN REG B OFFSET REG B DAC REG B 16 G1 DAC B G2 REFERENCE BUFFERS AGNDB TEMP SENSOR VOUTB CLR LDAC REFB TEMP Figure 1. Functional Block Diagram Rev. PrA | Page 3 of 33 AD5762R SPECIFICATIONS Preliminary Technical Data AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA, REFB = 5 V external; DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter ACCURACY Resolution Relative Accuracy (INL) Differential Nonlinearity Bipolar Zero Error Bipolar Zero TC3 Zero-Scale Error Zero-Scale TC3 Gain Error Gain TC3 DC Crosstalk3 REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage DC Input Impedance Input Current Reference Range Reference Output Output Voltage Reference TC Load3 Output Noise3 (0.1 Hz to 10 Hz) Noise Spectral Density3 Output Voltage Drift vs. Time Output Voltage Drift vs. Time Line Regulation Load Regulation Thermal Hysteresis OUTPUT CHARACTERISTICS3 Output Voltage Range4 Output Voltage Drift vs. Time Short Circuit Current Load Current Capacitive Load Stability RL = ∞ RL = 10 kΩ DC Output Impedance C Grade2 16 ±1 ±1 ±2 ±2 ±2 ±2 ±0.02 ±2 0.5 Unit Bits LSB max LSB max mV max ppm FSR/°C max mV max ppm FSR/°C max % FSR max ppm FSR/°C max LSB max Test Conditions/Comments Outputs unloaded Guaranteed monotonic At 25°C; error at other temperatures obtained using bipolar zero TC At 25°C; error at other temperatures obtained using zero scale TC At 25°C; error at other temperatures obtained using gain TC 5 1 ±10 1/7 4.997/5.003 ±10 1 18 75 ±40 ±50 TBD TBD TBD ±10.5263 ±14 ±13 ±15 10 ±1 200 1000 0.3 V nominal MΩ min µA max V min/V max V min/V max ppm/°C max MΩ min µV p-p typ nV/√Hz typ ppm/500hr typ ppm/1000hr typ ppm/V typ ppm/mA typ ppm typ V min/V max V min/V max ppm FSR/500 hours typ ppm FSR/1000 hours typ mA typ mA max pF max pF max Ω max ±1% for specified performance Typically 100 MΩ Typically ±30 nA At 25°C At 10 kHz AVDD/AVSS = ±11.4 V, REFA, REFB = 5V AVDD/AVSS = ±16.5 V, REFA, REFB = 7V RISCC = 6 kΩ, see Figure 31 For specified performance Rev. PrA | Page 4 of 33 Preliminary Technical Data Parameter DIGITAL INPUTS3 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance DIGITAL OUTPUTS (D0, D1, SDO)3 Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance DIE TEMPERATURE SENSOR3 Output Voltage at 25°C Output Voltage Scale Factor Output Voltage Range Output Load Current Power-On Time POWER REQUIREMENTS AVDD/AVSS DVCC Power Supply Sensitivity3 ∆VOUT/∆ΑVDD AIDD AISS DICC Power Dissipation 2 3 AD5762R C Grade2 2 0.8 ±1 10 0.4 DVCC − 1 0.4 DVCC − 0.5 ±1 5 1.4 5 1.175/1.9 200 80 11.4/16.5 2.7/5.25 −85 3.5 2.75 1.2 140 Unit V min V max µA max pF max V max V min V max V min µA max pF typ V typ mV/°C typ V min/V max µA max ms typ V min/V max V min/V max dB typ mA/channel max mA/channel max mA max mW typ Test Conditions/Comments DVCC = 2.7 V to 5.25 V, JEDEC compliant Per pin Per pin DVCC = 5 V ± 5%, sinking 200 µA DVCC = 5 V ± 5%, sourcing 200 µA DVCC = 2.7 V to 3.6 V, sinking 200 µA DVCC = 2.7 V to 3.6 V, sourcing 200 µA SDO only SDO only Die temperature −40°C to 105°C Current source only Outputs unloaded Outputs unloaded VIH = DVCC, VIL = DGND, 750 µA typ ±12 V operation output unloaded Temperature range : -40°C to +85°C; typical at 25°C. Device functionality is guaranteed to +105°C with degraded performance. Guaranteed by design and characterization; not production tested. 4 Output amplifier headroom requirement is 1.4 V minimum. Rev. PrA | Page 5 of 33 AD5762R AC PERFORMANCE CHARACTERISTIC Preliminary Technical Data AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA, REFB= 5 V external; DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested. Table 2. Parameter DYNAMIC PERFORMANCE1 Output Voltage Settling Time C Grade 8 10 2 5 8 25 80 8 2 2 0.1 45 1 60 80 Unit µs typ µs max µs typ V/µs typ nV-s typ mV max dB typ nV-s typ nV-s typ nV-s typ LSB p-p typ µV rms max kHz typ nV/√Hz typ nV/√Hz typ Test Conditions/Comments Full-scale step to ±1 LSB 512 LSB step settling Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise (0.1 Hz to 10 Hz) Output Noise (0.1 Hz to 100 kHz) 1/f Corner Frequency Output Noise Spectral Density Complete System Output Noise Spectral Density2 1 2 Effect of input bus activity on DAC outputs Measured at 10 kHz Measured at 10 kHz Guaranteed by design and characterization; not production tested. Includes noise contributions from integrated reference buffers,16-bit DAC and output amplifier. Rev. PrA | Page 6 of 33 Preliminary Technical Data TIMING CHARACTERISTICS AD5762R AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA, REFB= 5 V external; DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2, 3 t1 t2 t3 t4 t54 t6 t7 t8 t9 t10 t11 t12 t13 t14 t155, 6 t16 t17 t18 1 2 3 Limit at TMIN, TMAX 33 13 13 13 13 40 2 5 1.4 400 10 500 10 10 2 25 13 2 170 Unit ns min ns min ns min ns min ns min ns min ns min ns min µs min ns min ns min ns max µs max ns min µs max ns max ns min µs min ns min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th SCLK falling edge to SYNC rising edge Minimum SYNC high time Data setup time Data hold time SYNC rising edge to LDAC falling edge (all DACs updated) SYNC rising edge to LDAC falling edge (single DAC updated) LDAC pulse width low LDAC falling edge to DAC output response time DAC output settling time CLR pulse width low CLR pulse activation time SCLK rising edge to SDO valid SYNC rising edge to SCLK falling edge SYNC rising edge to DAC output response time (LDAC = 0) LDAC falling edge to SYNC rising edge Guaranteed by design and characterization; not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. See Figure 2, Figure 3, and Figure 4. 4 Standalone mode only. 5 Measured with the load circuit of Figure 5. 6 Daisy-chain mode only. Rev. PrA | Page 7 of 33 AD5762R t1 SCLK 1 2 24 Preliminary Technical Data t6 t4 SYNC t3 t2 t5 t7 SDIN DB23 t8 DB0 t10 LDAC t9 t10 t18 VOUT t12 t11 LDAC = 0 t12 VOUT t17 CLR t13 t14 06064-002 VOUT Figure 2. Serial Interface Timing Diagram t1 SCLK 24 48 t6 t4 SYNC t3 t2 t5 t16 t7 SDIN DB23 t8 DB0 DB23 DB0 INPUT WORD FOR DAC N SDO t15 DB23 INPUT WORD FOR DAC N–1 DB0 UNDEFINED LDAC INPUT WORD FOR DAC N t9 t10 Figure 3. Daisy Chain Timing Diagram Rev. PrA | Page 8 of 33 Preliminary Technical Data SCLK 24 48 AD5762R SYNC SDIN DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ SDO DB23 NOP CONDITION DB0 06064-004 UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 4. Readback Timing Diagram 200µA IOL TO OUTPUT PIN CL 50pF 200µA IOH VOH (MIN) OR VOL (MAX) 06064-005 Figure 5. Load Circuit for SDO Timing Diagram Rev. PrA | Page 9 of 33 AD5762R ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter AVDD to AGND, DGND AVSS to AGND, DGND DVCC to DGND Digital Inputs to DGND Digital Outputs to DGND REFA, REFB to AGND, PGND REFOUT to AGND TEMP VOUTA, VOUTB to AGND AGND to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) 32-Lead TQFP θJA Thermal Impedance θJC Thermal Impedance Lead Temperature Soldering Rating −0.3 V to +17 V +0.3 V to −17 V −0.3 V to +7 V −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to DVCC + 0.3 V −0.3 V to AVDD + 0.3V AVSS to AVDD AVSS to AVDD AVSS to AVDD −0.3 V to +0.3 V −40°C to +85°C −65°C to +150°C 150°C 65°C/W 12°C/W JEDEC Industry Standard J-STD-020 Preliminary Technical Data Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrA | Page 10 of 33 Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BIN/2sCOMP AVDD AVSS TEMP REFGND REFOUT REFB REFA AD5762R 32 25 24 PIN 1 INDICATOR SYNC SCLK SDIN SDO CLR LDAC D0 D1 1 AD5762R TOP VIEW (Not to Scale) 8 9 16 17 NC NC VOUTA AGNDA AGNDB VOUTB NC NC Figure 6. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 51 6 Mnemonic SYNC SCLK SDIN SDO CLR1 LDAC Description Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000. Load DAC. Logic input. This is used to update the DAC registers and consequently the analog outputs. When tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected. D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are configurable and readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND. Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it can be used to control other system components. Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain unchanged. Digital Ground Pin. Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V. Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V. Ground Reference Point for Analog Circuitry. Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V. This pin is used in association with an optional external resistor to AGND to program the short-circuit current of the output amplifiers. Refer to the Features section for further details. No Internal Connection No Internal Connection 7, 8 D0, D1 9 10 RSTOUT RSTIN 11 12 13, 31 14 15, 30 16 DGND DVCC AVDD PGND AVSS ISCC 17 18 NC NC RSTOUT RSTIN DGND DVCC AVDD PGND AVSS ISCC Rev. PrA | Page 11 of 33 AD5762R Pin No. 19 20 21 22 23 24 25 26 27 28 29 32 Mnemonic VOUTB AGNDB AGNDA VOUTA NC NC REFA REFB REFOUT REFGND TEMP BIN/2sCOMP Preliminary Technical Data Description Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. Ground Reference Pin for DAC B Output Amplifier. Ground Reference Pin for DAC A Output Amplifier. Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. Do not connect to this pin Do not connect to this pin External Reference Voltage. Reference input range is 1 V to 7 V; programs the fullscale output voltage. REFA = 5 V for specified performance. External Reference Voltage. Reference input range is 1 V to 7 V; programs the fullscale output voltage. REFB = 5 V for specified performance. Reference Output. This is the reference output from the internal voltage reference. The internal reference is 5 V ± 3 mV at 25°C, with a reference tempco of 10 ppm/°C. Reference Ground Return for the Reference Generator and Buffers. This pin provides an output voltage proportional to temperature. The output voltage is 1.4 V typical at 25°C die temperature; variation with temperature is 5 mV/°C. Determines the DAC Coding. This pin should be hardwired to either DVCC or DGND. When hardwired to DVCC, input coding is offset binary. When hardwired to DGND, input coding is twos complement (see Table 6). 1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition. Rev. PrA | Page 12 of 33 Preliminary Technical Data TERMINOLOGY Relative Accuracy or Integral nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 7. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic. A typical DNL vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5762R is monotonic over its full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (offset binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Figure 22. Bipolar Zero TC Bipolar zero TC is the measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally the output voltage should be 2 × VREF − 1 LSB. Full-scale error is expressed in percentage of full-scale range. Negative Full-Scale Error/Zero Scale Error Negative full-scale error is the error in the DAC output voltage when 0x0000 (offset binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage should be −2 × VREF. A plot of zero-scale error vs. temperature can be seen in Figure 21. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltageoutput D/A converter is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs. AD5762R Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. A plot of gain error vs. temperature can be seen in Figure 23. Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error considering all the various errors. A plot of total unadjusted error vs. reference can be seen in Figure 19. Zero-Scale Error TC Zero-scale error TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C. Gain Error TC Gain error TC is a measure of the change in gain error with changes in temperature. Gain Error TC is expressed in (ppm of FSR)/°C. Digital-to-Analog Glitch Energy Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 28). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC, and is expressed in LSBs. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Rev. PrA | Page 13 of 33 AD5762R Channel-to-Channel Isolation Channel-to-channel isolation is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dB. Reference TC Reference TC is a measure of the change in the reference output voltage with a change in temperature. It is expressed in ppm/°C. Preliminary Technical Data Digital Crosstalk Digital crosstalk is a measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Rev. PrA | Page 14 of 33 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 0.6 DNL ERROR (LSB) AD5762R 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 06064-007 TA = 25°C VDD/VSS = ±15V REFIN = 5V TA = 25°C VDD/VSS = ±12V REFIN = 5V 0.4 INL ERROR (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 10000 20000 30000 40000 50000 60000 0 10000 20000 30000 40000 50000 60000 DAC CODE DAC CODE Figure 7. Integral Nonlinearity Error vs. Code, VDD/VSS = ±15 V 1.0 TA = 25°C 0.8 VDD/VSS = ±12V REFIN = 5V 0.6 0.4 INL ERROR (LSB) Figure 10. Differential Nonlinearity Error vs. Code, VDD/VSS = ±12 V 0.5 0.4 0.3 INL ERROR (LSB) TA = 25°C VDD/VSS = ±15V REFIN = 5V 0.2 0 –0.2 –0.4 –0.6 –0.8 06064-008 0.2 0.1 0 –0.1 –0.2 –40 0 10000 20000 30000 40000 50000 60000 –20 0 20 40 60 80 100 DAC CODE TEMPERATURE (°C) Figure 8. Integral Nonlinearity Error vs. Code, VDD/VSS = ±12 V 1.0 0.8 0.6 DNL ERROR (LSB) Figure 11. Integral Nonlinearity Error vs. Temperature, VDD/VSS = ±15 V 0.5 TA = 25°C VDD/VSS = ±12V REFIN = 5V TA = 25°C VDD/VSS = ±15V REFIN = 5V 0.4 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 06064-011 INL ERROR (LSB) 0.3 0.2 0.1 0 0 10000 20000 30000 40000 50000 60000 –20 0 20 40 60 80 100 DAC CODE TEMPERATURE (°C) Figure 9. Differential Nonlinearity Error vs. Code, VDD/VSS = ±15 V Figure 12. Integral Nonlinearity Error vs. Temperature, VDD/VSS = ±12 V Rev. PrA | Page 15 of 33 06064-016 –1.0 –0.1 –40 06064-015 –1.0 06064-012 –1.0 AD5762R 0.15 0.10 0.05 DNL ERROR (LSB) Preliminary Technical Data 0.15 0.10 0.05 DNL ERROR (LSB) TA = 25°C REFIN = 5V 0 –0.05 –0.10 –0.15 –0.20 –0.25 –40 TA = 25°C VDD/VSS = ±15V REFIN = 5V 06064-019 0 –0.05 –0.10 –0.15 –0.20 –0.25 11.4 –20 0 20 40 60 80 100 12.4 13.4 14.4 15.4 16.4 TEMPERATURE (°C) SUPPLY VOLTAGE (V) Figure 13. Differential Nonlinearity Error vs. Temperature, VDD/VSS = ±15 V 0.15 0.10 0.05 DNL ERROR (LSB) Figure 16. Differential Nonlinearity Error vs. Supply Voltage 0.8 TA = 25°C 0.6 0.4 0 –0.05 –0.10 –0.15 –0.20 –0.25 –40 TA = 25°C VDD/VSS = ±12V REFIN = 5V 06064-020 INL ERROR (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 06064-027 –20 0 20 40 60 80 100 –1.0 1 2 3 4 5 6 7 TEMPERATURE (°C) REFERENCE VOLTAGE (V) Figure 14. Differential Nonlinearity Error vs. Temperature, VDD/VSS = ±12 V 0.5 0.4 0.3 TA = 25°C REFIN = 5V Figure 17. Integral Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±16.5 V 0.4 TA = 25°C 0.3 0.2 DNL ERROR (LSB) INL ERROR (LSB) 0.1 0 –0.1 –0.2 –0.3 –0.4 0.2 0.1 0 –0.1 –0.2 11.4 06064-023 12.4 13.4 14.4 15.4 16.4 1 2 3 4 5 6 7 SUPPLY VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 15. Integral Nonlinearity Error vs. Supply Voltage Figure 18. Differential Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±16.5 V Rev. PrA | Page 16 of 33 06064-031 06064-025 Preliminary Technical Data 0.8 REFIN = 5V 0.6 VDD/VSS = ±15V 0.6 0.8 REFIN = 5V VDD/VSS = ±15V AD5762R BIPOLAR ZERO ERROR (mV) BIPOLAR ZERO ERROR (mV) 0.4 VDD/VSS = ±12V 0.2 0.4 VDD/VSS = ±12V 0.2 0 0 –0.2 –0.2 06064-039 –20 0 20 40 60 80 100 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. Total Unadjusted Error vs. Reference Voltage, VDD/VSS = ±16.5 V 14 TA = 25°C REFIN = 5V 13 |IDD| 1.4 Figure 22. Bipolar Zero Error vs. Temperature REFIN = 5V 1.2 1.0 GAIN ERROR (mV) CURRENT (mA) 12 VDD/VSS = ±12V 0.8 0.6 0.4 0.2 0 –0.2 –40 11 10 |ISS| 9 VDD/VSS = ±15V 12.4 13.4 14.4 15.4 16.4 06064-037 –20 0 20 40 60 80 100 VDD/VSS (V) TEMPERATURE (°C) Figure 20. IDD/ISS vs. VDD/VSS 0.25 0.20 0.15 REFIN = 5V VDD/VSS = ±15V 0.0014 0.0013 VDD/VSS = ±12V 0.0012 0.0011 Figure 23. Gain Error vs. Temperature TA = 25°C 5V ZERO-SCALE ERROR (mV) 0.10 0.05 0 –0.05 –0.10 DICC (mA) 0.0010 0.0009 0.0008 –0.15 –0.20 06064-038 3V 0.0007 0.0006 –20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 VLOGIC 3.0 3.5 4.0 4.5 5.0 TEMPERATURE (°C) Figure 21. Zero-Scale Error vs. Temperature Figure 24. DICC vs. Logic Input Voltage Rev. PrA | Page 17 of 33 06064-041 –0.25 –40 06064-040 8 11.4 06064-039 –0.4 –40 –0.4 –40 AD5762R 7000 6000 TA = 25°C REFIN = 5V RISCC = 6kΩ Preliminary Technical Data –4 –6 VDD/VSS = ±15V VDD/VSS = ±12V OUTPUT VOLTAGE DELTA (µV) –8 –10 –12 VOUT (mV) 5000 4000 3000 2000 1000 –14 –16 –18 –20 –22 VDD/VSS = ±12V, REFIN = 5V, TA = 25°C, 0x8000 TO 0x7FFF, 500ns/DIV 06064-047 05303-042 0 –1000 –10 –24 –5 0 5 10 –26 –2.0–1.5–1.0–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 TIME (µs) SOURCE/SINK CURRENT (mA) Figure 25. Source and Sink Capability of Output Amplifier with Positive Full Scale Loaded 10000 9000 OUTPUT VOLTAGE DELTA (µV) Figure 28. Major Code Transition Glitch Energy, VDD/VSS = ±12 V 8000 7000 6000 5000 4000 3000 2000 1000 0 TA = 25°C REFIN = 5V RISCC = 6kΩ 15V SUPPLIES VDD/VSS = ±15V MIDSCALE LOADED REFIN = 0V 12V SUPPLIES 4 –1000 –12 –7 –2 3 8 05303-043 SOURCE/SINK CURRENT (mA) Figure 26. Source and Sink Capability of Output Amplifier with Negative Full Scale Loaded VDD/VSS = ±15V TA = 25°C REFIN = 5V CH4 50.0µV M1.00s CH4 26µV Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth) T VDD/VSS = ±12V, REFIN = 5V, TA = 25°C, RAMP TIME = 100µs, LOAD = 200pF||10kΩ 1 2 3 CH1 10.0V BW CH2 10.0V CH3 10.0mV BW M100µs T 29.60% A CH1 7.80mV Figure 27. Full-Scale Settling Time Figure 30. VOUT vs. VDD/VSS on Power-Up Rev. PrA | Page 18 of 33 06064-055 CH1 3.00V M1.00µs CH1 –120mV 06064-044 1 1µs/DIV 06064-048 50µV/DIV Preliminary Technical Data 10 9 VDD/VSS = ±15V TA = 25°C REFIN = 5V VDD/VSS = ±12V TA = 25°C AD5762R SHORT-CIRCUIT CURRENT (mA) 8 7 6 5 1 4 3 2 1 0 20 40 60 RISCC (kΩ) 80 100 120 06064-050 06064-053 0 5µV/DIV M1.00s A CH1 18mV Figure 31. Short-Circuit Current vs. RISCC T Figure 34. REFOUT Output Noise 0.1 Hz to 10 Hz VDD/VSS = ±12V TA = 25°C 1 2 3 CH1 10.0V BW CH2 10.0V CH3 5.00V BW M400µs T 29.60% A CH1 7.80mV Figure 32. REFOUT Turn-On Transient 06064-054 Figure 35. REFOUT Load Regulation VDD/VSS = ±12V TA = 25°C, 10µF CAPACITOR ON REFOUT 1 CH1 50.0µV M1.00s A CH1 15µV 06064-052 50µV/DIV Figure 36. REFOUT Histogram of Thermal Hysteresis Figure 33. REFOUT Output Noise 100 kHz Bandwidth Rev. PrA | Page 19 of 33 AD5762R Preliminary Technical Data Figure 37. TEMP Voltage vs. Temperature Rev. PrA | Page 20 of 33 Preliminary Technical Data THEORY OF OPERATION The AD5762R is a dual, 16-bit, serial input, bipolar voltage output DAC and operates from supply voltages of ±11.4 V to ±16.5 V and has a buffered output voltage of up to ±10.5263 V. Data is written to the AD5762R in a 24-bit word format, via a 3-wire serial interface. The AD5762R also offers an SDO pin, which is available for daisy chaining or readback. The AD5762R incorporates a power-on reset circuit, which ensures that the DAC registers power up loaded with 0x0000. The AD5762R features a digital I/O port that can be programmed via the serial interface, an analog die temperature sensor, on-chip 10 ppm/°C voltage reference, on-chip reference buffers and per channel digital gain and offset registers. AD5762R SERIAL INTERFACE The AD5762R is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI®, QSPI™, MICROWIRE™, and DSP standards. Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits and 16 data bits as shown in Table 7. The timing diagram for this operation is shown in Figure 2. Upon power-up, the DAC registers are loaded with zero code (0x0000) and the outputs are clamped to 0 V via a low impedance path. The outputs can be updated with the zero code value by asserting either LDAC or CLR. The corresponding output voltage depends on the state of the BIN/2sCOMP pin. If the BIN/2sCOMP pin is tied to DGND, then the data coding is twos complement and the outputs update to 0 V. If the BIN/2sCOMP pin is tied to DVCC, then the data coding is offset binary and the outputs update to negative full scale. To have the outputs power-up with zero code loaded to the outputs, the CLR pin should be held low during power-up. DAC ARCHITECTURE The DAC architecture of the AD5762R consists of a 16-bit current mode segmented R-2R DAC. The simplified circuit diagram for the DAC section is shown in Figure 38. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of the 15 matched resistors to either AGND or IOUT. The remaining 12 bits of the data word drive switches S0 to S11 of the 12-bit R2R ladder network. VREF 2R 2R R R R 2R 2R 2R 2R 2R Standalone Operation R/8 IOUT VOUT 06064-060 E15 E14 E1 S11 S10 S0 AGND 4 MSBs DECODED INTO 15 EQUAL SEGMENTS 12-BIT, R-2R LADDER Figure 38. DAC Ladder Structure REFERENCE BUFFERS The AD5762R can operate with either an external or an internal reference. The reference input has an input range up to 7 V. This input voltage is then used to provide a buffered positive and negative reference for the DAC cores. The positive reference is given by + VREF = 2 × VREFIN While the negative reference to the DAC cores is given by −VREF = −2 × VREFIN These positive and negative reference voltages (along with the gain register values) define the output ranges of the DACs. The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought back high again. If SYNC is brought high before the 24th falling SCLK edge, then the data written is invalid. If more than 24 falling SCLK edges are applied before SYNC is brought high, then the input data is also invalid. The input register addressed is updated on the rising edge of SYNC. In order for another serial transfer to take place, SYNC must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. When the data has been transferred into the chosen register of the addressed DAC, all DAC registers and outputs can be updated by taking LDAC low. Rev. PrA | Page 21 of 33 AD5762R 68HC11* MOSI SCK PC7 PC6 MISO AD5762R* SDIN SCLK SYNC LDAC SDO Preliminary Technical Data A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data. Readback Operation Before a readback operation is initiated, the SDO pin must be enabled by writing to the function register and clearing the SDO DISABLE bit; this bit is cleared by default. Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bit A2 to Bit A0, in association with Bit REG2, Bit REG1, and Bit REG0, select the register to be read. The remaining data bits in the write sequence are don’t care. During the next SPI write, the data appearing on the SDO output contain the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the fine gain register of Channel A on the AD5762R, the following sequence should be implemented: 1. Write 0xA0XXXX to the AD5762R input register. This configures the AD5762R for read mode with the fine gain register of Channel A selected. Note that all the data bits, DB15 to DB0, are don’t care. 2. Follow this with a second write, a NOP condition, 0x00XXXX. During this write, the data from the fine gain register is clocked out on the SDO line, that is, data clocked out contains the data from the fine gain register in Bit DB5 to Bit DB0. SDIN AD5762R* SCLK SYNC LDAC SDO SDIN AD5762R* SCLK SYNC LDAC SDO *ADDITIONAL PINS OMITTED FOR CLARITY Figure 39. Daisy Chaining the AD5762R Daisy-Chain Operation For systems that contain several devices, the SDO pin can be used to daisy chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD5762R devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. SIMULTANEOUS UPDATING VIA LDAC Depending on the status of both SYNC and LDAC, and after data has been transferred into the input register of the DACs, there are two ways in which the DAC registers and DAC outputs can be updated. Individual DAC Updating In this mode, LDAC is held low while data is being clocked into the input shift register. The addressed DAC output is updated on the rising edge of SYNC. Simultaneous Updating of All DACs In this mode, LDAC is held high while data is being clocked into the input shift register. All DAC outputs are updated by taking LDAC low any time after SYNC has been taken high. The update now occurs on the falling edge of LDAC. Rev. PrA | Page 22 of 33 Preliminary Technical Data OUTPUT I/V AMPLIFIER VREFIN 16-BIT DAC VOUT AD5762R The output voltage expression for the AD5762R is given by ⎡D⎤ VOUT = −2 × VREFIN + 4 × VREFIN ⎢ ⎥ ⎣ 65536 ⎦ where: D is the decimal equivalent of the code loaded to the DAC. VREFIN is the reference voltage applied at the REFA, REFB pins. LDAC DAC REGISTER INPUT REGISTER ASYNCHRONOUS CLEAR (CLR) SDO 06064-062 SCLK SYNC SDIN INTERFACE LOGIC Figure 40. Simplified Serial Interface of Input Loading Circuitry for One DAC Channel TRANSFER FUNCTION Table 6 shows the ideal input code to output voltage relationship for the AD5762R for both offset binary and twos complement data coding. Table 6. Ideal Output Voltage to Input Code Relationship for the AD5762R Digital Input Offset Binary Data Coding CLR is a negative edge triggered clear that allows the outputs to be cleared to either 0 V (twos complement coding) or negative full scale (offset binary coding). It is necessary to maintain CLR low for a minimum amount of time (see Figure 2) for the operation to complete. When the CLR signal is returned high, the output remains at the cleared value until a new value is programmed. If at power-on CLR is at 0 V, then all DAC outputs are updated with the clear value. A clear can also be initiated through software by writing the command 0x04XXXX to the AD5762R. Analog Output LSB 1111 0001 0000 1111 0000 LSB 1111 0001 0000 1111 0000 VOUT +2 VREFIN × (32767/32768) +2 VREFIN × (1/32768) 0V −2 VREFIN × (1/32768) −2 VREFIN × (32767/32768) VOUT +2 VREFIN × (32767/32768) +2 VREFIN × (1/32768) 0V −2 VREFIN × (1/32768) −2 VREFIN × (32767/32768) MSB 1111 1000 1000 0111 0000 MSB 0111 0000 0000 1111 1000 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 Twos Complement Data Coding 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 Rev. PrA | Page 23 of 33 AD5762R Table 7. AD5762R Input Register Format MSB DB23 R/W DB22 0 DB21 REG2 DB20 REG1 DB19 REG0 DB18 A2 DB17 A1 DB16 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 Preliminary Technical Data LSB DB8 DATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Table 8. Input Register Bit Functions Register R/W REG2, REG1, REG0 Function Indicates a read from or a write to the addressed register. Used in association with the address bits to determine if a read or write operation is to the data register, offset register, gain register, or function register. REG2 REG1 REG0 Function 0 0 0 Function Register 0 1 0 Data Register 0 1 1 Coarse Gain Register 1 0 0 Fine Gain Register 1 0 1 Offset Register These bits are used to decode the DAC channels. A2 A1 A0 Channel Address 0 0 0 DAC A 0 0 1 DAC B 1 0 0 BOTH DACs Data Bits. A2, A1, A0 D15:D0 FUNCTION REGISTER The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine the function addressed. The functions available via the function register are outlined in Table 9 and Table 10. Table 9. Function Register Options REG2 0 0 REG1 0 0 REG0 0 0 A2 0 0 A1 0 0 A0 0 1 DB15:DB6 Don’t Care DB5 LocalGroundOffset Adjust DB4 DB3 NOP, Data = Don’t Care D1 Direction D1 Value CLR, Data = Don’t Care LOAD, Data = Don’t Care DB2 D0 Direction DB1 D0 Value DB0 SDO Disable 0 0 0 0 0 0 1 1 0 0 0 1 Table 10. Explanation of Function Register Options Option NOP Local-GroundOffset Adjust D0/D1 Direction D0/D1 Value Description No operation instruction used in readback operations. Set by the user to enable local-ground-offset adjust function. Cleared by the user to disable local-ground-offset adjust function (default). Refer to Features section for further details. Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer to the Features section for further details. I/O Port Status Bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When enabled as inputs, these bits are don’t cares during a write operation. Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode. Addressing this function updates the DAC registers and consequently the analog outputs. SDO Disable CLR LOAD Rev. PrA | Page 24 of 33 Preliminary Technical Data DATA REGISTER AD5762R The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 8). The data bits are in positions DB15 to DB0 for the AD5762R as shown in Table 11. Table 11. Programming the AD5762R Data Register REG2 0 REG1 1 REG0 0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DAC Address 16-Bit DAC Data COARSE GAIN REGISTER The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 8). The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC as shown in Table 13. Table 12. Programming the AD5762R Coarse Gain Register REG2 0 REG1 1 REG0 1 A2 A1 DAC Address A0 DB15 …. DB2 Don’t Care DB1 CG1 DB0 CG0 Table 13. Output Range Selection Output Range ±10 V (default) ±10.2564 V ±10.5263 V CG1 0 0 1 CG0 0 1 0 FINE GAIN REGISTER The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 8). The AD5762R fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC channel by −32 LSBs to +31 LSBs in 1 LSB steps as shown in Table 14 and Table 15. The adjustment is made to both the positive full-scale points and the negative full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos complement. Table 14. Programming AD5762R Fine Gain Register REG2 1 REG1 0 REG0 0 A2 A1 A0 DAC Address DB15:DB6 Don’t Care DB5 FG5 DB4 FG4 DB3 FG3 DB2 FG2 DB1 FG1 DB0 FG0 Table 15. AD5762R Fine Gain Register Options Gain Adjustment +31 LSBs +30 LSBs No Adjustment (default) −31 LSBs −32 LSBs FG5 0 0 0 1 1 FG4 1 1 0 0 0 FG3 1 1 0 0 0 FG2 1 1 0 0 0 FG1 1 1 0 0 0 FG0 1 0 0 1 0 OFFSET REGISTER The offset register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 8). The AD5762R offset register is an 8-bit register and allows the user to adjust the offset of each channel by −16 LSBs to +15.875 LSBs in steps of ⅛ LSB as shown in Table 16 and Table 17. The offset register coding is twos complement. Table 16. Programming the AD5762R Offset Register REG2 1 REG1 0 REG0 1 A2 A1 A0 DAC Address DB15:DB8 Don’t Care DB7 OF7 DB6 OF6 DB5 OF5 DB4 OF4 DB3 OF3 DB2 OF2 DB1 OF1 DB0 OF0 Rev. PrA | Page 25 of 33 AD5762R Table 17. AD5762R Offset Register options Offset Adjustment +15.875 LSBs +15.75 LSBs No Adjustment (default) −15.875 LSBs −16 LSBs OF7 0 0 0 1 1 OF6 1 1 0 0 0 OF5 1 1 0 0 0 OF4 1 1 0 0 0 Preliminary Technical Data OF3 1 1 0 0 0 OF2 1 1 0 0 0 OF1 1 1 0 0 0 OF0 1 0 0 1 0 Rev. PrA | Page 26 of 33 Preliminary Technical Data OFFSET AND GAIN ADJUSTMENT WORKED EXAMPLE Using the information provided in the previous section, the following worked example demonstrates how the AD5762R functions can be used to eliminate both offset and gain errors. As the AD5762R is factory calibrated, offset and gain errors should be negligible. However, errors can be introduced by the system that the AD5762R is operating within, for example, a voltage reference value that is not equal to +5 V introduces a gain error. An output range of ±10 V and twos complement data coding is assumed. AD5762R Removing Gain Error The AD5762R can eliminate a gain error at negative full-scale output in the range of −9.77 mV to +9.46 mV with a step size of ½ of a 16-bit LSB. Calculate the step size of the gain adjustment Gain Adjust Step Size = 20 = 152.59 µV 216 × 2 Removing Offset Error The AD5762R can eliminate an offset error in the range of −4.88 mV to +4.84 mV with a step size of ⅛ of a 16-bit LSB. Calculate the step size of the offset adjustment, Offset Adjust Step Size = 20 = 38.14 µV 216 × 8 Measure the gain error by programming 0x8000 to the data register and measuring the resulting output voltage. The gain error is the difference between this value and −10 V, for this example, the gain error is −1.2 mV. How many gain adjustment steps does this value represent? Number of Steps = Measured Gain Value 1.2 mV = = 8 Steps Gain Step Size 152.59 µV Measure the offset error by programming 0x0000 to the data register and measuring the resulting output voltage, for this example the measured value is +614 µV. How many offset adjustment steps does this value represent? Number of Steps = Measured Offset Value 614 µV = = 16 Steps Offset Step Size 38.14 µV The gain error measured is negative (in terms of magnitude); therefore, a positive adjustment of eight steps is required. The gain register is 6 bits wide and the coding is twos complement, the required gain register value can be determined as follows: Convert adjustment value to binary; 001000. The value to be programmed to the gain register is simply this binary number. The offset error measured is positive, therefore, a negative adjustment of 16 steps is required. The offset register is 8 bits wide and the coding is twos complement. The required offset register value can be calculated as follows: Convert adjustment value to binary; 00010000. Convert this to a negative twos complement number by inverting all bits and adding 1; 11110000. 11110000 is the value that should be programmed to the offset register. Note: This twos complement conversion is not necessary in the case of a positive offset adjustment. The value to be programmed to the offset register is simply the binary representation of the adjustment value. Rev. PrA | Page 27 of 33 AD5762R AD5762R FEATURES ANALOG OUTPUT CONTROL In many industrial process control applications, it is vital that the output voltage be controlled during power-up and during brownout conditions. When the supply voltages are changing, the VOUT pins are clamped to 0 V via a low impedance path. To prevent the output amp being shorted to 0 V during this time, transmission gate G1 is also opened (see Figure 41). These conditions are maintained until the power supplies stabilize and a valid word is written to the DAC register. At this time, G2 opens and G1 closes. Both transmission gates are also externally controllable via the Reset In (RSTIN) control input. For instance, if RSTIN is driven from a battery supervisor chip, the RSTIN input is driven low to open G1 and close G2 on poweroff or during a brownout. Conversely, the on-chip voltage detector output (RSTOUT) is also available to the user to control other parts of the system. The basic transmission gate functionality is shown in Figure 41. RSTOUT RSTIN Preliminary Technical Data If the ISCC pin is left unconnected, the short circuit current limit defaults to 5 mA. It should be noted that limiting the short circuit current to a small value can affect the slew rate of the output when driving into a capacitive load, therefore, the value of short-circuit current programmed should take into account the size of the capacitive load being driven. DIGITAL I/O PORT The AD5762R contain a 2-bit digital I/O port (D1 and D0), these bits can be configured as inputs or outputs independently, and can be driven or have their values read back via the serial interface. The I/O port signals are referenced to DVCC and DGND. When configured as outputs, they can be used as control signals to multiplexers or can be used to control calibration circuitry elsewhere in the system. When configured as inputs, the logic signals from limit switches, for example can be applied to D0 and D1 and can be read back via the digital interface. DIE TEMPERATURE SENSOR The on-chip die temperature sensor provides a voltage output that is linearly proportional to the centigrade temperature scale. Its nominal output voltage is 1.4 V at +25°C die temperature, varying at 5 mV/°C, giving a typical output range of 1.175 V to 1.9 V over the full temperature range. Its low output impedance, and linear output simplify interfacing to temperature control circuitry and A/D converters. The temperature sensor is provided as more of a convenience rather than a precise feature; it is intended for indicating a die temperature change for recalibration purposes. VOLTAGE MONITOR AND CONTROL G1 VOUTA G2 AGNDA 06064-063 Figure 41. Analog Output Control Circuitry DIGITAL OFFSET AND GAIN CONTROL The AD5762R incorporates a digital offset adjust function with a ±16 LSB adjust range and 0.125 LSB resolution. The gain register allows the user to adjust the AD5762R’s full-scale output range. The full-scale output can be programmed to achieve full-scale ranges of ±10 V, ±10.25 V, and ±10.5 V. A fine gain trim is also available. LOCAL GROUND OFFSET ADJUST The AD5762R incorporates a local-ground-offset adjust feature which when enabled in the function register adjusts the DAC outputs for voltage differences between the individual DAC ground pins and the REFGND pin ensuring that the DAC output voltages are always with respect to the local DAC ground pin. For instance, if pin AGNDA is at +5 mV with respect to the REFGND pin and VOUTA is measured with respect to AGNDA then a −5mV error results, enabling the local-groundoffset adjust feature adjusts VOUTA by +5 mV, eliminating the error. PROGRAMMABLE SHORT-CIRCUIT PROTECTION The short-circuit current of the output amplifiers can be programmed by inserting an external resistor between the ISCC pin and PGND. The programmable range for the current is 500 µA to 10 mA, corresponding to a resistor range of 120 kΩ to 6 kΩ . The resistor value is calculated as follows: R= 60 Isc Rev. PrA | Page 28 of 33 Preliminary Technical Data APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Figure 42 shows the typical operating circuit for the AD5762R. The only external components needed for this precision 16-bit DAC are decoupling capacitors on the supply pins and reference inputs, and an optional short-circuit current setting resistor. Because the AD5762R incorporates a voltage reference and reference buffers, it eliminates the need for an external bipolar reference and associated buffers. This leads to an overall savings in both cost and board space. In Figure 42, VDD and VSS are both connected to ±15 V, but VDD and VSS can operate with supplies from ±11.4 V to ±16.5 V. In Figure 42, AGNDA and AGNDB are connected to REFGND. +15V –15V AD5762R Precision Voltage Reference Selection To achieve the optimum performance from the AD5762R over its full operating temperature range, an external voltage reference must be used. Thought should be given to the selection of a precision voltage reference. The voltage applied to the reference input is used to provide a buffered positive and negative reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the device. There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift, and output voltage noise. Initial accuracy error on the output voltage of an external reference could lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error. NC NC 24 23 10µF 100nF 10µF 100nF TEMP BIN/2sCOMP 32 31 30 29 28 27 26 25 TEMP BIN/2sCOMP REFGND REFOUT AVDD AVSS REFB REFA +5V 10µF SYNC SCLK SDIN SDO LDAC D0 D1 1 2 3 4 5 6 7 8 SYNC SCLK SDIN SDO CLR LDAC D0 D1 VOUTA 22 VOUTA AD5762R AGNDA 21 AGNDB 20 VOUTB 19 NC 18 17 Long term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. The temperature coefficient of a reference’s output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage on ambient conditions. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. Choosing a reference with as low an output noise voltage as practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET design) produce low output noise in the 0.1 Hz to 10 Hz region. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. VOUTB RSTOUT NC RSTIN DGND PGND DVCC AVDD AVSS 9 10 11 12 13 14 15 16 100nF RSTOUT RSTIN 100nF 10µF 10µF 100nF +5V 10µF +15V –15V Figure 42. Typical Operating Circuit Table 18. Some Precision References Recommended for Use with the AD5762R Part No. ADR435 ADR425 ADR02 ADR395 AD586 Initial Accuracy(mV Max) ±6 ±6 ±5 ±6 ±2.5 Long-Term Drift (ppm Typ) 30 50 50 50 15 Temp Drift (ppm/°C Max) 3 3 3 25 10 0.1 Hz to 10 Hz Noise (µV p-p Typ) 3.4 3.4 15 5 4 ISCC Rev. PrA | Page 29 of 33 AD5762R LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5762R is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5762R is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5762R should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5762R should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce cross-talk between them (not required on a multilayer board, which has a separate ground plane, however, it is helpful to separate the lines). It is essential to minimize noise on the reference inputs, because it couples through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feed through on the board. A microstrip technique is recommended, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. µCONTROLLER SERIAL CLOCK OUT Preliminary Technical Data ADuM14001 VIA ENCODE DECODE VOA TO SCLK SERIAL DATA OUT VIB ENCODE DECODE VOB TO SDIN SYNC OUT VIC ENCODE DECODE VOC TO SYNC CONTROL OUT VID ENCODE DECODE VOD TO LDAC 06064-065 1ADDITIONAL PINS OMITTED FOR CLARITY Figure 43. Isolated Interface MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5762R is via a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5762R requires a 24-bit data-word with data valid on the falling edge of SCLK. For all the interfaces, the DAC output update can be done automatically when all the data is clocked in, or it can be done under the control of LDAC. The contents of the DAC register can be read using the readback function. AD5762R to MC68HC11 Interface Figure 44 shows an example of a serial interface between the AD5762R and the MC68HC11 microcontroller. The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL = 0), and the clock phase bit (CPHA = 1). The SPI is configured by writing to the SPI control register (SPCR) (see the 68HC11User Manual). SCK of the MC68HC11 drives the SCLK of the AD5762R, the MOSI output drives the serial data line (DIN) of the AD5762R, and the MISO input is driven from SDO. The SYNC is driven from one of the port lines, in this case PC7. GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur. Isocouplers provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5762R makes it ideal for isolated interfaces, because the number of interface lines is kept to a minimum. Figure 43 shows a 4-channel isolated interface to the AD5762R using an ADuM1400. For more information, go to www.analog.com. Rev. PrA | Page 30 of 33 Preliminary Technical Data When data is being transmitted to the AD5762R, the SYNC line (PC7) is taken low and data is transmitted MSB first. Data appearing on the MOSI output is valid on the falling edge of SCK. Eight falling clock edges occur in the transmit cycle, so, in order to load the required 24-bit word, PC7 is not brought high until the third 8-bit word has been transferred to the DACs input shift register. MC68HC111 MISO MOSI SCK PC7 AD5762R The 8XC51 transmits data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Because the DAC expects a 24-bit word, SYNC (P3.3) must be left low after the first eight bits are transferred. After the third byte has been transferred, the P3.3 line is taken high. The DAC can be updated using LDAC via P3.4 of the 8XC51. AD5762R to ADSP2101/ADSP2103 Interface An interface between the AD5762R and the ADSP2101/ ADSP2103 is shown in Figure 46. The ADSP2101/ ADSP2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP2101/ADSP2103 are programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 24bit word length. Transmission is initiated by writing a word to the TX register after the SPORT has been enabled. As the data is clocked out of the DSP on the rising edge of SCLK, no glue logic is required to interface the DSP to the DAC. In the interface shown, the DAC output is updated using the LDAC pin via the DSP. Alternatively, the LDAC input could be tied permanently low, and then the update takes place automatically when TFS is taken high. ADSP2101/ ADSP21031 DR DT SCLK TFS RFS AD5762R1 SDO SDIN SCLK SYNC 1ADDITIONAL PINS OMITTED FOR CLARITY Figure 44. AD5762R to MC68HC11 Interface LDAC is controlled by the PC6 port output. The DAC can be updated after each 3-byte transfer by bringing LDAC low. This example does not show other serial lines for the DAC. For example, if CLR were used, it could be controlled by port output PC5. 06064-066 AD5762R1 SDO SDIN SCLK SYNC LDAC 06064-068 AD5762R to 8XC51 Interface The AD5762R requires a clock synchronized to the serial data. For this reason, the 8XC51 must be operated in Mode 0. In this mode, serial data enters and exits through RXD, and a shift clock is output on TXD. P3.3 and P3.4 are bit programmable pins on the serial port and are used to drive SYNC and LDAC, respectively. The 8CX51 provides the LSB of its SBUF register as the first bit in the data stream. The user must ensure that the data in the SBUF register is arranged correctly, because the DAC expects MSB first. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RXD is clocked out of the microcontroller on the rising edge of TXD and is valid on the falling edge. As a result, no glue logic is required between this DAC and the microcontroller interface. 8XC511 RxD TxD P3.3 P3.4 FO 1ADDITIONAL PINS OMITTED FOR CLARITY Figure 46. AD5762R to ADSP2101/ADSP2103 Interface AD5762R to PIC16C6x/7x Interface The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit set to 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5762R. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are needed. Figure 47 shows the connection diagram. AD5762R1 SDIN SCLK SYNC LDAC 1ADDITIONAL PINS OMITTED FOR CLARITY Figure 45. AD5762R to 8XC51 Interface 06064-067 Rev. PrA | Page 31 of 33 AD5762R PIC16C6x/7x1 SDI/RC4 SDO/RC5 SCLK/RC3 RA1 Preliminary Technical Data AD5762R1 SDO SDIN SCLK SYNC EVALUATION BOARD The AD5762R performance can be evaluated via the AD5764R evaluation board. The AD5764R comes with a full evaluation board to aid designers in evaluating the high performance of the part with a minimum of effort. All that is required with the evaluation board is a power supply and a PC. The AD5764R evaluation kit includes a populated, tested AD5764R printed circuit board. The evaluation board interfaces to the USB interface of the PC. Software is available with the evaluation board, which allows the user to easily program the AD5764R. The software runs on any PC that has Microsoft® Windows® 2000/XP installed. An application note is available that gives full details on operating the evaluation board. 1ADDITIONAL PINS OMITTED FOR CLARITY Figure 47. AD5762R to PIC16C6x/7x Interface 06064-069 Rev. PrA | Page 32 of 33 Preliminary Technical Data OUTLINE DIMENSIONS 0.75 0.60 0.45 1.20 MAX 32 1 PIN 1 AD5762R 9.00 BSC SQ 25 24 TOP VIEW 1.05 1.00 0.95 0° MIN (PINS DOWN) 7.00 BSC SQ 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 8 9 16 17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026ABA VIEW A 0.80 BSC LEAD PITCH 0.45 0.37 0.30 Figure 48. 32-Lead Thin Plastic Dual Flat Package [TQFP] (SU-32-2) Dimensions shown in millimeters ORDERING GUIDE1 Model AD5762RCSUZ AD5762RCSUZ-REEL7 Function Dual 16-bit DAC Dual 16-bit DAC INL ±1 LSB max ±1 LSB max Temperature −40°C to +85°C −40°C to +85°C Internal Reference +5V +5V Package Description 32-lead TQFP 32-lead TQFP Package Option SU-32-2 SU-32-2 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07248-0-12/07(PrA) Rev. PrA | Page 33 of 33