AD598AD

a FEATURES Single Chip Solution, Contains Internal Oscillator and Voltage Reference No Adjustments Required Insensitive to Transducer Null Voltage Insensitive to Primary to Secondary Phase Shifts DC Output Proportional to Position 20 Hz to 20 kHz Frequency Range Single or Dual Supply Operation Unipolar or Bipolar Output Will Operate a Remote LVDT at Up to 300 Feet Position Output Can Drive Up to 1000 Feet of Cable Will Also Interface to an RVDT Outstanding Performance Linearity: 0.05% of FS max Output Voltage: 611 V min Gain Drift: 50 ppm/8C of FS max Offset Drift: 50 ppm/8C of FS max PRODUCT DESCRIPTION The AD598 is a complete, monolithic Linear Variable Differential Transformer (LVDT) signal conditioning subsystem. It is used in conjunction with LVDTs to convert transducer mechanical position to a unipolar or bipolar dc voltage with a high degree of accuracy and repeatability. All circuit functions are included on the chip. With the addition of a few external passive components to set frequency and gain, the AD598 converts the raw LVDT secondary output to a scaled dc signal. The device can also be used with RVDT transducers. LVDT Signal Conditioner AD598 FUNCTIONAL BLOCK DIAGRAM EXCITATION (CARRIER) 3 2 VA 11 OSC AMP AD598 17 LVDT 10 A–B A+B FILTER AMP 16 VOUT VB PRODUCT HIGHLIGHTS 1. The AD598 offers a monolithic solution to LVDT and RVDT signal conditioning problems; few extra passive components are required to complete the conversion from mechanical position to dc voltage and no adjustments are required. 2. The AD598 can be used with many different types of LVDTs because the circuit accommodates a wide range of input and output voltages and frequencies; the AD598 can drive an LVDT primary with up to 24 V rms and accept secondary input levels as low as 100 mV rms. The AD598 contains a low distortion sine wave oscillator to drive the LVDT primary. The LVDT secondary output consists of two sine waves that drive the AD598 directly. The AD598 operates upon the two signals, dividing their difference by their sum, producing a scaled unipolar or bipolar dc output. 3. The 20 Hz to 20 kHz LVDT excitation frequency is determined by a single external capacitor. The AD598 input signal need not be synchronous with the LVDT primary drive. This means that an external primary excitation, such as the 400 Hz power mains in aircraft, can be used. The AD598 uses a unique ratiometric architecture (patent pending) to eliminate several of the disadvantages associated with traditional approaches to LVDT interfacing. The benefits of this new circuit are: no adjustments are necessary, transformer null voltage and primary to secondary phase shift does not affect system accuracy, temperature stability is improved, and transducer interchangeability is improved. 4. The AD598 uses a ratiometric decoding scheme such that primary to secondary phase shifts and transducer null voltage have absolutely no effect on overall circuit performance. The AD598 is available in two performance grades: Grade Temperature Range Package AD598JR 0°C to +70°C AD598AD –40°C to +85°C 20-Pin Small Outline (SOIC) 20-Pin Ceramic DIP It is also available processed to MIL-STD-883B, for the military range of –55°C to +125°C. 5. Multiple LVDTs can be driven by a single AD598, either in series or parallel as long as power dissipation limits are not exceeded. The excitation output is thermally protected. 6. The AD598 may be used in telemetry applications or in hostile environments where the interface electronics may be remote from the LVDT. The AD598 can drive an LVDT at the end of 300 feet of cable, since the circuit is not affected by phase shifts or absolute signal magnitudes. The position output can drive as much as 1000 feet of cable. 7. The AD598 may be used as a loop integrator in the design of simple electromechanical servo loops. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD598–SPECIFICATIONS (typical @ +258C and 615 V dc, C1 = 0.015 mF, R2 = 80 kV, RL = 2 kV, unless otherwise noted. See Figure 7.) Parameter Min AD598J Typ TRANSFER FUNCTION1 VOUT = OVERALL ERROR2 TMIN to TMAX 0.6 SIGNAL OUTPUT CHARACTERISTICS Output Voltage Range (TMIN to TMAX) Output Current (TMIN to TMAX) Short Circuit Current Nonlinearity3 (TMIN to TMAX) Gain Error4 Gain Drift Offset5 Offset Drift Excitation Voltage Rejection6 Power Supply Rejection (± 12 V to ± 18 V) PSRR Gain (TMIN to TMAX) PSRR Offset (TMIN to TMAX) Common-Mode Rejection (± 3 V) CMRR Gain (TMIN to TMAX) CMRR Offset (TMIN to TMAX) Output Ripple7 EXCITATION OUTPUT CHARACTERISTICS (@ 2.5 kHz) Excitation Voltage Range Excitation Voltage (R1 = Open)8 (R1 = 12.7 kΩ)8 (R1 = 487 Ω)8 Excitation Voltage TC9 Output Current TMIN to TMAX Short Circuit Current DC Offset Voltage (Differential, R1 = 12.7 kΩ) TMIN to TMAX Frequency Frequency TC, (R1 = 12.7 kΩ) Total Harmonic Distortion SIGNAL INPUT CHARACTERISTICS Signal Voltage Input Impedance Input Bias Current (AIN and BIN) Signal Reference Bias Current Excitation Frequency POWER SUPPLY REQUIREMENTS Operating Range Dual Supply Operation (± 10 V Output) Single Supply Operation 0 to +10 V Output 0 to –10 V Output Current (No Load at Signal and Excitation Outputs) TMIN to TMAX TEMPERATURE RANGE JR (SOIC) AD (DIP) PACKAGE OPTION SOIC (R-20) Side Brazed DIP (D-20) Max Min VA –VB VA +VB × 500 µA × R2 2.35 611 8 AD598A Typ Max 0.6 V 1.65 611 6 20 75 0.4 20 0.3 7 100 20 75 0.4 20 0.3 7 100 6500 61 6100 61 6200 Unit 6500 61 650 61 650 % of FS V mA mA ppm of FS % of FS ppm/°C of FS % of FS ppm/°C of FS ppm/dB 300 100 100 15 400 200 100 15 ppm/V ppm/V 100 100 25 6 4 200 200 25 6 4 ppm/V ppm/V mV rms 2.1 24 2.1 24 V rms 1.2 2.6 14 2.1 4.1 20 1.2 2.6 14 2.1 4.1 20 V rms V rms V rms ppm/°C mA rms mA rms mA 6100 20k mV Hz ppm/°C dB 3.5 V rms kΩ µA µA kHz 600 600 30 12 30 12 60 30 20 60 6100 20k 30 20 200 –50 0.1 200 –50 3.5 200 1 2 0 13 ± 13 5 10 20 36 17.5 17.5 0.1 200 1 2 0 13 ± 13 5 10 20 36 17.5 17.5 12 0 12 15 16 15 18 V V mA mA +85 °C °C +70 –40 V V AD598JR AD598AD –2– REV. A AD598 NOTES 1 VA and VB represent the Mean Average Deviation (MAD) of the detected sine waves. Note that for this Transfer Function to linearly represent positive displacement, the sum of V A and VB of the LVDT must remain constant with stroke length. See “Theory of Operation.” Also see Figures 7 and 12 for R2. 2 From TMIN, to TMAX, the overall error due to the AD598 alone is determined by combining gain error, gain drift and offset drift. For example the worst case overall error for the AD598AD from TMIN to TMAX is calculated as follows: overall error = gain error at +25°C (± 1% full scale) + gain drift from –40°C to +25°C (50 ppm/°C of FS × +65°C) + offset drift from –40°C to +25°C (50 ppm/°C of FS × +65°C) = ± 1.65% of full scale. Note that 1000 ppm of full scale equals 0.1% of full scale. Full scale is defined as the voltage difference between the maximum positive and maximum negative output. 3 Nonlinearity of the AD598 only, in units of ppm of full scale. Nonlinearity is defined as the maximum measured deviation of the AD598 output voltage from a straight line. The straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage. 4 See Transfer Function. 5 This offset refers to the (V A–VB)/(VA+VB) input spanning a full-scale range of ± 1. [For (VA–VB)/(VA+VB) to equal +1, V B must equal zero volts; and correspondingly for (VA–VB)/(VA+VB) to equal –1, VA must equal zero volts. Note that offset errors do not allow accurate use of zero magnitude inputs, practical inputs are limited to 100 mV rms.] The ± 1 span is a convenient reference point to define offset referred to input. For example, with this input span a value of R2 = 20 k Ω would give VOUT span a value of ± 10 volts. Caution, most LVDTs will typically exercise less of the ((V A–VB))/((VA+VB)) input span and thus require a larger value of R2 to produce the ± 10 V output span. In this case the offset is correspondingly magnified when referred to the output voltage. For example, a Schaevitz E100 LVDT requires 80.2 kΩ for R2 to produce a ± 10.69 V output and (V A–VB)/(VA+VB) equals 0.27. This ratio may be determined from the graph shown in Figure 18, (VA–VB)/(VA+VB) = (1.71 V rms – 0.99 V rms)/(1.71 V rms + 0.99 V rms). The maximum offset value referred to the ± 10.69 V output may be determined by multiplying the maximum value shown in the data sheet (± 1% of FS by 1/0.27 which equals ± 3.7% maximum. Similarly, to determine the maximum values of offset drift, offset CMRR and offset PSRR when referred to the ± 10.69 V output, these data sheet values should also be multiplied by (1/0.27). For this example for the AD598AD the maximum values of offset drift, PSRR offset and CMRR offset would be: 185 ppm/ °C of FS; 741 ppm/V and 741 ppm/V respectively when referred to the ± 10.69 V output. 6 For example, if the excitation to the primary changes by 1 dB, the gain of the system will change by typically 100 ppm. 7 Output ripple is a function of the AD598 bandwidth determined by C2, C3 and C4. See Figures 16 and 17. 8 R1 is shown in Figures 7 and 12. 9 Excitation voltage drift is not an important specification because of the ratiometric operation of the AD598. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tested are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. ORDERING GUIDE THERMAL CHARACTERISTICS SOIC Package Side Brazed Package θJC θJA 22°C/W 25°C/W 80°C/W 85°C/W Model Temperature Range Package Description Package Option AD598JR AD598AD 0°C to +70°C –40°C to +85C SOIC Ceramic DIP R-20 D-20 ABSOLUTE MAXIMUM RATINGS Total Supply Voltage +VS to –VS . . . . . . . . . . . . . . . . . +36 V Storage Temperature Range R Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C D Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range AD598JR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C AD598AD . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C Power Dissipation Up to +65°C . . . . . . . . . . . . . . . . . . . 1.2 W Derates Above +65°C . . . . . . . . . . . . . . . . . . . . . . . 12 mW/°C –VS EXC 1 2 19 OFFSET 1 EXC 2 3 18 OFFSET 2 17 SIGNAL REFERENCE LEVEL 1 4 LEVEL 2 5 FREQ 1 6 FREQ 2 7 –3– AD598 TOP VIEW (Not to Scale) 16 SIGNAL OUTPUT 15 FEEDBACK 14 OUTPUT FILTER B1 FILTER 8 13 A1 FILTER B2 FILTER 9 12 A2 FILTER VB 10 REV. A 20 +VS 1 11 VA AD598–Typical Characteristics (at +258C and V = 615 V, unless otherwise noted) S 120 40 OFFSET PSRR 12–15V 80 OFFSET PSRR 15–18V TYPICAL GAIN DRIFT – ppm/°C GAIN AND OFFSET PSRR – ppm/Volt 0 –40 GAIN PSRR 12–15V –80 –120 GAIN PSRR 15–18V –160 –200 40 20 0 –20 –40 –240 –60 –60 –20 0 20 60 100 –80 –60 140 –20 0 20 60 100 140 TEMPERATURE – °C TEMPERATURE – °C Figure 1. Gain and Offset PSRR vs. Temperature Figure 2. Typical Gain Drift vs. Temperature 5 20 OFFSET CMRR ± 3V TYPICAL OFFSET DRIFT – ppm/°C GAIN AND OFFSET CMRR – ppm/Volt 0 –5 –10 –15 –20 GAIN CMRR ± 3V –25 10 0 –10 –30 –35 –60 –20 0 20 60 100 –20 –60 140 TEMPERATURE – °C 2 10 AMP AD598 A–B A+B FILTER 140 The oscillator comprises a multivibrator which produces a triwave output. The triwave drives a sine shaper, which produces a low distortion sine wave whose frequency is determined by a single capacitor. Output frequency can range from 20 Hz to 20 kHz and amplitude from 2 V rms to 24 V rms. Total harmonic distortion is typically –50 dB. VA LVDT 100 The AD598 energizes the LVDT primary, senses the LVDT secondary output voltages and produces a dc output voltage proportional to core position. The AD598 consists of a sine wave oscillator and power amplifier to drive the primary, a decoder which determines the ratio of the difference between the LVDT secondary voltages divided by their sum, a filter and an output amplifier. EXCITATION (CARRIER) 17 60 an external sine wave reference source, two secondary windings connected in series, and the moveable core to couple flux between the primary and secondary windings. A block diagram of the AD598 along with an LVDT (Linear Variable Differential Transformer) connected to its input is shown in Figure 5. The LVDT is an electromechanical transducer whose input is the mechanical displacement of a core and whose output is a pair of ac voltages proportional to core position. The transducer consists of a primary winding energized by OSC 20 Figure 4. Typical Offset Drift vs. Temperature THEORY OF OPERATION 11 0 TEMPERATURE – °C Figure 3. Gain and Offset CMRR vs. Temperature 3 –20 AMP 16 VOUT The output from the LVDT secondaries consists of a pair of sine waves whose amplitude difference, (VA–VB), is proportional to core position. Previous LVDT conditioners synchronously detect this amplitude difference and convert its absolute value to VB Figure 5. AD598 Functional Block Diagram –4– REV. A AD598 a voltage proportional to position. This technique uses the primary excitation voltage as a phase reference to determine the polarity of the output voltage. There are a number of problems associated with this technique such as (1) producing a constant amplitude, constant frequency excitation signal, (2) compensating for LVDT primary to secondary phase shifts, and (3) compensating for these shifts as a function of temperature and frequency. As shown in Figure 6, the input to the integrator is [(A+B)d]B. Since the integrator input is forced to 0, the duty cycle d = B/(A+B). The output comparator which produces d = B/(A+B) also controls an output amplifier driven by a reference current. Duty cycle signals d and (1–d) perform separate modulations on the reference current as shown in Figure 6, which are summed. The summed current, which is the output current, is IREF × (1–2d). The AD598 eliminates all of these problems. The AD598 does not require a constant amplitude because it works on the ratio of the difference and sum of the LVDT output signals. A constant frequency signal is not necessary because the inputs are rectified and only the sine wave carrier magnitude is processed. There is no sensitivity to phase shift between the primary excitation and the LVDT outputs because synchronous detection is not employed. The ratiometric principle upon which the AD598 operates requires that the sum of the LVDT secondary voltages remains constant with LVDT stroke length. Although LVDT manufacturers generally do not specify the relationship between VA+VB and stroke length, it is recognized that some LVDTs do not meet this requirement. In these cases a nonlinearity will result. However, the majority of available LVDTs do in fact meet these requirements. Since d = B/(A+B), by substitution the output current equals IREF × (A–B)/(A+B). This output current is then filtered and converted to a voltage since it is forced to flow through the scaling resistor R2 such that: V OUT = I REF × ( A – B ) / (A + B ) × R2 CONNECTING THE AD598 The AD598 can easily be connected for dual or single supply operation as shown in Figures 7 and 12. The following general design procedures demonstrate how external component values are selected and can be used for any LVDT which meets AD598 input/output criteria. Parameters which are set with external passive components include: excitation frequency and amplitude, AD598 system bandwidth, and the scale factor (V/inch). Additionally, there are optional features, offset null adjustment, filtering, and signal integration which can be used by adding external components. The AD598 utilizes a special decoder circuit. Referring to the block diagram and Figure 6 below, an implicit analog computing loop is employed. After rectification, the A and B signals are multiplied by complementary duty cycle signals, d and (I–d) respectively. The difference of these processed signals is integrated and sampled by a comparator. It is the output of this comparator that defines the original duty cycle, d, which is fed back to the multipliers. V TO I INPUT A FILT BINARY SIGNAL d - DUTY CYCLE d COMP 0