AD606JR-REEL

a 50 MHz, 80 dB Demodulating Logarithmic Amplifier with Limiter Output AD606 a loadable output voltage of +0.1 V dc to +4 V dc. The logarithmic scaling is such that the output is +0.5 V for a sinusoidal input of –75 dBm and +3.5 V at an input of +5 dBm; over this range the logarithmic linearity is typically within ± 0.4 dB. All scaling parameters are proportional to the supply voltage. The AD606 can operate above and below these limits, with reduced linearity, to provide as much as 90 dB of conversion range. A second low-pass filter automatically nulls the input offset of the first stage down to the submicrovolt level. Adding external capacitors to both filters allows operation at input frequencies as low as a few hertz. The AD606’s limiter output provides a hard-limited signal output as a differential current of ± 1.2 mA from open-collector outputs. In a typical application, both of these outputs are loaded by 200 Ω resistors to provide a voltage gain of more than 90 dB from the input. Transition times are 1.5 ns, and the phase is stable to within ± 3° at 10.7 MHz for signals from –75 dBm to +5 dBm. The logarithmic amplifier operates from a single +5 V supply and typically consumes 65 mW. It is enabled by a CMOS logic level voltage input, with a response time of CF) and also on the value of RZ. The inclusion of this control loop has no effect on the high frequency response of the AD606. Nor does it have any effect on the low frequency response when the input amplitude is substantially above the input offset voltage. –6– RZ LADJ OPCM AD606JN COMM VLOG LMLO ISUM ILOG INLO BFIN Figure 5. Use of CZ and RZ for Offset Control Loop Compensation LMHI REV. B AD606 For operation above 10 MHz, it is not necessary to add the external capacitors CF1, CF2, and CZ, although an improvement in low frequency noise can be achieved by so doing (see APPLICATIONS). Note that the offset control loop does not materially affect the low-frequency cutoff at high input levels, when the offset voltage is swamped by the signal. Power-Up Interface APPLICATIONS The AD606 features a power-saving mode, controlled by the logic level at Pin 14 (PRUP). When powered down, the quiescent current is typically 65 µA, or about 325 µW. A CMOS logical HIGH applied to PRUP activates both internal references, and the system becomes fully functional within about 3.5 µs. When this input is a CMOS logical LOW, the system shuts down to the quiescent level within about 5 µs. The power-up time is somewhat dependent on the signal level and can be degraded by mismatch of the input coupling capacitors. The explanation is as follows. When the AD606 makes the transition from powered-down to fully active, the dc bias voltage at the input nodes INHI and INLO (about +2.5 V) inevitably changes slightly, as base current in the input transistors flows in the bias resistors. In fact, first-order correction for this is included in the specially designed offset buffer amplifier, but even a few millivolts of change at these inputs represents a significant equivalent “dBm” level. Now, if the coupling capacitors do not match exactly, some fractional part of this residual voltage step becomes coupled into the amplifier. For example, if there is a 10% capacitor mismatch, and INHI and INLO jump 20 mV at power-up, there is a 2 mV pulse input to the system, which may cause the offset control loop to ring. Note that 2 mV is roughly 40 times greater than the amplitude of a sinusoidal input at –75 dBm. As long as the ringing persists, the AD606 will be “blind” to the actual input, and VLOG will show major disturbances. The solution to this problem is first, to ensure that the loop filter does not ring, and second, to use well-matched capacitors at the signal input. Use the component values suggested above to minimize ringing. Note that the AD606 has more than 70 MHz of input bandwidth and 90 dB of gain! Careful shielding is needed to realize its full dynamic range, since nearly all application sites will be pervaded by many kinds of interference, radio and TV stations, etc., all of which the AD606 faithfully hears. In bench evaluation, we recommend placing all of the components in a shielded box and using feedthrough decoupling networks for the supply voltage. In many applications, the AD606’s low power drain allows the use of a 6 V battery inside the box. Basic RSSI Application Figure 6 shows the basic RSSI (Receiver Signal Strength Indicator) application circuit, including the calibration adjustments, either or both of which may be omitted in noncritical applications. This circuit may be used “as is” in such measurement applications as the log/IF strip in a spectrum or network analyzer or, with the addition of an FM or QPSK demodulator fed by the limiter outputs, as an IF strip in such communications applications as a GSM digital mobile radio or FM receiver. The slope adjustment works in this way: the buffer amplifier (which forms part of a Sallen-Key two-pole filter, see Figure 2) has a dc gain of plus two, and the resistance from BFIN (buffer in) to OPCM (output common) is nominally 9.375 kΩ. This resistance is driven from the logarithmic detector sections with a current scaled 2 µA/dB, generating 18.75 mV/dB at BFIN, hence 37.5 mV/dB at VLOG Now, a resistor (R4 in Figure 6) connected directly between BFIN and VLOG would form a controlled positive-feedback network with the internal 9.375 kΩ resistor which would raise the gain, and thus increase the slope voltage, while the same external resistor connected between BFIN and ground would form a shunt across the internal resistor and reduce the slope voltage. By connecting R4 to a potentiometer R2 across the output, the slope may be adjusted either way; the value for R4 shown in Figure 6 provides approximately ± 10% range, with essentially no effect on the slope at the midposition. The intercept may be adjusted by adding a small current into BFIN via R1 and R3. The AD606 is designed to have the nominal intercept value of –88 dBm when R1 is centered using this network, which provides a range of ± 5 dB. +5V 0.1 F 100pF RF INPUT COMM PRUP VPOS INHI NC FIL1 NC LADJ LMHI FIL2 51.1 COMM ISUM INLO AD606 OPCM VLOG LMLO ILOG BFIN R5 200 100pF +5V R1 200k INTERCEPT ADJUSTMENT 5dB R3 412k R4 174k R2 50k SLOPE ADJUSTMENT 10% LIMITER OUTPUT LOGARITHMIC OUTPUT NC = NO CONNECT Figure 6. Basic Application Circuit Showing Optional Slope and Intercept Adjustments REV. B –7– AD606 Adjustment Procedure The slope and intercept adjustments interact; this can be minimized by reducing the resistance of R1 and R2, chosen here to minimize power drain. Calibration can be achieved in several ways: The simplest is to apply an RF input at the desired operating frequency which is amplitude modulated at a relatively low frequency (say 1 kHz to 10 kHz) to a known modulation index. Thus, one might choose a ratio of 2 between the maximum and minimum levels of the RF amplitude, corresponding to a 6 dB (strictly, 6.02 dB) change in input level. The average RF level should be set to about –35 dBm (the midpoint of the AD606’s range). R2 is then adjusted so that the 6 dB input change results in the desired output voltage change, for example, 226 mV at 37.5 mV/dB. A better choice would be a 4:1 ratio (12.04 dB), to spread the residual error out over a larger segment of the whole transfer function. If a pulsed RF generator is available, the decibel increment might be enlarged to 20 dB or more. Using just a fixedlevel RF generator, the procedure is more time consuming, but is carried out in just the same way: manually change the level by a known number of decibels and adjust R2 until VLOG varies by the corresponding voltage. Having adjusted the slope, the intercept may now be simply adjusted using a known input level. A value of –35 dBm (397.6 mV rms, or 400 mV to within 0.05 dB) is recommended, and if the standard scaling is used (PX = –88.33 dBm, VY = 37.5 mV/dB), then VLOG should be set to +2 V at this input level. A Low Cost Audio Through RF Power Meter In contrast to the limited dynamic range of the diode and thermistor-styled sensors used in power meters, the AD606 can measure signals from below –80 dBm to over +10 dBm. An optional 50 Ω termination is included in the figure; this could form the lower arm of an external attenuator to accommodate larger signal levels. By the simple expedient of using a 13 dB attenuator, the LCD reading now becomes dBV (decibels above 1 V rms). This requires a series resistor of 174 Ω, presenting an input resistance of 224 Ω. Alternatively, the input resistance can be raised to 600 Ω using 464 Ω and 133 Ω. It is important to note that the AD606 inputs must be ac coupled. To extend the low frequency range, use larger coupling capacitors and an external loop filter, as outlined earlier. The nominal 0.5 V to 3.5 V output of the AD606 (for a –75 dBm to +5 dBm input) must be scaled and level shifted to fit within the +1 V to +4.5 V common-mode range of the ICL7136 for the +5 V supply used. This is achieved by the passive resistor network of R1, R2, and R3 in conjunction with the bias networks of R4 through R7, which provide the ICL7136 with its reference voltage, and R9 through R11, which set the intercept. The ICL7136 measures the differential voltage between INHI and INLO, which ranges from –75 mV to +5 mV for a –75 dBm to +5 dBm input. To calibrate the power meter, first adjust R6 for 100 mV between REF HI and REF LO. This sets the initial slope. Then adjust R10 to set INLO 80 mV higher than INHI. This sets the initial intercept. The slope and intercept may now be adjusted using a calibrated signal generator as outlined in the previous section. To extend the low frequency limit of the system to audio frequencies, simply change C1, C2, and C3 to 4.7 µF. The limiter output of the AD606 may be used to drive the highimpedance input of a frequency counter. +5V Figure 7 shows a simple power meter that uses the AD606 and an ICL7136 3-1/2 digit DMM IC driving an LCD readout. The circuit operates from a single +5 V supply and provides direct readout in dBm, with a resolution of 0.1 dBm. 0.1 F dBV INPUT +5V 174 C1* 100pF 0.1 F +5V C3* 150pF OPTIONAL DRIVE TO FREQUENCY COUNTER R4 4.99k 36 DISPLAY REF HI dBm INPUT R5 4.32k –75.0 40 LADJ COMM PRUP VPOS LMHI INHI FIL1 FIL2 200 +5V +5V R8 100k R9 5k R10 100k R6 500 R7 162 100mV 35 REF LO 180k 39 32 51.1 AD606JN COMM OPCM VLOG LMLO ISUM ILOG INLO BFIN COMM 38 50pF 2.513V NOM C2* 100pF INLO 34 NC NC NC 0.1 F 80mV FOR 0dBm SIGNAL INPUT 33 * FOR AUDIO MEASUREMENTS CHANGE C1, C2, AND C3 TO 4.7 F; POSITIVE POLARITY CONNECT TO PINS 1, 16 +5V R1 1M R2 54.9k C4 1F ICL7136CPL 0.1 F 1.8M 31 NC = NO CONNECT R3 54.9k 2.433V NOM INHI V– 0.047 F Figure 7. A Low Cost RF Power Meter –8– REV. B AD606 0.1 F 20dB ATTENUATOR AC INPUT R4 453 C1 4.7 F + LOW-PASS FILTER R1 100 LADJ PRUP COMM VPOS LMHI FIL1 FIL2 INHI +5V C4 4.7 F R5 51.1 C3 680pF COMM ISUM INLO AD606JN OPCM VLOG LMLO ILOG BFIN C2 4.7 F + R2 100 NC NC NC R3 1k NC = NO CONNECT TO DVM DIECAST BOX Figure 8. Circuit for Low Frequency Measurements Low Frequency Applications With reasonably sized input coupling capacitors and an optional input low-pass filter, the AD606 can operate to frequencies as low as 200 Hz with good log conformance. Figure 8 shows the schematic, with the low-pass filter included in the dashed box. This circuit should be built inside a die cast box and the signal brought in through a coaxial connector. The circuit must also have a low-pass filter to reject the attenuated RF signals that would otherwise be rectified along with the desired signal and be added to the log output. The shielded and filtered circuit has a 90 dB dynamic range, as shown in Figure 9. In this circuit, R4 and R5 form a 20 dB attenuator that extends the input range to 10 V rms. R3 isolates loads from VLOG. Capacitors C1 and C2 (4.7 µF each), R1, R2, and the AD606’s input resistance of 2.5 kΩ form a 100 Hz high-pass filter that is before the AD606; the corner frequency of this filter must be well below the lowest frequency of interest. In addition, the offset-correction loop introduces another pole at low signal levels that is transformed into another high-pass filter because it is in a feedback path. This indicates that there has to be a gradual transition from a 40 dB roll off at low signal levels to a 20 dB roll off at high signal levels, at which point the feedback low pass filter is effectively disabled since the incoming signal swamps the feedback signal. This low-pass filter introduces some attenuation due to R1 and R2 in conjunction with the 2.5 kΩ input resistance of the AD606. To minimize this effect, the value of R1 and R2 should be kept as small as possible–100 Ω is a good value since it balances the need to reduce the attenuation as mentioned above with the requirement for R1 and R2 to be much larger then the impedance of C1 and C2 at the low-pass corner frequency, in our case about 1 MHz. 90dB 4 3.5V 3 VLOG – Volts DC 2 1kHz – 10MHz 100Hz 1 0 –80 –60 –40 –20 0 20 40 INPUT SIGNAL – dBm Figure 9. Performance of Low Frequency Circuit at 100 Hz and 1 kHz to 10 MHz (Note Attenuation) REV. B –9– 8/30/99 9 AM AD606–Typical Performance Characteristics 0.5 –0.5 –1.5 –2.5 10.7MHz –3.5 –4.5 –5.5 –6.5 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL – dBm 70MHz 45MHz 5 NORMALIZED PHASE SHIFT – Degrees 10.7MHz 14 NORMALIZED LIMITER OUTPUT – dB 0 45MHz –5 70MHz POWER SUPPLY CURRENT – mA 0 20 12 10 8 6 4 2 0 –10 –15 –20 0 20 –25 –80 –60 –40 –20 INPUT LEVEL – dBm 0 0.5 1 1.5 2 2.5 3 3.5 4 PRUP VOLTAGE – Volts 4.5 5 Figure 10. Normalized Limiter Amplitude Response vs. Input Level at 10.7 MHz, 45 MHz and 70 MHz Figure 11. Normalized Limiter Phase Response vs. Input Level at 10.7 MHz, 45 MHz, and 70 MHz Figure 12. Supply Current vs. PRUP Voltage at +25 °C 4.5 TA = +25 C 4 4 3 5 4 LOGARITHMIC ERROR – dB LOGARITHMIC ERROR – dB 3.5 VLOG – Volts DC VS = 5.5V 3 2 1 0 –1 –2 –3 –4 TA = +70 C TA = –25 C TA = +25 C 2 1 0 –1 –2 –3 –4 –80 TA = +70 C TA = –25 C TA = +25 C 3 2.5 2 1.5 1 0.5 0 –80 –60 –40 –20 0 10 VS = 4.5V VS = 5V INPUT POWER – dBm –40 0 –60 –20 INPUT AMPLITUDE – dBm 10 –5 –80 –60 –40 –20 0 INPUT AMPLITUDE – dBm 10 Figure 13. VLOG Plotted vs. Input Level at 10.7 MHz as a Function of Power Supply Voltage Figure 14. Logarithmic Conformance as a Function of Input Level at 10.7 MHz at –25 °C, +25 °C, and +70 °C Figure 15. Logarithmic Conformance as a Function of Input Level at 45 MHz at –25 °C, +25 °C, and +70 °C Figure 16. Limiter Response at Onset of 10.7 MHz Modulated Pulse at –75 dBm Using 200 pF Input Coupling Capacitors Figure 17. VLOG Response to a 10.7 MHz CW Signal Modulated by a 25 µ s Wide Pulse with a 25 kHz Repetition Rate Using 200 pF Input Coupling Capacitors. The Input Signal Goes from +5 dBm to –75 dBm in 20 dB Steps. Figure 18. Limiter Response at Onset of 70 MHz Modulated Pulse at –55 dBm Using 200 pF Input Coupling Capacitors –10– REV. B AD606 Figure 19. VLOG Output for a Pulsed 10.7 MHz Input; Top Trace: –35 dBm to +5 dBm; Middle Trace: –15 dBm to –55 dBm; Bottom Trace: –35 dBm to – 75 dBm Figure 20. Example of Test Signal Used for Figure 19 Figure 21. VLOG Output for 10.7 MHz CW Input with PRUP Toggled ON and OFF; Top Trace: +5 dBm Input; Middle Trace: –35 dBm Input; Bottom Trace: –75 dBm; PRUP Input from HP8112A: 0 to 4 V, 10 µ s Pulsewidth with 10 kHz Repetition Rate +5V 0.1 F –10dB TO +30dB (10.7MHz SWEPT GAIN TESTS ONLY) FLUKE 6082A SYNTHESIZED SIGNAL GENERATOR MODULATED PULSE TESTS RF INPUT C1 100pF C3 150pF LADJ PRUP COMM VPOS LMHI FIL1 FIL2 INHI AD602 200 +5V 51.1 COMM OPCM VLOG LMLO ISUM ILOG INLO BFIN SWEPT GAIN TESTS AD606JN 200 HEWLETT PACKARD 8112A PULSE GENERATOR NC C2 100pF NC NC TEKTRONIX 7704A MAINFRAME OSCILLOSCOPE 10 x P6201 ATTN PROBES 6137 PROBES 7A18 AMP 7A24 AMP 7B53A TIME-BASE NC = NO CONNECT Figure 22. Test Setup for Characterization Data REV. B –11– AD606 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP (N-16) 0.87 (22.1) MAX 16 1 9 8 0.31 (7.87) PIN 1 0.25 (6.35) 0.35 (0.89) 0.18 (4.57) 0.300 (7.62) 0.18 (4.57) MAX 0.011 (0.28) 0.125 (3.18) MIN 0.018 (0.46) 0.100 (2.54) BSC 0.033 (0.84) SEATING PLANE 16-Lead Narrow-Body SOIC (R-16A) 0.3937 (10.00) 0.3859 (9.80) 0.1574 (4.00) 0.1497 (3.80) 16 1 9 8 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.050 (1.27) BSC 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 0.0099 (0.25) 45 0.0098 (0.25) 0.0040 (0.10) 8 0.0192 (0.49) SEATING 0.0099 (0.25) 0 PLANE 0.0138 (0.35) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) –12– REV. B PRINTED IN U.S.A. C1698b–0–8/99