AD623ARZ-R7

Single and Dual-Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier AD623 Data Sheet FEATURES GENERAL DESCRIPTION Easy to use Rail-to-rail output swing Input voltage range extends 150 mV below ground (single supply) Low power, 550 µA maximum quiescent current Gain set with one external resistor Gain range: 1 to 1000 High accuracy dc performance 0.10% gain error (G = 1) 0.35% gain error (G > 1) Noise: 35 nV/√Hz RTI noise at 1 kHz Optimal dynamic specifications 800 kHz bandwidth (G = 1) 20 µs settling time to 0.01% (G = 10) The AD623 is an integrated, single- or dual-supply instrumentation amplifier that delivers rail-to-rail output swing using supply voltages from 2.7 V to 12 V. The AD623 offers user flexibility by allowing single gain set resistor programming and by conforming to the 8-lead industry standard pinout configuration. With no external resistor, the AD623 is configured for unity gain (G = 1), and with an external resistor, the AD623 can be programmed for gains of up to 1000. The accuracy of the AD623 is the result of increasing ac common-mode rejection ratio (CMRR) coincident with increasing gain. Line noise harmonics are rejected due to constant CMRR up to 200 Hz. The AD623 has a wide input common-mode range and amplifies signals with commonmode voltages as low as 150 mV below ground. The AD623 maintains optimal performance with dual and single polarity power supplies. APPLICATIONS Low power medical instrumentation Transducer interfaces Thermocouple amplifiers Industrial process controls Difference amplifiers Low power data acquisition Table 1. Low Power Upgrades for the AD623 Part No. AD8235 AD8236 AD8237 AD8226 AD8227 AD8420 AD8422 AD8426 Total Supply Voltage, VS (V dc) 5.5 5.5 5.5 36 36 36 36 36 Typical Quiescent Current, IQ (µA) 30 33 33 350 325 85 300 325 (per channel) FUNCTIONAL BLOCK DIAGRAM +VS 7 2 –IN VDIFF 2 VCM VDIFF 2 A1 – + –RG – 1 8 RG 50kΩ 50kΩ 50kΩ 6 A3 OUTPUT 50kΩ + 3 A2 4 –VS 50kΩ 50kΩ 5 REF 00778-054 +RG +IN Figure 1. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD623 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Basic Connection ....................................................................... 24 Applications ....................................................................................... 1 Gain Selection ............................................................................. 24 General Description ......................................................................... 1 Reference Terminal .................................................................... 24 Functional Block Diagram .............................................................. 1 Input and Output Offset Voltage Error ................................... 24 Revision History ............................................................................... 2 Input Protection ......................................................................... 25 Specifications..................................................................................... 4 RF Interference ........................................................................... 25 Single Supply ................................................................................. 4 Grounding ................................................................................... 26 Dual Supplies ................................................................................ 6 Specifications Common to Dual and Single Supplies ............. 8 Input Differential and Common-Mode Range vs. Supply and Gain .............................................................................................. 28 Absolute Maximum Ratings............................................................ 9 Additional Information ............................................................. 29 ESD Caution .................................................................................. 9 Evaluation Board ............................................................................ 30 Pin Configuration and Function Descriptions ........................... 10 General Description ................................................................... 30 Typical Performance Characteristics ........................................... 11 Outline Dimensions ....................................................................... 31 Theory of Operation ...................................................................... 23 Ordering Guide .......................................................................... 32 Applications Information .............................................................. 24 REVISION HISTORY 9/2020—Rev. F to Rev. G Changed AD623A to AD623ANZ, AD623ARZ and AD623B to AD623BNZ, AD623BRZ .............................................. Throughout Changes to General Description Section ...................................... 1 Changes to Figure 5 Caption, Figure 6 Caption, and Figure 8 Caption ............................................................................................. 10 Changes to Figure 10 Caption, Figure 11, Figure 12, Figure 13, and Figure 14 ................................................................................... 12 Changes to Figure 15 to Figure 20 ................................................ 13 Changes to Figure 21 to Figure 26 ................................................ 14 Changes to Figure 27 to Figure 32 ................................................ 15 Changes to Figure 33 to Figure 38 ................................................ 16 Changes to Figure 39 to Figure 40 ................................................ 17 Added Figure 41 to Figure 44; Renumbered Sequentially ........ 17 Added Figure 45 to Figure 50........................................................ 18 Added Figure 51 to Figure 56........................................................ 19 Added Figure 57 to Figure 62........................................................ 20 Added Figure 63 to Figure 66........................................................ 21 Deleted Single-Supply Data Acquisition System Section and Figure 53; Renumbered Sequentially ........................................... 21 Added Figure 67 to Figure 69........................................................ 22 Change to Figure 70 ....................................................................... 23 Changes to Basic Connection Section and Reference Terminal Section .............................................................................................. 24 Changes to RF Interference Section ............................................ 25 Change to Figure 77 ....................................................................... 26 Changes to Figure 79 and Output Buffering Section ................. 27 Changes to Input Differential and Common-Mode Range vs. Supply and Gain Section................................................................ 28 Changes to Ordering Guide .......................................................... 32 4/2018—Rev. E to Rev. F Changes to Gain Error Parameter, Nonlinearity Parameter, Offset Referred to the Input vs. Supply (PSR) Parameter, and Output Swing Parameter, Table 2 ....................................................3 Changes to Gain Error Parameter and Offset Referred to the Input vs. Supply (PSR) Parameter, Table 3 .....................................5 Changes to Current Noise Parameter, Table 4 ...............................7 Changes to Ordering Guide .......................................................... 26 6/2016—Rev. D to Rev. E Changes to Features Section, General Description Section, and Figure 1 ........................................................................................1 Deleted Connection Diagram Section............................................1 Added Functional Block Diagram Section and Table 1; Renumbered Sequentially ................................................................1 Changes to Single Supply Section ...................................................3 Changes to Table 3.............................................................................6 Changed Both Dual and Single Supplies Section to Specifications Common to Dual and Single Supplies Section ....7 Changes to Table 5.............................................................................8 Added Pin Configuration and Function Descriptions Section, Figure 2, and Table 6; Renumbered Sequentially ..........................9 Changes to Figure 5 Caption, Figure 6 Caption, and Figure 8 Caption ............................................................................. 10 Changes to Figure 17 Caption through Figure 20 Caption ...... 11 Changes to Figure 21 Caption through Figure 26 Caption ...... 12 Changes to Figure 27 Caption and Figure 28 Caption .............. 13 Changes to Theory of Operation Section.................................... 17 Changes to Basic Connection Section ......................................... 18 Changes to Input and Output Offset Voltage Error Section, and Input Protection Section................................................................ 19 Rev. G | Page 2 of 32 Data Sheet AD623 Added Additional Information Section .......................................23 Added Evaluation Board Section and Figure 56 .........................24 Updated Outline Dimensions ........................................................25 Changes to Ordering Guide ...........................................................26 7/2008—Rev. C to Rev. D Updated Format.................................................................. Universal Changes to Features Section and General Description Section .. 1 Changes to Table 3 ............................................................................ 6 Changes to Figure 40 ...................................................................... 14 Changes to Theory of Operation Section .................................... 15 Changes to Figure 42 and Figure 43 ............................................. 16 Changes to Table 7 .......................................................................... 19 Updated Outline Dimensions........................................................ 22 Changes to Ordering Guide ........................................................... 23 9/1999—Rev. B to Rev. C Rev. G | Page 3 of 32 AD623 Data Sheet SPECIFICATIONS SINGLE SUPPLY Typical at 25°C, single supply, +VS = 5 V, −VS = 0 V, and load resistance (RL) = 10 kΩ, unless otherwise noted. Table 2. Parameter GAIN Gain Range Gain Error 1 G=1 G = 10 G = 100 G = 1000 Nonlinearity G = 1 to 1000 Gain vs. Temperature G=1 G > 11 VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average Temperature Coefficient (Tempco) Output Offset, VOSO Over Temperature Average Tempco Offset Referred to the Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average Tempco Input Offset Current Over Temperature Average Tempco Test Conditions/ Comments G=1+ (100 k/external resistor (RG)) AD623ANZ, AD623ARZ Min Typ Max AD623ARM Min Typ Max AD623BNZ, AD623BRZ Min Typ Max 1 1 1 1000 1000 Unit 1000 G1 output voltage (VOUT) = 0.15 V to 3.5 V G > 1 VOUT = 0.15 V to 4.5 V 0.03 0.10 0.10 0.10 0.10 0.35 0.35 0.35 0.03 0.10 0.10 0.10 0.10 0.35 0.35 0.35 0.03 0.10 0.10 0.10 0.05 0.35 0.35 0.35 % % % % G1 VOUT = 0.15 V to 3.5 V G > 1 VOUT = 0.15 V to 4.5 V 50 50 50 ppm 5 50 10 5 50 10 5 50 10 ppm/°C ppm/°C 25 200 350 2 200 500 650 2 25 100 160 1 µV µV µV/°C 500 1100 10 µV µV µV/°C Total referred to input (RTI) error = VOSI + VOSO/G 0.1 200 2.5 80 100 100 100 1000 1500 10 100 120 130 130 17 25 0.25 0.1 500 2.5 80 100 100 100 25 27.5 2 2.5 5 Rev. G | Page 4 of 32 2000 2600 10 100 120 130 130 17 25 0.25 5 0.1 200 2.5 80 100 100 100 25 27.5 2 2.5 100 120 130 130 17 25 0.25 5 dB dB dB dB 25 27.5 2 2.5 nA nA pA/°C nA nA pA/°C Data Sheet Parameter INPUT Input Impedance Differential Common-Mode Input Voltage Range 2 Common-Mode Rejection at 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT Output Swing DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01% G=1 G = 10 1 2 AD623 Test Conditions/ Comments AD623ANZ, AD623ARZ Min Typ Max AD623ARM Min Typ Max AD623BNZ, AD623BRZ Min Typ Max 2||2 2||2 2||2 2||2 2||2 2||2 Unit GΩ||pF GΩ||pF V VS = 3 V to 12 V (−VS) − 0.15 Common-mode voltage (VCM) = 0 V to 3 V VCM = 0 V to 3 V VCM = 0 V to 3 V VCM = 0 V to 3 V 70 80 70 80 77 86 dB 90 105 105 100 110 110 90 105 105 100 110 110 94 105 105 100 110 110 dB dB dB RL = 10 kΩ 0.2 RL = 100 kΩ 0.05 VS = 5 V Step size = 3.5 V Step size = 4 V, VCM = 1.8 V (+VS) − 1.5 (+VS) − 0.5 (+VS) − 0.15 (−VS) − 0.15 (+VS) − 1.5 0.2 (+VS) − 0.5 (+VS) − 0.15 0.05 (−VS) − 0.15 (+VS) − 1.5 0.2 (+VS) − 0.5 (+VS) − 0.15 0.05 V V 800 100 10 2 0.3 800 100 10 2 0.3 800 100 10 2 0.3 kHz kHz kHz kHz V/µs 30 20 30 20 30 20 µs µs Does not include effects of external resistor, RG. One input grounded. G = 1. Rev. G | Page 5 of 32 AD623 Data Sheet DUAL SUPPLIES Typical at 25°C dual supply, VS = ±5 V, and RL = 10 kΩ, unless otherwise noted. Table 3. Parameter GAIN Gain Range Gain Error 1 G=1 G = 10 G = 100 G = 1000 Nonlinearity G = 1 to 1000 Gain vs. Temperature G=1 G > 11 VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average Tempco Output Offset, VOSO Over Temperature Average Tempco Offset Referred to the Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average Tempco Input Offset Current Over Temperature Average Tempco INPUT Input Impedance Differential Common-Mode Input Voltage Range 2 Test Conditions/ Comments G = 1 + (100 k/RG) AD623ANZ, AD623ARZ Min Typ Max AD623ARM Min Typ Max AD623BNZ, AD623BRZ Min Typ Max 1 1 1 1000 1000 Unit 1000 G1 VOUT = −4.8 V to +3.5 V G > 1 VOUT = −4.8 V to 4.5 V 0.03 0.10 0.10 0.10 0.10 0.35 0.35 0.35 0.03 0.10 0.10 0.10 0.10 0.35 0.35 0.35 0.03 0.10 0.10 0.10 0.05 0.35 0.35 0.35 % % % % G1 VOUT = −4.8 V to +3.5 V G > 1 VOUT = −4.8 V to +4.5 V 50 50 50 ppm 5 50 10 5 50 10 5 50 10 ppm/°C ppm/°C 25 200 350 2 1000 1500 10 200 500 650 2 2000 2600 10 25 100 160 1 500 1100 10 µV µV µV/°C µV µV µV/°C Total RTI error = VOSI + VOSO/G 0.1 200 2.5 80 100 100 100 100 120 130 130 17 25 0.25 VS = +2.5 V to ±6 V (−VS) – 0.15 0.1 500 2.5 80 100 100 100 25 27.5 100 120 130 130 17 25 0.25 2 2.5 0.1 200 2.5 80 100 100 100 25 27.5 100 120 130 130 17 25 0.25 2 2.5 5 5 5 2||2 2||2 2||2 2||2 2||2 2||2 (+VS) – 1.5 Rev. G | Page 6 of 32 (−VS) – 0.15 (+VS) – 1.5 (−VS) – 0.15 dB dB dB dB 25 27.5 2 2.5 (+VS) – 1.5 nA nA pA/°C nA nA pA/°C GΩ||pF GΩ||pF V Data Sheet Parameter Common-Mode Rejection at 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT Output Swing DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01% G=1 G = 10 1 2 AD623 AD623ANZ, AD623ARZ Min Typ Max AD623ARM Min Typ Max AD623BNZ, AD623BRZ Min Typ Max Unit VCM = +3.5 V to −5.15 V VCM = +3.5 V to −5.15 V VCM = +3.5 V to −5.15 V VCM = +3.5 V to −5.15 V 70 80 70 80 77 86 dB 90 100 90 100 94 100 dB 105 110 105 110 105 110 dB 105 110 105 110 105 110 dB RL = 10 kΩ, VS = ±5 V RL = 100 kΩ (−VS) + 0.2 (−VS) + 0.05 Test Conditions/ Comments (+VS) − 0.5 (+VS) − 0.15 (−VS) + 0.2 (−VS) + 0.05 (+VS) − 0.5 (+VS) − 0.15 (−VS) + 0.2 (−VS) + 0.05 (+VS) − 0.5 (+VS) − 0.15 V V 800 100 10 2 0.3 800 100 10 2 0.3 800 100 10 2 0.3 kHz kHz kHz kHz V/µs 30 20 30 20 30 20 µs µs VS = ±5 V, 5 V step Does not include effects of external resistor, RG. One input grounded. G = 1. Rev. G | Page 7 of 32 AD623 Data Sheet SPECIFICATIONS COMMON TO DUAL AND SINGLE SUPPLIES Table 4. Parameter NOISE Voltage Noise, 1 kHz Input, Voltage Noise, eni Output, Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 1000 Current Noise 0.1 Hz to 10 Hz REFERENCE INPUT Input Resistance, RIN Input Current, IIN Test Conditions/ Comments Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance AD623ARM Min Typ Max AD623BNZ, AD623BRZ Min Typ Max Unit Total RTI noise = √((eNI)2 + (2eNO/G)2) f = 1 kHz Input voltage (V+IN) = 0 V, reference voltage (VREF) = 0 V Voltage Range Gain to Output POWER SUPPLY Operating Range AD623ANZ, AD623ARZ Min Typ Max 35 50 35 50 35 50 nV/√Hz nV/√Hz 3.0 1.5 100 2.5 3.0 1.5 100 2.5 3.0 1.5 100 2.5 µV p-p µV p-p fA/√Hz pA p-p 100 ± 20% 50 100 ± 20% 50 100 ± 20% 50 kΩ −VS 60 +VS −VS 1± 0.0002 Dual supply Single supply Dual supply Single supply ±2.5 2.7 375 305 −40 60 +VS −VS 1± 0.0002 ±6 12 550 480 625 ±2.5 2.7 +85 −40 Rev. G | Page 8 of 32 375 305 60 µA +VS V V/V ±6 12 550 480 625 V V µA µA µA +85 °C 1± 0.0002 ±6 12 550 480 625 ±2.5 2.7 +85 −40 375 305 Data Sheet AD623 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage Internal Power Dissipation1 Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) 1 Rating 12 V 650 mW ±6 V Indefinite −65°C to +125°C −40°C to +85°C 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Specification is for device in free air: 8-Lead PDIP Package: θJA = 95°C/W 8-Lead SOIC Package: θJA = 155°C/W 8-Lead MSOP Package: θJA = 200°C/W Rev. G | Page 9 of 32 AD623 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD623 8 +RG –IN 2 7 +VS +IN 3 6 OUTPUT –VS 4 5 REF TOP VIEW (Not to Scale) 00778-001 –RG 1 Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic −RG −IN +IN −VS REF OUTPUT +VS +RG Description Inverting Terminal of External Gain Setting Resistor, RG. Inverting In-Amp Input. Noninverting In-Amp Input. Negative Supply Terminal. In-Amp Output Reference Input. The voltage input establishes the common-mode voltage of the output. In-Amp Output. Positive Supply Terminal. Noninverting Terminal of External Gain Setting Resistor, RG. Rev. G | Page 10 of 32 Data Sheet AD623 TYPICAL PERFORMANCE CHARACTERISTICS At 25°C, VS = ±5 V, and RL = 10 kΩ, unless otherwise noted. 300 22 280 260 20 240 18 220 16 200 14 UNITS UNITS 180 160 140 12 10 120 100 8 80 6 60 4 40 2 20 20 40 60 80 100 120 140 0 –600 –500 –400 –300 –200 –100 0 00778-006 0 INPUT OFFSET VOLTAGE (µV) 00778-003 0 –100 –80 –60 –40 –20 100 200 300 400 500 OUTPUT OFFSET VOLTAGE (µV) Figure 3. Typical Distribution of Input Offset Voltage, N-8 and R-8 Package Options Figure 6. Typical Distribution of Output Offset Voltage, +VS = 5 V, −VS = 0 V, VREF = +0.125 V, N-8 and R-8 Package Options 480 210 420 180 360 150 120 UNITS UNITS 300 240 90 180 60 120 30 60 0 200 400 600 800 OUTPUT OFFSET VOLTAGE (µV) 0 00778-007 –800 –600 –400 –200 00778-004 0 –0.245 –0.240 –0.235 –0.230 –0.225 –0.220 –0.215 –0.210 INPUT OFFSET CURRENT (nA) Figure 4. Typical Distribution of Output Offset Voltage, N-8 and R-8 Package Options Figure 7. Typical Distribution for Input Offset Current, N-8 and R-8 Package Options 22 20 20 18 18 16 16 14 12 UNITS 12 10 10 8 8 6 4 4 2 2 0 –80 –60 –40 –20 0 20 40 INPUT OFFSET VOLTAGE (µV) 60 80 100 00778-005 6 Figure 5. Typical Distribution of Input Offset Voltage, +VS = 5 V, −VS = 0 V, VREF = +0.125 V, N-8 and R-8 Package Options 0 –0.025 –0.020 –0.015 –0.010 –0.005 0 0.005 INPUT OFFSET CURRENT (nA) 0.010 00778-008 UNITS 14 Figure 8. Typical Distribution for Input Offset Current, +VS = 5 V, −VS = 0 V, VREF = +0.125 V, N-8 and R-8 Package Options Rev. G | Page 11 of 32 Data Sheet 22 1400 21 1200 20 1000 19 800 600 17 400 16 200 15 0 75 80 85 90 95 100 105 110 115 120 125 130 CMRR (dB) 14 –4 0 2 4 Figure 12. Bias Current (IBIAS) vs. Common-Mode Voltage, N-8 Package Option 1k 16 IBIAS (nA) 15 G=1 100 14 13 G= 10 12 G= 100 100 1k 10k 100k FREQUENCY (Hz) 11 –6 –4 –2 0 2 4 COMMON-MODE VOLTAGE (V) Figure 10. Voltage Noise Spectral Density vs. Frequency, N-8 Package Option 00778-113 10 00778-010 G= 1000 10 1 Figure 13. IBIAS vs. Common-Mode Voltage, RM-8 and R-8 Package Options 30 1k G G G G = 1000 = 100 = 10 =1 25 IBIAS (nA) 20 100 15 10 10 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 11. Voltage Noise Spectral Density vs. Frequency, RM-8 and R-8 Package Options 0 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 14. IBIAS vs. Temperature, N-8 Package Option Rev. G | Page 12 of 32 140 00778-012 5 00778-111 VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz RTI) –2 COMMON-MODE VOLTAGE (V) Figure 9. Typical Distribution for CMRR (G = 1) VOLTAGE NOISE SPECTRAL DENSITY (nV/ Hz RTI) 18 00778-011 IBIAS (nA) 1600 00778-009 UNITS AD623 Data Sheet AD623 16 20.0 19.5 15 19.0 14 IBIAS (nA) IBIAS (nA) 18.5 13 18.0 17.5 12 17.0 11 –40 –20 0 20 40 60 80 100 120 16.0 –4 00778-115 10 –60 140 TEMPERATURE (°C) Figure 15. IBIAS vs. Temperature, RM-8 and R-8 Package Options –1 0 1 2 Figure 18. IBIAS vs. Common-Mode Voltage, VS = ±2.5 V, N-8 Package Option 19 18 IBIAS (nA) 17 100 16 15 10 1 10 100 1k FREQUENCY (Hz) 13 –4 –3 –2 –1 0 1 2 COMMON-MODE VOLTAGE (V) 00778-119 14 00778-013 CURRENT NOISE SPECTRAL DENSITY (fA/ Hz) –2 COMMON-MODE VOLTAGE (V) 1k Figure 19. IBIAS vs. Common-Mode Voltage, VS = ±2.5 V, RM-8 and R-8 Package Option Figure 16. Current Noise Spectral Density vs. Frequency, N-8 Package Option 1k CH1 10mV A 1s 100mV VERT 00778-015 100 10 1 10 100 FREQUENCY (Hz) Figure 17. Current Noise Spectral Density vs. Frequency, RM-8 and R-8 Package Options 1k 00778-117 CURRENT NOISE SPECTRAL DENSITY (fA/√Hz) –3 00778-014 16.5 Figure 20. 0.1 Hz to 10 Hz Current Noise (0.71 pA/DIV), N-8 Package Option Rev. G | Page 13 of 32 Data Sheet 2.0 120 1.5 110 1.0 0.5 0 –0.5 –1.0 –1.5 100 G = ×1000 90 G = ×100 80 70 G = ×10 60 50 G = ×1 40 0 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) Figure 21. 0.1 Hz to 10 Hz Current Noise vs. Time, RM-8 and R-8 Package Option 1µV/DIV 30 00778-121 –2.0 1 10 100 1k 10k 100k FREQUENCY (Hz) 00778-017 COMMON-MODE REJECTION (dB) CURRENT NOISE (pA p-p) AD623 Figure 24. Common-Mode Rejection vs. Frequency, +VS = 5 V, − VS = 0 V, VREF = 2.5 V, for Various Gain Settings, N-8 Package Option 120 1s 00778-016 COMMON-MODE REJECTION (dB) 110 100 90 80 70 60 50 40 30 G = 1000 G = 100 G = 10 G=1 20 10 10 100 1k 10k 00778-125 0 100k FREQUENCY (Hz) Figure 22. 0.1 Hz to 10 Hz RTI Voltage Noise (1 DIV = 1 μV p-p), N-8 Package Option Figure 25. Common-Mode Rejection vs. Frequency, +VS = 5 V, − VS = 0 V, VREF = 2.5 V, for Various Gain Settings, RM-8 and R-8 Package Options 4 120 G=1 G = 1000 2 1 0 –1 –2 –3 100 G = ×1000 90 80 G = ×100 70 60 G = ×10 50 G = ×1 40 –4 0 1 2 3 4 5 6 7 8 9 TIME (s) Figure 23. RTI Voltage Noise, 0.1 Hz to 10 Hz vs. Time, RM-8 and R-8 Package Options 10 30 1 10 100 1k FREQUENCY (Hz) 10k 100k 00778-018 COMMON-MODE REJECTION (dB) 110 00778-123 RTI VOLTAGE NOISE (µV p-p) 3 Figure 26. Common-Mode Rejection vs. Frequency for Various Gain Settings, N-8 Package Option Rev. G | Page 14 of 32 AD623 130 5 120 4 110 3 COMMON-MODE INPUT (V) 100 90 80 70 60 50 40 30 100 1k 10k 100k –2 –1 0 1 2 3 4 5 4 3 COMMON-MODE INPUT (V) G = 100 30 G = 10 10 G=1 2 1 VS = ±2.5 V 0 –1 –2 –3 –4 –20 –5 1k 10k 100k 1M FREQUENCY (Hz) –6 –5 00778-019 –30 100 –4 –3 –2 –1 0 1 2 3 4 5 MAXIMUM OUTPUT VOLTAGE (V) Figure 31. Common-Mode Input vs. Maximum Output Voltage, G = 1, RL = 100 kΩ for Two Supply Voltages, RM-8 and R-8 Package Options Figure 28. Gain vs. Frequency (+VS = 5 V, −VS = 0 V), VREF = 2.5 V, for Various Gain Settings, N-8 Package Option 5 70 G G G G 4 3 COMMON-MODE INPUT (V) 60 = 1000 = 100 = 10 =1 50 40 30 20 10 VS = ±2.5V 2 1 0 –1 –2 –3 –4 0 100 1k 10k 100k 1M FREQUENCY (Hz) 00778-129 –10 10 –5 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 MAXIMUM OUTPUT VOLTAGE (V) Figure 32. Common-Mode Input vs. Maximum Output Voltage, G ≥ 10, RL = 100 kΩ, for Two Supply Voltages, N-8 Package Option Figure 29. Gain vs. Frequency (+VS = 5 V, −VS = 0 V), VREF = 2.5 V, for Various Gain Settings, RM-8 and R-8 Package Options Rev. G | Page 15 of 32 00778-021 GAIN (dB) –3 5 G = 1000 –10 GAIN (dB) –4 Figure 30. Common-Mode Input vs. Maximum Output Voltage, G = 1, RL = 100 kΩ for Two Supply Voltages, N-8 Package Option 50 0 –3 MAXIMUM OUTPUT VOLTAGE (V) 70 20 –2 –6 –5 Figure 27. Common-Mode Rejection vs. Frequency for Various Gain Settings, RM-8 and R-8 Package Options 40 –1 –5 FREQUENCY (Hz) 60 0 –4 G = 1000 G = 100 G = 10 G=1 0 10 VS = ±2.5V 1 00778-020 10 2 00778-131 20 00778-127 COMMON-MODE REJECTION (dB) Data Sheet AD623 Data Sheet 5 5 4 4 2 COMMON-MODE INPUT (V) COMMON-MODE INPUT (V) 3 VS = ±2.5 V 1 0 –1 –2 –3 3 2 1 –4 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 MAXIMUM OUTPUT VOLTAGE (V) –1 00778-133 –6 –6 0 4 4 COMMON-MODE INPUT (V) 0 5 3 2 1 1 2 3 4 5 MAXIMUM OUTPUT VOLTAGE (V) –1 00778-022 0 0 1 2 3 4 5 MAXIMUM OUTPUT VOLTAGE (V) 00778-137 0 –1 Figure 37. Common-Mode Input vs. Maximum Output Voltage, G ≥ 10, +VS = 5 V, −VS = 0 V, RL = 100 kΩ, RM-8 and R-8 Package Options Figure 34. Common-Mode Input. vs. Maximum Output Voltage, G = 1, +VS = 5 V, −VS = 0 V, RL = 100 kΩ, N-8 Package Option 140 5 120 4 G = 1000 POSITIVE PSRR (dB) COMMON-MODE INPUT (V) 4 3 2 1 100 G = 100 80 60 G = 10 40 G=1 0 20 0 1 2 3 MAXIMUM OUTPUT VOLTAGE (V) 4 5 0 00778-135 –1 Figure 35. Common-Mode Input vs. Maximum Output Voltage, G = 1, +VS = 5 V, −VS = 0 V, RL = 100 kΩ, RM-8 and R-8 Package Options 1 10 100 1k FREQUENCY (Hz) 10k 100k 00778-024 COMMON-MODE INPUT (V) 5 1 3 Figure 36. Common-Mode Input vs. Maximum Output Voltage, G ≥ 10, +VS = 5 V, −VS = 0 V, RL = 100 kΩ, N-8 Package Option 5 2 2 MAXIMUM OUTPUT VOLTAGE (V) Figure 33. Common-Mode Input vs. Maximum Output Voltage, G ≥ 10, RL = 100 kΩ, for Two Supply Voltages, RM-8 and R-8 Package Options 3 1 00778-023 –5 Figure 38. Positive Power Supply Rejection Ratio (PSRR) vs. Frequency, N-8 Package Option Rev. G | Page 16 of 32 Data Sheet AD623 140 140 G G G G 120 = 1000 = 100 = 10 =1 G = 1000 120 NEGATIVE PSRR (dB) 80 60 40 100 80 G = 10 60 G=1 40 20 20 1 10 100 1k 10k 100k FREQUENCY (Hz) 0 00778-139 0 1 10 100 1k 10k 100k FREQUENCY (Hz) 00778-026 POSITIVE PSRR (dB) G = 100 100 Figure 42. Negative PSRR vs. Frequency for Various Gain Settings, N-8 Package Option Figure 39. Positive PSRR vs. Frequency, RM-8 and R-8 Package Options 160 140 G G G G 140 120 G = 1000 = 1000 = 100 = 10 =1 NEGATIVE PSRR (dB) POSITIVE PSRR (dB) 120 100 G = 100 80 60 G = 10 40 100 80 60 40 G=1 20 1 10 100 1k 10k 100k FREQUENCY (Hz) 00778-025 0 0 1 100 1k 10k 100k FREQUENCY (Hz) Figure 43. Negative PSRR vs. Frequency for Various Gain Settings, RM-8 and R-8 Package Options Figure 40. Positive PSRR vs. Frequency, +VS = 5V, −VS = 0 V, for Various Gain Settings, N-8 Package Option 10 140 G G G G = 1000 = 100 = 10 =1 8 OUTPUT VOLTAGE (V p-p) 120 100 80 60 40 6 4 VS = ±5V VS = ±2.5V 2 0 1 10 100 1k 10k 100k FREQUENCY (Hz) 0 0 20 40 60 80 100 FREQUENCY (kHz) Figure 44. Large Signal Response, G ≤ 10 for Two Supply Voltages Figure 41. Positive PSRR vs. Frequency, +VS = 5V, −VS = 0 V, for Various Gain Settings, RM-8 and R-8 Package Options Rev. G | Page 17 of 32 00778-027 20 00778-141 POSITIVE PSRR (dB) 10 00778-143 20 AD623 Data Sheet 1k SETTLING TIME (µs) 500µV 1V 10µs 100 1 100 1k GAIN (V/V) Figure 48. Large Signal Pulse Response and Settling Time, G = −10 (0.250 mV = 0.01%), CL = 100 pF, N-8 Package Option Figure 45. Settling Time to 0.01% vs. Gain, for a 5 V Step at Output, CL = 100 pF 1V 3 300 2 200 1 100 0 0 20µs OUTPUT VOLTAGE (V) 500µV –100 –1 –200 00778-029 –2 VOUT DELTA_mV –3 –10 –300 0 10 20 30 40 50 60 70 80 TIME (µs) Figure 46. Large Signal Pulse Response and Settling Time, G = −1 (0.250 mV = 0.01%), CL = 100 pF, N-8 Package Option Figure 49. Large Signal Pulse Response and Settling Time, G = −10 (0.250 mV = 0.01%), CL = 100 pF, RM-8 and R-8 Package Options 300 3 100 0 0 –1 –100 –2 –200 –3 –20 0 20 40 60 80 100 TIME (µs) 120 140 160 –300 180 00778-031 1 50µs ERROR VOLTAGE (mV) 200 2V 00778-147 OUTPUT VOLTAGE (V) 10mV 2 ERROR VOLTAGE (mV) 10 00778-149 1 00778-028 00778-030 10 Figure 47. Large Signal Pulse Response and Settling Time, G = −1 (0.250 mV = 0.01%), CL = 100 pF, RM-8 and R-8 Package Options Rev. G | Page 18 of 32 Figure 50. Large Signal Pulse Response and Settling Time, G = 100, CL = 100 pF, N-8 Package Option Data Sheet AD623 300 3 1 100 0 0 –1 –100 –2 –200 –3 –40 10 60 110 160 210 260 310 –300 360 TIME (µs) 00778-033 200 ERROR VOLTAGE (mV) 2 2µs 00778-151 OUTPUT VOLTAGE (V) 20mV Figure 51. Large Signal Pulse Response and Settling Time, G = 100, CL = 100 pF, RM-8 and R-8 Package Options Figure 54. Small Signal Pulse Response, G = 1, RL = 10 kΩ, CL = 100 pF, N-8 Package Option 120 2V 20mV 500µs 100 OUTPUT VOLTAGE (mV) 80 60 40 20 0 –20 –40 –60 00778-032 –80 –120 0 2 4 6 8 10 12 14 16 18 20 TIME (µs) Figure 52. Large Signal Pulse Response and Settling Time, G = −1000 (5 mV = 0.01%), CL = 100 pF, N-8 Package Option 3 Figure 55. Small Signal Pulse Response, G = 1, RL = 10 kΩ, CL = 100 pF, RM-8 and R-8 Package Options 300 1 100 0 0 –1 –100 –2 –200 –0.5 0 0.5 1.0 TIME (ms) 1.5 2.0 2.5 –300 3.0 00778-034 200 ERROR VOLTAGE (mV) 2 5µs 00778-153 OUTPUT VOLTAGE (V) 20mV –3 –1.0 00778-155 –100 Figure 53. Large Signal Pulse Response and Settling Time, G = −1000 (5 mV = 0.01%), CL = 100 pF, RM-8 and R-8 Package Options Figure 56. Small Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF, N-8 Package Option Rev. G | Page 19 of 32 AD623 Data Sheet 120 20mV 100 500µs OUTPUT VOLTAGE (mV) 80 60 40 20 0 –20 –40 –60 00778-036 –80 –120 0 5 10 15 20 25 30 35 40 TIME (µs) 00778-157 –100 Figure 57. Small Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF, RM-8 and R-8 Package Options Figure 60. Small Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF, N-8 Package Option 120 20mV 50µs 100 OUTPUT VOLTAGE (mV) 80 60 40 20 0 –20 –40 –60 00778-035 –80 –120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 TIME (ms) Figure 58. Small Signal Pulse Response, G = 100, RL = 10 kΩ, CL = 100 pF, N-8 Package Option 00778-161 –100 Figure 61. Small Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF, RM-8 and R-8 Package Options 120 200µV 100 60 40 20 0 –20 –40 –60 –80 1V –120 0 0.5 1.0 1.5 2.0 TIME (ms) 2.5 3.0 3.5 4.0 00778-159 –100 00778-037 OUTPUT VOLTAGE (mV) 80 Figure 59. Small Signal Pulse Response, G = 100, RL = 10 kΩ, CL = 100 pF, RM-8 and R-8 Package Options Figure 62. Gain Nonlinearity, G = −1 (50 ppm/DIV), N-8 Package Option Rev. G | Page 20 of 32 Data Sheet AD623 5 6 4 GAIN NONLINEARITY (ppm) –5 –10 –15 –20 2 0 –2 –4 –25 –3.8 –2.8 –1.8 –0.8 0.2 1.2 2.2 3.2 OUTPUT VOLTAGE (V) –6 –4.8 00778-163 –30 –4.8 –3.8 –2.8 –1.8 –0.8 0.2 1.2 2.2 3.2 4.2 OUTPUT VOLTAGE (V) Figure 63. Gain Nonlinearity vs. Output Voltage, G = −1, RM-8 and R-8 Package Options Figure 65. Gain Nonlinearity vs. Output Voltage, G = −10, RM-8 and R-8 Package Options 20µV 50µV 1V 00778-039 00778-038 1V 00778-165 GAIN NONLINEARITY (ppm) 0 Figure 64. Gain Nonlinearity, G = −10 (6 ppm/DIV), N-8 Package Option Figure 66. Gain Nonlinearity, G = −100, 15 ppm/DIV, N-8 Package Option Rev. G | Page 21 of 32 AD623 Data Sheet GAIN NONLINEARITY (ppm) 60 50 40 30 20 0 –10 –20 –3.8 –2.8 –1.8 –0.8 0.2 1.2 2.2 3.2 4.2 OUTPUT VOLTAGE (V) (V+) –2.5 (V–) +0.5 V– 1.5 2.0 00778-040 OUTPUT VOLTAGE SWING (V) (V+) –1.5 1.0 –3.5 2 –4.0 SWING FROM –VS 1 –4.5 –5.0 1 2 3 4 5 6 7 OUTPUT CURRENT (mA) (V+) –0.5 OUTPUT CURRENT (mA) 3 8 9 10 11 Figure 69. Positive and Negative Output Voltage Swing vs. Output Current, RM-8 and R-8 Package Options V+ 0.5 –3.0 0 Figure 67. Gain Nonlinearity vs. Output Voltage, G = −100, RM-8 and R-8 Package Options 0 SWING FROM +VS 4 0 00778-167 –30 –4.8 –2.5 NEGATIVE OUTPUT VOLTAGE SWING (V) POSITIVE OUTPUT VOLTAGE SWING (V) 5 00778-169 70 Figure 68. Output Voltage Swing vs. Output Current, N-8 Package Option Rev. G | Page 22 of 32 Data Sheet AD623 THEORY OF OPERATION The AD623 is an instrumentation amplifier based on a modified classic 3-op-amp approach to ensure single- or dual-supply operation even at common-mode voltages at the negative supply rail. Low voltage offsets (input and output), absolute gain accuracy, and one external resistor to set the gain make the AD623 a versatile instrumentation amplifier. pin is 100 kΩ. Therefore, in applications requiring voltage conversion, a small resistor between Pin 5 (REF) and Pin 6 (OUTPUT) is all that is needed. +VS 7 The input signal is applied to positive-negative-positive (PNP) transistors acting as voltage buffers and providing a commonmode signal to the input amplifiers (see Figure 70). An absolute value 50 kΩ resistor in each amplifier feedback ensures gain programmability. –RG The differential output is +RG –IN 2 1 4 –VS 50kΩ 50kΩ 50kΩ 6 RG 50kΩ 8  100 kΩ  VC VO = 1 + RG   50kΩ 50kΩ +VS 5 OUTPUT REF 7 +IN 3 4 –VS 00778-041 The differential voltage is then converted to a single-ended voltage using the output amplifier, which also rejects any common-mode signal at the output of the input amplifiers. Figure 70. Simplified Schematic Because the amplifiers can swing to either supply rail, as well as have their common-mode range extended to below the negative supply rail, the range over which the AD623 can operate is further enhanced (see Figure 30, Figure 31, Figure 32, and Figure 33). The output voltage at Pin 6 (OUTPUT) is measured with respect to the potential at Pin 5 (REF). The impedance of the REF Because of the voltage feedback topology of the internal op amps, the bandwidth of the instrumentation amplifier decreases with increasing gain. At unity gain, the output amplifier limits the bandwidth. Rev. G | Page 23 of 32 AD623 Data Sheet APPLICATIONS INFORMATION BASIC CONNECTION Table 7. Required Values of Gain Resistors Figure 71 and Figure 72 show the basic connection circuits for the AD623. The +VS and −VS terminals are connected to the power supply. The supply can be either bipolar (VS = ±2.5 V to ±6 V) or single supply (−VS = 0 V, +VS = 2.7 V to 12 V). Capacitively decouple power supplies close to the power pins of the device. For optimal results, use surface-mount 0.1 µF ceramic chip capacitors and 10 µF electrolytic tantalum capacitors. Desired Gain 2 5 10 20 33 40 50 65 100 200 500 1000 +VS 10µF 0.1µF +2.5V TO +6V VIN RG RG OUTPUT RG REF VOUT REF (INPUT) 10µF –VS VOUT The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. The reference terminal provides a direct means of injecting a precise offset to the output. The reference terminal is also useful when bipolar signals are being amplified because the terminal can provide a virtual ground voltage. The voltage on the reference terminal can vary from −VS to +VS. REF (INPUT) INPUT AND OUTPUT OFFSET VOLTAGE ERROR –2.5V TO –6V Figure 71. Dual-Supply Basic Connection +VS 0.1µF 10µF +3V TO +12V RG RG OUTPUT RG REF 00778-055 VIN Calculated Gain Using 1% Resistors 2 5.02 10.09 20.12 33.36 40.21 49.78 64.29 99.04 201.4 501 1001 REFERENCE TERMINAL 00778-042 0.1µF 1% Standard Table Value of RG 100 kΩ 24.9 kΩ 11 kΩ 5.23 kΩ 3.09 kΩ 2.55 kΩ 2.05 kΩ 1.58 kΩ 1.02 kΩ 499 Ω 200 Ω 100 Ω Figure 72. Single-Supply Basic Connection The input voltage, which can be either single-ended (tie either −IN or +IN to ground) or differential, is amplified by the programmed gain. The output signal appears as the voltage difference between the OUTPUT pin and the externally applied voltage on the REF input. For a ground referenced output, ground REF. The offset voltage (VOS) of the AD623 is attributed to two sources: those originating in the two input stages where the instrumentation amplifier gain is established, and those originating in the subtractor output stage. The output error is divided by the programmed gain when referred to the input. In practice, the input errors dominate at high gain settings, whereas the output error prevails when the gain is set at or near unity. Calculate the VOS error for any given gain as follows: GAIN SELECTION The gain of the AD623 is programmed by the RG resistor, or more precisely, by whatever impedance appears between Pin 1 and Pin 8. The AD623 offers accurate gains using 0.1% to 1% tolerance resistors. Table 7 shows the required values of RG for the various gains. Note that for G = 1, the RG terminals are unconnected (RG = ∞). For any arbitrary gain, RG can be calculated by Total Error Referred to Input (RTI) = Input Error + (Output Error/G) Total Error Referred to Output (RTO) = (Input Error × G) + Output Error The RTI offset errors and noise voltages for different gains are listed in Table 8. RG = 100 kΩ/(G − 1) Rev. G | Page 24 of 32 Data Sheet AD623 INPUT PROTECTION Internal supply referenced clamping diodes allow the input, reference, output, and gain terminals of the AD623 to safely withstand overvoltages of 0.3 V above or below the supplies. This overvoltage protection is true at all gain settings and when cycling power on and off. Overvoltage protection is particularly important because the signal source and amplifier can be powered separately. enough to significantly increase the noise of the circuit. To preserve common-mode rejection in the pass band of the amplifier, the C1 and C2 capacitors must be ±5% tolerance, or low cost 20% capacitors can be tested and binned to provide closely matched devices. +VS 0.33µF R1 4.02kΩ 1% 0.01µF C1 1000pF 5% –IN If the overvoltage exceeds this value, limit the current through these diodes to about 10 mA using external current-limiting resistors (see Figure 73). The size of this resistor is defined by the supply voltage and the required overvoltage protection. R2 C3 4.02kΩ 0.047µF 1% RG AD623 +IN C2 1000pF 5% VOUT REFERENCE 0.33µF 0.01µF +VS NOTES: 1. LOCATE C1 TO C3 AS CLOSE TO THE INPUT PINS AS POSSIBLE. I = 10mA MAX VOVER AD623 RLIM Figure 74. Circuit to Attenuate RF Interference OUTPUT RG RLIM RLIM = VOVER –VS + 0.7V 10mA –VS 00778-043 VOVER 00778-044 +VS Figure 73. Input Protection RF INTERFERENCE All instrumentation amplifiers can rectify high frequency outof-band signals. When rectified, these signals appear as dc offset errors at the output. The circuit in Figure 74 provides RFI suppression without reducing performance within the pass band of the instrumentation amplifier. Resistor 1 (R1) and Capacitor 1 (C1), and likewise, Resistor 2 (R2) and Capacitor 2 (C2), form a low-pass resistor capacitor (RC) filter that has a −3 dB bandwidth equal to f = 1/(2 π R1C1). Using the component values shown in Figure 74, this filter has a −3 dB bandwidth of approximately 40 kHz. The R1 and R2 resistors were chosen to be large enough to isolate the input of the circuit from the capacitors but not large C3 is needed to maintain common-mode rejection at low frequencies. R1 and R2, as well as C1 and C2, form a bridge circuit whose output appears across the input pins of the instrumentation amplifier. Any mismatch between C1 and C2 unbalances the bridge and reduces the common-mode rejection. C3 ensures that any RF signals are common-mode (the same on both instrumentation amplifier inputs) and are not applied differentially. This second low-pass network, R1 + R2 and C3, has a −3 dB frequency equal to 1/(2π(R1 + R2)(C3)). Using a C3 value of 0.047 µF, the −3 dB signal bandwidth of this circuit is approximately 400 Hz. The typical dc offset shift over frequency is less than 1.5 µV, and the RF signal rejection of the circuit is greater than 71 dB. The 3 dB signal bandwidth of this circuit can be increased to 900 Hz by reducing R1 and R2 to 2.2 kΩ. The performance is similar to using 4 kΩ resistors, except that the circuitry preceding the instrumentation amplifier must drive a lower impedance load. Table 8. RTI Error Sources Gain 1 2 5 10 20 50 100 1000 Maximum Total Input Offset Error (µV) AD623ANZ, AD623BNZ, AD623ARZ AD623BRZ 1200 600 700 350 400 200 300 150 250 125 220 110 210 105 200 100 Maximum Total Input Offset Drift (µV/°C) AD623ANZ, AD623BNZ, AD623ARZ AD623BRZ 12 11 7 6 4 3 3 2 2.5 1.5 2.2 1.2 2.1 1.1 2 1 Rev. G | Page 25 of 32 Total Input Referred Noise (nV/√Hz) AD623ANZ, AD623BNZ, AD623ARZ AD623BRZ 62 62 45 45 38 38 35 35 35 35 35 35 35 35 35 35 AD623 Data Sheet The circuit in Figure 74 must be built using a printed circuit board (PCB) with a ground plane on both sides. All component leads must be as short as possible. The R1 and R2 resistors can be common 1% metal film units. However, the C1 and C2 capacitors must be ±5% tolerance devices to avoid degrading the common-mode rejection of the circuit. Either the traditional 5% silver mica units or Panasonic ±2% polyphenylene sulfide (PPS) film capacitors are recommended. problems can be solved by simply tying the REF pin to the appropriate local ground. Tie the REF pin to a low impedance point for optimal CMR. The use of ground planes is recommended to minimize the impedance of ground returns (and therefore the size of dc errors). To isolate low level analog signals from a noisy digital environment, many data acquisition components have separate analog and digital ground returns (see Figure 76). All ground pins from mixed signal components, such as analog-to-digital converters (ADCs), must be returned through the high quality analog ground plane. Maximum isolation between analog and digital is achieved by connecting the ground planes back at the supplies. The digital return currents from the ADC that flow in the analog ground plane, in general, have a negligible effect on noise performance. In many applications, shielded cables minimize noise. For optimal CMR over frequency, the shield must be properly driven. Figure 75 shows an active guard driver that is configured to improve ac common-mode rejection by bootstrapping the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. +VS –IN 1 AD623 AD8031 RG 2 OUTPUT 6 5 8 3 REF 4 –VS Figure 75. Common-Mode Shield Driver GROUNDING Because the AD623 output voltage is developed with respect to the potential on the reference terminal, many grounding ANALOG POWER SUPPLY +5V –5V 2 1 3 6 VDD 4 VIN1 4 6 3 5 +5V 0.1µF 0.1µF 7 AD623 GND 14 AGND DGND 12 AGND VDD MICROPROCESSOR ADC AD7892-2 VIN2 00778-046 0.1µF 0.1µF DIGITAL POWER SUPPLY GND Figure 76. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies POWER SUPPLY +5V GND 0.1µF 0.1µF 2 7 1 4 AD623 3 0.1µF 5 6 VDD 4 VIN1 6 14 AGND DGND ADC 12 VDD MICROPROCESSOR AD7892-2 Figure 77. Optimal Ground Practice in a Single-Supply Environment Rev. G | Page 26 of 32 AGND 00778-047 +IN 7 00778-045 RG 2 100Ω If there is only a single power supply available, it must be shared by both digital and analog circuitry. Figure 77 shows how to minimize interference between the digital and analog circuitry. As in the previous case, use separate analog and digital ground planes (reasonably thick traces can be used as an alternative to a digital ground plane). Connect these ground planes at the ground pin of the power supply. Run separate traces from the power supply to the supply pins of the digital and analog circuits. Ideally, each device has its own power supply trace, but these can be shared by a number of devices, as long as a single trace is not used to route current to both digital and analog circuitry. 2 Data Sheet AD623 Ground Returns for Input Bias Currents Output Buffering Input bias currents are dc currents that must flow to bias the input transistors of an amplifier, which are usually transistor base currents. When amplifying floating input sources, such as transformers or ac-coupled sources, there must be a direct dc path into each input so that the bias current can flow. Figure 78, Figure 79, and Figure 80 show how a bias current path can be provided for transformer coupling, thermocouple, and capacitive ac coupling. In dc-coupled resistive bridge applications, providing this path is generally not necessary because the bias current simply flows from the bridge supply through the bridge into the amplifier. However, if the impedances that the two inputs see are large and differ by a large amount (>10 kΩ), the offset current of the input stage causes dc errors proportional with the input offset voltage of the amplifier. The AD623 is designed to drive loads of 10 kΩ or greater. If the load is less than this value, the output of the AD623 must be buffered with a precision single-supply op amp, such as the OP113. This op amp can swing from 0 V to 4 V on its output while driving a load as small as 600 Ω (see Figure 81). Table 9 summarizes the performance of some buffer op amps. 5V 0.1µF VIN RG AD623 Table 9. Buffering Options 7 AD623 5 8 REF 4 LOAD –VS TO POWER SUPPLY GROUND Figure 78. Ground Returns for Bias Currents with Transformer-Coupled Inputs +VS 2 5V AD623 3 0.1µF OUTPUT 6 5 8 +IN Because the common-mode input range of the AD623 extends 0.1 V below ground, it is possible to measure small differential signals that have low or no common-mode component. Figure 82 shows a thermocouple application where one side of the J-type thermocouple is grounded. 7 1 RG Amplifying Signals with Low Common-Mode Voltage REF 4 J-TYPE THERMOCOUPLE LOAD –VS 00778-049 –IN TO POWER SUPPLY GROUND 7 AD623 2V 100kΩ 100kΩ 4 –VS REF LOAD 00778-050 3 OUTPUT 6 5 8 +IN OUTPUT Over a temperature range of −200°C to +200°C, the J-type thermocouple delivers a voltage ranging from −7.890 mV to +10.777 mV. A programmed gain on the AD623 of 100 (RG = 1.02 kΩ) and a voltage on the REF pin of 2 V result in the output voltage ranging from 1.110 V to 3.077 V relative to ground. 2 RG AD623 Figure 82. Amplifying Bipolar Signals with Low Common-Mode Voltage +VS 1 RG 1.02kΩ REF Figure 79. Ground Returns for Bias Currents with Thermocouple Inputs –IN Description Single-supply, high output current Rail-to-rail input and output, low supply current 00778-053 3 +IN Op Amp OP113 OP191 OUTPUT 6 00778-048 RG 00778-051 Figure 81. Output Buffering 2 1 VOUT OP113 REFERENCE +VS –IN 5V 0.1µF TO POWER SUPPLY GROUND Figure 80. Ground Returns for Bias Currents with AC-Coupled Inputs Rev. G | Page 27 of 32 AD623 Data Sheet |VDIFFMAX| = 2 (+VS − 0.7 V − VCM)/Gain INPUT DIFFERENTIAL AND COMMON-MODE RANGE vs. SUPPLY AND GAIN |VDIFFMAX| = 2 (VCM − −VS + 0.590 V)/Gain Figure 83 shows a simplified block diagram of the AD623. The voltages at the outputs of Amplifier 1 (A1) and Amplifier 2 (A2) are given by VA2 = VCM + VDIFF/2 + 0.6 V + VDIFF × RF/RG = VCM + 0.6 V + VDIFF × Gain/2 Input Range ≤ Available Output Swing/Gain For a bipolar input voltage with a common-mode voltage that is roughly half way between the rails, VDIFFMAX is half the value that the previous equations yield because the REF pin is at midsupply. Note that the available output swing is given for different supply conditions in the Specifications section. VA1 = VCM − VDIFF/2 + 0.6 V + VDIFF × RF/RG = VCM + 0.6 V − VDIFF × Gain/2 +VS 7 –IN 4 –VS – 1 RF 50kΩ 50kΩ 50kΩ GainMAX = 2 (+VS − 0.7 V − VCM)/VDIFF + 6 GAIN RG VCM A3 8 RF 50kΩ 50kΩ 50kΩ +VS VDIFF 2 The equations can be rearranged to result in the maximum gain for a fixed set of input conditions. The maximum gain is the lesser of the two equations. A1 – +IN Again, it is recommended that the resulting gain multiplied by the input range is less than the available output swing. If this is not the case, the maximum gain is given by 5 REF 7 A2 + GainMAX = 2 (VCM − −VS + 0.590 V)/VDIFF OUTPUT GainMAX = Available Output Swing/Input Range 3 4 –VS 00778-055 VDIFF 2 2 However, the range on the differential input voltage range is also constrained by the output swing. Therefore, the range of VDIFF may need to be lower according to the following equation: Figure 83. Simplified Block Diagram The voltages on these internal nodes are critical in determining whether the output voltage is clipped. The VA1 and VA2 voltages can swing from approximately 10 mV above the negative supply (−VS or ground) to within approximately 100 mV of the positive rail before clipping occurs. Based on this, and from the previous equations, the maximum and minimum input common-mode voltages are given by the following equations: VCMMAX = +VS − 0.7 V − VDIFF × Gain/2 VCMMIN = −VS − 0.590 V + VDIFF × Gain/2 These equations can be rearranged to give the maximum possible differential voltage (positive or negative) for a particular commonmode voltage, gain, and power supply. Because the signals on A1 and A2 can clip on either rail, the maximum differential voltage is the lesser of the two equations. Also, for bipolar inputs (that is, input range = 2 VDIFF), the maximum gain is half the value yielded by the previous equations because the REF pin must be at midsupply. The maximum gain and resulting output swing for different input conditions is shown in Table 10. Output voltages are referenced to the voltage on the REF pin. For the purposes of computation, it is necessary to break down the input voltage into its differential and common-mode components. Therefore, when one of the inputs is grounded or at a fixed voltage, the common-mode voltage changes as the differential voltage changes. An example of this is the thermocouple amplifier in Figure 82. The inverting input on the AD623 is grounded. Therefore, when the input voltage is −10 mV, the voltage on the noninverting input is −10 mV. For the purpose of the signal swing calculations, this input voltage must be composed of a common-mode voltage of −5 mV (that is, (+IN + −IN)/2) and a differential input voltage of −10 mV (that is, +IN − −IN). Rev. G | Page 28 of 32 Data Sheet AD623 Table 10. Maximum Attainable Gain and Resulting Output Swing for Different Input Conditions VCM (V) 0 0 0 0 0 2.5 2.5 2.5 1.5 1.5 0 0 Differential Voltage (VDIFF) ±10 mV ±100 mV ±10 mV ±100 mV ±1 V ±10 mV ±100 mV ±1 V ±10 mV ±100 mV ±10 mV ±100 mV REF Pin (V) 2.5 2.5 0 0 0 2.5 2.5 2.5 1.5 1.5 1.5 1.5 Supply Voltages (V) +5 +5 ±5 ±5 ±5 +5 +5 +5 +3 +3 +3 +3 ADDITIONAL INFORMATION For an updated design of the AD623, see the AD8223. For a selection guide to all Analog Devices instrumentation amplifiers, see the Instrumentation Amplifiers page on the Analog Devices website at www.analog.com/inamps. Maximum Gain 118 11.8 490 49 4.9 242 24.2 2.42 142 14.2 118 11.8 Closest 1% Gain Resistor 866 Ω 9.31 kΩ 205 Ω 2.1 kΩ 26.1 kΩ 422 Ω 4.32 kΩ 71.5 kΩ 715 Ω 7.68 kΩ 866 Ω 9.31 kΩ Resulting Gain 116 11.7 488 48.61 4.83 238 24.1 2.4 141 14 116 11.74 Output Swing (V) ±1.2 ±1.1 ±4.8 ±4.8 ±4.8 ±2.3 ±2.4 ±2.4 ±1.4 ±1.4 ±1.1 ±1.1 For additional information on instrumentation amplifiers, refer to the following:  MT-061, Instrumentation Amplifier (In-Amp) Basics  MT-070, In-Amp Input RFI Protection  A Designer's Guide to Instrumentation Amplifiers, Counts, Lew and Charles Kitchen Rev. G | Page 29 of 32 AD623 Data Sheet EVALUATION BOARD The EVAL-INAMP-62RZ can be used to evaluate the AD620, AD621, AD622, AD623, AD627, AD8223, and AD8225 instrumentation amplifiers. In addition to the basic in-amp connection, circuit options enable the user to adjust the offset voltage, apply an output reference, or provide shield drivers with user supplied components. The board is shipped with an assortment of instrumentation amplifier ICs in the legacy SOIC pinout, such as the AD620, AD621, AD622, AD623, AD8223, and AD8225. The board also has an alternative footprint for a through-hole, 8-lead PDIP. Figure 84 shows a photograph of the evaluation boards for all Analog Devices instrumentation amplifiers. For additional information, see the EVAL-INAMP user guide (UG-261). Rev. G | Page 30 of 32 00778-056 GENERAL DESCRIPTION Figure 84. Evaluation Boards for Analog Devices In-Amps Data Sheet AD623 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070606-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 85. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 86. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. G | Page 31 of 32 012407-A 8 4.00 (0.1574) 3.80 (0.1497) AD623 Data Sheet 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA 0.80 0.55 0.40 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 Figure 87. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD623ANZ AD623ARZ AD623ARZ-R7 AD623ARZ-RL AD623ARMZ AD623ARMZ-REEL AD623ARMZ-REEL7 AD623BNZ AD623BRZ AD623BRZ-R7 AD623BRZ-RL EVAL-INAMP-62RZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP], 13" Tape and Reel 8-Lead Mini Small Outline Package [MSOP], 7" Tape and Reel 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel Evaluation Board Z = RoHS Compliant Part. ©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00778-9/20(G) Rev. G | Page 32 of 32 Package Option N-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 N-8 R-8 R-8 R-8 Marking Code J0A J0A J0A