AD633JRZ

Low Cost Analog Multiplier AD633 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM X1 4-quadrant multiplication Low cost, 8-lead SOIC and PDIP packages Complete—no external components required Laser-trimmed accuracy and stability Total error within 2% of full scale Differential high impedance X and Y inputs High impedance unity-gain summing input Laser-trimmed 10 V scaling reference 1 X2 A 1 10V Z 1 00786-023 Y1 W Y2 Figure 1. APPLICATIONS Multiplication, division, squaring Modulation/demodulation, phase detection Voltage-controlled amplifiers/attenuators/filters GENERAL DESCRIPTION The AD633 is a functionally complete, four-quadrant, analog multiplier. It includes high impedance, differential X and Y inputs, and a high impedance summing input (Z). The low impedance output voltage is a nominal 10 V full scale provided by a buried Zener. The AD633 is the first product to offer these features in modestly priced 8-lead PDIP and SOIC packages. The AD633 is laser calibrated to a guaranteed total accuracy of 2% of full scale. Nonlinearity for the Y input is typically less than 0.1% and noise referred to the output is typically less than 100 μV rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, 20 V/μs slew rate, and the ability to drive capacitive loads make the AD633 useful in a wide variety of applications where simplicity and cost are key concerns. The versatility of the AD633 is not compromised by its simplicity. The Z input provides access to the output buffer amplifier, enabling the user to sum the outputs of two or more multipliers, increase the multiplier gain, convert the output voltage to a current, and configure a variety of applications. Rev. J The AD633 is available in 8-lead PDIP and SOIC packages. It is specified to operate over the 0°C to 70°C commercial temperature range (J Grade) or the −40°C to +85°C industrial temperature range (A Grade). PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. The AD633 is a complete four-quadrant multiplier offered in low cost 8-lead SOIC and PDIP packages. The result is a product that is cost effective and easy to apply. No external components or expensive user calibration are required to apply the AD633. Monolithic construction and laser calibration make the device stable and reliable. High (10 MΩ) input resistances make signal source loading negligible. Power supply voltages can range from ±8 V to ±18 V. The internal scaling voltage is generated by a stable Zener diode; multiplier accuracy is essentially supply insensitive. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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This content may be frequently modified. AD633 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Multiplier Connections ................................................................9  Applications ....................................................................................... 1  Squaring and Frequency Doubling .............................................9  Functional Block Diagram .............................................................. 1  Generating Inverse Functions .....................................................9  General Description ......................................................................... 1  Variable Scale Factor .................................................................. 10  Product Highlights ........................................................................... 1  Current Output ........................................................................... 10  Revision History ............................................................................... 2  Linear Amplitude Modulator ................................................... 10  Specifications..................................................................................... 3  Voltage-Controlled, Low-Pass and High-Pass Filters............ 10  Absolute Maximum Ratings............................................................ 4  Voltage-Controlled Quadrature Oscillator................................... 11  Thermal Resistance ...................................................................... 4  Automatic Gain Control (AGC) Amplifiers ........................... 11  ESD Caution .................................................................................. 4  Evaluation Board ............................................................................ 13  Pin Configurations and Function Descriptions ........................... 5  Outline Dimensions ....................................................................... 16  Typical Performance Characteristics ............................................. 6  Ordering Guide .......................................................................... 17  Functional Description .................................................................... 8  Error Sources................................................................................. 8  Applications Information ................................................................ 9  REVISION HISTORY 8/13—Rev. I to Rev. J Reorganized Layout ............................................................ Universal Change to Table 1 ............................................................................. 3 Changes to Figure 4 .......................................................................... 6 Added Figure 10, Renumbered Sequentially ................................ 7 Changes to Figure 15 ........................................................................ 9 Changes to Figure 20 ...................................................................... 10 Changes to Figure 31 ...................................................................... 14 Added Figure 32.............................................................................. 15 2/12—Rev. H to Rev. I Changes to Figure 1 .......................................................................... 1 Changes to Figure 2 .......................................................................... 5 Changes to Generating Inverse Functions Section ...................... 8 Changes to Figure 15 ........................................................................ 9 Added Evaluation Board Section and Figure 23 to Figure 29, Renumbered Sequentially.............................................................. 12 Changes to Ordering Guide .......................................................... 15 4/10—Rev. F to Rev. G Changes to Equation 1 ......................................................................6 Changes to Equation 5 and Figure 14 .............................................7 Changes to Figure 21.........................................................................9 10/09—Rev. E to Rev. F Changes to Format ............................................................. Universal Changes to Figure 21.........................................................................9 Updated Outline Dimensions ....................................................... 11 Changes to Ordering Guide .......................................................... 12 10/02—Rev. D to Rev. E Edits to Title of 8-Lead Plastic SOIC Package (RN-8) .................1 Edits to Ordering Guide ...................................................................2 Change to Figure 13 ..........................................................................7 Updated Outline Dimensions ..........................................................8 4/11—Rev. G to Rev. H Changes to Figure 1, Deleted Figure 2 ........................................... 1 Added Figure 2, Figure 3, Table 4, Table 5 .................................... 5 Deleted Figure 9, Renumbered Subsequent Figures .................... 6 Changes to Figure 15 ........................................................................ 9 Rev. J | Page 2 of 20 Data Sheet AD633 SPECIFICATIONS TA = 25°C, VS = ±15 V, RL ≥ 2 kΩ. Table 1. Parameter TRANSFER FUNCTION MULTIPLIER PERFORMANCE Total Error TMIN to TMAX Scale Voltage Error Supply Rejection Nonlinearity, X Nonlinearity, Y X Feedthrough Y Feedthrough Output Offset Voltage 2 DYNAMICS Small Signal Bandwidth Slew Rate Settling Time to 1% OUTPUT NOISE Spectral Density Wideband Noise OUTPUT Output Voltage Swing Short Circuit Current INPUT AMPLIFIERS Signal Voltage Range Offset Voltage (X, Y) CMRR (X, Y) Bias Current (X, Y, Z) Differential Resistance POWER SUPPLY Supply Voltage Rated Performance Operating Range Supply Current 1 2 Conditions AD633J, AD633A Typ Max Min W= −10 V ≤ X, Y ≤ +10 V (X1 − X2 )(Y1 − Y2 ) 10 V ±1 ±3 ±0.25% ±0.01 ±0.4 ±0.1 ±0.3 ±0.1 ±5 SF = 10.00 V nominal VS = ±14 V to ±16 V X = ±10 V, Y = +10 V Y = ±10 V, X = +10 V Y nulled, X = ±10 V X nulled, Y = ±10 V Unit +Z ±2 1 ±11 ±0.41 ±11 ±0.41 ±501 % full scale % full scale % full scale % full scale % full scale % full scale % full scale % full scale mV VO = 0.1 V rms VO = 20 V p-p ΔVO = 20 V 1 20 2 MHz V/µs µs f = 10 Hz to 5 MHz f = 10 Hz to 10 kHz 0.8 1 90 µV/√Hz mV rms µV rms ±111 RL = 0 Ω 30 Differential Common mode ±101 ±101 VCM = ±10 V, f = 50 Hz 60 1 ±5 80 0.8 10 401 ±301 2.01 ±15 ±81 Quiescent 4 ±181 61 V mA V V mV dB µA MΩ V V mA This specification was tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed; however, only this specification was tested on all production units. Allow approximately 0.5 ms for settling following power on. Rev. J | Page 3 of 20 AD633 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Internal Power Dissipation Input Voltages 1 Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range AD633J AD633A Lead Temperature (Soldering, 60 sec) ESD Rating 1 Rating ±18 V 500 mW ±18 V Indefinite −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE 0°C to 70°C −40°C to +85°C 300°C 1000 V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage. Package Type 8-Lead PDIP 8-Lead SOIC ESD CAUTION Rev. J | Page 4 of 20 θJA 90 155 Unit °C/W °C/W Data Sheet AD633 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS X1 1 X2 2 Y1 3 A 1 10V 1 +VS Y1 7 W Y2 2 6 Z –VS 3 Z 4 8 1 8 X2 7 X1 6 +VS 5 W 1 1 1 10V A 1 4 5 –VS AD633JN/AD633AN (X1 – X2)(Y1 – Y2) +Z 10V 00786-001 W= AD633JR/AD633AR W= Figure 2. 8-Lead PDIP Table 4. 8-Lead PDIP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic X1 X2 Y1 Y2 −VS Z W +VS Description X Multiplicand Noninverting Input X Multiplicand Inverting Input Y Multiplicand Noninverting Input Y Multiplicand Inverting Input Negative Supply Rail Summing Input Product Output Positive Supply Rail (X1 – X2)(Y1 – Y2) +Z 10V 00786-002 Y2 Figure 3. 8-Lead SOIC Table 5. 8-Lead SOIC Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Rev. J | Page 5 of 20 Mnemonic Y1 Y2 −VS Z W +VS X1 X2 Description Y Multiplicand Noninverting Input Y Multiplicand Inverting Input Negative Supply Rail Summing Input Product Output Positive Supply Rail X Multiplicand Noninverting Input X Multiplicand Inverting Input AD633 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 100 0dB = 0.1V rms, RL = 2kΩ 90 CL = 1000pF 80 CL = 0.01µF CMRR (dB) –10 70 50 –20 40 00786-003 NORMAL CONNECTION 100k 1M FREQUENCY (Hz) 30 20 100 10M 1k 10k FREQUENCY (Hz) 100k 1M 10k 100k Figure 7. CMRR vs. Frequency Figure 4. Frequency Response 1.5 600 500 400 200 –60 00786-004 300 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 1.0 0.5 00786-007 NOISE SPECTRAL DENSITY (µV/ Hz) 700 BIAS CURRENT (nA) 00786-006 –30 10k 0 10 140 Figure 5. Input Bias Current vs. Temperature (X, Y, or Z Inputs) 100 1k FREQUENCY (Hz) Figure 8. Noise Spectral Density vs. Frequency 14 PEAK-TO-PEAK FEEDTHROUGH (mV) 1k 12 OUTPUT, RL ≥ 2kΩ 10 ALL INPUTS 8 6 00786-005 PEAK POSITIVE OR NEGATIVE SIGNAL (V) TYPICAL FOR X, Y INPUTS 60 4 8 10 12 14 16 18 PEAK POSITIVE OR NEGATIVE SUPPLY (V) Y-FEEDTHROUGH 100 X-FEEDTHROUGH 10 1 0.1 10 20 Figure 6. Input and Output Signal Ranges vs. Supply Voltages 00786-008 OUTPUT RESPONSE (dB) 0 100 1k 10k 100k FREQUENCY (Hz) Figure 9. AC Feedthrough vs. Frequency Rev. J | Page 6 of 20 1M 10M Data Sheet AD633 3 OUTPUT (±mV) 2 1 0 −1 −3 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (Minutes) 3.5 4.0 4.5 5.0 00786-009 −2 Figure 10. Typical VOS vs. Time, For Five Minutes Following Power Up Rev. J | Page 7 of 20 AD633 Data Sheet FUNCTIONAL DESCRIPTION The AD633 is a low cost multiplier comprising a translinear core, a buried Zener reference, and a unity-gain connected output amplifier with an accessible summing node. Figure 1 shows the functional block diagram. The differential X and Y inputs are converted to differential currents by voltage-tocurrent converters. The product of these currents is generated by the multiplying core. A buried Zener reference provides an overall scale factor of 10 V. The sum of (X × Y)/10 + Z is then applied to the output amplifier. The amplifier summing node Z allows the user to add two or more multiplier outputs, convert the output voltage to a current, and configure various analog computational functions. Inspection of the block diagram shows the overall transfer function is (X1 − X2 )(Y1 − Y2 ) 10 V +Z Multiplier errors consist primarily of input and output offsets, scale factor error, and nonlinearity in the multiplying core. The input and output offsets can be eliminated by using the optional trim of Figure 11. This scheme reduces the net error to scale factor errors (gain error) and an irreducible nonlinearity component in the multiplying core. The X and Y nonlinearities are typically 0.4% and 0.1% of full scale, respectively. Scale factor error is typically 0.25% of full scale. The high impedance Z input should always reference the ground point of the driven system, particularly if it is remote. Likewise, the differential X and Y inputs should reference their respective grounds to realize the full accuracy of the AD633. +VS (1) 300kΩ 50kΩ 1kΩ ±50mV TO APPROPRIATE INPUT TERMINAL (FOR EXAMPLE, X2, Y2, Z) –VS Figure 11. Optional Offset Trim Configuration Rev. J | Page 8 of 20 00786-010 W= ERROR SOURCES Data Sheet AD633 APPLICATIONS INFORMATION +15V The AD633 is well suited for such applications as modulation and demodulation, automatic gain control, power measurement, voltage-controlled amplifiers, and frequency doublers. These applications show the pin connections for the AD633JN (8-lead PDIP), which differs from the AD633JR (8-lead SOIC). 0.1µF R C MULTIPLIER CONNECTIONS Figure 12 shows the basic connections for multiplication. The X and Y inputs normally have their negative nodes grounded, but they are fully differential, and in many applications, the grounded inputs may be reversed (to facilitate interfacing with signals of a particular polarity while achieving some desired output polarity), or both may be driven. +15V 0.1µF Y INPUT + – X2 2 W= W 7 AD633JN + 3 Y1 Z 6 – 4 Y2 –VS 5 (X1 – X2)(Y1 – Y2) 10V +Z 00786-011 SQUARING AND FREQUENCY DOUBLING As is shown in Figure 13, squaring of an input signal, E, is achieved simply by connecting the X and Y inputs in parallel to produce an output of E2/10 V. The input can have either polarity, but the output is positive. However, the output polarity can be reversed by interchanging the X or Y inputs. The Z input can be used to add a further signal to the output. +15V X1 +VS 8 2 X2 W 7 3 Y1 Z 6 4 Y2 –VS 5 W= AD633JN 1 10 V  Y1 Z 6 4 Y2 –VS 5 –15V E sin 0 t  45 E sin 0t  45 2 2 E2 10V The amplitude of the output is only a weak function of frequency; the output amplitude is 0.5% too low at ω = 0.9 ω0 and ω0 = 1.1 ω0. GENERATING INVERSE FUNCTIONS Inverse functions of multiplication, such as division and square rooting, can be implemented by placing a multiplier in the feedback loop of an op amp. Figure 15 shows how to implement square rooting with the transfer function for the condition E < 0. E 1  cos 2 t   20 V 10kΩ 0.1µF E < 0V 10kΩ 2 7 AD711 3 2 1 sin 2 θ  2 +15V 0.1µF 0.01µF 4 (2) Equation 2 shows a dc term at the output that varies strongly with the amplitude of the input, E. This can be avoided using the connections shown in Figure 14, where an RC network is used to generate two signals whose product has no dc term. It uses the identity cos θ sin θ  (5) +15V When the input is a sine wave E sin ωt, this squarer behaves as a frequency doubler, because 10 V (4) which has no dc component. Resistors R1 and R2 are included to restore the output amplitude to 10 V for an input amplitude of 10 V. Figure 13. Connections for Squaring E sin t  R2 3kΩ W   10E V 0.1µF 2 E2 10V E2 40 V  sin 2 0 t  00786-012 1 3 W= R1 1kΩ The 1N4148 diode is required to prevent latchup, which can occur in such applications if the input were to change polarity, even momentarily. 0.1µF E W 7 AD633JN At ωo = 1/CR, the X input leads the input signal by 45° (and is attenuated by √2), and the Y input lags the X input by 45° (and is also attenuated by √2). Because the X and Y inputs are 90° out of phase, the response of the circuit is (satisfying Equation 3) W Figure 12. Basic Multiplier Connections X2 –15V  0.1µF 2 Figure 14. Bounceless Frequency Doubler OPTIONAL SUMMING INPUT, Z –15V +VS 8 0.1µF +VS 8 X1 1 X1 (3) Rev. J | Page 9 of 20 6 1 X1 +VS 8 2 X2 W 7 3 Y1 Z 6 Y2 –VS 5 AD633JN –15V 1N4148 4 0.1µF 0.1µF –15V W = √ –(10V)E Figure 15. Connections for Square Rooting 000786-014 X INPUT 1 00786-013 E AD633 Data Sheet Likewise, Figure 16 shows how to implement a divider using a multiplier in a feedback loop. The transfer function for the divider is E EX R 10kΩ 0.1µF 7 2 1 X1 +VS 8 2 X2 W 7 AD633JN 6 AD711 3 Y1 Z 6 4 Y2 –VS 5 0.1µF 3 4 0.1µF +15V W' = –10V 00786-015 –15V –15V E EX Figure 16. Connections for Division VARIABLE SCALE FACTOR In some instances, it may be desirable to use a scaling voltage other than 10 V. The connections shown in Figure 17 increase the gain of the system by the ratio (R1 + R2)/R1. This ratio is limited to 100 in practical applications. The summing input, S, can be used to add an additional signal to the output, or it can be grounded. +15V 0.1µF X INPUT + 1 X1 +VS 8 – 2 X2 W 7 W= AD633JN Y INPUT R1 + 3 Y1 Z 6 – 4 Y2 –VS 5 (X1 – X2)(Y1 – Y2) R1 + R2 +S R1 10V 1kΩ ≤ R1, R2 ≤ 100kΩ 0.1µF MODULATION + INPUT ±EM – 2 X2 W 7 W = 1+ 3 Y1 Z 6 4 Y2 –VS 5 VOLTAGE-CONTROLLED, LOW-PASS AND HIGHPASS FILTERS Figure 20 shows a single multiplier used to build a voltagecontrolled, low-pass filter. The voltage at Output A is a result of filtering ES. The break frequency is modulated by EC, the control input. The break frequency, f2, equals EC (8) 10 ( 2 π RC ) and the roll-off is 6 dB per octave. This output, which is at a high impedance point, may need to be buffered. dB f 2 f1 CURRENT OUTPUT +15V 0.1µF CONTROL INPUT EC +15V SIGNAL INPUT ES 0.1µF +VS 8 R – 2 X2 IO = W 7 AD633JN Y INPUT + 3 Y1 Z 6 – 4 Y2 –VS 5 1 R 1 X1 +VS 8 2 X2 W 7 3 Y1 Z 6 4 Y2 –VS 5 –6dB/OCTAVE OUTPUT A OUTPUT B 1 + T1P 1 + T2P 1 OUTPUT A = 1 + T2P C 1 T1 = = RC ω1 OUTPUT B = AD633JN R 0.1µF (X1 – X2)(Y1 – Y2) 10V 1kΩ ≤ R ≤ 100kΩ –15V T2 = 1 ω2 = 10RC EC Figure 20. Voltage-Controlled, Low-Pass Filter 0.1µF –15V Figure 18. Current Output Connections 00786-017 X INPUT X1 f 0 The voltage output of the AD633 can be converted to a current output by the addition of a resistor, R, between the W and Z pins of the AD633 as shown in Figure 18. 1 EC sin ωt Figure 19. Linear Amplitude Modulator Figure 17. Connections for Variable Scale Factor + EM 10V 0.1µF 0.1µF 00786-016 +VS 8 –15V f2 = –15V X1 AD633JN CARRIER INPUT EC sin ωt R2 S 1 00786-018 E The AD633 can be used as a linear amplitude modulator with no external components. Figure 19 shows the circuit. The carrier and modulation inputs to the AD633 are multiplied to produce a double sideband signal. The carrier signal is fed forward to the Z input of the AD633 where it is summed with the double sideband signal to produce a double sideband with the carrier output. +15V 0.1µF EX (7) LINEAR AMPLITUDE MODULATOR +15V R 10kΩ 1 ( X1 − X2 )(Y1 − Y2 ) R 10 V IO = (6) 00786-019 W ′ = − (10 V ) This arrangement forms the basis of voltage-controlled integrators and oscillators as is shown later in this section. The transfer function of this circuit has the form The voltage at Output B, the direct output of the AD633, has the same response up to frequency f1, the natural breakpoint of RC filter, and then levels off to a constant attenuation of f1/f2 = 10/EC f1 = Rev. J | Page 10 of 20 1 2 π RC (9) Data Sheet AD633 For example, if R = 8 kΩ and C = 0.002 µF, then Output A has a pole at frequencies from 100 Hz to 10 kHz for EC ranging from 100 mV to 10 V. Output B has an additional 0 at 10 kHz (and can be loaded because it is the low impedance output of the multiplier). The circuit can be changed to a high-pass filter Z interchanging the resistor and capacitor as shown in Figure 21. dB f1 f2 f 0 +15V 0.1µF SIGNAL INPUT ES 1 X1 +VS 8 2 X2 W 7 3 Y1 Z 6 4 Y2 –VS 5 AUTOMATIC GAIN CONTROL (AGC) AMPLIFIERS OUTPUT B AD633JN C OUTPUT A R 00786-020 0.1µF –15V Figure 21. Voltage-Controlled, High-Pass Filter VOLTAGE-CONTROLLED QUADRATURE OSCILLATOR Figure 22 shows two multipliers being used to form integrators with controllable time constants in second-order differential equation feedback loop. R2 and R5 provide controlled current output operation. The currents are integrated in capacitors C1 and C2, and the resulting voltages at high impedance are applied to the X inputs of the next AD633. The frequency control input, Figure 23 shows an AGC circuit that uses an rms-to-dc converter to measure the amplitude of the output waveform. The AD633 and A1, ½ of an AD712 dual op amp, form a voltage-controlled amplifier. The rms-to-dc converter, an AD736, measures the rms value of the output signal. Its output drives A2, an integrator/comparator whose output controls the gain of the voltage-controlled amplifier. The 1N4148 diode prevents the output of A2 from going negative. R8, a 50 kΩ variable resistor, sets the output level of the circuit. Feedback around the loop forces the voltages at the inverting and noninverting inputs of A2 to be equal, thus the AGC. D5 1N5236 D1 1N914 D3 1N914 (10V) cos ωt D2 1N914 D4 1N914 +15V 0.1µF R1 1kΩ 1 X1 +VS 8 2 X2 W 7 R4 16kΩ 0.1µF R2 16kΩ AD633JN EC C2 0.01µF +15V 3 4 Y1 Y2 Z 6 C1 0.01µF –VS 5 1 X1 +VS 8 2 X2 W 7 R3 330kΩ R5 16kΩ AD633JN 3 Y1 Z 6 4 Y2 –VS 5 0.1µF 0.1µF (10V) sin ωt C3 0.01µF –15V –15V Figure 22. Voltage-Controlled Quadrature Oscillator Rev. J | Page 11 of 20 f= EC 10V = kHz 00786-021 CONTROL INPUT EC OUTPUT B +6dB/OCTAVE OUTPUT A EC, connected to the Y inputs, varies the integrator gains with a calibration of 100 Hz/V. The accuracy is limited by the Y input offsets. The practical tuning range of this circuit is 100:1. C2 (proportional to C1 and C3), R3, and R4 provide regenerative feedback to start and maintain oscillation. The diode bridge, D1 through D4 (1N914s), and Zener diode D5 provide economical temperature stabilization and amplitude stabilization at ±8.5 V by degenerative damping. The output from the second integrator (10 V sin ωt) has the lowest distortion. AD633 Data Sheet R2 1kΩ R3 10kΩ R4 10kΩ AGC THRESHOLD ADJUSTMENT +15V 0.1µF +15V 0.1µF 1 X1 +VS 8 2 X2 W 7 3 Y1 Z 6 4 Y2 –VS 5 C1 1µF 8 1/2 AD712 1 R5 10kΩ 3 AD633JN E 2 A1 R6 1kΩ 0.1µF –15V C2 0.02µF C3 0.2µF 1 CC COMMON 8 2 VIN +VS 7 3 CF OUTPUT 6 4 –VS +15V 0.1µF AD736 0.1µF R10 10kΩ CAV 5 –15V C4 33µF A2 6 1N4148 7 1/2 AD712 4 +15V R8 50kΩ 5 0.1µF OUTPUT LEVEL ADJUST 00786-022 R9 10kΩ EOUT –15V Figure 23. Connections for Use in Automatic Gain Control Circuit Rev. J | Page 12 of 20 Data Sheet AD633 EVALUATION BOARD 00786-026 The evaluation board of the AD633 enables simple bench-top experimenting to be performed with easy control of the AD633. Built-in flexibility allows convenient configuration to accommodate most operating configurations. Figure 24 is a photograph of the AD633 evaluation board. 00786-024 Figure 25. Component Side Copper Figure 24. AD633 Evaluation Board Referring to the schematic in Figure 31, inputs to the multiplier are differential and dc-coupled. Three-position slide switches enhance flexibility by enabling the multiplier inputs to be connected to an active signal source, to ground, or to a test loop connected directly to the device pin for direct measurements, such as bias current. Inputs may be connected single ended or differentially, but must have a dc path to ground for bias current. If an input source’s impedance is non-zero, an equal value impedance must be connected to the opposite polarity input to avoid introducing additional offset voltage. 00786-027 Any dual-polarity power supply capable of providing 10 mA or greater is all that is required, in addition to whatever test equipment the user wishes to perform the intended tests. Figure 26. Circuit Side Copper The AD633-EVALZ can be configured for multiplier or divider operation by switch S1. Refer to Figure 16 for divider circuit connections. 00786-028 Figure 25 through Figure 28 are the signal, power, and groundplane artworks, and Figure 29 shows the component and circuit side silkscreen. Figure 30 shows the assembly. Figure 27. Inner Layer Ground Plane Rev. J | Page 13 of 20 Data Sheet 00786-031 00786-029 AD633 Figure 28. Inner Layer Power Plane 00786-030 Figure 30. AD633-EVALZ Assembly Figure 29. Component Side Silk Screen GND +V C5 10µF 25V + + Y1_IN D IN SEL_Y1 G2 G3 G4 G5 G6 C6 10µF 25V −V +V GND G1 −V X2_TP X2_IN IN FUNCT(1) SEL_X2 GND M Y1_TP Y2_IN Y2_TP IN SEL_Y2 GND 1 2 TEST 3 –VS C1 0.1µF Z_IN 4 TEST AD633ARZ Y1 DUT1 X2 Y2 –VS Z X1_IN (DENOM) X1_TP X1 +VS W IN 8 SELX1 7 TEST 6 +V X2_IN +V 5 C2 0.1µF Y2_TP D IN 3 R2 10kΩ SEL_Y2 GND R1 100Ω GND FUNCT(2) 7 FUNCTION SWITCH – S1 MULTIPLY: [(X1-X2)(Y1-Y2)/10V] + Z 4 R3 10kΩ NOM_TP 6 Z2 2 AD711 – M TEST C3 0.1µF + C4 0.1µF DIVIDE: −10V (NUM/DENOM) −V NUMERATOR D S1 M OUT_TP Figure 31. Schematic of the AD633 Evaluation Board Rev. J | Page 14 of 20 OUT 00786-032 TEST Data Sheet AD633 POWER SUPPLY X INPUT DC VOLTAGE Y INPUT DC VOLTAGE 00786-033 OUT – DMM Figure 32. AD633-EVALZ Configured for Bench Experiments Rev. J | Page 15 of 20 AD633 Data Sheet OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070606-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 33. 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 34. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. J | Page 16 of 20 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Data Sheet AD633 ORDERING GUIDE Model 1 AD633ANZ AD633ARZ AD633ARZ-R7 AD633ARZ-RL AD633JN AD633JNZ AD633JR AD633JR-REEL AD633JR-REEL7 AD633JRZ AD633JRZ-R7 AD633JRZ-RL AD633-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Package Description 8-Lead Plastic Dual-in-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel 8-Lead Plastic Dual-in-Line Package [PDIP] 8-Lead Plastic Dual-in-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel Evaluation Board Z = RoHS Compliant Part. Rev. J | Page 17 of 20 Package Option N-8 R-8 R-8 R-8 N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 AD633 Data Sheet NOTES Rev. J | Page 18 of 20 Data Sheet AD633 NOTES Rev. J | Page 19 of 20 AD633 Data Sheet NOTES ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00786-0-9/13(J) Rev. J | Page 20 of 20