AD647S

a FEATURES Low Offset Voltage Drift Matched Offset Voltage Matched Offset Voltage Over Temperature Matched Bias Currents Crosstalk: –124 dB at 1 kHz Low Bias Current: 35 pA max Warmed Up Low Offset Voltage: 250 V max Low Input Voltage Noise: 2 V p-p High Open Loop Gain: 108 dB Low Quiescent Current: 2.8 mA max Low Total Harmonic Distortion Standard Dual Amplifier Pinout Available in Hermetic Metal Can Package, Hermetic Surface Mount (20-Pin LCC) and Chip Form MIL-STD-883B Processing Also Available Single Version Available: AD547 Ultralow Drift, Dual BiFET Op Amp AD647 PRODUCT DESCRIPTION The AD647 is an ultralow drift, dual JFET amplifier that combines high performance and convenience in a single package. The AD647 uses the most advanced ion-implantation and laser wafer drift trimming technologies to achieve the highest performance currently available in a dual JFET. Ion-implantation permits the fabrication of matched JFETs on a monolithic bipolar chip. Laser wafer drift trimming trims both the initial offset voltage and its drift with temperature to provide offsets as low as 100 µV (250 µV max) and drifts of 2.5 µV/°C max. In addition to outstanding individual amplifier performance, the AD647 offers guaranteed and tested matching performance on critical parameters such as offset voltage, offset voltage drift and bias currents. The high level of performance makes the AD647 especially well suited for high precision instrumentation amplifier applications that previously would have required the costly selection and matching of space wasting single amplifiers. The AD647 is offered in four performance grades, three commercial (the J, K and L) and one extended (the S). All are supplied in hermetically sealed 8-pin TO-99 packages and are available processed to MIL-STD-883B. The LCC version is also available processed to MIL-STD-883B. R EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PRODUCT HIGHLIGHTS 1. The AD647 is guaranteed and tested to tight matching specifications to ensure high performance and to eliminate the selection and matching of single devices. 2. Laser wafer drift trimming reduces offset voltage and offset voltage drifts to 250 µV and 2.5 µV/°C max. 3. Voltage noise is guaranteed at 4 µV p-p max (0.1 Hz to 10 Hz) on K, L and S grades. 4. Bias current (35 pA K, L, S; 75 pA J) is specified after five minutes of operation. 5. Total supply current is a low 2.8 mA max. 6. High open loop gain ensures high linearity in precision instrumentation amplifier applications. 7. The standard dual amplifier pinout permits the direct substitution of the AD647 for lower performance devices. 8. The AD647 is available in chip form. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD647–SPECIFICATIONS (@ +25 C and V = S 15 V dc) Max Min 250,000 250,000 AD647L Typ Max Min 250,000 100,000 ± 12 ± 13 25 1.0 50 3.0 0.25 2.5 100 10 2 35 10 2 10 12 ± 12 ± 13 25 1.0 50 3.0 0.5 5.0 100 35 AD647S Typ Max Units V/V V/V V V mA MHz kHz V/µs mV µV/°C µV/V pA pA mV µV/°C pA dB M Ω pF M Ω pF V V dB 4 70 45 30 25 ± 15 µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz V V mA °C °C Model Min OPEN LOOP GAIN VO = ± 10 V, RL ≥ 2 kΩ TMIN to TMAX, RL = 2 kΩ OUTPUT CHARACTERISTICS Voltage @ R L = 2 kΩ, TMIN to TMAX Voltage @ RL = 10 kΩ, TMIN to TMAX Short Circuit Current FREQUENCY RESPONSE Unity Gain Small Signal Full Power Response Slew Rate, Unity Gain INPUT OFFSET VOLTAGE 1 Initial Offset Input Offset Voltage vs. Temperature Input Offset Voltage vs. Supply, TMIN to TMAX INPUT BIAS CURRENT 2 Either Input Offset Current MATCHING CHARACTERISTICS 3 Input Offset Voltage Input Offset Voltage T MIN to TMAX Input Bias Current Crosstalk INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE RANGE Differential 4 Common Mode Common-Mode Rejection INPUT NOISE Voltage 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz POWER SUPPLY Rated Performance Operating Quiescent Current TEMPERATURE RANGE Operating, Rated Performance Storage PACKAGE OPTION TO-99 Style (H-08B) LCC (E-20A) 100,000 100,000 10 12 AD647J Typ Max Min 250,000 250,000 AD647K Typ ± 12 ± 13 25 1.0 50 3.0 1.0 10 200 10 5 75 10 12 ± 12 ± 13 25 1.0 50 3.0 0.5 5 100 10 2 35 10 12 2.0 2.0 2.0 2.0 1.0 10 35 –124 1012 6 1012 6 ± 20 ± 12 –124 1012 6 1012 6 ± 20 ± 12 0.5 5 25 –124 1012 6 1012 6 ± 20 ± 12 0.25 2.5 25 –124 1012 6 1012 6 ± 20 ± 12 0.5 10.0 25 10 76 10 80 10 80 4 10 80 4 2 70 45 30 25 ± 15 70 45 30 25 ± 15 70 45 30 25 ± 15 ±5 ± 18 2.8 +70 +150 ±5 ± 18 2.8 +70 +150 ±5 ± 18 2.8 +70 +150 ±5 ± 18 2.8 +125 +150 0 –65 AD647JH 0 –65 AD647KH 0 –65 AD647LH –55 –65 AD647SH AD647SE AD647SE/883BH NOTES 1 Input Offset Voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C. 2 Bias Current specifications are guaranteed at maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperatures, the current doubles every 10°C. 3 Matching is defined as the difference between parameters of the two amplifiers. 4 Defined as the maximum safe voltage between inputs, such that neither exceeds ± 10 V from ground. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. Specifications subject to change without notice. METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). Contact factory for latest dimensions. –2– REV. A Typical Characteristics–AD647 REV. A –3– AD647 –4– REV. A AD647 APPLICATION NOTES THE AD647 USED WITH THE AD7546 The AD647 is fully specified under actual operating conditions to insure high performance in any application, but there are some steps that will improve on even this high level of performance. The bias current of a JFET amplifier doubles with every 10°C increase in junction temperature. Any heat source that can be eliminated or minimized will significantly improve bias current performance. To account for normal power dissipation, the largest contributor to chip self-heating, the bias currents of the AD647 are guaranteed fully warmed up with ± 15 V supplies. A decrease in supply voltage will decrease power consumption, resulting in a corresponding drop in bias currents. Open loop gain and bias currents, to some extent, are affected by output loading. In applications where high linearity is essential, load impedance should be kept as high as possible to minimize degradation of open loop gain. The outstanding ac and dc performance of the AD647 make it an ideal choice for critical instrumentation applications. In such applications, leakage paths, line losses and external noise sources should be considered in the layout of printed circuit boards. A guard ring surrounding the inputs and connected to a low impedance potential (at the same level as the inputs) should be placed on both sides of the circuit board. This will eliminate leakage paths that could degrade bias current performance. All signal paths should be shielded to minimize noise pickup. Figure 24 shows the AD647 used with the AD7546 16-bit segment DAC. In this application, amplifier performance is critical to the overall performance of the AD7546. A1 is used as a dual precision buffer. Here the offset voltage match, low offset voltage and high open loop gain of the AD647 ensure monotonicity and high linearity over the entire operating temperature range. A2 serves a dual function amplifier A is a Track and Hold circuit that deglitches the DAC output and amplifier B acts as an output amplifier. The performance of the amplifiers of A2 is crucial to the accuracy of the system. The errors of these amplifiers are added to the errors due strictly to DAC imperfections. For this reason great care should be used in the selection of these amplifiers. The matching characteristics, low bias current and low temperature coefficients of the AD647 make it ideal for this application. Figure 24. AD647 Used with AD7546 16-Bit DAC USING THE AD647 IN LOG AMPLIFIER APPLICATIONS Figure 23. AD647 Used as DAC Output Amplifier A CMOS DAC AMPLIFIER Log amplifiers or log ratio amplifiers are useful in a wide range of analog computational applications, ranging from the simple linearization of exponential transducer outputs to the use of logarithms in computations involving multi-term products or arbitrary exponents. Log amps also facilitate the compression of wide ranging analog input signals into a range that can be easily handled using standard circuit techniques. The output impedance of a CMOS DAC, such as the AD7541, varies with digital input code. This causes a corresponding variation in the noise gain of the DAC-amplifier combination. This noise gain modulation introduces a nonlinearity whose magnitude is dependent on the amount of offset voltage present. Laser wafer drift trimming lowers the initial offset voltage and the offset voltage drift of the AD647, therefore minimizing the effect of this nonlinearity and its drift with temperature. This, in conjunction with the low bias current and high open loop gain, makes the AD647 ideal for DAC output amplifier applications. Figure 25. Log-Ratio Amplifier REV. A –5– AD647 The picoamp level input current and low offset voltage of the AD647 make it suitable for wide dynamic range log amplifiers. Figure 25 is a schematic of a log ratio circuit employing the AD647 that can achieve less than 1% conformance error over 5 decades of current input, 1 nA to 100 µA. For voltage inputs, the dynamic range is typically 50 mV to 10 V for 1% error, limited on the low end by the amplifiers’ input offset voltage. The conversion between current (or voltage) input and log output is accomplished by the base-emitter junctions of the dual transistor Q1. Assuming Q1 has β > 100, which is the case for the specified transistor, the base-emitter voltage on side 1 is to a close approximation VBE A = kT/q ln I1/IS1 This circuit is arranged to take the difference of the VBEs of Q1A and Q1B, thus producing an output voltage proportional to the log of the ratio of the inputs VOUT = –K (VBE A – VBE B ) = KkT q (ln I1/IS1 –ln I2/IS2) cuits. DC error sources such as offset voltage and bias currents represent the largest individual contributors to output error. Offset voltages will be passed by the filtering network and may, depending on the design of the filter circuit, be amplified and generate unacceptable output offset voltages. In filter circuits for low frequency ranges large value resistors are used to generate the low-pass filter function. Input bias currents passing through these resistors will generate an additional offset voltage that will also be passed to the output of the filter. The use of the AD647 will minimize these error sources and, therefore, maximize filter accuracy. The wide variety of performance levels of the AD647 allows for just the amount of accuracy required for any given application. AD647 AS AN INSTRUMENTATION AMPLIFIER The circuit shown in Figure 26 uses the AD647 to construct an ultra high precision instrumentation amplifier. In this type of application the matching characteristics of a monolithic dual amplifier are crucial to ensure high performance. VOUT = –K kT/q ln Il /I2 The scaling constant, K is set by R1 and RTC to about 16, to produce a 1 V change in output voltage per decade difference in input signals. RTC is a special resistor with a +3500 ppm/°C temperature coefficient, which makes K inversely proportional to temperature, compensating for the “T” in kT/q. The log ratio transfer characteristic is therefore independent of temperature. This particular log ratio circuit is free from the dynamic problems that plague many other log circuits. The –3 dB bandwidth is 50 kHz over the top 3 decades, 100 nA to 100 µA, and decreases smoothly at lower input levels. This circuit needs no additional frequency compensation for stable operation from input current sources, such as photodiodes, which may have 100 pF of shunt capacitance. For larger input capacitances a 20 pF integration capacitor around each amplifier will provide a smoother frequency response. This log ratio amplifier can be readily adjusted for optimum accuracy by following this simple procedure. First, apply V1 = V2 = –10.00 V and adjust “Balance” for VOUT = 0.00 V. Next apply V1 = –10.00 V, V2 = –100 V and adjust gain for VOUT = +1.00 V. Repeat this procedure until gain and balance readings are within 2 mV of ideal values. ACTIVE FILTERS Figure 26. Precision FET Input Instrumentation Amplifier OUTLINE DIMENSIONS Dimensions shown in inches and (mm). TO-99 E-20A –6– REV. A PRINTED IN U.S.A. In active low-pass filtering applications the dc accuracy of the amplifiers used is critical to the performance of the filter cir- The use of an AD647L as the input amplifier A1, guarantees maximum offset voltage of 250 µV, drift of 2.5 µV/°C and bias currents of 35 pA. A2 serves two less critical functions in the amplifier and, therefore can be an AD647J. Amplifier A is an active data guard which increases ac CMRR and minimizes extraneous signal pickup and leakage. Amplifier B is the output amplifier of the instrumentation amplifier. To attain the precision available from this configuration, a great deal of care should be taken when selecting the external components. CMRR will depend on the matching of resistors R1, R2, R3, and R4. The gain drift performance of this circuit will be affected by the matching TC of the resistors used. C683a–3–2/84