AD6620AS

a FEATURES High Input Sample Rate 65 MSPS Single Channel Real 32.5 MSPS Diversity Channel Real 32.5 MSPS Single Channel Complex NCO Frequency Translation Worst Spur Better than –100 dBc Tuning Resolution Better than 0.02 Hz 2nd Order Cascaded Integrator Comb FIR Filter Linear Phase, Fixed Coefficients Programmable Decimation Rates: 2, 3 . . . 16 5th Order Cascaded Integrator Comb FIR Filter Linear Phase, Fixed Coefficients Programmable Decimation Rates: 1, 2, 3 . . . 32 Programmable Decimating RAM Coefficient FIR Filter Up to 130 Million Taps per Second 256 20-Bit Programmable Coefficients Programmable Decimation Rates: 1, 2, 3 . . . 32 Bidirectional Synchronization Circuitry Phase Aligns NCOs Synchronizes Data Output Clocks Serial or Parallel Baseband Outputs Pin Selectable Serial or Parallel Serial Works with SHARC, ADSP-21xx, Most Other DSPs 16-Bit Parallel Port, Interleaved I and Q Outputs Two Separate Control and Configuration Ports Generic P Port, Serial Port 3.3 V Optimized CMOS Process JTAG Boundary Scan GENERAL DESCRIPTION REAL, DUAL REAL, OR COMPLEX INPUTS 65 MSPS Digital Receive Signal Processor AD6620 FUNCTIONAL BLOCK DIAGRAM I CIC FILTERS I FIR FILTER I OUTPUT FORMAT SERIAL OR PARALLEL OUTPUTS Q COS –SIN Q Q COMPLEX NCO EXTERNAL SYNC CIRCUITRY JTAG PORT P OR SERIAL CONTROL both narrowband and wideband carriers to be extracted. The RAM-based architecture allows easy reconfiguration for multimode applications. The decimating filters remove unwanted signals and noise from the channel of interest. When the channel of interest occupies less bandwidth than the input signal, this rejection of out-ofband noise is called “processing gain.” By using large decimation factors, this “processing gain” can improve the SNR of the ADC by 36 dB or more. In addition, the programmable RAM Coefficient filter allows antialiasing, matched filtering, and static equalization functions to be combined in a single, costeffective filter. The input port accepts a 16-bit Mantissa, a 3-bit Exponent, and an A/B Select pin. These allow direct interfacing with the AD6600, AD6640, AD9042 and most other high speed ADCs. Three input modes are provided: Single Channel Real, Single Channel Complex, and Diversity Channel Real. When paired with an interleaved sampler such as the AD6600, the AD6620 can process two data streams in the Diversity Channel Real input mode. Each channel is processed with coherent frequency translation and output sample clocks. In addition, external synchronization pins are provided to facilitate coherent frequency translation and output sample clocks among several AD6620s. These features can ease the design of systems with diversity antennas or antenna arrays. Units are packaged in an 80-lead PQFP (plastic quad flatpack) and specified to operate over the industrial temperature range (–40°C to +85°C). The AD6620 is a digital receiver with four cascaded signalprocessing elements: a frequency translator, two fixedcoefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compatible. As ADCs achieve higher sampling rates and dynamic range, it becomes increasingly attractive to accomplish the final IF stage of a receiver in the digital domain. Digital IF Processing is less expensive, easier to manufacture, more accurate, and more flexible than a comparable highly selective analog stage. The AD6620 diversity channel decimating receiver is designed to bridge the gap between high speed ADCs and general purpose DSPs. The high resolution NCO allows a single carrier to be selected from a high speed data stream. High dynamic range decimation filters with a wide range of decimation rates allow R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD6620 TABLE OF CONTENTS ARCHITECTURE GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SPECIFICATIONS/TIMING . . . . . . . . . . . . . . . . . . . . . . . 4 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 11 EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 11 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12 PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 13 INPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 FREQUENCY TRANSLATOR . . . . . . . . . . . . . . . . . . . . . 20 2ND ORDER CASCADED INTEGRATOR COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5TH ORDER CASCADED INTEGRATOR COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . 25 CONTROL REGISTERS AND ON-CHIP RAM . . . . . . . 27 PROGRAMMING THE AD6620 . . . . . . . . . . . . . . . . . . . 29 MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 31 SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 34 JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . 36 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 43 As shown in Figure 1, the AD6620 has four main signal processing stages: a Frequency Translator, two Cascaded Integrator Comb FIR Filters (CIC2, CIC5), and a RAM Coefficient FIR Filter (RCF). Multiple modes are supported for clocking data into and out of the chip. Programming and control is accomplished via serial and microprocessor interfaces. Input data to the chip may be real or complex. If the input data is real, it may be clocked in as a single channel or interleaved with a second channel. The two-channel input mode, called Diversity Channel Real, is typically used in diversity receiver applications. Input data is clocked in 16-bit parallel words, IN[15:0]. This word may be combined with exponent input bits EXP[2:0] when the AD6620 is being driven by floating-point or gain-ranging analog-to-digital converters such as the AD6600. Frequency translation is accomplished with a 32-bit complex Numerically Controlled Oscillator (NCO). Real data entering this stage is separated into in-phase (I) and quadrature (Q) components. This stage translates the input signal from a digital intermediate frequency (IF) to baseband. Phase and amplitude dither may be enabled on-chip to improve spurious performance of the NCO. A phase offset word is available to create a known phase relationship between multiple AD6620s. Following frequency translation is a fixed coefficient, high speed decimating filter that reduces the sample rate by a programmable ratio between 2 and 16. This is a second order, cascaded integrator comb FIR filter shown as CIC2 in Figure 1. (Note: Decimation of 1 in CIC2 requires 2× or greater clock into AD6620). The data rate into this stage equals the input data rate, fSAMP. The data rate out of CIC2, fSAMP2, is determined by the decimation factor, MCIC2. RCF EXP[2:0] IN[15:0] 3 16 INPUT DATA INTERLEAVE DEINTERLEAVE CIC5 MCICS fSAMP5 23 23 fSAMP2 OUTPUT SCALING, SOUT MULTIPLEXER I-RAM 256 20 C-RAM 256 20 Q-RAM 256 20 MRCF FREQUENCY 3 TRANSLATOR I 18 16 Q 18 EXP SCALING SCALING CIC2 MCICS MULTIPLEXER SCALING COMPLEX NCO DVOUT I/QOUT MULTIPLEXER A/BOUT EXPLNV, EXPOFF PHASE OFFSET CLK A/B RESET TIMING SYNC NCO SYNC CIC SYNC RCF SYNC I/O RCF COEFFICIENTS NUMBER OF TAPS DECIMATE FACTOR CIC2, CIC5 DECIMATE FACTORS ADDRESS OFFSET fSAMP SCALE FACTORS OUTPUT NCO FREQUENCY SCALE PHASE OFFSET FACTOR DITHER SYNC MASK CONTROL REGISTERS INPUT MODE MICROPORT AND REAL, DUAL, COMPLEX SERIAL ACCESS FIXED OR WITH EXPONENT SYNC M/S PARALLEL 16 SERIAL JTAG TRST TCK TMS TDI TDO MICROPROCESSOR INTERFACE D[7:0] A[2:0] CS R/W DS DTACK (W/R) (R/D) (RDY) MODE PAR/SER PARALLEL OUTPUTS AND SERIAL I/O 16 OUT[15:0] SCLK SDI SDO SDFS SDFE SBM WL[1:0] AD SDIV[3:0] Figure 1. Block Diagram –2– REV. 0 AD6620 Following CIC2 is the second fixed-coefficient decimating filter. This filter, CIC5, further reduces the sample rate by a programmable ratio from 1 to 32. The data rate out of CIC5, fSAMP5, is determined by the decimation factors of MCIC5 and MCIC2. Each CIC stage is a FIR filter whose response is defined by the decimation rate. The purpose of these filters is to reduce the data rate of the incoming signal so that the final filter stage, a FIR RAM coefficient sum-of-products filter (RCF), can calculate more taps per output. As shown in Figure 1, on-chip multiplexers allow both CIC filters to be bypassed if a multirate clock is used. The fourth stage is a sum-of-products FIR filter with programmable 20-bit coefficients, and decimation rates programmable from 1 to 32. The RAM Coefficient FIR Filter (RCF in Figure 1) can handle a maximum of 256 taps. The overall filter response for the AD6620 is the composite of all three cascaded decimating filters: CIC2, CIC5, and RCF. Each successive filter stage is capable of narrower transition bandwidths but requires a greater number of CLK cycles to calculate the output. More decimation in the first filter stage will minimize overall power consumption. Data comes out via a parallel port or a serial interface. Figure 2 illustrates the basic function of the AD6620: to select and filter a single channel from a wide input spectrum. The frequency translator “tunes” the desired carrier to baseband. CIC2 and CIC5 have fixed order responses; the RCF filter provides the sharp transitions. More detail is provided in later sections of the data sheet. WIDEBAND INPUT SPECTRUM C' D' SIGNAL OF INTEREST "IMAGE" B' A' A (–fsamp/2 TO fsamp/2) SIGNAL OF INTEREST C D B –fS /2 –3fS /8 –5fS /16 –fS /4 –3fS /16 –fS /8 –fS /16 DC fS /16 fS /8 3fS /16 fS /4 5fS /16 3fS /8 fS /2 Figure 2a. Wideband Input Spectrum (e.g., 30 MHz from High Speed ADC) NCO "TUNES" SIGNAL TO BASEBAND AFTER FREQUENCY TRANSLATION A B C D D' C' B' A' –fS /2 –3fS /8 –5fS /16 –fS /4 –3fS /16 –fS /8 –fS /16 DC fS /16 fS /8 3fS /16 fS /4 5fS /16 3fS /8 fS /2 Figure 2b. Frequency Translation (e.g. Single 1 MHz Channel Tuned to Baseband) CIC2, CIC5, AND RCF 0 –10 –20 –30 –40 –50 dBc –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY Figure 2c. Baseband Signal is Decimated and Filtered by CIC2, CIC5, RCF REV. 0 –3– AD6620–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter VDD TAMBIENT Test Level I IV Min 3.0 –40 AD6620AS Typ 3.3 +25 Max 3.6 +85 Units V °C ELECTRICAL CHARACTERISTICS Parameter (Conditions) LOGIC INPUTS Logic Compatibility Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance 1, 2, 3, 4, 5, 6, 7 Temp (NOT 5 V TOLERANT) Full Full Full Full Full +25°C Full Full Full Full Full Full Full Full Full Test Level Min AD6620AS Typ 3.3 V CMOS Max Units I I I I V 2.0 –0.3 1 1 4 VDD + 0.3 0.8 10 10 V V µA µA pF LOGIC OUTPUTS2, 4, 7, 8, 9, 10, 11 Logic Compatibility Logic “1” Voltage (IOH = 0.5 mA) Logic “0” Voltage (IOL = 1.0 mA) IDD SUPPLY CURRENT CLK = 20 MHz12 CLK = 65 MHz13 Reset Mode14 POWER DISSIPATION CLK = 20 MHz12 CLK = 65 MHz13 Reset Mode14 I I V I I V I I 2.4 3.3 V CMOS/TTL VDD – 0.2 0.2 0.4 52 167 V V mA mA mA mW mW mW 227 1 170 550 750 3.3 NOTES 1 Input-Only Pins: CLK, RESET, IN[15:0], EXP[2:0], A/B, PAR/SEL. 2 Bidirectional Pins: SYNC_NCO, SYNC_CIC, SYNC_RCF. 3 Microinterface Input Pins: DS (RD), R/W (WR), CS. 4 Microinterface Bidirectional Pins: A[2:0], D[7:0]. 5 JTAG Input Pins: TRST, TCK, TMS, TDI. 6 Serial Mode Input Pins: SDI, SBM, WL[1:0], AD, SDIV[3:0]. 7 Serial Mode Bidirectional Pins: SCLK, SDFS. 8 Output Pins: OUT[15:0], DV OUT, A/BOUT, I/QOUT. 9 Microinterface Output Pins: DTACK (RDY). 10 JTAG Output Pins: TDO. 11 Serial Mode Output Pins: SDO, SDFE. 12 Conditions for IDD @ 20 MHz. M CIC2 = 2, MCIC5 = 2, MRCF = 1, 4 RCF taps of alternating positive and negative full scale. 13 Conditions for IDD @ 65 MHz. M CIC2 = 2, MCIC5 = 2, MRCF = 1, 4 RCF taps of alternating positive and negative full scale. 14 Conditions for IDD in Reset ( RESET = 0). Specifications subject to change without notice. – 4– REV. 0 AD6620 TIMING CHARACTERISTICS (C Parameter (Conditions) CLK Timing Requirements: tCLK CLK Period CLK Width Low tCLKL tCLKH CLK Width High Reset Timing Requirements: tRESL RESET Width Low Input Data Timing Requirements: tSI Input1 to CLK Setup Time tHI Input1 to CLK Hold Time Parallel Output Switching Characteristics: tDPR CLK to OUT[15:0] Rise Delay CLK to OUT[15:0] Fall Delay tDPF tDPR CLK to DVOUT Rise Delay tDPF CLK to DVOUT Fall Delay CLK to IQOUT Rise Delay tDPR tDPF CLK to IQOUT Fall Delay tDPR CLK to ABOUT Rise Delay tDPF CLK to ABOUT Fall Delay SYNC Timing Requirements: tSY SYNC2 to CLK Setup Time tHY SYNC2 to CLK Hold Time SYNC Switching Characteristics: tDY CLK to SYNC3 Delay Time Serial Input Timing: tSSI SDI to SCLKt Setup Time SDI to SCLKt Hold Time tHSI tHSRF SDFS to SCLKu Hold Time tSSF SDFS to SCLKt Setup Time4 tHSF SDFS to SCLKt Hold Time4 Serial Frame Output Timing: tDSE SCLKu to SDFE Delay Time tSDFEH SDFE Width High tDSO SCLKu to SDO Delay Time SCLK Switching Characteristics, SBM = “1”: tSCLK SCLK Period3 tSCLKL SCLK Width Low tSCLKH SCLK Width High tSCLKD CLK to SCLK Delay Time Serial Frame Timing, SBM = “1”: tDSF SCLKu to SDFS Delay Time tSDFSH SDFS Width High SCLK Timing Requirements, SBM = “0”: tSCLK SCLK Period tSCLKL SCLK Width Low tSCLKH SCLK Width High LOAD = 40 pF All Outputs) Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level I IV IV I IV IV IV IV IV IV IV IV IV IV IV IV V IV IV IV IV IV IV V IV I V V V IV V I IV IV Min 15.4 7.0 7.0 30.0 –1.0 6.5 8.0 7.5 6.5 5.5 7.0 6.0 7.0 5.5 –1.0 6.5 7.0 1.0 2.0 4.0 1.0 2.0 3.5 tSCLK 4.5 2 × tCLK 6.5 1.0 tSCLK 15.4 0.4 × tSCLK 0.4 × tSCLK 11.0 11.0 23.5 19.5 19.5 19.0 11.5 19.5 13.5 19.5 13.5 AD6620AS Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.5 × tCLK 0.5 × tCLK 0.5 × tSCLK 0.5 × tSCLK 13.0 4.0 0.5 × tSCLK 0.5 × tSCLK NOTES 1 Specification pertains to: IN[15:0], EXP[2:0], A/B. 2 Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF. 3 SCLK period will be ≥ 2 × tCLK when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word. 4 SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad. Specifications subject to change without notice. REV. 0 –5– AD6620 TIMING CHARACTERISTICS (C Parameter (Conditions) LOAD = 40 pF All Outputs) Temp Test Level Min AD6620AS Typ Max Units MICROPROCESSOR PORT, MODE = 0 MODE 0 Input Timing Requirements: tSC Control1 to CLK Setup Time Control1 to CLK Hold Time tHC tHA Address2 to CLK Hold Time tZR CS to Data Enabled Time CS to Data Disabled Time tZD tSAM CS to Address/Data Setup Time MODE 0 Read Switching Characteristics: CLK to Data Valid Time tDD tRDY RD to RDY Time MODE 0 Write Timing Requirements: tSC Control1 to CLK Setup Time tHC Control1 to CLK Hold Time Micro Data3 to CLK Hold Time tHM tHA Address2 to CLK Hold Time tSAM Address/Data Setup Time to CS MODE 0 Write Switching Characteristics: tRDY RD to RDY Time MICROPROCESSOR PORT, MODE = 1 MODE1 Input Timing Requirements: Control1 to CLK Setup Time tSC tHC Control1 to CLK Hold Time Address2 to CLK Hold Time tHA tZR CS to Data Enabled Time tZD CS to Data Disabled Time Address/Data Setup Time to CS tSAM MODE1 Read Switching Characteristics: tDD CLK to Data Valid Time tDTACK CLK to DTACK Time MODE1 Write Timing Requirements: Control1 to CLK Setup Time tSC tHC Control1 to CLK Hold Time tHM Micro Data3 to CLK Hold Time Address2 to CLK Hold Time tHA tSAM Address/Data Setup Time to CS MODE1 Write Switching Characteristics: tDTACK CLK to DTACK Time NOTES 1 Specification pertains to: R/W ( WR), DS (RD), CS. 2 Specification pertains to: A[2:0]. 3 Specification pertains to: D[7:0]. Specifications subject to change without notice. Full Full Full Full Full Full Full Full Full Full Full Full Full Full IV IV IV IV IV IV I IV IV IV IV IV IV IV 3.0 5.0 3.0 5.0 5.0 0.0 10.0 4.0 3.0 5.0 3.0 3.0 0.0 4.0 19.5 15.0 30.0 19.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Full Full Full Full Full Full Full Full Full Full Full Full Full Full IV IV IV IV IV IV I V IV IV IV IV IV V 3.0 5.0 3.0 5.0 5.0 0.0 10.0 5.5 0.0 5.0 6.5 3.0 0.0 5.5 15.5 30.0 15.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns –6– REV. 0 AD6620 TIMING DIAGRAMS CLK, INPUTS, PARALLEL OUTPUTS SYNC PULSES: SLAVE OR MASTER RESET with PAR/SER = “1” establishes Parallel Outputs active. t CLK t CLKH CLK t SY SYNC NCO SYNC CIC SYNC RCF t HY CLK t CLKL Figure 6. SYNC Slave Timing Requirements Figure 3. CLK Timing Requirements t DY CLK CLK t SI IN[15:0] EXP[2:0] A/B DATA t HI SYNC NCO SYNC CIC SYNC RCF Figure 7. SYNC Master Delay Figure 4. Input Data Timing Requirements t DPR t DPF t DPF RESET CLK t RESL DVOUT VALID OUTPUT DATA Figure 8. Reset Timing Requirements I/QOUT I Q I Q OUT[15:0] IA QA IB QB Figure 5. Parallel Output Switching Characteristics REV. 0 –7– AD6620 SERIAL PORT: BUS MASTER SERIAL PORT: CASCADE MODE RESET with PAR/SER = “0” establishes Serial Port active. SBM = “1” puts AD6620 in Serial Bus Master mode SCLK is output; SDFS is output. RESET with PAR/SER = “0” establishes Serial Port active. SBM = “0” puts AD6620 in Serial Port Cascade mode, SCLK is input; SDFS is input. t SCLK CLK t SCLKH t SCLKD SCLK t SCLK t SCLKH t SCLKL Figure 13. SCLK Timing Requirements SCLK t SCLKL SCLK Figure 9. SCLK Switching Characteristics t SSI t HSI SCLK SDI DATA t SSI t HSI Figure 14. Serial Input Data Timing Requirements SDI DATA SCLK Figure 10. Serial Input Data Timing Requirements t SSF t HSF t DSF SCLK t DSE SDFS Figure 15. SDFS Timing Requirements t SDFSH SDFS t SDFEH SDFE SCLK t DSO t DSE Figure 11. Serial Frame Switching Characteristics SDO I15 I14 Q1 Q0 t DSO t SDFEH SDFE SCLK Figure 16. SDO, SDFE Switching Characteristics SDO I15 I14 I13 Figure 12. Serial Output Data Switching Characteristics –8– REV. 0 AD6620 MICROPORT MODE0, READ Timing is synchronous to CLK; MODE = 0. t DD CLK1 N N+1 N+2 t HC N+3 N+4 N WR2 t SC RD2 t HC CS3 t ZD t ZR D[7:0] DATA VALID t SAM A[2:0] ADDRESS VALID t HA t RDY RDY1 t RDY NOTES: 1 RDY IS DRIVEN LOW ASYNCHRONOUSLY BY RD AND CS GOING LOW AND RETURNS HIGH ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000), CLK "N+2" OTHERWISE. 2 THE 3 SIGNAL, WR, MAY REMAIN HIGH AND RD MAY REMAIN LOW TO CONTINUE READ MODE. CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE READ. Figure 17. MODE0 Read Timing Requirements and Switching Characteristics MICROPORT MODE0, WRITE Timing is synchronous to CLK; MODE = 0. t SC CLK1 N N+1 t HC N+2 N+3 N* WR2 RD2 t SC t HC CS3 t SAM D[7:0] DATA VALID t HM t SAM A[2:0] t HA ADDRESS VALID RDY t RDY t RDY NOTES: 1 RDY IS DRIVEN LOW ASYNCHRONOUSLY BY WR AND CS GOING LOW AND RETURNS HIGH ON THE RISING EDGE OF CLK "N+2". 2 THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA. 3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE. * THE NEXT WRITE MAY BE INITIATED ON CLK, N*. Figure 18. MODE0 Write Timing Requirements and Switching Characteristics REV. 0 –9– AD6620 MICROPORT MODE1, READ Timing is synchronous to CLK; MODE = 1. t DD t HC N+3 N+4 N CLK1 N N+1 N+2 R/W2 t SC DS2 t SC CS3 t HC t ZD t ZR D[7:0] DATA VALID t SAM A[2:0] ADDRESS VALID t HA t DTACK DTACK NOTES: 1 DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000), CLK "N=2" OTHERWISE. 2 3 t DTACK THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE. CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS AND FORCE DTACK HIGH. Figure 19. MODE1 Read Timing Requirements and Switching Characteristics MICROPORT MODE1, WRITE Timing is synchronous to CLK; MODE = 1. t SC CLK1 N N+1 t HC N+2 N+3 N* R/W2 DS2 t SC CS3 t HC t SAM D[7:0] DATA VALID t HM t SAM A[2:0] ADDRESS VALID t HA t DTACK DTACK t DTACK NOTES: 1 ON RISING EDGE OF "N+3" CLK, DTACK IS DRIVEN LOW. 2 3 THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA. CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE AND FORCE DTACK HIGH. * THE NEXT WRITE MAY BE INITIATED ON CLK, N*. Figure 20. MODE1 Write Timing Requirements and Switching Characteristics –10– REV. 0 AD6620 ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.5 V Input Voltage . . . . –0.3 V to VDD + 0.3 V (Not 5 V Tolerant) Output Voltage Swing . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF Junction Temperature Under Bias . . . . . . . . . . . . . . . . +130°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280°C *Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. I. 100% Production Tested. II. 100% Production Tested at +25°C, and Sampled Tested at Specified Temperatures. III. Sample Tested Only. IV. Parameter Guaranteed by Design and Analysis. V. Parameter is Typical Value Only. VI. 100% Production Tested at +25°C, and Sampled Tested at Temperature Extremes. Thermal Characteristics 80-Lead Plastic Quad Flatpack: θJA = 44°C/Watt ORDERING GUIDE Model AD6620AS AD6620S/PCB Temperature Range –40°C to +85°C (Ambient) Package Description 80-Lead PQFP (Plastic Quad Flatpack) Evaluation Board with AD6620AS and Software Package Option S-80A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6620 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –11– AD6620 PIN FUNCTION DESCRIPTIONS Name VDD VSS CLK RESET IN[15:0] EXP[2:0] A/B SYNC_NCO SYNC_CIC SYNC_RCF MODE A[2:0] D[7.0] DS or RD R/W or WR CS DTACK or RDY PAR/SER DVOUT A/BOUT I/QOUT TRST TCK TMS TDI TDO Type P G I I I I I I/O I/O I/O I I I/O/T I I I O I O O O I I I I I Description +3.3 V Supply Ground Input Clock Active Low Reset Pin Input Data (Mantissa) Input Data (Exponent) Channel (A/B) Select Sync Signal for NCO Sync Signal for CIC Stages Sync Signal for RCF Sets Microport Mode: Mode 1, (MODE = 1), Mode 0, (MODE = 0) Microprocessor Interface Address Microprocessor Interface Data Mode 1: Data Strobe Line, Mode 0: Read Signal Read/Write Line (Write Signal) Chip Select, Enables the Chip for µP Access Acknowledgment of a Completed Transaction (Signals when µP Port Is Ready for an Access) Parallel/Serial Control Select (PAR = 1, SER = 0) Data Valid Pin for the Parallel Output Data Signals to Which Channel the Output Belongs to (A = 1, B = 0) Signals Whether I or Q Data Is Present (I = 1, Q = 0) Test Reset Pin Test Clock Input Test Mode Select Input Test Data Input Test Data Output Pin Types: I = Input, O = Output, P = Power Supply, G = Ground, T = Three-state. SHARED PINS Parallel Outputs (PAR/SER = 1 at RESET) Name OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT[6:4] OUT3 OUT2 OUT1 OUT0 Type O O O O O O O O O O O O O O Description Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data Parallel Output Data (LSB) Name SCLK SDI SDO SDFS SDFE SBM WL1 WL0 AD NC SDIV3 SDIV2 SDIV1 SDIV0 Serial Port (PAR/SER = 0 at RESET) Type I/O I O/T I/O O I I I I NC I I I I Description Serial Clock Input (SBM =0) Serial Clock Output (SBM = 1) Serial Data Input Serial Data Output Serial Data Frame Sync Input (SBM = 0) Serial Data Frame Sync Output (SBM = 1) Serial Data Frame End Serial Bus Master (Master = 1, Cascade = 0) Serial Port Word Length, Bit 1 Serial Port Word Length, Bit 0 Append Data Unused, Do Not Connect SCLK Divide Value, Bit 3 SCLK Divide Value, Bit 2 SCLK Divide Value, Bit 1 SCLK Divide Value, Bit 0 Pin Types: I = Input, O = Output, P = Power Supply, G = Ground, T = Three-state. –12– REV. 0 AD6620 PIN CONFIGURATIONS Parallel Output Data (MSB) OUT15 OUT14 VDD OUT13 OUT12 OUT11 VSS OUT10 OUT9 OUT5 OUT4 OUT8 OUT7 VDD OUT6 VSS OUT3 OUT2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 D6 1 D5 2 D4 3 VSS 4 D3 5 D2 6 D1 7 VDD 8 D0 9 DS 10 DTACK 11 R/W 12 VSS 13 MODE 14 A2 15 A1 16 A0 17 CS 18 EXP0 19 EXP1 20 OUT1 D7 PIN 1 IDENTIFIER 60 59 58 OUT0 (LSB) A/BOUT I/QOUT 57 VDD 56 DVOUT 55 54 53 PAR/SER AD6620 TOP VIEW (Not to Scale) RESET TRST 52 TCK 51 50 49 48 TMS TDO TDI VDD 47 SYNC NCO 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SYNC CIC SYNC RCF VSS CLK A/B IN0 (LSB) VSS EXP2 IN15 (MSB) IN12 IN11 IN14 VSS IN13 VDD IN3 VSS IN4 VDD IN10 IN9 Serial Port SDIV3 SDIV2 SDIV1 60 SDIV0 59 A/BOUT 58 I/QOUT 57 VDD 56 DVOUT 55 PAR/SER 54 RESET 53 TRST 52 TCK 51 TMS 50 TDO 49 TDI 48 VDD 47 SYNC NCO 46 SYNC CIC 45 SYNC RCF 44 VSS 43 CLK 42 A/B 41 IN0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D7 SCLK SDO SDFS SDFE VSS SBM WL1 IN8 IN7 VDD NC NC SDI VDD WL0 AD IN6 IN5 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 D6 1 D5 2 D4 3 VSS 4 D3 5 D2 6 D1 7 VDD 8 D0 9 DS 10 DTACK 11 R/W 12 VSS 13 MODE 14 A2 15 A1 16 A0 17 CS 18 EXP0 19 EXP1 20 PIN 1 IDENTIFIER AD6620 TOP VIEW (Not to Scale) EXP2 IN15 IN14 VSS IN13 IN4 NC IN6 IN5 NC = NO CONNECT REV. 0 IN12 IN11 THE HIGHEST NUMBERED BIT IS THE MSB FOR ALL PORTS VDD IN10 IN9 –13– VDD IN3 VSS IN8 IN7 IN2 IN1 IN2 IN1 AD6620 400 375 0 –20 350 POWER – mW 325 300 RCF DECIMATION REJECTION – dB –40 –60 CIC5 DECIMATION 275 CIC2 DECIMATION 250 225 –80 –100 –120 –140 1 2 3 LOG2 – M 4 5 0 1 2 3 COMPOSITE FREQUENCY RESPONSE – MHz Figure 21. Typical Power vs. Decimation Rates Figure 24. High Decimation GSM Filter 0 –12 –24 –36 –48 –60 –72 SPUR = –104dB PHASE DITHER OFF Input sample rate 65 MSPS, decimation is 240, FIR taps is 240. Unshown spectrum is below that shown. Decimation distribution is 3, 10, 8, respectively. 0 –20 –40 –96 –108 –120 –132 0 fSAMP REJECTION – dB –84 –60 –80 –100 –120 –140 Figure 22. Typical NCO Spur Without Dither 0 2 4 6 8 0 –12 –24 –36 –48 –60 –72 –84 –96 –108 –120 –132 0 fSAMP SPUR = –118dB PHASE DITHER ON COMPOSITE FREQUENCY RESPONSE – MHz Figure 25. High Decimation AMPS Filter Input sample rate 58.32 MSPS, decimation is 300, FIR taps is 128. Unshown spectrum is below that shown. Decimation distribution among CIC2, CIC5 and RCF is 10, 30 and 1, respectively. Figure 23. Worst Case NCO Spur with Dither –14– REV. 0 AD6620 INPUT DATA PORT The input data port accepts a clock (CLK), a 16-bit mantissa IN[15:0], a 3-bit exponent EXP[2:0], and channel select Pin A/B. These pins allow direct interfacing to both standard fixed-point ADCs such as the AD9225 and AD6640, as well as to gain-ranging ADCs such as the AD6600. These inputs are not +5 V tolerant and the ADC I/O should be set to +3.3 V. The input data port accepts data in one of three input modes: Single Channel Real, Diversity Channel Real, or Single Channel Complex. The input mode is selected by programming the Input Mode Control Register located at internal address space 300h. Single Channel Real mode is used when a single channel ADC drives the input to the AD6620. Diversity Channel Real mode is the two channel mode used primarily for diversity receiver applications. Single Channel Complex mode accepts complex data in conjunction with the A/B input which identifies in-phase and quadrature samples (primarily for cascaded 6620s). The input data port is sampled on the rising edge of CLK at a maximum rate of 65 MSPS. The 16-bit mantissa, IN[15:0] is interpreted as a twos complement integer. For most applications with ADCs having fewer than 16 bits, the active bits should be MSB justified and the unused LSBs should be tied low. The 3-bit exponent, EXP[2:0] is interpreted as an unsigned integer. The exponent can be modified by the 3-bit exponent offset ExpOff (Control Register 0x305, Bits (7–5)) and an exponent invert ExpInv (Control Register 0x305, Bit 4). ExpOff sets the offset of the input exponent, EXP[2:0]. ExpInv determines the direction of this offset. Equations below show how the exponent is handled. Thus for fixed-point ADCs, the exponents are typically static and no input scaling is used in the AD6620. D11 (MSB) IN15 AD6640 AD6620 D0 (LSB) IN4 IN3 IN2 IN1 IN0 EXP2 EXP1 EXP0 A/B +3.3V Figure 26. Typical Interconnection of the AD6640 Fixed Point ADC and the AD6620 Scaling with Floating-Point ADCs An example of the exponent control feature combines the AD6600 and the AD6620. The AD6600 is an 11-bit ADC with 3 bits of gain ranging. In effect, the 11-bit ADC provides the mantissa, and the 3 bits of relative signal strength indicator (RSSI) are the exponent. Only five of the eight available steps are used by the AD6600. See the AD6600 data sheet for additional details. For gain-ranging ADCs such as the AD6600, scaled _ input = IN × 2– mod(Exp+ ExpOff , 8), ExpInv = 0 scaled _ input = IN × 2 – mod(7– Exp+ ExpOff , 8) scaled _ input = IN × 2– mod(7– Exp+ ExpOff , 8), ExpInv = 1 where: IN is the value of IN[15:0], Exp is the value of EXP[2:0], and ExpOff is the value of ExpOff. The RSSI output of the AD6600 numerically grows with increasing signal strength of the analog input (RSSI = 5 for a large signal, RSSI = 0 for a small signal). With the Exponent Offset equal to zero and the Exponent Invert Bit equal to zero, the AD6620 would consider the smallest signal at the parallel input (EXP = 0) the largest and, as the signal and EXP word increase, it shifts the data down internally (EXP = 5, will shift the 11-bit data right by 5 bits internally before going into the CIC2). The AD6620 regards the largest signal possible on the AD6600 as the smallest signal. Thus the Exponent Invert Bit is used to make the AD6620 exponent agree with the AD6600 RSSI. When it is set high, it forces the AD6620 to shift the data up for growing EXP instead of down. The exponent invert bit should always be set high for use with the AD6600. Table I. AD6600 Transfer Function with AD6620 ExpInv = 1, and No ExpOff , ExpInv = 1 where: IN is the value of IN[15:0], Exp is the value of EXP[2:0], and ExpOff is the value of ExpOff. Input Scaling In general there are two reasons for scaling digital data. The first is to avoid “clipping” or, in the case of the AD6620 register, “wrap-around” in subsequent stages. Wrap-around is not a concern for the input data since the NCO is designed to accept the largest possible input at the AD6620 data port. The second use of scaling is to preserve maximum dynamic range though the chip. As data flows from one stage to the next it is important to keep the math functions performed in the MSBs. This will keep the desired signal as far above the noise floor as possible, thus maximizing signal-to-noise ratio. Scaling with Fixed-Point ADCs For fixed-point ADCs the AD6620 exponent inputs, EXP[2:0] are typically not used and should be tied low. The ADC outputs are tied directly to the AD6620 Inputs, MSB-justified. The exponent offset (ExpOff) and exponent invert (ExpInv) should both be programmed to 0. Thus the input equation, ADC Input Level Largest RSSI[2.0] 101 (5) 100 (4) 011 (3) 010 (2) 001 (1) 000 (0) Data Division / 32 (