AD6622PCB

a FEATURES Wideband Digital IF Parallel Output Wideband Digital IF Parallel Input Allows Cascade of Chips for Additional Channels Programmable IF and Modulation for Each Channel Programmable Interpolating RAM Coefficient Filter High-Speed CIC Interpolating Filter NCO Frequency Translation Worst Spur Better than 100 dBc Tuning Resolution Better than 0.02 Hz Real or Complex Outputs Digital Summation of Channels Clipped or Wrapped Overrange Two’s Complement or Offset Binary Output Separate 3-Wire Serial Data Input for Each Channel Microprocessor Control JTAG Boundary Scan APPLICATIONS Cellular/PCS Base Stations Micro/Pico Cell Base Stations WBCDMA Wireless Local Loop Base Stations Phase Array Beam Forming Antennas Four-Channel, 75 MSPS Digital Transmit Signal Processor (TSP) AD6622 FUNCTIONAL BLOCK DIAGRAM CH A SPORT RCF CIC FILTER CIC FILTER CIC FILTER CIC FILTER NCO 18 CH B SPORT RCF NCO CH C SPORT RCF NCO SUMMATION 18 CH D SPORT RCF NCO JTAG PORT PRODUCT DESCRIPTION The AD6622 comprises four identical digital Transmit Signal Processors (TSPs) complete with synchronization circuitry and cascadable wideband channel summation. An external digitalto-analog converter (DAC) is all that is required to complete a wide band digital up-converter. On-chip tuners allow the relative phase and frequency for each RF carrier to be independently controlled. Each TSP has three cascaded signal processing elements: a RAM-programmable Coefficient interpolating Filter (RCF), a programmable Cascaded Integrator Comb (CIC) interpolating filter, and a Numerically Controlled Oscillator/tuner (NCO). The outputs of the four TSPs are summed and scaled on-chip. In multichannel wideband transmitters, multiple AD6622s may be combined using the chip’s cascadable output summation stage. Each channel provides independent serial data inputs that may be directly connected to the serial port of DSP chips. User programmable FIR filters can be used to filter linear inputs. All control registers and coefficient values are programmed through a generic microprocessor interface. Two microprocessor bus modes are supported. All inputs and outputs are LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compatible. R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD6622–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter VDD TAMBIENT Test Level IV IV Min 2.4 –40 AD6622AS Typ 3.0 +25 Max 3.3 +70 Unit V °C ELECTRICAL CHARACTERISTICS Parameter (Conditions) LOGIC INPUTS (5 V TOLERANT) Logic Compatibility Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance LOGIC OUTPUTS Logic Compatibility Logic “1” Voltage (IOH = 0.25 mA) Logic “0” Voltage (IOL = 0.25 mA) IDD SUPPLY CURRENT CLK = 60 MHz, 3.3 V1 CLK = GSM Example CLK = IS-136 Example CLK = WBCDMA Example Sleep Mode POWER DISSIPATION CLK = 60 MHz, 3.3 V1 CLK = GSM Example CLK = IS-136 Example CLK = WBCDMA Example Sleep Mode Temp Full Full Full Full Full 25°C Full Full Full Full Test Level Min AD6622AS Typ 3.0 V CMOS IV IV IV IV V 2.0 –0.3 1 1 4 VDD + 0.3 +0.8 10 10 V V µA µA pF Max Unit IV IV IV V V V IV IV V V V IV VDD – 0.05 VDD – 0.035 0.02 0.05 506 2972 2402 2092 0.1 1.77 0.892 0.722 0.6272 0.33 5661 V V mA mA mA mA mA W W W W mW Full Full 0.5 1.87 Full 1.65 NOTES 1 This specification denotes an absolute maximum supply current for the device. The conditions include all channels active, minimum interpolation in both CIC stages, maximum switching of input data, and maximum VDD of 3.3 V. In an actual application the power will be less; see the Thermal Management section of the data sheet for further details. 2 GSM interpolation = 120 at 65 MHz, 4 channels active, IS-136 interpolation = 2560 at 62.208 MHz, 4 channels active. WBCDMA interpolation = 64, 4 channels interleaved at 61.44 MHz. Specifications subject to change without notice. – 2– REV. 0 AD6622 TIMING CHARACTERISTICS1 (C Name Parameter (Conditions) CLK Timing Requirements: tCLK CLK Period CLK Width Low tCLKL tCLKH CLK Width High RESET Timing Requirements: tRESL RESET Width Low Input Wideband Data Timing Requirements: tSI Input to CLK Setup Time tHI Input to CLK Hold Time Parallel Output Switching Characteristics: tSO CLK to Output Setup Time tHO CLK to Output Hold Time tZO Output Three-State Time SYNC Timing Requirements: tSS SYNC to CLK Setup Time tHS SYNC to CLK Hold Time Serial Port Timing Requirements: tDSCLK CLK to SCLK Delay tDSDFS SCLK to SDFS Delay tSSI SDI to SCLK Setup Time SDI to SCLK Hold Time tHSI tSCS Serial Clock Skew MICROPROCESSOR PORT, MODE INM (MODE = 0) MODE INM Write Timing: tHWR WR(R/W) to RDY(DTACK) Hold Time tSAM Address/Data to WR(R/W) Setup Time Address/Data to RDY(DTACK) Hold Time tHAM tDRDY WR(R/W) to RDY(DTACK) Delay tACCFAST WR(R/W) to RDY(DTACK) High Delay tACCMEDIUM WR(R/W) to RDY(DTACK) High Delay tACCSLOW WR(R/W) to RDY(DTACK) High Delay MODE INM Read Timing: Address to RD(DS) Setup Time tSAM tHA Address to Data Hold Time Data Three-State Delay tZD tDD RDY(DTACK) to Data Delay tDRDY RD(DS) to RDY(DTACK) Delay RD(DS) to RDY(DTACK) High Delay tACCFAST tACCMEDIUM RD(DS) to RDY(DTACK) High Delay tACCSLOW RD(DS) to RDY(DTACK) High Delay Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV IV IV IV IV IV IV IV 0 0 0 2 × tCLK 3 × tCLK 4 × tCLK 0 0 3.4 2 × tCLK 3 × tCLK 4 × tCLK 10.2 3 × tCLK 4 × tCLK 5 × tCLK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LOAD = 40 pF, all outputs unless specified) Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level IV IV IV IV IV IV IV IV V IV IV V IV IV IV IV Min 13.3 5.5 5.5 30.0 0.5 3.5 12 4.1 5 2.6 1.5 8.5 –1.2 8.5 5.5 7 +2.4 AD6622AS Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.5 × tCLK 0.5 × tCLK 7 10.5 tCLK – 10 10.2 3 × tCLK 4 × tCLK 5 × tCLK REV. 0 –3– AD6622 Name Parameter (Conditions) Temp Test Level Min AD6622AS Typ Max Unit MICROPROCESSOR PORT, MODE MNM (MODE = 1) MODE MNM Write Timing: tHDS DS(RD) to DTACK(RDY) Hold Time tHRW R/W(WR) to DTACK(RDY) Hold Time Address/Data to R/W(WR) Setup Time tSAM tHAM Address/Data to R/W(WR) Hold Time tDDTACK DS(RD) to DTACK(RDY) Delay R/W(WR) to DTACK(RDY) Low Delay tACCFAST tACCMEDIUM R/W(WR) to DTACK(RDY) Low Delay tACCSLOW R/W(WR) to DTACK(RDY) Low Delay MODE MNM Read Timing: tSAM Address to DS(RD) Setup Time Address to Data Hold Time tHA Data Three-State Delay tZD tDD DTACK(RDY) to Data Delay DS(RD) to DTACK(RDY) Delay tDDTACK tACCFAST DS(RD) to DTACK(RDY) Low Delay tACCMEDIUM DS(RD) to DTACK(RDY) Low Delay tACCSLOW DS(RD) to DTACK(RDY) Low Delay NOTES 1 All Timing Specifications valid over VDD range of 2.4 V to 3.3 V. Specifications subject to change without notice. Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV IV IV IV IV IV IV IV IV 0 0 0 0 2 × tCLK 3 × tCLK 4 × tCLK 0 0 0 2 × tCLK 3 × tCLK 4 × tCLK tCLK – 10 1 × tCLK 3 × tCLK 4 × tCLK 5 × tCLK 1 × tCLK 3 × tCLK 4 × tCLK 5 × tCLK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCLK tCLKL CLK tSI tHI CLK tCLKH IN[17:0], QIN tSO OUT[17:0], QOUT tHO tZO OEN tZO Figure 3. Wideband Input Timing CLK tSS tHS Figure 1. Parallel Output Switching Characteristics CLK tDSCLK SCLK tDSDFS SDFS tSSI SDI DATAn tHSI tDSDFS CLKn SYNC Figure 4. SYNC Timing Inputs Figure 2. Serial Port Switching Characteristics –4– REV. 0 AD6622 RD (DS) tHWR WR (R/W) CS tSAM A[2:0] VALID ADDRESS tSAM D[7:0] VALID DATA tHAM tHAM tDRDY RDY (DTACK) tACC 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF WR TO THE RE OF RDY. 2. tACCFAST REQUIRES A MAXIMUM OF THREE CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 5, 3, 2, 1 3. tACCMEDIUM REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 4 AND 0 IF THE ACCESS IS TO A CONTROL REGISTER VERSUS A RAM REGISTER. 4. tACCSLOW REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS. Figure 5. INM Microport Write Timing Requirements RD (DS) WR (R/W) CS tSAM A[2:0] tZD D[7:0] tDRDY RDY (DTACK) tACC tDD VALID DATA VALID ADDRESS tHA tZD 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF WR TO THE RE OF RDY. 2. tACCFAST REQUIRES A MAXIMUM OF THREE CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 5, 3, 2, 1 3. tACCMEDIUM REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 4 AND 0 IF THE ACCESS IS TO A CONTROL REGISTER VERSUS A RAM REGISTER. 4. tACCSLOW REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS. Figure 6. INM Microport Read Timing Requirements REV. 0 –5– AD6622 tHDS DS (RD) tHRW R/W (WR) CS tSAM A[2:0] tHAM VALID ADDRESS tSAM tHAM VALID DATA tDDTACK D[7:0] DTACK (RDY) tACC 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK. 2. tACCFAST REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 3, 2, 1 3. tACCMEDIUM REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 4, 5, AND 0 IF THE ACCESS IS TO A CONTROL REGISTER VERSUS A RAM REGISTER. 4. tACCSLOW REQUIRES A MAXIMUM OF SIX CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS. Figure 7. MNM Microport Write Timing Requirements tHDS DS (RD) R/W (WR) CS tSAM A[2:0] tZD D[7:0] tDD VALID DATA VALID ADDRESS tHA tZD tDDTACK DTACK (RDY) tACC 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK. 2. tACCFAST REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 3, 2, 1 3. tACCMEDIUM REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 4, 5, AND 0 IF THE ACCESS IS TO A CONTROL REGISTER VERSUS A RAM REGISTER. 4. tACCSLOW REQUIRES A MAXIMUM OF SIX CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS. Figure 8. MNM Microport Read Timing Requirements –6– REV. 0 AD6622 ABSOLUTE MAXIMUM RATINGS * EXPLANATION OF TEST LEVELS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V Input Voltage . . . . –0.3 V to VDD +0.3 V (Not 5 V Tolerant) IN[17:0], QIN, OEN Input Voltage . . . . . . . . . . . . . –0.3 V to +3.6 V (5 V Tolerant) CLK, RESET, DS, R/W, MODE, A[2:0], D[7:0], SYNC, TRST, TCK, TMS, TDI, SDINA, SDINB, SDINC, SDIND Output Voltage Swing . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280°C *Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the devices at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. I. 100% Production Tested. II. 100% Production Tested at 25°C, and Sample Tested at Specified Temperatures. III. Sample Tested Only. IV. Parameter Guaranteed by Design and Analysis. V. Parameter is Typical Value Only. VI. 100% Production Tested at 25°C, and Sample Tested at Temperature Extremes. THERMAL CHARACTERISTICS 128-Lead MQFP: θJA = 33°C/W, No Airflow θJA = 27°C/W, 200 LFPM Airflow θJA = 24°C/W, 400 LFPM Airflow θJC = 5.5°C/W Thermal measurements made in the horizontal position on a 2-layer board. ORDERING GUIDE Model AD6622AS AD6622S/PCB Temperature Range –40°C to +70°C (Ambient) Package Description 128-Lead MQFP (Metric Quad Flatpack) Evaluation Board with AD6622 and Software Package Option S-128A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6622 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –7– AD6622 PIN CONFIGURATION 100 TRST 99 GND 98 GND 97 IN0 96 GND 95 GND 85 GND 84 GND 83 GND 82 IN9 73 GND 72 GND 69 GND 68 GND 102 GND 101 TCK GND 103 VDD 104 GND 105 TMS 106 TDO 107 TDI 108 SCLKA 109 VDD 110 SDFSA 111 SDINA 112 SCLKB 113 SDFSB 114 GND 115 GND 116 GND 117 SDINB 118 SCLKC 119 SDFSC 120 SDINC 121 VDD 122 SCLKD 123 SDFSD 124 SDIND 125 GND 126 VDD 127 GND 128 1 65 GND 81 IN10 80 IN11 79 IN12 77 IN13 76 IN14 75 IN15 74 IN16 90 VDD 89 IN5 78 VDD 71 IN17 70 QIN 94 IN1 93 IN2 92 IN3 88 IN6 87 IN7 86 IN8 66 VDD 67 CLK 91 IN4 64 GND 63 GND 62 SYNC 61 RESET 60 CS 59 VDD 58 A0 57 A1 56 A2 55 MODE 54 GND AD6622 TOP VIEW (Not to Scale) 53 GND 52 GND 51 R/W(WR) 50 DTACK(RDY) 49 DS(RD) 48 D0 47 VDD 46 D1 45 D2 44 D3 43 D4 42 GND 41 VDD 40 D5 39 GND PIN 1 IDENTIFIER 21 22 23 24 OUT14 25 OUT15 27 QOUT 30 OUT7 15 GND 20 OUT16 28 OUT17 29 GND 31 OUT4 11 OUT6 13 OUT8 16 OUT9 17 OUT10 18 OUT5 12 OUT3 10 GND 19 OUT0 OUT1 OUT2 OUT11 OUT12 DENOTES I/O POWER PIN DENOTES CORE POWER PIN OUT13 GND 32 GND GND GND GND GND GND D6 37 GND 38 D7 33 GND 34 GND 35 GND 36 OEN VDD 14 VDD 26 2 3 5 6 7 8 4 9 –8– REV. 0 AD6622 PIN FUNCTION DESCRIPTIONS Pin Number Name Type P Description Ground Connection 1, 3–5, 9, 19–21, 31, 32, GND 34–36, 38, 39, 42, 52–54, 63–65, 68, 69, 72, 73, 83–85, 95, 96, 98, 99, 102, 103, 105, 115–117, 126, 128 2 OEN 27–29, 22–25, 15–18, 10–13, 6–8 14, 26, 41, 47, 122 59, 66, 78, 90, 104, 110, 127 30 33, 37, 40, 43–46, 48 49 50 51 55 56–58 60 61 62 67 70 71, 74–77, 79–82, 86–89, 91–94, 97 100 101 106 107 108 109 111 112 113 114 118 119 120 121 123 124 125 OUT[17:0] VDD VDD QOUT D[7:0] DS (RD) DTACK (RDY) R/W (WR) MODE A[2:0] CS RESET SYNC CLK QIN IN[17:0] TRST TCK TMS TDO TDI SCLKA SDFSA SDINA SCLKB SDFSB SDINB SCLKC SDFSC SDINC SCLKD SDFSD SDIND I O/T P P O/T I/O/T I O I I I I I I I I I I I I O I O O I O O I O O I O O I Active High Output Enable Pin (Actively Pulled Down If Not Connected) (Not 5 V Tolerant) Wideband Output Data +3.0 V Supply (I/O Supply) +3.0 V Supply (Core Supply) Indicates Q Output Data (Complex Output Mode) Microprocessor Interface Data INM Mode: Read Signal, MNM Mode: Data Strobe Signal Acknowledgment of a Completed Transaction (Signals when µP Port Is Ready for an Access) Open Drain, Must Be Pulled Up Externally Read/Write Line (Write Signal) Sets Microport Mode: MODE = 1, MNM Mode; MODE = 0, INM Mode Microprocessor Interface Address Chip Select, Enable the Chip for µP Access Active Low Reset Pin (Actively Pulled Up If Not Connected) SYNC Signal for Synchronizing Multiple AD6622s (Actively Pulled Down If Not Connected) Input Clock (Actively Pulled Down If Not Connected) Indicates Q Input Data (Complex Input Mode) (Actively Pulled Down If Not Connected) (Not 5 V Tolerant) Wideband Input Data (Allows Cascade of Multiple AD6622 Chips In a System) (Actively Pulled Down If Not Connected) (Not 5 V Tolerant) Test Reset Pin (Actively Pulled Up If Not Connected) Test Clock Input (Actively Pulled Down If Not Connected) Test Mode Select (Actively Pulled Up If Not Connected) Test Data Output Test Data Input (Actively Pulled Down If Not Connected) Serial Clock Output Channel A Serial Data Frame Sync Output Channel A Serial Data Input Channel A (Actively Pulled Down If Not Connected) Serial Clock Output Channel B Serial Data Frame Sync Output Channel B Serial Data Input Channel B (Actively Pulled Down If Not Connected) Serial Clock Output Channel C Serial Data Frame Sync Output Channel C Serial Data Input Channel C (Actively Pulled Down If Not Connected) Serial Clock Output Channel D Serial Data Frame Sync Output Channel D Serial Data Input Channel D (Actively Pulled Down If Not Connected) REV. 0 –9– AD6622 AD6622 SDINA SDFSA SCLKA SPORT DATA I RCF Q I CIC FILTER Q NCO DATa QIN IN [17:0] DATb SUMMATION RESET CLK SDINB SDFSB SCLKB SPORT DATA I RCF Q I CIC FILTER Q NCO SYNC SDINC SDFSC SCLKC SPORT DATA I RCF Q I CIC FILTER Q NCO DATc OEN QOUT SDIND SDFSD SCLKD SPORT DATA I RCF Q I CIC FILTER Q NCO DATd OUT [17:0] JTAG D[7:0] DS TRST TDO TCK TMS TDI MICROPORT DTACK R/W MODE A[2:0] CS Figure 9. Functional Block Diagram THEORY OF OPERATION As digital-to-analog converters (DACs) achieve higher sampling rates, analog bandwidth, and dynamic range, it becomes increasingly attractive to accomplish the first IF stage of a transmitter in the digital domain. Digital IF signal processing provides repeatable manufacturing, higher accuracy, and more flexibility than comparable high-dynamic-range analog designs. The AD6622 Four-Channel Transmit Signal Processor (TSP) is designed to bridge the gap between DSPs and high-speed DACs. The wide range of interpolation factors in each filter stage makes the AD6622 useful for creating both narrowband and wideband carriers in a high-speed sample stream. The high-resolution NCO allows flexibility in frequency planning and supports both digital and analog air interface standards. The RAM-based architecture allows easy reconfiguration for multimode applications. The interpolating filters remove unwanted images of signals sampled at a fraction of the wideband rate. When the channel of interest occupies far less bandwidth than the wideband output signal, rejecting out-of-band noise is called “processing gain.” For large interpolation factors, this processing gain allows a 14-bit DAC to express the sum of multiple 16-bit signals sampled at a lower rate without significantly increasing the noise floor about each carrier. In addition, the programmable RAM coefficient stage allows anti-imaging, and static equalization functions to be combined in a single, cost-effective filter. The high-speed NCO can be used to tune a quadrature sampled signal to an IF channel, or the NCO can be directly frequencymodulated at an IF channel. Multicarrier phase synchronization pins and phase offset registers allow intelligent management of the relative phase of the independent RF channels. This capability supports the requirements for phased array antenna architectures and management of the wideband peak/power ratio to minimize clipping at the DAC. The wideband input and output ports allow multiple AD6622s to be cascaded into a single DAC. The master clock for the entire system is based on the DAC clock rate (up to 75 MSPS). The external 18-bit resolution reduces summation of truncation noise. The wideband ports can be configured for real or quadrature outputs. Quadrature sampled outputs (I and Q) are limited to half the master clock rate on the shared output bus. FUNCTIONAL OVERVIEW The following descriptions explain the functionality of each of the core sections of the AD6622. Detailed timing, application, and specifications are described in detail in their respective portions of the data sheet. SERIAL DATA PORT The AD6622 has four independent Serial Ports (A, B, C, and D) of which accepts data to its own channel (1, 2, 3, or 4) of the device. Each serial port has three pins: SCLK, SDFS, and SDIN. The SCLK and SDFS pins are outputs that provide serial clock and framing. The SDIN pins are inputs that accept channel data. The serial ports do not accept configuration or control inputs. The serial ports do not accept external clock or framing signals, although it is possible to synchronize the AD6622 serial ports to meet an external timing requirement. The serial clock output, SCLK, is created by a programmable internal counter that divides down the master clock. When the channel is reset, SCLK is held low. SCLK starts on the first rising edge of CLK after Channel Reset is removed (D0 through D3 of External Address 4). Once active, the SCLK frequency is determined by the master CLK frequency and the SCLK divider, according to the equation below. The SCLK divider is a 5-bit unsigned value located in Channel Register 0x0D. The user must select the SCLK divider to ensure that SCLK is fast enough to accept full input sample words at the input sample rate. See the design example at the end of this section. The maximum SCLK frequency is 1/2 of the master clock frequency. The minimum SCLK frequency is 1/64 of the master clock frequency. f SCLK = fCLK 2 × (SCLK DIVIDER + 1) (1) –10– REV. 0 AD6622 The serial data frame sync output, SDFS, is pulsed high for one SCLK cycle at the input sample rate. The input sample rate is determined by the master clock divided by channel interpolation factor. If the SCLK rate is not an integer multiple of the input sample rate, the SDFS will continually adjust the period by one SCLK cycle in order to keep the average SDFS rate equal to the input sample rate. When the channel is in sleep mode, SDFS is held low. The first SDFS is delayed by the channel reset latency after the Channel Reset is removed. The channel reset latency varies dependent on channel configuration. The serial data input, SDIN, accepts 32-bit words as channel input data. The 32-bit word is interpreted as two 16 bit two’s complement quadrature words, I followed by Q, MSB first. The first bit is shifted into the serial port starting on the second rising edge of SCLK after SDFS goes high, as shown by the timing diagram below. CLK tDSCLK PROGRAMMABLE INTERPOLATING RAM COEFFICIENT FILTER (RCF) Each channel has a fully independent RAM Coefficient Filter (RCF). The RCF accepts data from the serial port, filters it, and passes the result to the CIC filter. The RCF implements a FIR filter with optional interpolation. The FIR filter can produce impulse responses up to 128 output samples long. The FIR response may be interpolated up to a factor of 128, although the best filter performance is usually achieved if the RCF interpolation factor is confined to 8 or below. FIR Filter Implementation The RCF accepts quadrature samples from the serial port with a fixed point resolution of 16 bits each, for I and Q. RCF SERIAL PORT DATA MEM 16,16 ACCUMULATOR 16,16 16,16 SDFS SCLK SDIN IQ TO CIC FILTER SCLK tDSDFS SDFS tSSI SDI DATAn tDSDFS CLKn COEFFICIENT MEM RCF COARSE SCALE Figure 11. RCF Block Diagram tHSI Figure 10. Serial Port Switching Characteristics As an example of the serial port operation, consider a CLK frequency of 62.208 MSPS and a channel interpolation of 2560. In that case, the input sample rate is 24.3 kSPS (62.208 MSPS/ 2560), which is also the SDFS rate. Substituting, fSCLK ≥ 32 × fSDFS into the equation below and solving for SCLKDIVIDER, we find the maximum value for SCLKDIVIDER according to Equation 2. SCLK DIVIDER ≤ fCLK 64 × fSDFS –1 (2) The AD6622 RCF realizes a sum-of-products filter using a polyphase implementation. This mode is equivalent to an interpolator followed by a FIR filter running at the interpolated rate. In Figure 12, the interpolating block increases the rate by the RCF interpolation factor (LRCF) by inserting LRCF-1 zero valued samples between every input sample. The next block is a filter with a finite impulse response length (NRCF) and an impulse response of h[n], where n is an integer from 0 to NRCF-1. fIN a fIN LRCF b LRCF NRCF TAP fIN FIR FILTER h[n] c LRCF Figure 12. RCF Interpolation Evaluating this equation for our example, SCLKDIVIDER must be less than or equal to 39. Since the SCLKDIVIDER channel register is a 5-bit unsigned number it can only range from 0 to 31. Any value in that range will be valid for this example, but if it is important that the SDFS period is constant, then there is another restriction. For regular frames, the ratio fSCLK/fSDFS must be equal to an integer of 32 or larger. For this example, constant SDFS periods can only be achieved with an SCLK divider of 19. In conclusion, the SDFS rate is determined by the AD6622 master clock rate and the interpolation rate of the channel. The SDFS rate is equal to the channel input rate. The channel interpolation is equal to RCF interpolation times CIC5 interpolation, times CIC2 interpolation L = LRCF × LCIC 5 × LCIC 2 The difference equation for Figure 12 is written below, where h[n] is the RCF impulse response, b[n] is the interpolated input sample sequence at point “b” in Figure 12, and c[n] is the output sample sequence at point “c” in the Figure 12. c[n ] = ∑ h[k − n ] × b[n ] k=0 N RCF −1 (4) This difference equation can be described by the transfer function from point “b” to “c” as shown Equation 5. H bc ( z ) = ∑ h[n ] × z − n n=0 N RCF −1 (5) (3) The SCLK rate is determined by the AD6622 master clock rate and SCLKDIVIDER. The SCLK is a divided version of the AD6622 master CLK. The SCLK divide ratio is determined by SCLKDIVIDER as shown in Equation 2. The SCLK must be fast enough to input 32 bits of data prior to the next SDFS. Extra SCLKs are ignored by the serial port. REV. 0 The actual implementation of this fi lter uses a polyphase decomposition to skip the multiply-accumulates when b[n] is zero. Compared to the diagram above, this implementation has the benefits of reducing by a factor of LRCF both the time needed to calculate an output and the required data memory (DMEM). The price of these benefits is that the user must place the coefficients into the coefficient memory (CMEM) indexed by the interpolation phase. The process of selecting the coefficients and placing them into the CMEM is broken into three steps shown below. –11– AD6622 1. Select the Impulse Response Length (NRCF) and the Interpolation Factor (L RCF ). The Impulse Response Length (NRCF) is limited in three ways: by the available calculation time, by the data memory size (DMEM), and by the coefficient memory size (CMEM). The equation below shows that NRCF is limited to the minimum of these three conditions. Time Restriction ↓ CMEM Restriction ↓ (6) WorstCasePeakp = 2− g × ∑ |h[k × LRCF + p ]| k=0 N RCF –1 LRCF (8) L  N RCF ≤ min  , 16 × LRCF , 128 2  ↑ DMEM Restriction where: L = LRCF × LCIC5 × LCIC2 6. The worst-case peak is calculated similarly to the channel center gain, except that the input sequence swings from fullscale positive to full-scale negative to match the polarity of the coefficient by which it will be multiplied, so that each product is positive. This results in a maximal that must be less than one to guarantee no possibility of wrapping. Note that when LRCF is greater than one, each phase may produce its worst-case peak in response to a different input sequence. 7. Programming DMEM and CMEM. The DMEM must be initialized to all zeros to avoid any unpredictable start-up transients since a reset does not clear the memory. The impulse response h[n] must be reordered by phase for the CMEM as shown in the code below. Several filters with impulse lengths that total less than 128 can be programmed into the CMEM simultaneously and selected later using the RCF offset pointer (ORCF) which is set by Channel Register 0x0B. /* Reorder Fir Coefficients for AD6622 CMEM */ for (p=0; p24; Write_Micro(3,d3); /*write Byte 2*/ d2=(NCO_FREQ & 0xFF0000)>>16; Write_Micro(2,d2); /*write Byte 1*/ d1=(NCO_FREQ & 0xFF00)>>8; Write_Micro(1,d1); /*write Byte 0, Byte 0 is written last and causes an internal write to occur*/ d0=NCO_FREQ & 0xFF; Write_Micro(0,d0); } The AD6622 provides considerable flexibility for the control of the synchronization, relative phasing, and scaling of the individual channel inputs. Implementation of a multichannel transmitter invariably begins with an analysis of the output spectrum that must be generated. DIGITAL-TO-ANALOG CONVERTER (DAC) SELECTION The selection of a high-performance DAC depends on a number of factors. The dynamic range of the DAC must be considered from a noise and spectral purity perspective. The 14-bit AD9754 and AD9772 are the best choices for overall bandwidth, noise, and spectral purity. In order to minimize the complexity of the analog interpolation filter which must follow the DAC, the sample rate of the master clock is generally set to at least three times the maximum analog frequency of interest. In the case where a 15 MHz band of interest is to be up-converted to RF, the lowest frequency might be 5 MHz and the upper band edge at 20 MHz (offset from dc to afford the best image reject filter after the first digital IF). The minimum sample rate would be set to 75 MSPS. Consideration must also be given to data rate of the incoming data stream, interpolation factors, and the clock rate of the DSP. REV. 0 –25– AD6622 MULTIPLE TSP OPERATION Each of the four Transmit Signal Processors (TSPs) of the AD6622 can adequately reject the interpolation images of narrow bandwidth carriers such as AMPS, IS-136, GSM, EDGE, and PHS. Wider bandwidth carriers such as IS-95 and UMTS require a coordinated effort of multiple processing channels. This section demonstrates how to coordinate multiple TSPs to create wider bandwidth channels without sacrificing image rejection. As an example, a UMTS carrier is modulated using four TSPs (an entire AD6622). The same principals can be applied to different designs using more or fewer TSPs. This section does not explore techniques for using multiple TSPs to solve problems other than Serial Port or RCF throughput. Designing filter coefficients and control settings for deinterleaved TSPs is no harder than designing a filter for a single TSP. For example, if four TSPs are to be used, simply divide the input data rate by four and generate the filter as normal. For any design, a better filter can always be realized by incrementing the number of TSPs to be used. When it is time to program the TSPs, only two small differences must be programmed. First each channel is configured with exactly the same filter, scalars, modes and NCO frequency. Since each channel receives data at 1/4 the data rate and in a staggered fashion, the Start Hold-Off Counters must also be staggered (see Programming Multiple TSPs section below). Second, the phase offset of each NCO must be set to match the demultiplexed ratio (1/4 in this example). Thus the phase offset should be set to 90 degrees (16384, which is 1/4 of a 16-bit register). Determining the Number of TSPs to Use Time Restriction ↓ CMEM Restriction ↓ (25) L  N RCF ≤ min  , 16 × LRCF , 128 2  ↑ DMEM Restriction where: L = LRCF × LCIC5 × LCIC2 = N TSP × fCLK f IN Deinterleaving the input data into multiple TSPs will extend the time restriction and may possibly extend the DMEM restriction, but will not extend the CMEM restriction. Deinterleaving the input stream to multiple TSPs divides the input sample rate to each TSP by the number of TSPs used (NTSP). To keep the output rate fixed, L must be increased by a factor of NCH, which extends the time restriction. This increase in L may be achieved by increasing any one or more of LRCF, LCIC5, or LCIC2 within their normal limits. Achieving a larger L by increasing LRCF instead of LCIC5 or LCIC2, will relieve the DMEM restriction as well. In a UMTS example, NTSP = 4, fCLK = 61.44 MHz, and fIN = 3.84 MHz, resulting in L = 64. Factoring L into LRCF = 8, LCIC = 8, and LCIC2 = 1, results in a maximum NRCF = 32 due to the time restriction. Figure 22 shows an example RCF impulse response that has a frequency response as shown in Figure 23 from 0 Hz to 7.68 MHz (fIN × LRCF/NTSP). The composite RCF and CIC frequency response is shown in Figure 24, on the same frequency scale. This figure demonstrates a good approximation to a root-raised-cosine with a roll-off factor of 0.22, a pass-band ripple of 0.1 dB, and a stopband ripple better than –65 dB until the lobe of the first image which peaks at –50 dB about 5.6 MHz from the carrier center. This lobe could be reduced by shifting more of the interpolation towards the RCF, but that would sacrifice near-in performance. As shown, the first image can easily be rejected by an analog filter further up the signal path. Scaling must be considered as normal with an interpolation factor of L, to guarantee no overflow in the RCF, CIC, or NCOs. The output level at the summation port should be calculated using an interpolation factor of L/NTSP. Programming Multiple TSPs There are three limitations of a single TSP that can be overcome by deinterleaving an input stream into multiple TSPs: Serial Port bandwidth, the time restriction to the RCF impulse response length (NRCF), and the DMEM restriction to NRCF. If the input sample rate is faster than the Serial Port can accept data, the data can be deinterleaved into multiple Serial Ports. Recalling from the Serial Port description, the SCLK frequency (fSCLK) is determined by the equation below. To minimize the number of processing channels, SCLKDIVIDER should be set as low as possible to get the highest fSCLK that the serial data source can accept. f SCLK = fCLK 2 × (SCLK DIVIDER + 1) (23) A minimum of 32 SCLK cycles are required to accept an input sample, so the minimum number of TSPs (NTSP) due to limited Serial Port bandwidth is a function of the input sample rate (fIN), as shown by the equation below. Configuring the TSPs for deinterleaved operation is straightforward. All of the Channel Registers and CMEM of each TSP are programmed identically, except the Start Hold-Off Counters and NCO Phase Offset. In order to separate the input timing to each TSP, the HoldOff Counters must be used to start each TSP successively in response to a common Start SYNC. The Start SYNC may originate from the SYNC pin or the Microport. Each subsequent TSP must have a Hold-Off Counter value L/NTSP larger than its predecessor’s. If the TSPs are located on cascaded AD6622s, the Hold-Off Counters of the upstream device should be incremented by an additional one. In the UMTS example, L = 64 and NTSP = 4, so in order to respond as quickly as possible to a Start SYNC, the Hold-Off Counter values should be 1, 17, 33, and 49.  32 × f IN  NTSP ≥ ceil    fSCLK  (24) For a sample UMTS system, we will assume fCLK = 61.44 MHz, and the serial data source can drive data at 30.72 MBPS (SCLKDIVIDER = 0). To achieve fIN = 3.84 MHz, the minimum NTSP is 4. (This is TSP channels, not TSP ICs.) Multiple TSPs are also required if the RCF does not have enough time or DMEM space to calculate the required RCF filter. Recalling the maximum NTAPS equation from the RCF description, are three restrictions to the RCF impulse response length, NRCF. –26– REV. 0 AD6622 Driving Multiple TSP Serial Ports 10 0 –10 –20 –30 dBc When properly configured, the AD6622 will drive each SDFS out of phase. Each new piece of data should be driven only into the TSP that pulses its SDFS pin at that time. In the UMTS example, L = 64 and NTSP = 4, so each serial port need only accept every 4th input sample. Each serial port is shifting at peak capacity, so sample 1, 2, and 3 begin shifting into Serial Ports B, C, and D before Sample 0 is completed into Serial Port A. SDFSA SDFSB SDFSC SDFSD 2 3 6 7 0 1 4 5 RAM COEFFICIENT FILTER –40 –50 –60 –70 –80 –90 –100 0 1000 2000 3000 4000 kHz 5000 6000 7000 8000 Figure 21. SDFS Timing for WBCDMA AD6622 1.024 MCPS 32 8.196MSPS 65.536MSPS RAM I COEF Q CIC NCO FILTER 8.196MSPS 65.536MSPS RAM I CIC NCO COEF Q FILTER 8.196MSPS 65.536MSPS RAM I COEF Q CIC NCO FILTER 8.196MSPS 65.536MSPS RAM I CIC NCO COEF Q FILTER Figure 24. Typical FIR Frequency Response for WBCDMA 0 –10 –20 –30 –40 –50 SPEC( f ) dB HCIC(f) ( LEVEL ) 5 1.024 MCPS DATA REFORMATTER SUMMATION dBc DAC 4.096 MCPS 32 32 1.024 MCPS 32 1.024 MCPS 32 65.536 MSPS –60 –70 –80 –90 –100 –110 –120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 f MHz dB(AD6624(f)) COMPLEX SIGNAL 32 BITS (16 I, 16 Q) REAL OR IMAGINARY SIGNAL Figure 25. Typical Composite Frequency Response for WBCDMA THERMAL MANAGEMENT Figure 22. Block Diagram for WBCDMA 1.0 0.5 COEF – J The power dissipation of the AD6622 is primarily determined by three factors: the clock rate, the number of channels active, and the distribution of interpolation rates. The faster the clock rate the more power dissipated by the CMOS structures of the AD6622; the more channels active, the higher the overall power of the chip. Low interpolation rates in the CIC stages (CIC5, CIC2) results in higher power dissipation. All these factors should be analyzed as each application has different thermal requirements. The AD6622 128-lead MQFP is specially designed to provide excellent thermal performance. To achieve the best performance, the power and ground leads should be connected directly to planes on the PC board. This provides the best thermal transfer from the AD6622 to the PC board. 0 0 5 10 15 20 25 30 Figure 23. Typical Impulse Response for WBCDMA REV. 0 –27– AD6622 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 128-Lead MQFP (Metric Quad Flatpack) (S-128A) 0.685 (17.40) 0.669 (17.00) 0.555 (14.10) 0.547 (13.90) 128 1 103 102 0.134 (3.40) MAX 0.041 (1.03) 0.031 (0.78) SEATING PLANE 0.791 (20.10) 0.783 (19.90) TOP VIEW (PINS DOWN) 0.921 (23.40) 0.906 (23.00) 0.003 (0.08) MAX 0.010 (0.25) MIN 0.110 (2.80) 0.102 (2.60) 38 39 65 64 0.020 (0.50) BSC 0.011 (0.27) 0.007 (0.17) – 28– REV. 0 PRINTED IN U.S.A. C3772–8–5/00 (rev. 0) 00968