AD6630PCB

a FEATURES 24 dB Gain 4 dB Noise Figure Easy Match to SAW Filters Output Limiter Adjustable +8.5 dBm to +12 dBm 700 MHz Bandwidth 10 V Single or Dual 5 V Power Supply 300 mW Power Dissipation APPLICATIONS ADC IF Drive Amp Communications Receivers PCS/Cellular Base Stations GSM, CDMA, TDMA Differential, Low Noise IF Gain Block with Output Clamping AD6630 FUNCTIONAL BLOCK DIAGRAM NC 1 NC 2 IP2 3 IP1 4 IP1 5 IP2 6 CLLO 7 CLHI 8 NC = NO CONNECT + + + AD6630 16 15 14 13 12 11 10 9 VCC CD1 OP VEE CMD OP CD2 VCC PRODUCT DESCRIPTION The AD6630 is an IF gain block designed to interface between SAW filters and differential input analog-to-digital converters. The AD6630 has a fixed gain of 24 dB and has been optimized for use with the AD6600 and AD6620 in digitizing narrowband IF carriers in the 70 MHz to 250 MHz range. Taking advantage of the differential nature of SAW filters, the AD6630 has been designed as a differential in/differential out gain block. This architecture allows 100 dB of adjacent channel blocking using low cost SAW filters. The AD6630 provides output limiting for ADC and SAW protection with 10° phase variation in recovery from overdrive situations. Designed for “narrow-band” cellular/PCS receivers, the high linearity and low noise performance of the AD6630 allows for implementation in a wide range of applications ranging from GSM to CDMA to AMPS. The clamping circuitry also maintains the phase integrity of an overdriven signal. This allows phase demodulation of single carrier signals with an overrange signal. While the AD6630 is optimized for use with the AD6600 Dual Channel, Gain Ranging ADC with RSSI, it can also be used in many other IF applications. The AD6630 is designed with an input impedance of 200 Ω and an output of 400 Ω. In the typical application shown below, these values match the real portion of a typical SAW filter. Other devices can be matched using standard matching network techniques. The AD6630 is built using Analog Devices’ high speed complementary bipolar process. Units are available in a 300 mil SOIC (16 leads) plastic surface mount package and specified to operate over the industrial temperature range (–40°C to +85°C). AD6630 MAIN LOCAL OSCILLATOR AD6600 AD6620 DSP AD6630 DIVERSITY Figure 1. Reference Design R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD6630–SPECIFICATIONS NORMAL OPERATING CONDITIONS Parameter (Conditions) SINGLE SUPPLY VOLTAGE POSITIVE SUPPLY VOLTAGE NEGATIVE SUPPLY VOLTAGE AMBIENT TEMPERATURE PACKAGE THERMAL RESISTANCE OPERATING FREQUENCY1 70 Min 8.5 4.25 –5.25 –40 80 250 5.0 –5.0 Typ Max 10.5 5.25 –4.25 +85 Units V V V °C °C/W MHz DC SPECIFICATIONS Inputs should be AC coupled.) Parameter SUPPLY CURRENT OUTPUT DC LEVEL Temp Full Full (TMIN = –40 C, TMAX = +85 C. Output dc levels are nominally at VM, where VM = VCC + VEE = [+5 V + (–5 V)] = 0. Test Level II II VM–150 Min Typ 30 Max 48 VM+150 Units mA mV AC SPECIFICATIONS performance limits are correlated to 5 MHz testing based on characterization data.) Parameter1 GAIN (POWER) @ 70 MHz GAIN (POWER) @ 250 MHz –3 dB BANDWIDTH OUTPUT REFERRED IP3 @ 70 MHz 2 2 (TMIN = –40 C, TMAX = +85 C. All AC production tests are performed at 5 MHz. 70 MHz and 250 MHz Test Level II II V V V V V II II II II V V V V V V IV IV IV 8.5 7.5 11 9 3700 200 2 400 2 4 11 13.8 9.25 12.5 14.3 10.6 Temp Full Full +25°C Full Full Full Full Full Full Full Full +25°C +25°C +25°C +25°C +25°C +25°C Full Full Full 4, 5 3, 5 Min 23 22 Typ 24 23 700 22 19 45 45 Max 25 24 Units dB dB MHz dBm dBm dBm dBm dBm dBm dBm dBm V/µs Ω pF Ω pF dB dBm dBm dBm OUTPUT REFERRED IP3 @ 250 MHz OUTPUT REFERRED IP2 @ 70 MHz2 OUTPUT REFERRED IP2 @ 250 MHz2 OUTPUT REFERRED 1 dB COMPRESSION POINT @ 70 MHz LOW LEVEL CLAMP3 OUTPUT REFERRED 1 dB COMPRESSION POINT @ 250 MHz LOW LEVEL CLAMP3 OUTPUT REFERRED 1 dB COMPRESSION POINT @ 70 MHz HIGH LEVEL CLAMP4 OUTPUT REFERRED 1 dB COMPRESSION POINT @ 250 MHz HIGH LEVEL CLAMP4 OUTPUT SLEW RATE INPUT IMPEDANCE (REAL) INPUT CAPACITANCE OUTPUT IMPEDANCE (REAL) OUTPUT CAPACITANCE NOISE FIGURE LOW LEVEL CLAMP MAXIMUM OUTPUT @ 70 MHz3, 5 HIGH LEVEL CLAMP MAXIMUM OUTPUT @ 70 MHz LOW LEVEL CLAMP MAXIMUM OUTPUT @ 250 MHz – 2– REV. 0 AD6630 Parameter HIGH LEVEL CLAMP MAXIMUM OUTPUT @ 250 MHz PHASE VARIATION CMRR PSRR 8 7 6 4, 5 Temp Full +25°C +25°C +25°C Test Level IV V V V Min Typ 11.2 9 50 30 Max 12.2 Units dBm Degree dB dB NOTES 1 All specifications are valid across the operating frequency range when the source and load impedance are a conjugate match to the amplifier’s input and output impedance. 2 Test is for two tones separated by 1 MHz for IFs at 70 MHz and 250 MHz at –23 dBm per tone input. 3 Low Level Clamp is selected by connecting pin CLLO to the negative supply, while pin CLHI is left floating. Clamping can be set at lower levels by connecting pin CLLO and CLHI to the negative supply through an external resistor. 4 High Level Clamp is selected by connecting pin CLHI to the negative supply, while pin CLLO is left floating, this allows the maximum linear range of the device to be utilized. 5 Output clamp levels are measured for hard clamping with a +3 dBm input level. Valid for a maximum input level of +8 dBm/200 Ω = 3.2 V p-p—differential. 6 Measured as the change in output phase when the input level is changed from –53 dBm to +8 dBm (i.e., from linear operation to clamping). 7 Ratio of the differential output signal (referenced to the input) to the common-mode input signal presented to all input pins. 8 Ratio of signal on supply to differential output (