150 MSPS, Wideband,
Digital Downconverter (DDC)
AD6636
Synchronous serial I/O operation (SPI®-, SPORT-compatible)
Supports 8-bit or 16-bit microport modes
3.3 V I/O, 1.8 V CMOS core
User-configurable, built-in, self-test (BIST) capability
JTAG boundary scan
FEATURES
4/6 independent wideband processing channels
Processes 6 wideband carriers (UMTS, CDMA2000)
4 single-ended or 2 LVDS parallel input ports
(16 linear bit plus 3-bit exponent) running at 150 MHz
Supports 300 MSPS input using external interface logic
Three 16-bit parallel output ports operating up to 200 MHz
Real or complex input ports
Quadrature correction and dc correction for complex inputs
Supports output rate up to 34 MSPS per channel
RMS/peak power monitoring of input ports
Programmable attenuator control for external gain ranging
3 programmable coefficient FIR filters per channel
2 decimating half-band filters per channel
6 programmable digital AGC loops with 96 dB range
APPLICATIONS
Multicarrier, multimode digital receivers
GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA,
WiMAX
Micro and pico cell systems, software radios
Broadband data applications
Instrumentation and test equipment
Wireless local loops
In-building wireless telephony
EXPA [2:0]
CLKB
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
EXPB [2:0]
CLKC
ADC C/CI
NCO
CMOS
REAL
PORTS
A, B,
C, D
EXPD [2:0]
LVDS
PORTS
AB, CD
SYNC [3:0]
I,Q
CORR.
FIR2
HB2
M = Byp, 2
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
PEAK/
RMS
MEAS.
RESET
FIR1
HB1
M = Byp, 2
NCO
CMOS
EXPC [2:0] COMPLEX
PORTS
(AI, AQ)
CLKD (BI, BQ)
ADC D/CQ
CIC5
M = 1-32
DATA ROUTER MATRIX
ADC B/AQ
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
PA
LHB
L = Byp, 2
AGC
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
PARALLEL PORTS
ADC A/AI
INPUT MATRIX
CLKA
DATA ROUTING
FUNCTIONAL BLOCK DIAGRAM
PB
PC
PLL CLOCK
MULTIPLIER
NOTE: CHANNELS RENDERED AS
16-BIT
MICROPORT INTERFACE
SPORT/SPI INTERFACE
ARE AVAILABLE ONLY IN 6-CHANNEL PART
M = DECIMATION
JTAG
L = INTERPOLATION
04998-0-001
PRN GEN
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD6636
TABLE OF CONTENTS
General Description ......................................................................... 4
FIR Half-Band Block.................................................................. 30
Specifications..................................................................................... 6
Intermediate Data Router ......................................................... 33
Recommended Operating Conditions ...................................... 6
MonoRate RAM Coefficient Filter (MRCF)........................... 33
Electrical Characteristics............................................................. 6
Decimating RAM Coefficient Filter (DRCF) ......................... 34
General Timing Characteristics, ................................................ 7
Channel RAM Coefficient Filter (CRCF) ............................... 36
Microport Timing Characteristics, ............................................ 8
Interpolating Half-Band Filter.................................................. 38
Serial Port Timing Characteristics, , ........................................... 9
Output Data Router ................................................................... 38
Explanation of Test Levels for Specifications............................ 9
Automatic Gain Control............................................................ 40
Absolute Maximum Ratings.......................................................... 10
Parallel Port Output ................................................................... 44
Thermal Characteristics ............................................................ 10
User-Configurable, Built-In Self-Test (BIST)......................... 48
ESD Caution................................................................................ 10
Chip Synchronization ................................................................ 48
Pin Configuration and Function Descriptions........................... 11
Serial Port Control ..................................................................... 49
Pin Listing for Power, Ground, Data, and Address Buses..... 13
Microport .................................................................................... 58
Timing Diagrams............................................................................ 14
Memory Map .................................................................................. 60
Theory of Operation ...................................................................... 20
Reading the Memory Map Table.............................................. 60
ADC Input Port .......................................................................... 20
Global Register Map .................................................................. 62
PLL Clock Multiplier ................................................................. 21
Input Port Register Map ............................................................ 65
ADC Gain Control ..................................................................... 22
Channel Register Map ............................................................... 68
ADC Input Port Monitor Function.......................................... 23
Output Port Register Map ......................................................... 73
Quadrature I/Q Correction Block............................................ 25
Design Notes ................................................................................... 77
Input Crossbar Matrix ............................................................... 27
Outline Dimensions ....................................................................... 79
Numerically Controlled Oscillator (NCO) ............................. 27
Ordering Guide .......................................................................... 79
Fifth-Order CIC Filter ............................................................... 29
Rev. A | Page 2 of 80
AD6636
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Changes to Format ............................................................. Universal
Changes to Figure 1...........................................................................1
Changes to Applications...................................................................1
Changes to General Description .....................................................4
Changes to Table 3 ............................................................................7
Changes to Table 5 ............................................................................9
Changes to Table 8 ..........................................................................11
Changes to Figure 17 ......................................................................18
Changes to Figure 18 and Figure 19 .............................................19
Changes to Figure 25 ......................................................................23
Changes to Mean Power Mode (Control Bits 01) Section .........24
Changes to NCO Frequency Section............................................27
Changes to Figure 30 ......................................................................28
Changes to 6-Tap Fixed Coefficient Filter (FIR2) Section ........32
Changes to Decimate-by-2, Half-Band Filter (HB2) Section....32
Changes to Table 17 ........................................................................32
Changes to Clock Rate Section......................................................34
Changes to Programming DRCF Register for a Symmetric
Filter Section ...................................................................................35
Changes to Channel RAM Coefficient Filter (CRCF)
Section ..............................................................................................36
Changes to Programming CRCF Register for a Symmetrical
Filter Section ....................................................................................37
Changes to Desired Signal Level Mode Section..........................41
Changes to Figure 41 ......................................................................45
Changes to Figure 42 and Figure 43 .............................................46
Changes to Start with Soft Sync Section ......................................48
Changes to Hop with Soft Sync Section.......................................49
Changes to Hop with Pin Sync Section........................................49
Replaced Serial Control Port Section ...........................................49
Changes to Intel (INM) Mode Section.........................................58
Changes to Motorola (MNM) Mode Section..............................59
Changes to Table 30 ........................................................................61
Changes to Channel Register Map Section .................................68
Changes to AGC Control Register Section ....................71
Changes to BIST Control Section....................................73
Changes to Parallel Port Output Control .......................73
Changes to Table 44 ........................................................................74
Changes to Design Notes ...............................................................77
Changes to Figure 59 ......................................................................77
8/04—Revision 0: Initial Version
Rev. A | Page 3 of 80
AD6636
GENERAL DESCRIPTION
The AD6636 is a digital downconverter intended for IF
sampling or oversampled baseband radios requiring wide
bandwidth input signals. The AD6636 has been optimized for
the demanding filtering requirements of wideband standards,
such as CDMA2000, UMTS, and TD-SCDMA, but is flexible
enough to support wider standards such as WiMAX. The
AD6636 is designed for radio systems that use either an IF
sampling ADC or a baseband sampling ADC.
The AD6636 channels have the following signal processing
stages: a frequency translator, a fifth-order cascaded integrated
comb filter, two sets of cascaded fixed-coefficient FIR and halfband filters, three cascaded programmable coefficient sum-ofproduct FIR filters, an interpolating half-band filter (IHB), and
a digital automatic gain control (AGC) block. Multiple modes
are supported for clocking data into and out of the chip and
provide flexibility for interfacing to a wide variety of digitizers.
Programming and control are accomplished via serial or
microport interfaces.
Input ports can take input data at up to 150 MSPS. Up to
300 MSPS input data can be supported using two input ports
(some external interface logic is required) and two internal
channels processing in tandem. Biphase filtering in the output
data router is selected to complete the combined filtering mode.
The four input ports can operate in CMOS mode, or two ports
can be combined for LVDS input mode. The maximum input
data rate for each input port is 150 MHz.
Frequency translation is accomplished with a 32-bit complex
numerically controlled oscillator (NCO). It has greater than
110 dBc SFDR. This stage translates either a real or complex
input signal from intermediate frequency (IF) to a baseband
complex digital output. Phase and amplitude dither can be
enabled on-chip to improve spurious performance of the NCO.
A 16-bit phase-offset word is available to create a known phase
relationship between multiple AD6636 chips or channels. The
NCO can also be bypassed so that baseband I and Q inputs can
be provided directly from baseband sampling ADCs through
input ports.
Following frequency translation is a fifth-order CIC filter with a
programmable decimation between 1 and 32. This filter is used
to lower the sample rate efficiently, while providing sufficient
alias rejection at frequencies with higher frequency offsets from
the signal of interest.
Following the CIC5 are two sets of filters. Each set has a nondecimating FIR filter and a decimate-by-2 half-band filter. The
FIR1 filter provides about 30 dB of rejection, while the HB1
filter provides about 77 dB of rejection. They can be used
together to achieve a 107 dB stop band alias rejection, or they
can be individually bypassed to save power. The FIR2 filter
provides about 30 dB of rejection, while the HB2 filter provides
about 65 dB of rejection. The filters can be used either together
to achieve more than 95 dB stop band alias rejection, or can be
individually bypassed to save power. FIR1 and HB1 filters can
run with a maximum input rate of 150 MSPS. In contrast, FIR2
and HB2 can run with a maximum input rate of 75 MSPS (input
rate to FIR2 and HB2 filters).
The programmable filtering is divided into three cascaded RAM
coefficient filters (RCFs) for flexible and power efficient
filtering. The first filter in the cascade is the MRCF, consisting
of a programmable nondecimating FIR. It is followed by
programmable FIR filters (DRCF) with decimation from 1 to
16. They can be used either together to provide high rejection
filters, or independently to save power. The maximum input
rate to the MRCF is one-fourth of the PLL clock rate.
The channel RCF (CRCF) is the last programmable FIR filter
with programmable decimation from 1 to 16. It typically is used
to meet the spectral mask requirements for the air standard of
interest. This could be an RRC, antialiasing filter or any other
real data filter. Decimation in preceding blocks is used to keep
the input rate of this stage as low as possible for the best filter
performance.
The last filter stage in the chain is an interpolate-by-2 half-band
filter, which is used to up-sample the CRCF output to produce
higher output oversampling. Signal rejection requirements for
this stage are relaxed because preceding filters have filtered the
blockers and adjacent carriers already.
Each input port of the AD6636 has its own clock used for
latching onto the input data, but the Input Port A clock (CLKA)
is also used as the input for an on-board PLL clock multiplier.
The output of the PLL clock is used for processing all filters and
processing blocks beyond the data router following the CIC
filter. The PLL clock can be programmed to have a maximum
clock rate of 200 MHz.
A data routing block (DR) is used to distribute data from the
CICs to the various channel filters. This block allows multiple
back-end filter chains to work together to process high
bandwidth signals or to make even sharper filter transitions
than a single channel can perform. It can also allow complex
filtering operations to be achieved in the programmable filters.
The digital AGC provides the user with scaled digital outputs
based on the rms level of the signal present at the output of the
digital filters. The user can set the requested level and time
constant of the AGC loop for optimum performance of the
postprocessor. This is a critical function in the base station for
CDMA applications where the power level must be well
controlled going into the RAKE receivers. It has programmable
clipping and rounding control to provide different output
resolutions.
Rev. A | Page 4 of 80
AD6636
PRODUCT HIGHLIGHTS
The overall filter response for the AD6636 is the composite of
all the combined filter stages. Each successive filter stage is
capable of narrower transition bandwidths but requires a
greater number of CLK cycles to calculate the output. More
decimation in the first filter stage minimizes overall power
consumption. Data from the device is interfaced to a
DSP/FPGA/baseband processor via either high speed parallel
ports (preferred) or a DSP-compatible microprocessor interface.
•
Six independent digital filtering channels
•
101 dB SNR noise performance, 110 dB spurious
performance
•
Four input ports capable of 150 MSPS input data rates
•
RMS/peak power monitoring of input ports and 96 dB
range AGCs before the output ports
The AD6636 is available both in 4-channel and 6-channel
versions. The data sheet primarily discusses the 6-channel part.
The only difference between the 6-channel and 4-channel
devices is that Channel 4 and Channel 5 are not available on the
4-channel version, (see Figure 1). The 4-channel device still has
the same input ports, output ports, and memory map. The
memory map section for Channel 4 and Channel 5 can be
programmed and read back, but it serves no purpose.
•
Three programmable RAM coefficient filters, three halfband filters, two fixed coefficient filters, and one fifthorder CIC filter per channel
•
Complex filtering and biphase filtering (300 MSPS ADC
input) by combining filtering capability of multiple
channels
•
Three 16-bit parallel output ports operating at up to a
200 MHz clock
•
Blackfin®-compatible and TigerSHARC®-compatible 16-bit
microprocessor port
•
Synchronous serial communications port is compatible
with most serial interface standards, SPORT, SPI, and SSR
Rev. A | Page 5 of 80
AD6636
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Table 1.
Parameter
VDDCORE
VDDIO
TAMBIENT
Temp
Full
Full
Full
Test Level
IV
IV
IV
Min
1.7
3.0
−40
Typ
1.8
3.3
+25
Max
1.9
3.6
+85
Unit
V
V
°C
Temp
Test Level
Min
Typ
Max
Unit
Full
Full
Full
Full
Full
25°C
IV
IV
IV
IV
IV
V
3.3
2.0
−0.3
3.6
+0.8
10
10
V CMOS
V
V
μA
μA
pF
Full
Full
Full
IV
IV
IV
3.3
2.0
25°C
25°C
V
V
450
50
mA
mA
25°C
25°C
V
V
400
25
mA
mA
25°C
25°C
V
V
250
15
mA
mA
25°C
25°C
V
V
175
10
mA
mA
25°C
25°C
25°C
25°C
V
V
V
V
975
800
500
350
mW
mW
mW
mW
ELECTRICAL CHARACTERISTICS 1
Table 2.
Parameter
LOGIC INPUTS (NOT 5 V TOLERANT)
Logic Compatibility
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
LOGIC OUTPUTS
Logic Compatibility
Logic 1 Voltage (IOH = 0.25 mA)
Logic 0 Voltage (IOL = 0.25 mA)
SUPPLY CURRENTS
WCDMA (61.44 MHz) Example1
IVDDCORE
IVDDIO
CDMA 2000 (61.44 MHz) Example1
IVDDCORE
IVDDIO
TDS-CDMA (76.8 MHz) Example1, 2
IVDDCORE
IVDDIO
GSM (65 MHz) Example1, 2
IVDDCORE
IVDDIO
TOTAL POWER DISSIPATION
WCDMA (61.44 MHz)1
CDMA2000 (61.44 MHz)1
TD-SCDMA (76.8 MHz)1, 2
GSM (65 MHz)1, 2
1
2
One input port, all six channels, and the relevant signal processing blocks are active.
PLL is turned off for power savings.
Rev. A | Page 6 of 80
1
1
4
VDDIO − 0.2
0.2
0.4
V CMOS
V
V
AD6636
GENERAL TIMING CHARACTERISTICS 1, 2
Table 3.
Parameter
CLK TIMING REQUIREMENTS
tCLK
CLKx Period (x = A, B, C, D)
tCLKL
CLKx Width Low (x = A, B, C, D)
tCLKH
CLKx Width High (x = A, B, C, D)
tCLKSKEW
CLKA to CLKx Skew (x = B, C, D)
INPUT WIDEBAND DATA TIMING REQUIREMENTS
tSI
INx [15:0] to ↑CLKx Setup Time (x = A, B, C, D)
tHI
INx [15:0] to ↑CLKx Hold Time (x = A, B, C, D)
tSEXP
EXPx [2:0] to ↑CLKx Setup Time (x = A, B, C, D)
tHEXP
EXPx [2:0] to ↑CLKx Hold Time (x = A, B, C, D)
tDEXP
↑CLKx to EXPx[2:0] Delay (x = A, B, C, D)
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER)
tDPREQ
↑PCLK to ↑Px REQ Delay (x = A, B, C)
tDPP
↑PCLK to Px [15:0] Delay (x = A, B, C)
tDPIQ
↑PCLK to Px IQ Delay (x = A, B, C)
tDPCH
↑PCLK to Px CH[2:0] Delay (x = A, B, C)
tDPGAIN
↑PCLK to Px Gain Delay (x = A, B, C)
tSPA
Px ACK to ↑PCLK Setup Time (x = A, B, C)
tHPA
Px ACK to ↑PCLK Hold Time (x = A, B, C)
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE)
tPCLK
PCLK Period
tPCLKL
PCLK Low Period
tPCLKH
PCLK High Period
tDPREQ
↑PCLK to ↑Px REQ Delay (x = A, B, C)
tDPP
↑PCLK to Px [15:0] Delay (x = A, B, C)
tDPIQ
↑PCLK to Px IQ Delay (x = A, B, C)
tDPCH
↑PCLK to Px CH[2:0] Delay (x = A, B, C)
tDPGAIN
↑PCLK to Px Gain Delay (x = A, B, C)
tSPA
Px ACK to ↓PCLK Setup Time (x = A, B, C)
tHPA
Px ACK to ↓PCLK Hold Time (x = A, B, C)
MISC PINS TIMING REQUIREMENTS
tRESET
RESET Width Low
tDIRP
CPUCLK/SCLK to IRP Delay
tSSYNC
SYNC(0, 1, 2, 3) to ↑CLKA Setup Time
tHSYNC
SYNC(0, 1, 2, 3) to ↑CLKA Hold Time
1
2
Temp
Test Level
Min
Typ
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
I
IV
IV
IV
IV
IV
IV
IV
IV
IV
6.66
1.71
1.70
tCLK − 1.3
0.5 × tCLK
0.5 × tCLK
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
1.77
2.07
0.48
0.38
0.23
4.59
0.90
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
5.0
1.7
0.7
4.72
4.8
4.83
4.88
5.08
6.09
1.0
Full
Full
Full
Full
IV
V
IV
IV
30
All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.
CLOAD = 40 pF on all outputs, unless otherwise noted.
Rev. A | Page 7 of 80
0.75
1.13
3.37
1.11
5.98
Unit
ns
ns
ns
ns
10.74
3.86
5.29
5.49
5.35
4.95
0.5 × tPCLK
0.5 × tPCLK
8.87
8.48
10.94
10.09
11.49
7.5
0.87
0.67
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD6636
MICROPORT TIMING CHARACTERISTICS 1, 2
Table 4.
Parameter
MICROPORT CLOCK TIMING REQUIREMENTS
tCPUCLK
CPUCLK Period
tCPUCLKL
CPUCLK Low Time
tCPUCLKH CPUCLK High Time
INM MODE WRITE TIMING (MODE = 0)
tSC
Control 3 to ↑CPUCLK Setup Time
tHC
Control3 to ↑CPUCLK Hold Time
tSAM
Address/Data to ↑CPUCLK Setup Time
tHAM
Address/Data to ↑CPUCLK Hold Time
tDRDY
↑CPUCLK to RDY (DTACK) Delay
tACC
Write Access Time
INM MODE READ TIMING (MODE = 0)
tSC
Control3 to ↑CPUCLK Setup Time
tHC
Control3 to ↑CPUCLK Hold Time
tSAM
Address to ↑CPUCLK Setup Time
tHAM
Address to ↑CPUCLK Hold Time
tDD
↑CPUCLK to Data Delay
tDRDY
↑CPUCLK to RDY (DTACK) Delay
tACC
Read Access Time
MNM MODE WRITE TIMING (MODE = 1)
tSC
Control3 to ↑CPUCLK Setup Time
tHC
Control3 to ↑CPUCLK Hold Time
tSAM
Address/Data to ↑CPUCLK Setup Time
tHAM
Address/Data to ↑CPUCLK Hold Time
tDDTACK
↑CPUCLK to DTACK (RDY) Delay
tACC
Write Access Time
MNM MODE READ TIMING (MODE = 1)
tSC
Control3 to ↑CPUCLK Setup Time
tHC
Control3 to ↑CPUCLK Hold Time
tSAM
Address to ↑CPUCLK Setup Time
tHAM
Address to ↑CPUCLK Hold Time
tDD
CPUCLK to Data Delay
tDDTACK
↑CPUCLK to DTACK (RDY) Delay
tACC
Read Access Time
Temp
Test Level
Min
Typ
Full
Full
Full
IV
IV
IV
10.0
1.53
1.70
0.5 × tCPUCLK
0.5 × tCPUCLK
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
0.80
0.09
0.76
0.20
3.51
6.72
ns
ns
ns
ns
ns
Full
IV
3 × tCPUCLK
9 × tCPUCLK
ns
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
IV
1.00
0.03
0.80
0.20
4.50
6.72
ns
ns
ns
ns
ns
ns
Full
IV
3 × tCPUCLK
9 × tCPUCLK
ns
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
1.00
0.00
0.00
0.57
4.10
5.72
ns
ns
ns
ns
ns
Full
IV
3 × tCPUCLK
9 × tCPUCLK
ns
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
IV
1.00
0.00
0.00
0.57
4.20
6.03
ns
ns
ns
ns
ns
ns
Full
IV
3 × tCPUCLK
9 × tCPUCLK
ns
1
Rev. A | Page 8 of 80
Unit
ns
ns
ns
5.0
5.0
All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.
CLOAD = 40 pF on all outputs, unless otherwise noted.
3
Specification pertains to control signals: R/W (WR), DS (RD), and CS.
2
Max
AD6636
SERIAL PORT TIMING CHARACTERISTICS 1, 2 , 3
Table 5.
Parameter
SERIAL PORT CLOCK TIMING REQUIREMENTS
tSCLK
SCLK Period
tSCLKL
SCLK Low Time
tSCLKH
SCLK High Time
SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0)
tSSDI
SDI to ↑SCLK Setup Time
tHSDI
SDI to ↑SCLK Hold Time
tSSCS
SCS to ↑SCLK Setup Time
tHSCS
SCS to ↑SCLK Hold Time
tDSDO
↑SCLK to SDO Delay Time
SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1)
tSSDI
SDI to ↑SCLK Setup Time
tHSDI
SDI to ↑SCLK Hold Time
tSSRFS
SRFS to ↓SCLK Setup Time
tHSRFS
SRFS to ↓SCLK Hold Time
tSSTFS
STFS to ↓SCLK Setup Time
tHSTFS
STFS to ↑SCLK Hold Time
tSSCS
SCS to ↑SCLK Setup Time
1
2
3
Temp
Test Level
Min
Typ
Full
Full
Full
IV
IV
IV
10.0
1.60
1.60
0.5 × tSCLK
0.5 × tSCLK
Full
Full
Full
IV
IV
IV
1.30
0.40
4.12
ns
ns
ns
Full
IV
−2.78
ns
Full
IV
4.28
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
0.80
0.40
1.60
−0.13
1.60
−0.30
4.12
tHSCS
SCS to ↑SCLK Hold Time
Full
IV
−2.76
tDSDO
↑SCLK to SDO Delay Time
Full
IV
4.29
All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.
CLOAD = 40 pF on all outputs, unless otherwise noted.
SCLK rise/fall time should be 3 ns maximum.
EXPLANATION OF TEST LEVELS FOR SPECIFICATIONS
Table 6.
Test Level
I
II
III
IV
V
VI
Description
100% production tested.
100% production tested at 25°C, and sample tested at specified temperatures.
Sample tested only.
Parameter guaranteed by design and analysis.
Parameter is typical value only.
100% production tested at 25°C, and sampled tested at temperature extremes.
Rev. A | Page 9 of 80
Max
Unit
ns
ns
ns
7.96
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.95
ns
AD6636
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
ELECTRICAL
VDDCORE Supply Voltage
(Core Supply)
VDDIO Supply Voltage
(Ring or IO Supply)
Input Voltage
Output Voltage
Load Capacitance
ENVIRONMENTAL
Operating Temperature
Range (Ambient)
Maximum Junction
Temperature Under Bias
Storage Temperature
Range (Ambient)
Rating
2.2 V
4.0 V
−0.3 to +3.6 V (Not 5 V Tolerant)
−0.3 to VDDIO + 0.3 V
200 pF
−40°C to +85°C
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
256-ball CSP_BGA package:
θJA = 25.4°C /W, no airflow
125°C
θJA = 23.3°C /W, 0.5 m/s airflow
−65°C to +150°C
θJA = 22.6°C /W, 1.0 m/s airflow
θJA = 21.9°C /W, 2.0 m/s airflow
Thermal measurements made in the horizontal position on a
4-layer board with vias.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 10 of 80
AD6636
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
GND
INC3
IND4
IND7
CLKD
CLKC
IND11
GND
VDDCORE
IND14
IND15
SYNC1
TDO
PBGAIN
PB11
GND
A
B
IND0
VDDIO
INC2
IND5
IND6
IND8
IND10
IND12
IND13
INC14
SYNC3
SYNC0
TRST
PBCH2
VDDIO
PB12
B
C
EXPA1
EXPD1
INC0
INC1
IND3
INC5
IND9
INC10
INC13
SYNC2
TMS
TCLK
PBCH0
PB8
PB15
PB10
C
D
EXPB0
EXPC2
EXPC1
EXPD0
IND2
INC4
INC7
INC9
INC12
TDI
PBCH1
PBIQ
PB14
PB9
PB13
PACH1
D
E
INA14
INA15
EXPA0
LVDS_
RSET
GND
IND1
INC6
INC8
INC11
INC15
PBREQ
PBACK
PB4
PB5
PB1
PCLK
E
F
INA12
INA13
EXPB1
EXPC0
EXPD2
GND
VDDIO
VDDIO
VDDIO
VDDIO
GND
PB6
PB0
PB7
PAREQ
PA0
F
G
INA11
INB13
INB15
EXPB2
EXPA2
VDDCORE
GND
GND
GND
GND
VDDCORE
PB3
PAGAIN
PB2
PACH0
PA2
G
H VDDCORE
INA10
INB12
INB11
INB14
VDDCORE
GND
GND
GND
GND
VDDCORE
PACH2
PAIQ
PAACK
PA1
GND
H
J
GND
INA9
INB10
INB8
INB9
VDDCORE
GND
GND
GND
GND
VDDCORE
PA3
PA7
PA5
PA4
VDDCORE
J
K
CLKA
INA8
INA7
INB6
INB7
VDDCORE
GND
GND
GND
GND
VDDCORE
PA12
PA15
PA9
PA8
PA6
K
L
CLKB
INA6
INB4
INB1
INB3
GND
VDDIO
VDDIO
VDDIO
VDDIO
GND
PC3
PCACK
PCCH1
PA13
PA10
L
M
INA5
INB5
INB2
INB0
GND
DTACK
(RDY, SDO)
D13
D15
D5
A5
PC12
PC7
PC2
PC0
PCCH0
PA11
M
N
INA4
INA3
INA0
R/W (WR,
STFS)
CS (SCS)
CHIPID2
D12
D2
D1
A4
A0 (SDI)
PC15
PC5
PC1
PCCH2
PA14
N
P
INA2
INA1
RESET
DS (RD,
SRFS)
SMODE
CHIPID3
GND
D9
D4
A6
A2
PC11
PC10
PC4
PCIQ
PCGAIN
P
R
CPUCLK
(SCLK)
VDDIO
MSB_
FIRST
EXT_
FILTER
CHIPID1
D14
D10
D11
D6
D0
A3
A1
PC9
PC6
VDDIO
PCREQ
R
T
GND
IRP
MODE
CHIPID0
D7
D8
D3
VDDCORE
GND
GND
A7
PC14
PC13
PC8
GND
GND
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
= VDDCORE
= VDDIO
= GROUND
04998-0-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. CSP_BGA Pin Configuration
Table 8. Pin Function Descriptions
Mnemonic
Type
Pin No.
POWER SUPPLY
VDDCORE
Power
See Table 9
VDDIO
Power
See Table 9
GND
Ground
See Table 9
INPUT (ADC) PORTS (CMOS/LVDS)
CLKA
Input
K1
CLKB
CLKC
CLKD
INA[0:15]
INB[0:15]
INC[0:15]
IND[0:15]
EXPA[0:2]
Input
Input
Input
Input
Input
Input
Input
Bidirectional
L1
A6
A5
See Table 9
See Table 9
See Table 9
See Table 9
E3, C1, G5
Function
1.8 V Digital Core Supply.
3.3 V Digital I/O Supply.
Digital Core and I/O Ground.
Clock for Input Port A. Used to clock INA[15:0] and EXPA[2:0] data. Additionally, this clock
is used to drive internal circuitry and PLL clock multiplier.
Clock for Input Port B. Used to clock INB[15:0] and EXPB[2:0] data.
Clock for Input Port C. Used to clock INC[15:0] and EXPC[2:0] data.
Clock for Input Port D. Used to clock IND[15:0] and EXPD[2:0] data.
Input Port A (Parallel).
Input Port B (Parallel).
Input Port C (Parallel).
Input Port D (Parallel).
Exponent Bus Input Port A. Gain control output.
Rev. A | Page 11 of 80
AD6636
Mnemonic
EXPB[0:2]
EXPC[0:2]
EXPD[0:2]
CLKA, CLKB
CLKC, CLKD
INA[0:15],
INB[0:15]
INC[0:15],
IND[0:15]
OUTPUT PORTS
PCLK
PA[0:15]
PACH[0:2]
Type
Bidirectional
Bidirectional
Bidirectional
Input
Input
LVDS Input
Pin No.
D1, F3, G4
F4, D3, D2
D4, C2, F5
K1, L1
A6, A5
See Table 9
LVDS Input
See Table 9
Bidirectional
Output
Output
PAIQ
PAGAIN
PAACK
PAREQ
PB[0:15]
PBCH[0:2]
Output
Output
Input
Output
Output
Output
PBIQ
PBGAIN
PBACK
PBREQ
PC[0:15]
PCCH[0:2]
Output
Output
Input
Output
Output
Output
PCIQ
PCGAIN
PCACK
PCREQ
MISC PINS
RESET
IRP 1
SYNC[0:3]
Output
Output
Input
Output
E16
See Table 9
G15, D16,
H12
H13
G13
H14
F15
See Table 9
C13, D11,
B14
D12
A14
E12
E11
See Table 9
M15, L14,
N15
P15
P16
L13
R16
Input
Output
Input
LVDS_RSET
Input
EXT_FILTER
Input
MICROPORT CONTROL
D[0:15]
Bidirectional
A[0:7]
Input
Input
DS (RD)
1
Output
DTACK (RDY)
Function
Exponent Bus Input Port B. Gain control output.
Exponent Bus Input Port C. Gain control output.
Exponent Bus Input Port D. Gain control output.
LVDS Differential Clock for LVDS_A Input Port (LVDS_CLKA+, LVDS_CLKA−).
LVDS Differential Clock for LVDS_C Input Port (LVDS_CLKC+, LVDS_CLKC−).
In LVDS input mode, INA[0:15] and INB[0:15] form a differential pair LVDS_A+[0:15]
(positive node) and LVDS_A–[0:15] (negative node), respectively.
In LVDS input mode, INC[0:15] and IND[0:15] form a differential pair LVDS_C+[0:15]
(positive node) and LVDS_C–[0:15] (negative node), respectively.
Parallel Output Port Clock. Master mode output, and slave mode input.
Parallel Output Port A Data Bus.
Channel Indicator Output Port A.
Parallel Port A I/Q Data Indicator. Logic 1 indicates I data on data bus.
Parallel Port A Gain Word Output Indicator. Logic 1 indicates gain word on data bus.
Parallel Port A Acknowledge (Active High).
Parallel Port A Request (Active High).
Parallel Output Port B Data Bus.
Channel Indicator Output Port B.
Parallel Port B I/Q Data Indicator. Logic 1 indicates I data on data bus.
Parallel Port B Gain Word Output Indicator. Logic 1 indicates gain word on data bus.
Parallel Port B Acknowledge (Active High).
Parallel Port B Request (Active High).
Parallel Output Port C Data Bus.
Channel Indicator Output Port C.
Parallel Port C I/Q Data Indicator. Logic 1 indicates I data on data bus.
Parallel Port C Gain Word Output Indicator. Logic 1 indicates gain word on data bus.
Parallel Port C Acknowledge (Active High).
Parallel Port C Request (Active High).
P3
T2
B12, A12,
C10, B11
E4
R4
Master Reset (Active Low).
Interrupt Pin (Open Drain Output, Needs External Pull-Up Resistor 1 kΩ).
Synchronization Inputs. SYNC pins are independent of channels or input ports and
independent of each other.
LVDS Resistor Set Pin (Analog Pin). See Design Notes.
PLL Loop Filter (Analog Pin). See Design Notes.
See Table 9
See Table 9
P4
M6
Bidirectional Microport Data. This bus is three-stated when CS is high.
Microport Address Bus.
Active Low Data Strobe when MODE = 1. Active low read strobe when MODE = 0.
Active Low Data Acknowledge when MODE = 1. Microport status pin when MODE = 0.
Open drain output, needs external pull-up resistor 1 kΩ.
Read/Write Strobe when MODE = 1. Active low write strobe when MODE = 0.
Mode Select Pin. When SMODE = 0: Logic 0 = Intel mode; Logic 1 = Motorola mode.
When SMODE = 1: Logic 0 = SPI mode; Logic 1 = SPORT mode.
Active Low Chip Select. Logic 1 three-states the microport data bus.
Microport CLK Input (Input Only).
Chip ID Input Pins.
R/W (WR)
MODE
Input
Input
N4
T3
CS
CPUCLK
CHIPID[0:3]
Input
Input
Input
N5
R1
T4, R5, N6,
P6
Rev. A | Page 12 of 80
AD6636
Mnemonic
Type
SERIAL PORT CONTROL
SCLK
Input
SDO1
Output
SDI 2
Input
STFS
Input
SRFS
Input
Input
SCS
MSB_FIRST
Input
SMODE
JTAG
TRST1
TCLK2
TMS1
TDO
TDI1
1
2
Pin No.
Function
R1
M6
N11
N4
P4
N5
R3
Input
P5
Serial Clock.
Serial Port Data Output (Open drain output, needs external pull-up resistor 1KΩ).
Serial Port Data Input.
Serial Transmit Frame Sync.
Serial Receive Frame Sync.
Serial Chip Select.
Select MSB First into SDI Pin and MSB First Out of SDO Pin.
Logic 0 = MSB first; Logic 1 = LSB first.
Serial Mode Select. Pull high when serial port is used and low when microport is used.
Input
Input
Input
Output
Input
B13
C12
C11
A13
D10
Test Reset Pin. Pull low when JTAG is not used.
Test Clock.
Test Mode Select.
Test Data Output. Three-stated when JTAG is in reset.
Test Data Input.
Pin with a pull-up resistor of nominal 70 kΩ.
Pin with a pull-down resistor of nominal 70 kΩ.
PIN LISTING FOR POWER, GROUND, DATA, AND ADDRESS BUSES
Table 9.
Mnemonic
VDDCORE
VDDIO
GND
INA[0:15]
INB[0:15]
INC[0:15]
IND[0:15]
PA[0:15]
PB[0:15]
PC[0:15]
D[0:15]
A[0:7]
Pin No.
A9, G6, G11, H1, H6, H11, J6, J11, J16, K6, K11, T8
B2, B15, F7, F8, F9, F10, L7, L8, L9, L10, R2, R15
A1, A8, A16, E5, F6, F11, G7, G8, G9, G10, H7, H8, H9, H10, H16, J1, J7, J8, J9, J10, K7, K8, K9, K10, L6, L11,
M5, P7, T1, T9, T10, T15, T16
N3, P2, P1, N2, N1, M1, L2, K3, K2, J2, H2, G1, F1, F2, E1, E2
M4, L4, M3, L5, L3, M2, K4, K5, J4, J5, J3, H4, H3, G2, H5, G3
C3, C4, B3, A2, D6, C6, E7, D7, E8, D8, C8, E9, D9, C9, B10, E10
B1, E6, D5, C5, A3, B4, B5, A4, B6, C7, B7, A7, B8, B9, A10, A11
F16, H15, G16, J12, J15, J14, K16, J13, K15, K14, L16, M16, K12, L15, N16, K13
F13, E15, G14, G12, E13, E14, F12, F14, C14, D14, C16, A15, B16, D15, D13, C15
M14, N14, M13, L12, P14, N13, R14, M12, T14, R13, P13, P12, M11, T13, T12, N12
R10, N9, N8, T7, P9, M9, R9, T5, T6, P8, R7, R8, N7, M7, R6, M8
N11, R12, P11, R11, N10, M10, P10, T11
Rev. A | Page 13 of 80
AD6636
TIMING DIAGRAMS
04998-0-003
RESET
tRESL
Figure 3. Reset Timing Requirements
tCLKH
04998-0-004
CLKx
tCLKL
Figure 4. CLK Switching Characteristics
(x = A, B, C, D for Individual Input Ports)
tCLK
tCLKL
CLKA
tCLKH
04998-0-005
tCLKSKEW
CLKx
Figure 5. CLK Skew Characteristics
(x = B, C, D for Individual Input Ports)
tCPUCLKH
04998-0-006
CPUCLK
tCPUCLKL
Figure 6. CPUCLK Switching Characteristics
04998-0-007
tSCLKH
SCLK
tSCLKL
Figure 7. SCLK Switching Characteristics
CLKA
tHSYNC
04998-0-008
tSSYNC
SYNC [3:0]
Figure 8. SYNC Timing Inputs
Rev. A | Page 14 of 80
AD6636
tCLK
tCLKL
CLKx
tCLKH
04998-0-009
tDEXP
EXPx[2:0]
Figure 9. Gain Control Word Output Switching Characteristics
(x = A, B, C, D for Individual Input Ports)
CLKx
tSI
tHI
tSEXP
tHEXP
04998-0-010
INx[15:0]
EXPx[15:0]
Figure 10. Input Port Timing for Data
(x = A, B, C, D for Individual Input Ports)
PCLK
tSPA
tHPA
PxACK
tDPREQ
PxREQ
Px [15:0]
PxIQ
I [15:0]
tDPP
tDPP
Q [15:0]
RSSI [11:0]
tDPIQ
tDPP
I [15:0]
Q [15:0]
tDPP
RSSI [11:0]
tDPIQ
tDPCH
PxCH [2:0]
tDPP
tDPCH
PxCH [2:0] = CHANNEL #
PxCH [2:0] = CHANNEL #
tDPGAIN
PxGAIN
Figure 11. Master Mode PxACK to PCLK Switching Characteristics
(x = A, B, C, D for Individual Output Ports)
Rev. A | Page 15 of 80
tDPGAIN
04998-0-011
tDPP
AD6636
PCLK
PxACK
tDPREQ
TIED LOGIC HIGH ALL THE TIME
PxREQ
tDPP
I [15:0]
tDPP
Q [15:0]
tDPP
RSSI [11:0]
I [15:0]
tDPIQ
PxIQ
Q [15:0]
tDPP
RSSI [11:0]
tDPIQ
tDPCH
PxCH [2:0]
tDPP
tDPCH
PxCH [2:0] = CHANNEL #
PxCH [2:0] = CHANNEL #
tDPGAIN
04998-0-012
Px [15:0]
tDPP
tDPGAIN
PxGAIN
Figure 12. Master Mode PxREQ to PCLK Switching Characteristics
CPUCLK
RD
tSC
tHC
tSC
tHC
WR
CS
tSAM
tHAM
A [7:0]
VALID ADDRESS
tSAM
tHAM
D [15:0]
VALID DATA
tDRDY
tACC
NOTE:
tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO 9 CPUCLK CYCLES.
Figure 13. INM Microport Write Timing Requirements
Rev. A | Page 16 of 80
04998-0-013
RDY
AD6636
CPUCLK
tHC
tSC
RD
WR
tHC
tSC
CS
tSAM
A [7:0]
tHAM
VALID ADDRESS
tDD
D [15:0]
VALID DATA
tDRDY
tACC
NOTE:
tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO 9 CPUCLK CYCLES.
04998-0-014
RDY
Figure 14. INM Microport Read Timing Requirements
CPUCLK
tSC
tHC
tSC
tHC
tSC
tHC
DS
R/W
CS
tHAM
tSAM
A [7:0]
VALID ADDRESS
tSAM
D [15:0]
tHAM
VALID DATA
tACC
NOTE:
tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO 9 CPUCLK CYCLES.
Figure 15. MNM Microport Write Timing Requirements
Rev. A | Page 17 of 80
04998-0-015
tDDTACK
DTACK
AD6636
CPUCLK
tSC
tHC
tSC
tHC
DS
R/W
tSC
tHC
tSAM
tHAM
CS
A [7:0]
VALID ADDRESS
tDD
VALID
DATA
D [15:0]
tDDTACK
DTACK
04998-0-016
tACC
NOTE:
tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO 9 CPUCLK CYCLES.
Figure 16. MNM Microport Read Timing Requirements
SCLK
tSSCS
tHSCS
SCS
SMODE
LOGIC 1
tSSDI
SDI
tHSDI
D0
tSSRFS
D1
D2
D3
D4
D5
D6
D7
tHSRFS
MODE
LOGIC 1
Figure 17. SPORT Mode Write Timing Characteristics
Rev. A | Page 18 of 80
04998-0-017
SRFS
AD6636
SCLK
tSSCS
tHSCS
SCS
SMODE
LOGIC 1
tDSDO
SDO
D0
D1
D2
D3
D4
D5
D6
D7
tHSTFS
tSSTFS
04998-0-018
STFS
MODE
LOGIC 1
Figure 18. SPORT Mode Read Timing Characteristics
SCLK
tSSCS
tHSCS
SCS
SMODE
LOGIC 1
tHSDI
tSSDI
SDI
D1
D2
D3
D4
D5
D6
D7
04998-0-019
D0
MODE
LOGIC 0
Figure 19. SPI Mode Write Timing Characteristics
SCLK
SCS
tSSCS
tHSCS
SMODE
LOGIC 0
tDSDO
D0
D1
D2
D3
D4
D5
LOGIC 0
MODE
Figure 20. SPI Mode Read Timing Characteristics
Rev. A | Page 19 of 80
D6
D7
04998-0-020
SDO
AD6636
THEORY OF OPERATION
These four input ports can operate at up to 150 MSPS. Each
input port has its own clock (CLKA, CLKB, CLKC, and CLKD)
used for registering input data into the AD6636. To allow slow
input rates while providing fast processing clock rates, the
AD6636 contains an internal PLL clock multiplier that supplies
the internal signal processing clock. CLKA is used as an input
to the PLL clock multiplier. Additional programmability allows
the input data to be clocked into the part either on the rising
edge or the falling edge of the input clock.
In addition, the front end of the AD6636 contains circuitry that
enables high speed signal-level detection, gain control, and
quadrature I/Q correction. This is accomplished with a unique
high speed level-detection circuit that offers minimal latency
and maximum flexibility to control all four input signals
(typically ADC inputs) individually. The input ports also
provide input power-monitoring functions via various modes
and magnitude and phase I/Q correction blocks. See the
Quadrature I/Q Correction Block section for details.
Each individual processing channel can receive input data from
any of the four input ports individually. This is controlled using
3-bit crossbar mux-select bit words in the ADC input control
register. Each individual channel has a similar 3-bit selection. In
addition to the four input ports, an internal test signal (PN—
pseudorandom noise sequence) can also be selected. This
internal test signal is discussed in the User-Configurable, BuiltIn Self-Test (BIST) section.
Input Data Format
Each input port consists of a 16-bit mantissa and a 3-bit
exponent (16 + 3 floating-point input, or up to 16-bit fixedpoint input). When interfacing to standard fixed-point ADCs,
the exponent bit should either be connected to ground or be
programmed as outputs for gain control output. If connected to
a floating-point ADC (also called gain ranging ADC), the
exponent bits from the ADC can be connected to the input
exponent bits of the AD6636. The mantissa data format is twos
complement, and the exponent is unsigned binary.
The 3-exponent bits are shared with the gain range control bits
in the hardware. When floating-point ADCs are not used, these
three pins on each ADC input port can be used as gain range
control output bits.
Input Timing
The data from each high speed input port is latched either on
the rising edge or the falling edge of the port’s individual CLKx
(where x stands for A, B, C, or D input ports). The ADC clock
invert bit in ADC clock control register selects the edge of the
clock (rising or falling) used to register input data into the
AD6636.
CLKx
tSI
INx [15:0]
EXPx [2:0]
tHI
DATA n
DATA n + 1
04998-0-021
The AD6636 features four identical, independent high speed
ADC input ports named A, B, C, and D. These input ports have
the flexibility to allow independent inputs, diversity inputs, or
complex I/Q inputs. Any of the ADC input ports can be routed
to any of the six tuner channels; that is, any of the six. The
AD6636 channels can receive input data from any of the input
ports. Time-multiplexed inputs on a single port are not
supported in the AD6636.
Figure 21. Input Data Timing Requirements
(Rising Edge of Clock, x = A, B, C, or D for Four Input Ports)
CLKx
tSI
INx [15:0]
EXPx [2:0]
tHI
DATA n
DATA n + 1
04998-0-022
ADC INPUT PORT
Figure 22. Input Data Timing Requirements
(Falling Edge of Clock, x = A, B, C, or D for Four Input Ports)
The clock signals (CLKA, CLKB, CLKC, and CLKD) can
operate at up to 150 MHz. In applications using high speed
ADCs, the ADC sample clock, data valid, or data-ready strobe
are typically used to clock the AD6636.
Connection to Fixed-Point ADC
For fixed-point ADCs, the AD6636 exponent inputs, EXP[2:0],
are not typically used and should be tied low. Alternatively,
because these pins are shared with gain range control bits, if the
gain ranging block is used, these pins can be used as outputs of
the gain range control block. The ADC outputs are tied directly
to the AD6636 inputs, MSB justified. Therefore, for fixed-point
ADCs, the exponents are typically static and no input scaling is
used in the AD6636. Figure 23 shows a typical interconnection.
Rev. A | Page 20 of 80
AD6636
D13 (MSB)
indicate Input Port A, and the complex input bit should be
selected.
IN15
AD6645
When the input ports are paired for complex input operation,
only one set of exponent bits is driven externally with gain
control output. Therefore, when Input Port A and Input Port B
form a complex input, EXPA[2:0] are output and, similarly, for
Input Port C and Input Port D, EXPC[2:0] are output.
14-BIT ADC
AD6636
IN2
IN1
IN0
GAIN RANGING CONTROL
BITS OR GROUNDED
EXPONENT BITS
EXP2
EXP1
EXP0
LVDS Input Ports
04998-0-023
D0 (LSB)
Figure 23. Typical Interconnection of the AD6645 Fixed-Point ADC and AD6636
Scaling with Floating-Point ADC
An example of the exponent control feature combines the
AD6600 and the AD6636. The AD6600 is an 11-bit ADC with
three bits of gain ranging. In effect, the 11-bit ADC provides the
mantissa, and the three bits of the relative signal strength
indicator (RSSI) are the exponent. Only five of the eight
available steps are used by the AD6600. See the AD6600 data
sheet for details.
Table 10. Weighting Factors for Different Exp[2:0] Values
ADC Input
Level
Largest
Smallest
AD6636
Exp[2:0]
000 (0)
001 (1)
010 (2)
011 (3)
100 (4)
101 (5)
110 (6)
111 (7)
Data
Divide-By
/1 (>> 0)
/2 (>> 1)
/4 (>> 2)
/8 (>> 3)
/16 (>> 4)
/32 (>> 5)
/64 (>> 6)
/128 (>> 7)
Signal
Attenuation (dB)
0
6
12
18
24
30
36
42
Complex (I/Q) Input Ports
The four individual ADC input ports of the AD6636 can be
configured to function as two complex input ports.
Additionally, if required, only two input ports can be made to
function as a complex port, while the remaining two input ports
function as real individual input ports.
In complex mode, Input Port A is paired with Input Port B to
receive I and Q data, respectively. Similarly, Input Port C can be
paired with Input Port D to receive I and Q data, respectively.
These two pairings are controlled individually using Bit 24 and
Bit 25 of the ADC input control register.
The AD6636 input ports can be configured in CMOS mode or
LVDS mode. In CMOS input mode, the four input ports can be
configured as two complex input ports. In LVDS mode, two CMOS
input ports are each combined to form one LVDS input port.
CMOS Input Port INA[15:0] and CMOS Input Port INB[15:0]
form the positive and negative differential nodes,
LVDS_A+[15:0] and LVDS_A−[15:0], respectively. Similarly,
INC[15:0] and IND[15:0] form the positive and negative
differential nodes, LVDS_C+[15:0] and LVDS_C− [15:0],
respectively. CLKA and CLKB form the differential pair,
Pin LVDS_CLKA+ and Pin LVDS_CLKA−. Similarly, CLKC
and CLKD form the differential pair Pin LVDS_CLKC+ and
Pin LVDS_CLKC−.
By default, the AD6636 powers up in CMOS mode and can be
programmed to CMOS mode by using the CMOS mode bit
(Bit 10 of the LVDS control register). Writing Logic 1 to Bit 8 of
the LVDS control register enables an autocalibrate routine that
calibrates the impedance of the LVDS pads to match the output
impedance of the LVDS signal source impedance. The LVDS pads
in the AD6636 have an internal impedance of 100 Ω across the
differential signals; therefore, an external resistor is not required.
PLL CLOCK MULTIPLIER
In the AD6636, the input clock rate must be the same as the
input data rate. In a typical digital downconverter architecture,
the clock rate is a limitation on the number of filter taps that
can be calculated in the programmable RAM coefficient filters
(MRCF, DRCF, and CRCF). For slower ADC clock rates (or for
any clock rate), this limitation can be overcome by using a PLL
clock multiplier to provide a higher clock rate to the RCF filters.
Using this clock multiplier, the internal signal processing clock
rate can be increased up to 200 MHz. The CLKA signal is used
as an input to the PLL clock multiplier.
PLL CLOCK GENERATION
1
ADC_CLK
0
Rev. A | Page 21 of 80
CLKA
DIVIDE BY N
(1, 2, 4 OR 8)
PLL CLOCK
MULITPLIER
(4x TO 20x)
0
PLL_CLK
1
BYPASS_PLL
2
N
5 1 FOR BYPASS
M
Figure 24. PLL Clock Generation
04998-0-024
As explained previously, each individual channel can receive
input signals from any of the four input ports using the crossbar
mux select bits in the ADC input control register. In addition to
the three bits, a 1-bit selection is provided for choosing the
complex input port option for any individual channel. For
example, if Channel 0 needs to receive complex input from
Input Port A and Input Port B, the mux select bits should
AD6636
The PLL clock multiplier is programmable and uses input clock
rates between 4 MHz and 150 MHz to give a system clock rate
(output) of as high as 200 MHz.
The output clock rate is given by
PLL_CLK =
CLKA × M
N
where:
CLKA is the Input Port A clock rate.
M is a 5-bit programmable multiplication factor.
N is a predivide factor.
M is a 5-bit number between 4 and 20 (both values included). N
(predivide) can be 1, 2, 4, or 8. The multiplication factor M is
programmed using a 5-bit PLL clock multiplier word in the
ADC clock control register. A value outside the valid range of 4
to 20 bypasses the PLL clock multiplier and, therefore, the PLL
clock is the same as the input clock. The predivide factor N is
programmed using a 2-bit ADC pre-PLL clock divider word in
the ADC clock control register, as listed in Table 11.
Table 11. PLL Clock Generation Predivider Control
Predivide Word [1:0]
00
01
10
11
Divide-by Value for the Clock
Divide-by-1, bypass
Divide-by-2
Divide-by-4
Divide-by-8
Function
The gain-control block features a programmable upper
threshold register and a lower threshold register. The ADC
input data is compared to both these registers. If ADC input
data is larger than the upper threshold register, then the gain
control output is decremented by 1. If ADC input data is
smaller than the lower threshold register, then the gain control
output is incremented by 1. When decrementing the gain
control output, the change is immediate. But when
incrementing the output, a dwell-time register is used to delay
the change. If the ADC input is larger than the upper threshold
register value, the gain-control output is decremented to
prevent overflow immediately.
When the ADC input is lower than the lower threshold register,
a dwell timer is loaded with the value in the programmable,
20-bit, dwell-time register. The counter decrements once every
input clock cycle, as long as the input signal remains below the
lower threshold register value. If the counter reaches 1, the gain
control output is incremented by 1. If the signal goes above the
lower threshold register value, the gain adjustment is not made,
and the normal comparison to lower and upper threshold
registers is initiated once again. Therefore, the dwell timer
provides temporal hysteresis and prevents the gain from
switching continuously.
For the best signal processing advantage, the user should
program the clock multiplier to give a system clock output as
close as possible to, but not exceeding, 200 MHz. The internal
blocks of the AD6636 that run off of the PLL clock are rated to
run at a maximum of 200 MHz. The default power-up state for
the PLL clock multiplier is the bypass state, where CLKA is
passed on as the PLL clock.
In a typical application, if the ADC signal goes below the lower
threshold for a time greater than the dwell time, then the gain
control output is incremented by 1. Gain control bits control the
gain ranging block, which appears before the ADC in the signal
chain. With each increment of the gain control output, gain in
the gain-ranging block is increased by 6.02 dB. This increases
the dynamic range of the input signal into the ADC by 6.02 dB.
This gain is compensated for in the AD6636 by relinearizing
(see the Relinearization section). Therefore, the AD6636 can
increase the dynamic range of the ADC by 42 dB, provided that
the gain-ranging block can support it.
ADC GAIN CONTROL
Relinearization
Each ADC input port has individual, high speed, gain-control
logic circuitry. Such gain-control circuitry is useful in applications that involve large dynamic range inputs or in which gain
ranging ADCs are employed. The AD6636 gain-control logic
allows programmable upper and lower thresholds and a
programmable dwell-time counter for temporal hysteresis.
The gain in the gain-ranging block (external) is compensated
for by relinearizing, using the exponent bits, EXP[2:0], of the
input port. For this purpose, the gain control bits are connected
to the EXP[2:0] bits, providing an attenuation of 6.02 dB for
every increase in the gain control output. After the gain in the
external gain-ranging block and the attenuation in the AD6636
(using EXP bits), the signal gain is essentially unchanged. The
only change is the increase in the dynamic range of the ADC.
Each input port has a 3-bit output from the gain control block.
These three output pins are shared with the 3-bit exponent
input pins for each input port. The operation is controlled by
the gain control enable bit in the gain control register of the
individual input ports. Logic 1 in this bit programs the
EXP[2:0] pins as gain-control outputs, and Logic 0 configures
the pins as input exponent pins. To avoid bus contention, these
pins are set, by default, as input exponent pins.
External gain-ranging blocks or gain-ranging ADCs have a
delay associated with changing the gain of the signal. Typically,
these delays can be up to 14 clock cycles. The gain change in the
AD6636 (via EXP[2:0]) must be synchronized with the gain
change in the gain-ranging block (external). This is allowed in
the AD6636 by providing a flexible delay, programmable 6-bit
word in the gain control register. The value in this 6-bit word
Rev. A | Page 22 of 80
AD6636
gives the delay in input clock cycles. A programmable pipeline
delay given by the 6-bit value (maximum delay of 63 clock
cycles) is placed between the gain control output and the
EXP[2:0] input. Therefore, the external gain-ranging block’s
settling delays are compensated for in the AD6636.
ADC INPUT PORT MONITOR FUNCTION
Note that any gain changes that are initiated during the
relinearization period are ignored. For example, if the AD6636
detects that a gain adjustment is required during the relinearization period of a previous gain adjustment, then the new
adjustment is ignored.
The AD6636 provides a power-monitor function that can
monitor and gather statistics about the received signal in a
signal chain. Each input port is equipped with an individual
power-monitor function that can operate both in real and
complex modes of the input port. This function block can
operate in one of three modes, which measure the following
over a programmable period of time:
•
Peak power
Setting Up the Gain Control Block
•
Mean power
To set up the gain control block for individual input ports, the
individual upper threshold registers and lower threshold
registers should be written with appropriate values. The 10-bit
values written into upper and lower threshold registers are
compared to the 10 MSB bits of the absolute magnitude
calculated using the input port data. The 20-bit dwell timer
register should have the appropriate number of clock cycles to
provide temporal hysteresis.
•
Number of samples crossing a threshold
These functions are controlled via the 2-bit power-monitor
function select bits of the power monitor control register for
each individual input port. The input ports can be set for
different modes, but only one function can be active at a time
for any given input port.
A 6-bit relinearization pipeline delay word is set to synchronize
with the settling delay in the external gain ranging circuitry.
Finally, the gain control enable bit is written with Logic 1 to
activate the gain control block. On enabling, the gain control
output bits are made 000 (output on EXP[2:0] pins), which
represent the minimum gain for the external gain-ranging
circuitry and corresponding minimum attenuation during
relinearization. The normal functioning takes over, as explained
previously in this section.
Complex Inputs
For complex inputs (formed by pairing two input ports), only
one set of EXP[2:0] pins should be used as the gain control
output. For the pair of Input Port A and Input Port B, gain
control circuitry for Input Port A is active, and EXPA[2:0]
should be connected externally as the gain control output. The
gain control circuitry for Input Port B is not activated (shut
down), and EXPB[2:0] is forced to be equal to EXP[2:0].
UPPER
THRESHOLD
REGISTER
B
A
FROM INPUT
PORTS
COMPARE
A>B
B
DECREASE
EXTERNAL GAIN
EXP [2:0]
COMPARE
AB
04998-0-026
FROM
INPUT
PORTS
Figure 26. ADC Input Peak Detector Block Diagram
Mean Power Mode (Control Bits 01)
In this mode, the mean power of the input port signal is
integrated (by adding an accumulator) over a programmable
time period (given by AMPR) to give the mean power of the
input signal. This mode is set by programming Logic 1 in the
power monitor function select bits of the power monitor
control register for each individual input port. The 24-bit
AMPR, representing the period over which integration is
performed, must be programmed before activating this mode.
After enabling this mode, the value in the AMPR is loaded into
a monitor period timer, and the countdown is started
immediately. The 15-bit mean power of input signal is rightshifted by nine bits to give 6-bit data. This 6-bit data is added to
the contents of a 24-bit holding register, thus performing an
accumulation. The integration continues until the monitor
period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the value
in the MSR is transferred to the power-monitor holding register
(after some formatting), which can be read through the
microport or the serial port. The monitor period timer is
reloaded with the value in the AMPR, and the countdown is
started. Also, the first input sample signal power is updated in
the MSR, and the accumulation continues with the subsequent
input samples. If the interrupt is enabled, an interrupt is
generated, and the interrupt status register is updated when the
AMPR reaches a count of 1. Figure 27 illustrates the mean
power-monitoring logic.
The value in the MSR is a floating-point number with 4 MSBs
and 20 LSBs. If the 4 MSBs are EXP and the 20 LSBs are MAG,
the value in dBFS can be decoded by
⎡ MAG
⎤
Mean Power = 10 log ⎢⎛⎜ 20 ⎞⎟ 2 −( EXP −1) ⎥
2
⎠
⎝
⎣
⎦
In this mode of operation, the magnitude of the input port
signal is monitored over a programmable time period (given by
AMPR) to count the number of times it crosses a certain
programmable threshold value. This mode is set by programming Logic 1x (where x is a don’t care bit) in the power-monitor
function select bits of the power monitor control register for
each individual input port. Before activating this mode, the user
needs to program the 24-bit AMPR and the 10-bit upper
threshold register for each individual input port. The same
upper threshold register is used for both power monitoring and
gain control (see the ADC Gain Control section).
After entering this mode, the value in the AMPR is loaded into
a monitor period timer, and the countdown is started. The
magnitude of the input signal is compared to the upper
threshold register (programmed previously) on each input clock
cycle. If the input signal has magnitude greater than the upper
threshold register, then the MSR register is incremented by 1.
The initial value of the MSR is set to 0. This comparison and
increment of the MSR register continues until the monitor
period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the value
in the MSR is transferred to the power monitor holding register,
which can be read through the microport or the serial port. The
monitor period timer is reloaded with the value in the AMPR,
and the countdown is started. The MSR register is also cleared
to a value of 0. If interrupts are enabled, an interrupt is
generated, and the interrupt status register is updated when the
AMPR reaches a count of 1. Figure 28 illustrates the threshold
crossing logic. The value in the MSR is the number of samples
that have an amplitude greater than the threshold register.
FROM
MEMORY
MAP
POWER MONITOR
PERIOD REGISTER
DOWN
COUNTER
TO
INTERRUPT
CONTROLLER
IS COUNT = 1?
LOAD
FROM
INPUT
PORTS
FROM
MEMORY
MAP
CLEAR
A COMPARE
A>B
COMPARE
A>B
LOAD
POWER MONITOR
HOLDING
REGISTER
TO
MEMORY
MAP
B
UPPER
THRESHOLD
REGISTER
Figure 28. ADC Input Threshold Crossing Block Diagram
Rev. A | Page 24 of 80
04998-0-028
DOWN
COUNTER
TO
INTERRUPT
CONTROLLER
04998-0-027
LOAD
FROM
MEMORY
MAP
POWER MONITOR
PERIOD REGISTER
AD6636
Additional Control Bits
For additional flexibility in the power monitoring process, two
control bits are provided in the power-monitor control register.
They are the disable monitor period timer bit and the clear-onread bit. These options have the same function in all three
modes of operation.
If the clear-on-read bit is Logic 0, the read operation to the
microport or serial port does not clear the MSR value after it is
transferred into the holding register. The value from the
previous monitor time period persists, and it continues to be
compared, accumulated, or incremented, based on new input
signal magnitude values.
Disable Monitor Period Timer Bit
QUADRATURE I/Q CORRECTION BLOCK
When the disable monitor period timer bit is written with
Logic 1, the timer continues to run but does not cause the
contents of the MSR to be transferred to the holding register
when the count reaches 1. This function of transferring the
MSR to the power monitor holding register and resetting the
MSR is now controlled by a read operation on the microport or
serial port.
When the I and Q paths are digitized using separate ADCs, as
in quadrature IF down-conversion, a mismatch often occurs
between I and Q due to variations in the ADCs from the
manufacturing process. The AD6636 is equipped with two
quadrature correction blocks that can be used to correct I/Q
mismatch errors in a complex baseband input stream. These
I/Q mismatches can result in spectral distortions and removing
them is useful.
Clear-on-Read Bit
This control bit is valid when the disable monitor period timer
bit is Logic 1 only. When both of these bits are set, a read
operation to either the microport or the serial port reads the
MSR value, and the monitor period timer is reloaded with the
AMPR value. The MSR is cleared (written with current input
signal magnitude in peak power and mean power mode; written
with a 0 in threshold crossing mode), and normal operation
continues.
When the monitor period timer is disabled and the clear-onread bit is set, a read operation to the power monitor holding
register clears the contents of the MSR and, therefore, the power
monitor loop restarts.
Two such blocks are present, one each for the I/Q signal formed
by combining the A and B inputs and the C and D inputs,
respectively. The I/Q correction block can be enabled when the
Port A (or Port C) complex data active bit is enabled in the
ADC input control register. This block is bypassed when real
input data is present on the ADC input ports because there is
no possibility of I/Q mismatch in real data.
The I/Q or quadrature correction block consists of three
independent subblocks: dc correction, phase correction, and
amplitude correction. Three individual bits in the AB (or CD)
correction control registers can be used to enable or disable
each of these subblocks independently. Figure 29 shows the
contents and definitions of the registers related to the
quadrature correction block.
DC
ESTIMATE
I [15:0] FROM
INPUT PORT
I_OUT [15:0]
TO NEXT BLOCK
PHASE ESTIMATE
[13:0]
MAGNITUDE
MAGNITUDE
ERROR
ESTIMATE [13:0] ESTIMATION
Q [15:0] FROM
INPUT PORT
PHASE
ERROR
ESTIMATION
Q_OUT [15:0]
TO NEXT BLOCK
DC
ESTIMATE
Figure 29. Quadrature Correction Block Diagram
Rev. A | Page 25 of 80
PHASE
ESTIMATE
[13:0]
04998-0-029
When a microport or serial port read is performed on the
power monitor holding register, the MSR value is transferred to
the holding register. After the read operation, the timer is
reloaded with the AMPR value. If the timer reaches 1 before the
microport or serial port read, the MSR value is not transferred
to the holding register, as in normal operation. The timer still
generates an interrupt on the AD6636 interrupt pin and updates
the interrupt status register. An interrupt appears on the IRP
pin, if interrupts are enabled in the interrupt enable register.
AD6636
Table 12. Correction Control Registers
Phase Correction
Register
I/Q Correction Control
When using complex ADC input, the I and Q datapaths
typically have phase offset, caused mainly by the local oscillator
and demodulator IC. The AD6636 phase-offset correction
circuit can be used to compensate for this phase offset.
DC Offset Correction I
DC Offset Correction Q
Amplitude Offset
Correction
Phase Offset Correction
Bits
15 to 12
11 to 8
7 to 4
3
2
1
0
31 to 16
15 to 0
31 to 16
Description
Amplitude Loop BW
Phase Loop BW
DC Loop BW
Reserved (Logic 0)
Amplitude Correction
Enable
Phase Correction Enable
DC Correction Enable
DC Offset Q
DC Offset I
Amplitude Correction
15 to 0
Phase Correction
DC Correction
All ADCs have a nominal dc offset related to them. If the ADCs
in the I and Q path have different dc offsets due to variations in
the manufacturing process, the dc correction circuit can be
used to compensate for these dc offsets. Writing Logic 1 into the
dc correction enable bit of the AB (or CD) correction control
register enables the dc correction block. Two dc estimation
blocks are used, one each for the I and Q paths. The estimated
dc value is subtracted from the I and Q paths. Therefore, the dc
signal is removed independently from the I and Q path signals.
A cascade of two low-pass decimating filters estimates the dc
offset in the feedback loop. A decimating first-order CIC filter
is followed by an interpolating second-order CIC filter. The
decimation and interpolation values of the CIC filters are the
same and are programmable between 212 and 224 in powers of 2.
The 4-bit dc loop BW word in the I/Q correction control AB (or
CD) register is used to program this decimation (interpolation)
value. When the dc loop BW is a 0, decimation is 212, and when
the dc loop BW is 11, decimation is 224.
When the dc correction circuit is enabled, the dc correction
values are estimated. The values, which are estimated independently in the I and Q paths, are subtracted independently from
their respective datapaths. These dc correction values are also
available for output continuously through the dc correction I
and dc correction Q registers. These registers contain 16-bit dc
offset values whose MSB-justified values are subtracted directly
from MSB-justified ADC inputs for the I and Q paths.
When the dc correction circuit is disabled, the value in the dc
correction register is used for continuously subtracting the dc
offset from I and Q datapaths. This method can be used to
manually set the dc offset instead of using the automatic dc
correction circuit.
When the phase correction enable bit is Logic 1, the phase error
between I and Q is estimated (ideally, the phase should be 90°).
The phase mismatch is estimated over a period of time
determined by the integrator loop bandwidth. This integrator is
implemented as a first-order CIC decimating filter, whose
decimation value can vary between 212 and 224 in powers of 2.
Phase loop BW (Bits [11:8]) of the I/Q correction control
register determine this decimation value. When phase loop BW
equals 0, the decimation value is 212, and when phase loop BW
is 11, the decimation value is 224.
While the phase offset correction circuit is enabled, the
tan(phase_mismatch) is estimated continuously. This value is
multiplied with Q path data and added to I path data
continuously. The estimated value is also updated in the phase
offset correction register. The tan(phase_mismatch) can be
±0.125 with a 14-bit resolution. This converts to a phase
mismatch of about ±7.125°.
When the phase offset correction circuit is disabled, the value in
the phase correction register is multiplied by the Q path data
and added to the I path data continuously. This method can be
used to manually set the phase offset instead of using the
automatic phase offset correction circuit.
Amplitude Correction
When using complex ADC input, the I and Q datapaths
typically have amplitude offset, caused mainly by the local
oscillator and the demodulator IC. The AD6636 amplitude
offset correction circuit can be used to compensate for this
amplitude offset.
When the amplitude correction enable bit is Logic 1, the
amplitude error between the I and Q datapaths is estimated.
The amplitude mismatch is estimated over a period of time
determined by the integrator loop bandwidth. This integrator is
implemented as a first-order CIC decimating filter, whose
decimation value can vary between 212 and 224 in powers of 2.
Phase loop BW (Bits [11:8]) of the I/Q correction control
register determines this decimation value. When the phase loop
BW equals 0, the decimation value is 212, and when phase loop
BW is 11, the decimation value is 224.
While the amplitude offset correction circuit is enabled, the
difference (MAG(Q) – MAG(I)) is estimated continuously. This
value is multiplied with the Q path data and added to the Q
path data continuously. The estimated value is also updated in
the phase offset correction register. The difference (MAG(Q) –
Rev. A | Page 26 of 80
AD6636
MAG(I)) can be between 1.125 and 0.875 with a 14-bit
resolution.
When the amplitude offset correction circuit is disabled, the value
in the amplitude offset correction register is multiplied by the
Q path data and added to the Q path data continuously. This
method can be used to manually set the amplitude offset instead of
using the automatic amplitude offset correction circuit.
INPUT CROSSBAR MATRIX
The AD6636 has four ADC input ports and six channels. Two
input ports can be paired to support complex input ports.
Crossbar mux selection allows each channel to select its input
signal from the following sources: four real input ports, two
complex input ports, and internally generated pseudorandom
sequence (referred to as a PN sequence, which can be either real
or complex). Each channel has an input crossbar matrix to
select from the above-listed input signal choices.
The selection of the input signal for a particular channel is
made using a 3-bit crossbar mux select word and a 1-bit
complex data input bit selection in the ADC input control
register. Each channel has a separate selection for individual
control. Table 13 lists the valid combinations of the crossbar
mux select word, the complex data input bit values, and the
corresponding input signal selections.
The amplitude of the sine and cosine are represented using
17 bits. The worst-case spurious signal from the NCO is better
than −100 dBc for all output frequencies.
Because the filtering in the AD6636 is low-pass filtering, the
carrier of interest is tuned down to dc (frequency = 0 Hz). This
is illustrated in Figure 30. Once the signal of interest is tuned
down to dc, the unwanted adjacent carriers can be rejected
using the low-pass filtering that follows.
NCO Frequency
The NCO frequency value is given by the 32-bit twos
complement number entered in the NCO frequency register.
Frequencies between −CLK/2 and CLK/2 (CLK/2 excluded)
are represented using this frequency word:
0x8000 0000 represents a frequency given by −CLK/2.
0x0000 0000 represents dc (frequency is 0 Hz).
0x7FFF FFFF represents CLK/2 − CLK/232.
The NCO frequency word can be calculated by
NCO_FREQ = 2 32
mod( f ch , f clk )
f clk
where:
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
Each channel consists of an independent complex NCO and a
complex mixer. This processing stage has a digital tuner
consisting of three multipliers and a 32-bit complex NCO. The
NCO serves as a quadrature local oscillator capable of producing an NCO frequency of between −CLK/2 and +CLK/2 with a
resolution of CLK/232 in complex mode, where CLK is the input
clock frequency.
The frequency word used for generating the NCO is a 32-bit
word. This word is used to generate a 20-bit phase word. A
16-bit phase offset word is added to this phase word. Eighteen
bits of this phase word are used to generate the sine and cosine
of the required NCO frequency.
NCO_FREQ is the 32-bit twos complement number representing the NCO frequency register.
fch is the desired carrier frequency.
fclk is the clock rate for the channel under consideration.
mod( ) is a remainder function. For example, mod(110, 100) =
10 and, for negative numbers, mod(−32, 10) = −2.
Note that this equation applies to the aliasing of signals in the
digital domain (that is, aliasing introduced when digitizing
analog signals).
Table 13. Crossbar Mux Selection for Channel Input Signal
Complex Input Bit
0
0
0
0
0
1
Crossbar Mux Select Bit
000
001
010
011
100
000
1
001
1
010
Input Signal Selection
Input Port A magnitude and exponent pins drive the channel.
Input Port B magnitude and exponent pins drive the channel.
Input Port C magnitude and exponent pins drive the channel.
Input Port D magnitude and exponent pins drive the channel.
Internal PN sequence’s magnitude and exponent bits drive the channel.
Input Ports A and B form a pair to drive I and Q paths of the channel, respectively.
Input Port A exponent pins drive the channel exponent bits.
Input Ports C and D form a pair to drive I and Q paths of the channel, respectively.
Input Port C exponent pins drive the channel exponent bits.
Internal PN sequence’s magnitude and exponent bits drive the channel.
Rev. A | Page 27 of 80
AD6636
WIDEBAND INPUT SPECTRUM (–fsample/2 TO +fsample/2)
SIGNAL OF INTEREST IMAGE
–fs/2
–7fs/16
–3fs/8
–5fs/16
SIGNAL OF INTEREST
–fs/4
–3fs/16
–fs/8
–fs/16
DC
fs/16
fs/8
3fs/16
fs/4
5fs/16
3fs/8
7fs/16
fs/2
5fs/16
3fs/8
7fs/16
fs/2
WIDEBAND INPUT SPECTRUM (30MHz FROM HIGH SPEED ADC)
NCO TUNES SIGNAL TO
–fs/2
–7fs/16
–3fs/8
–5fs/16
–fs/4
–3fs/16
–fs/8
–fs/16
DC
SIGNAL OF INTEREST IMAGE
fs/16
fs/8
3fs/16
fs/4
FREQUENCY TRANSLATION (SINGLE 1MHz CHANNEL TUNED TO BASEBAND)
04998-0-030
SIGNAL OF INTEREST
AFTER FREQUENCY TRANSLATION
Figure 30. Frequency Translation Principle Using the NCO and Mixer
For example, if the carrier frequency is 100 MHz and the clock
frequency is 80 MHz,
mod ( f ch , f clk ) 20
=
= 0.25
f clk
80
This, in turn, converts to 0x4000 0000 in the 32-bit twos
complement representation for NCO_FREQ.
channel functions simply as a real filter on complex data. This is
useful for baseband sampling applications in which the input
Port A (or C) is connected to the I signal path within the filter
and the Input Port B (or D) is connected to the Q signal path.
This can be desired if the digitized signal has already been
converted to baseband in prior analog stages or by other digital
preprocessing.
Clear Phase Accumulator on Hop
If the carrier frequency is 70 MHz and the clock frequency is
80 MHz,
mod ( f ch , f clk ) 10
=
= 0.125
f clk
80
This, in turn, converts to 0xE000 0000 in the twos complement
32-bit representation.
Mixer
The NCO is accompanied by a mixer. Its operation is similar to
an analog mixer. It does the down-conversion of input signals
(real or complex) by using the NCO frequency as a local
oscillator. For real input signals, this mixer performs a real
mixer operation (with two multipliers). For complex input
signals, the mixer performs a complex mixer operation (with
four multipliers). The mixer adjusts its operation based on the
input signal (real or complex) provided to each individual
channel.
Bypass
The NCO and the mixer can be bypassed individually in each
channel by writing Logic 1 in the NCO bypass bit in the NCO
control register of the channel under consideration. When
bypassed, down-conversion is not performed and the AD6636
When the clear NCO accumulator bit of the NCO control
register is set (Logic 1), the NCO phase accumulator is cleared
prior to a frequency hop. See the Chip Synchronization section
for details on frequency hopping. This ensures a consistent
phase of the NCO on each hop. The NCO phase offset is
unaffected by this setting and is still in effect. If phasecontinuous hopping is needed, this bit should be cleared (NCO
accumulator is not cleared). The last phase in the NCO phase
register is the initiating point for the new frequency.
Phase Dither
The AD6636 provides a phase dither option for improving the
spurious performance of the NCO. Writing Logic 1 in the phase
dither enable bit of the NCO control register of the individual
channels enables phase dither. When phase dither is enabled,
random phase is added to the LSBs of the phase accumulator of
the NCO. When phase dither is enabled, spurs due to phase
truncation in the NCO are randomized.
The energy from these spurs is spread into the noise floor and
the spurious-free dynamic range is increased at the expense of a
very slight decrease in the SNR. The choice of whether to use
phase dither in a system is ultimately decided by the system
goals. If lower spurs are desired at the expense of a slightly
Rev. A | Page 28 of 80
AD6636
raised noise floor, phase dither should be employed. If a low
noise floor is desired and the higher spurs can be tolerated or
filtered by subsequent stages, then phase dither is not needed.
Amplitude Dither
This can be used to improve spurious performance of the NCO.
Amplitude dither is enabled by writing Logic 1 in the amplitude
dither enable bit of the NCO control register of the channel
under consideration. When this feature is enabled, random
amplitude is added to the LSBs of the sine and cosine
amplitudes. Amplitude dither improves performance by
randomizing the amplitude quantization errors within the
angular-to-Cartesian conversion of the NCO. This option can
reduce spurs at the expense of a slightly raised noise floor.
Amplitude and phase dither can be used together, separately, or
not at all.
NCO Frequency Hold-Off Register
When the NCO frequency registers are written by the
microport or serial port, data is passed to a shadow register.
Data can be moved to the main registers when the channel
comes out of sleep mode, or when a sync hop occurs. In either
event, a counter can be loaded with the NCO frequency holdoff register value. The 16-bit unsigned integer counter starts
counting down, clocked by the input port clock selected at the
crossbar mux. When the counter reaches 0, the new frequency
value in the shadow register is written to the NCO frequency
register. Writing 1 in this hold-off register updates the NCO
frequency register as soon as the start sync or hop sync occurs.
See the Chip Synchronization section for details.
Phase Offset
FIFTH-ORDER CIC FILTER
The signal processing stage immediately after the NCO is a CIC
filter stage. This stage implements a fixed-coefficient,
decimating, cascade integrated comb filter. The input rate to
this filter is the same as the data rate at the input port; the
output rate from this stage is dependent on the decimation factor.
f CIC =
f in
M CIC
The decimation ratio, MCIC, can be programmed from 2 to 32
(only integer values). The 5-bit word in the CIC decimation
register is used to set the CIC decimation factor. A binary value
of one less than the decimation factor is written into this
register. The decimation ratio of 1 can be achieved by bypassing
the CIC filter stage. The frequency response of the filter is given
by the following equations. The gain and pass-band droop of
the CIC should be calculated by these equations. Both parameters can be offset in the RCF stage.
⎛ 1 − Z − MCIC
1
H ( z ) = (S +5 ) × ⎜
⎜ 1− Z −1
2 CIC
⎝
⎞
⎟
⎟
⎠
5
⎛
⎛
⎜ SIN ⎜ M CIC × f
⎜
⎜
f in
1
⎝
H ( f ) = (S +5 ) × ⎜
2 CIC
⎛
⎜ SIN⎜ π f ⎞⎟
⎜
⎜ f ⎟
⎝ in ⎠
⎝
⎞⎞
⎟⎟
⎟⎟
⎠
⎟
⎟
⎟
⎠
5
where:
fin is the data input rate to the channel under consideration.
The phase offset register can be written with a value that is
added as an offset to the phase accumulator of the NCO. This
16-bit register is interpreted as a 16-bit unsigned integer. A
0x0000 in this register corresponds to a 0 radian offset and a
0xFFFF corresponds to an offset of 2π × (1 − 1/216) radians.
This register allows multiple NCOs (multiple channels) to be
synchronized to produce complex sinusoids with a known and
steady phase difference.
Hop Sync
When the channel’s NCO frequency needs to be changed from
one frequency to a different frequency, a hop sync should be
issued to the channel. This feature is discussed in detail in the
Chip Synchronization section.
SCIC, the scale factor, is a programmable unsigned integer
between 0 and 20.
The attenuation of the data into the CIC stage should be
controlled in 6 dB increments. For the best dynamic range, SCIC
should be set to the smallest value possible (lowest attenuation
possible) without creating an overflow condition. This can be
accomplished safely using the following equation, where
input_level is the largest possible fraction of the full-scale value
at the input port. This value is output from the NCO stage and
pipelined into the CIC filter.
SCIC = ceil (log 2 (M CIC 5 × input_level )) − 5
OLCIC =
(M CIC 5 ) × input_level
2 SCIC
+5
Bypass
The fifth-order CIC filter can be bypassed when no decimation
is required of it. When it is bypassed, the scaling operation is
not performed. In bypass mode, the output of the CIC filter is
the same as the input of the CIC filter.
Rev. A | Page 29 of 80
AD6636
CIC Rejection
Table 14 illustrates the amount of bandwidth as a percentage of
the data rate into the CIC stage, which can be protected with
various decimation rates and alias rejection specifications. The
maximum input rate into the CIC is 150 MHz (the same as the
maximum input port data rate). The data may be scaled to any
other allowable sample rate.
Solution: First determine the percentage of the sample rate that
is represented by the pass band.
BW fraction = 100 ×
1.4 MHz
100 MHz
= 1.4
Table 14 can be used to decide the minimum decimation
required in the CIC stage to preserve a certain bandwidth. The
CIC5 stage can protect a much wider bandwidth to any given
rejection, when a decimation ratio lower than that identified in
the table is used. The table helps to calculate an upper boundary
on decimation, MCIC, given the desired filter characteristics.
In the −100 dB column in Table 14, find the value greater than
or equal to the pass-band percentage of the clock rate. Then
find the corresponding rate decimation factor (MCIC). For an
MCIC of 6, the frequency that has −100 dB of alias rejection is
1.48%, which is slightly larger than the 1.4% calculated.
Therefore, for this example, the maximum bound on the CIC
decimation rate is 6. A higher MCIC means less alias rejection
than the 100 dB required.
Table 14. SSB CIC5 Alias Rejection Table (fin = 1)
FIR HALF-BAND BLOCK
−70 dB
6.393
5.11
4.057
3.326
2.808
2.425
2.133
1.902
1.716
1.563
1.435
1.326
1.232
1.151
1.079
1.016
0.96
0.91
0.865
0.824
0.786
0.752
0.721
0.692
0.666
0.641
0.618
0.597
0.577
0.559
0.541
−80 dB
5.066
4.107
3.271
2.687
2.27
1.962
1.726
1.54
1.39
1.266
1.162
1.074
0.998
0.932
0.874
0.823
0.778
0.737
0.701
0.667
0.637
0.61
0.584
0.561
0.54
0.52
0.501
0.484
0.468
0.453
0.439
−90 dB
4.008
3.297
2.636
2.17
1.836
1.588
1.397
1.247
1.125
1.025
0.941
0.87
0.809
0.755
0.708
0.667
0.63
0.597
0.568
0.541
0.516
0.494
0.474
0.455
0.437
0.421
0.406
0.392
0.379
0.367
0.355
−100 dB
3.183
2.642
2.121
1.748
1.48
1.281
1.128
1.007
0.909
0.828
0.76
0.703
0.653
0.61
0.572
0.539
0.509
0.483
0.459
0.437
0.417
0.399
0.383
0.367
0.353
0.34
0.328
0.317
0.306
0.297
0.287
The output of the CIC filter is pipelined into the FIR HB (halfband) block. Each channel has two sets of cascading fixedcoefficient FIR and fixed-coefficient half-band filters. The halfband filters decimate by 2. Each of these filters (FIR1, HB1,
FIR2, HB2) are described in the following sections.
3-Tap Fixed-Coefficient Filter (FIR1)
The 3-tap FIR filter is useful in certain filter configurations in
which extra alias protection is needed for the decimating HB1
filter. It is a simple sum-of-products FIR filter with three filter
taps and 2-bit fixed coefficients. Note that this filter does not
decimate. The coefficients of this symmetric filter are {1, 2, 1}.
The normalized coefficients used in the implementation are
{0.25, 0.5, 0.25}.
The user can either use or bypass this filter. Writing Logic 0 to
the FIR1 enable bit in the FIR-HB control register bypasses this
fixed-coefficient filter. The filter is useful in certain filter
configurations only and bypassing it for other applications
results in power savings.
0
0.34
0.66
–8.33
FIR1 RESPONSE
–16.67
–25.00
–33.33
–41.67
–50.00
–58.33
–66.67
–75.00
–81
–83.33
–91.67
–100.00
Example Calculations
0
Goal: Implement a filter with an input sample rate of 100 MHz
requiring 100 dB of alias rejection for a ± 1.4 MHz pass band.
Rev. A | Page 30 of 80
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FRACTION OF FIR1 INPUT SAMPLE RATE
0.9
Figure 31. FIR1 Filter Response to the Input Rate of the Filter
04998-0-031
−60 dB
8.078
6.367
5.022
4.107
3.463
2.989
2.627
2.342
2.113
1.924
1.765
1.631
1.516
1.416
1.328
1.25
1.181
1.119
1.064
1.013
0.967
0.925
0.887
0.852
0.819
0.789
0.761
0.734
0.71
0.687
0.666
dBc
MCIC5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AD6636
0
This filter runs at the same sample rate as the CIC filter output
rate and is given by
0.43
0.57
10
20
30
fFIR1 = fin/MCIC
40
where:
50
dBc
HB1 RESPONSE
fin is the input rate in to the channel.
60
70
–77
80
MCIC is the decimation ratio in the CIC filter stage.
90
The maximum input and output rates for this filter are
150 MHz.
100
120
Decimate-by-2, Half-Band Filter (HB1)
0
Table 15. Fixed Coefficients for HB1 Filter
Coefficient
Number
C1, C11
C3, C9
C5, C7
C6
Normalized
Coefficient
+0.013671875
−0.103515625
+0.58984375
+1
Decimal Coefficient
(10-Bit)
+7
−53
+302
+512
Similar to the FIR1 filter, this filter can be used or bypassed.
Writing Logic 0 to the HB1 enable bit in the FIR-HB control
register bypasses this fixed-coefficient HB filter. The filter is
useful in certain filter configurations only and bypassing it for
other applications results in power savings. For example, it is
useful in narrow-band and wideband output applications in
which more filtering is required as compared to very wide
bandwidth applications in which a higher output rate may
prohibit the use of a decimating filter. The response of the filter
is shown in Figure 32.
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FRACTION OF HB1 INPUT SAMPLE RATE
0.9
Figure 32. HB1 Filter Response to the Input Rate of the Filter
The filter has a maximum input sample rate of 150 MHz
and, when the filter is not bypassed, the maximum output rate
is 75 MHz.
The filter has a ripple of 0.0012 dB and rejection of 77 dB. For
an alias rejection of 77 dB, the alias-protected bandwidth is 14%
of the filter input sample rate. The bandwidth of the filter for a
ripple of 0.00075 dB is also the same as the alias-protected
bandwidth, due to the nature of half-band filters. The 3 dB
bandwidth of this filter is 44% of the filter input sample rate.
For example, if the sample rate into the filter is 50 MHz, then
the alias-protected bandwidth of the HB1 filter is 7 MHz. If the
bandwidth of the required carrier is greater than 7 MHz, then
HB1 may not be useful.
0
0.43
0.57
–10
–20
–30
–40
–50
dBc
The next stage of the FIR-HB block is a decimate-by-2, halfband filter. The 11-tap, symmetrical, fixed-coefficient HB1 filter
has low power consumption due to its polyphase implementation. The filter has 22 bits of input and output data with 10-bit
coefficients. Table 15 lists the coefficients of the half-band filter.
The normalized coefficients used in the implementation and
the 10-bit decimal equivalent value of the coefficients are also
listed. Other coefficients are 0s.
0.1
04998-0-032
110
–60
–70
FIR1 + HB1 RESPONSE
–80
–90
The input sample rate of this filter is the same as the CIC filter
output rate and is given by
–100
–107
–120
0
fHB1 = fin/MCIC
where:
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FRACTION OF HB1 INPUT SAMPLE RATE
0.9
04998-0-033
–110
Figure 33. Composite Response of FIR1 and HB1 Filters to their Input Rate
fin is the input rate in to the channel.
MCIC is the decimation ratio in the CIC filter stage.
Rev. A | Page 31 of 80
AD6636
0
6-Tap Fixed Coefficient Filter (FIR2)
–25.00
FIR2 RESPONSE
–30
–33.33
–41.67
–50.00
–58.33
–66.67
–75.00
–83.33
Decimal Coefficient
(5-Bit)
−2
+3
+15
The user can either use or bypass this filter. Writing Logic 0 to
the FIR2 enable bit in the FIR-HB control register bypasses this
fixed-coefficient filter. The filter is useful in certain filter
configurations only and bypassing it for other applications
results in power savings. The filter is especially useful in
increasing the stop-band attenuation of the HB2 filter that
follows. Therefore, it is optimal to use both FIR2 and HB2 in a
configuration.
This filter runs at a sample rate given by one of the following
equations:
If HB1 is bypassed,
fFIR2 = fHB1
If HB1 is not bypassed,
fFIR2 = fHB1/2,
where:
fHB1 is the input rate of the HB1 filter.
fFIR2 is the input rate of the FIR2 filter.
The maximum input and output rate for this filter is 75 MHz.
The response of the FIR2 filter is shown in Figure 34.
–100.00
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FRACTION OF FIR2 INPUT SAMPLE RATE
0.9
04998-0-034
–91.67
Table 16. 6-Tap FIR2 Filter Coefficients
Normalized
Coefficient
−0.125
+0.1875
+0.9375
0.61
–16.67
dBc
Following the first cascade of the FIR1 and HB1 filters is the
second cascade of the FIR2 and HB2 filters. The 6-tap, fixedcoefficient FIR2 filter is useful in providing extra alias
protection for the decimating HB2 filter in certain filter
configurations. It is a simple sum-of-products FIR filter with six
filter taps and 5-bit fixed coefficients. Note that this filter does
not decimate. The normalized coefficients used in the
implementation and the 5-bit decimal equivalent value of the
coefficients are listed in Table 16.
Coefficient
Number
C0, C5
C1, C4
C2, C3
0.39
–8.33
Figure 34. FIR2 Filter Response to the Input Rate of the Filter
Decimate-by-2, Half-Band Filter (HB2)
The second stage of the second cascade of the FIR-HB block is a
decimate-by-2, half-band filter. The 27-tap, symmetric, fixedcoefficient HB2 filter has low power consumption due to its
polyphase implementation. The filter has 20 bits of input and
output data with 12-bit coefficients. The normalized
coefficients used in the implementation and the 10-bit decimal
equivalent value of the coefficients are listed in Table 17. Other
coefficients are 0s.
Table 17. HB2 Filter Fixed Coefficients
Coefficient
Number
C1, C27
C3, C25
C5, C23
C7, C21
C9, C19
C11, C17
C13, C15
C14
Normalized
Coefficient
+0.00097656
−0.00537109
+0.015
−0.0380859
+0.0825195
−0.1821289
+0.6259766
+1
Decimal Coefficient
(12-Bit)
+2
−11
+32
−78
+169
−373
+1282
+2048
Similar to the HB1 filter, the user can either use or bypass this
filter. Writing Logic 0 to the HB1 enable bit in the FIR-HB
control register bypasses this fixed-coefficient HB filter. The
filter is useful in certain filter configurations only and bypassing
it for other applications results in power savings. For example,
the filter is useful in narrow-band applications in which more
filtering is required, as compared to wide-band applications, in
which a higher output rate may prohibit the use of a decimating
filter. The response of the HB2 filter is shown in Figure 35.
Rev. A | Page 32 of 80
AD6636
0.01
0.34
0.01
0.66
–9.99
–9.99
–19.99
–19.99
–29.99
–29.99
–39.99
–39.99
0.66
–49.99
–65
–70.00
–60.00
FIR2 + HB2
RESPONSE
–70.00
–80.00
–80.00
HB2 RESPONSE
–90.00
–100.00
–100.00
–110.00
–110.00
–120.00
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FRACTION OF HB2 INPUT SAMPLE RATE
0.9
04998-0-035
–90.00
Figure 35. HB2 Filter Response to the Input Rate of the Filter
–120.00
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FRACTION OF HB2 INPUT SAMPLE RATE
0.9
Figure 36. Composite Response of FIR2 and HB2 filters to their Input Rates
The filter input sample rate is the same as the FIR2 filter output
rate and is given by one of the following equations:
If HB1 is bypassed,
fHB2 = fFIR2 = fHB1
If HB1 is not bypassed,
fHB2 = fFIR2 =
–90
04998-0-036
–60.00
dBc
dBc
–49.99
0.34
f HB1
2
INTERMEDIATE DATA ROUTER
Following the FIR-HB cascade filters is the intermediate data
router. This data router consists of muxes that allow the I and Q
data from any channel front end (input port + NCO + CIC +
FIR-HB) to be processed by any channel back end (MRCF +
DRCF + CRCF). The choice of channel front end is made by
programming a 3-bit MRCF data select word in the MRCF
control register. The valid values for this word and their
corresponding settings are listed in Table 18.
Table 18. Data Router Select Settings
where:
fHB1 is the input rate of the HB1 filter.
fFIR2 is the input rate of the FIR2 filter.
fHB2 is the input rate of the HB2 filter.
The input to the filter has a maximum of 75 MHz. When not
bypassed, the maximum output rate is 37.5 MHz.
The filter has a ripple of 0.00075 dB and rejection of 81 dB. For
an alias rejection of 81 dB, the alias-protected bandwidth is 33%
of the filter input sample rate. The bandwidth of the filter for a
ripple of 0.00075 dB is the same as alias-protected bandwidth,
due to the nature of half-band filters. The 3 dB bandwidth of
this filter is 47% of the filter input sample rate. For example, if
the sample rate into the filter is 25 MHz, then the aliasprotected bandwidth of the HB2 filter is 8.25 MHz (33% of
25 MHz). If the bandwidth of the required carrier is greater
than 8.25 MHz, then HB2 may not be useful.
MRCF Data Select [2:0]
000
001
010
011
1x0
1x1
Data Source
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Allowing different channel back ends to select different channel
front ends is useful in the polyphase implementation of filters.
When multiple AD6636 channels are used to process a single
carrier, a single-channel front end feeds more than one channel
back end. After processing through the channel back ends (RCF
filters), the data is interleaved back from the polyphased channels.
MONORATE RAM COEFFICIENT FILTER (MRCF)
The MRCF is a programmable sum-of-products FIR filter. This
filter block comes after the first data router and before the
DRCF and CRCF programmable filters. It consists of a maximum
of eight taps with 6-bit programmable coefficients. Note that this
block does not decimate and is used as a helper filter for the
DRCF and CRCF filters that follow in the signal chain.
The number of filter taps that are to be calculated is programmable using the 3-bit number-of-taps word in the MRCF
control register of the channel under consideration. The 3-bit
word programmed is one less than the number of filter taps.
The coefficients themselves are programmed in eight MRCF
Rev. A | Page 33 of 80
AD6636
coefficient memory registers for individual channels. The input
and output data to the block are both 20 bit.
Symmetry
Though the MRCF filter does not require symmetrical filters, if
the filter is symmetrical, the symmetry bit in the MRCF control
register should be set. When this bit is set, only half of the
impulse response needs to be programmed into the MRCF
coefficient memory registers. For example, if the number of
filter taps is equal to five or six and the filter is symmetrical,
only three coefficients need to be written into the coefficient
memory. For both symmetrical and asymmetrical filters, the
number of filter taps is limited to eight.
Clock Rate
The MRCF filter runs on an internal, high speed PLL clock.
This clock rate can be as high as 200 MHz. If the half clock rate
bit in the MRCF control register is set, only half the PLL clock
rate is used (maximum of 100 MHz). This results in power
savings but can only be used if certain conditions are met.
Because this filter is nondecimating, the input and output rates
are both the same and equal to one of the following:
Following the MRCF is the programmable DRCF FIR filter.
This filter can calculate up to 64 asymmetrical filter taps or up
to 128 symmetrical filter taps. The filter is also capable of a
programmable decimation rate of from 1 to 16. A flexible
coefficient offset feature allows loading multiple filters into the
coefficient RAM and changing the filters on the fly. The
decimation phase feature allows a polyphase implementation,
where multiple AD6636 channels are used for processing a
single carrier.
The DRCF filter has 20-bit input and output data and 14-bit
coefficient data. The number of filter taps to calculate is
programmable and is set in the DRCF taps register. The value
of the number of taps minus one is written to this register.
For example, a value of 19 in the register corresponds to
20 filter taps.
The decimation rate is programmable using the 4-bit DRCF
decimation rate word in the DRCF control register. Again, the
value written is the decimation rate minus one.
Bypass
The DRCF filter can be used in normal operation or bypassed
using the DRCF bypass bit in the DRCF control register. When
the DRCF filter is bypassed, no scaling is applied and the output
of the filter is the same as the input to the DRCF filter.
If HB2 is bypassed,
fMRCF = fHB2
If HB2 is not bypassed,
Scaling
f
fMRCF = HB2
2
If fPLLCLK is the PLL clock and if f MRCF × N TAPS ≤
f PLLCLK
, then
2
half of the PLL clock can be used for processing (power
savings). Otherwise, the PLL clock should be used.
The MRCF filter can be used in normal operation or bypassed
using the MRCF bypass bit in the MRCF control register. When
the filter is bypassed, the output of the filter is the same as the
input of the filter. Bypassing the MRCF filter when it is not
required results in power savings.
Scaling
The output of the MRCF filter can be scaled by using the 2-bit
MRCF scaling word in the MRCF control register. Table 19
shows the valid values for the 2-bit word and their corresponding settings.
Table 19. MRCF Scaling Factor Settings
Scaling Factor
18.06 dB attenuation
12.04 dB attenuation
6.02 dB attenuation
No scaling, 0 dB
The output of the DRCF filter can be scaled using the 2-bit
DRCF scaling word in the DRCF control register. Table 20 lists
the valid values for the 2-bit word and their corresponding
settings.
Table 20. DRCF Scaling Factor Settings
Bypass
MRCF Scale Word [1:0]
00
01
10
11
DECIMATING RAM COEFFICIENT FILTER (DRCF)
DRCF Scale Word [1:0]
00
01
10
11
Scaling Factor
18.06 dB attenuation
12.04 dB attenuation
6.02 dB attenuation
No scaling, 0 dB
Symmetry
The DRCF filter does not require symmetrical filters. However,
if the filter is symmetrical, the symmetry bit in the DRCF
control register should be set. When this bit is set, only half of
the impulse response needs to be programmed into the DRCF
coefficient memory registers. For example, if the number of
filter taps is equal to 15 or 16 and the filter is symmetrical, only
eight coefficients need to be written into the coefficient
memory. Because a total of 64 taps can be written into the
memory registers, the DRCF can perform 64 asymmetrical
filter taps or 128 symmetrical filter taps.
Rev. A | Page 34 of 80
AD6636
Coefficient Offset
Programming DRCF Registers for an Asymmetrical Filter
More than one set of filter coefficients can be loaded into the
coefficient RAM at any given time (given sufficient RAM
space). The coefficient offset can be used in this case to access
the two or more different filters. By changing the coefficient
offset, the filter coefficients being accessed can be changed on
the fly. This decimal offset value is programmed in the DRCF
coefficient offset register. When this value is changed during the
calculation of a particular output data sample, the sample
calculation is completed using the old coefficients, and the new
coefficient offset from the next data sample calculation is used.
To program the DRCF registers for an asymmetrical filter:
1.
Write NTAPS – 1 in the DRCF taps register, where NTAPS
is the number of filter taps. The absolute maximum value
for NTAPS is 64 in asymmetrical filter mode.
2.
Write 0 to the DRCF coefficient offset register.
3.
Write 0 to the symmetrical filter bit in the DRCF control
register.
4.
Write the start address for the coefficient RAM, typically
equal to the coefficient offset register, in the DRCF start
address register.
5.
In the DRCF stop address register, write the stop address
for the coefficient RAM, typically equal to
Decimation Phase
When more than one channel of AD6636 is used to process one
carrier, polyphase implementation of corresponding channels’
DRCF or CRCF is possible using the decimation phase feature.
This feature can only be used under certain conditions. The
decimation phase is programmed using the 4-bit DRCF
decimation phase word of the DRCF control register.
Coefficient Offset + NTAPS − 1
6.
Write all coefficients in reverse order (start with last
coefficient) to the DRCF coefficient memory register. If in
8-bit microport mode or serial port mode, write the lower
byte of the memory register first and then the higher byte.
7.
After each write access to the DRCF coefficient memory
register, the internal RAM address is incremented starting
with the start address and ending with the stop address.
Maximum Number of Taps Calculated
The output rate of the DRCF filter is given by
f DRCF =
f MRCF
M DRCF
where:
fMRCF is the data rate out of the MRCF filter and into the DRCF
filter.
MDRCF is the decimation rate in the DRCF filter.
The DRCF filter consists of two multipliers (one each for the
I and Q paths). Each multiplier, working at the high speed clock
rate (PLL clock), can do one multiply (or one tap) per high
speed clock cycle. Therefore, the maximum number of filter
taps that can be calculated (symmetrical or asymmetrical filter)
is given by
⎛f
Maximum Number of Taps = ceil⎜⎜ PLLCLK
⎝ f DRCF
⎞
⎟ −1
⎟
⎠
Note that each write or read access increments the internal
RAM address. Therefore, all coefficients should be read first
before reading them back. Also, for debugging purposes, each
RAM address can be written individually by making the start
address and stop address the same. Therefore, to program one
RAM location, the user writes the address of the RAM location
to both the start and stop address registers, and then writes the
coefficient memory register.
Programming DRCF Registers for a Symmetric Filter
To program the DRCF registers for a symmetrical filter:
1.
Write NTAPS – 1 in the DRCF taps register, where NTAPS
is the number of filter taps. The absolute maximum value
for NTAPS is 128 in symmetric filter mode.
2.
Write ceil(64 – NTAPS/2) to the DRCF coefficient offset
register, where the ceil function takes the closest integer
greater than or equal to the argument.
3.
Write 1 to the symmetrical filter bit in the DRCF control
register.
4.
Write the start address for the coefficient RAM, typically
equal to coefficient offset register, in the DRCF start
address register.
where:
fPLLCLK is the high speed internal processing clock generated by
the PLL clock multiplier.
fDRCF is the output rate of the DRCF filter calculated above.
Rev. A | Page 35 of 80
AD6636
5.
6.
Write the stop address for the coefficient RAM, typically
equal to ceil(NTAPS/2) – 1, in the DRCF stop address
register.
Write all coefficients to the DRCF coefficient memory
register, starting with the middle of the filter and working
towards the end of the filter. When coefficients are
numbered 0 to NTAPS – 1, the middle coefficient is given
by the coefficient number ceil(NTAPS/2). If in 8-bit
microport mode or serial port mode, write the lower byte
of the memory register first and then the higher byte. After
each write access to the DRCF coefficient memory register,
the internal RAM address is incremented starting with the
start address and ending with stop address.
Note that each write or read access increments the internal
RAM address. Therefore, all coefficients should be written first
before reading them back. Also, for debugging purposes, each
RAM address can be written individually by making the start
and stop addresses the same. Therefore, to program one RAM
location, the user writes the address of the RAM location to
both the start and stop address registers, and then writes to the
coefficient memory register.
CHANNEL RAM COEFFICIENT FILTER (CRCF)
Following the DRCF is the programmable decimating CRCF
FIR filter. The only difference between the DRCF and CRCF
filters is the coefficient bit width. The DRCF has 14-bit
coefficients, while the CRCF has 20-bit coefficients.
This filter can calculate up to 64 asymmetrical filter taps or up
to 128 symmetrical filter taps. The filter is capable of a
programmable decimation rate from 1 to 16. The flexible
coefficient offset feature allows loading multiple filters into the
coefficient RAM and changing the filters on the fly. The
decimation phase feature allows for a polyphase implementation in which multiple AD6636 channels are used to process a
single carrier.
The CRCF filter has 20-bit input and output data and 20-bit
coefficient data. The number of filter taps to calculate is
programmable and is set in the CRCF taps register. The value of
the number of taps minus one is written to this register. For
example, a value of 19 in the register corresponds to 20 filter
taps. The decimation rate is programmable using the 4-bit
CRCF decimation rate word in the CRCF control register.
Again, the value written is the decimation rate minus one.
Scaling
The output of the CRCF filter can be scaled using the 2-bit
CRCF scaling word in the CRCF control register. Table 21
shows the valid values for the 2-bit word and the corresponding
settings. | ∑COEFF | is the sum of all coefficients (in normalized
form) used to calculate the FIR filter.
Table 21. CRCF Scaling Factor Settings
CRCF Scale Word [1:0]
00
01
10
11
Scaling Factor
18.06 dB attenuation
12.04 dB attenuation
6.02 dB attenuation
No scaling, 0 dB
Symmetry
The CRCF filter does not require symmetrical filters. However,
if the filter is symmetrical, the symmetry bit in the CRCF
control register should be set. When this bit is set, only half the
impulse response needs to be programmed into the CRCF
coefficient memory registers. For example, if the number of
filter taps is equal to 15 or 16 and the filter is symmetric, then
only eight coefficients need to be written into the coefficient
memory. Because a total of 64 taps can be written into the
memory registers, the CRCF can perform 64 asymmetrical filter
taps or 128 symmetrical filter taps.
Coefficient Offset
More than one set of filter coefficients can be loaded into the
coefficient RAM at any time (given sufficient RAM space). The
coefficient offset can be used in this case to access the two or
more different filters. By changing the coefficient offset, the
filter coefficients being accessed can be changed on the fly. This
decimal offset value is programmed in the CRCF coefficient
offset register. When this value is changed during the calculation of a particular output data sample, the sample calculation is
completed using the old coefficients, and the new coefficient
offset is brought into effect from the next data sample
calculation.
Decimation Phase
When more than one channel of the AD6636 is used to process
one carrier, polyphase implementation of the corresponding
channels’ DRCF or CRCF is possible using the decimation
phase feature. This feature can only be used under certain
conditions. The decimation phase is programmed using the
4-bit CRCF decimation phase word of the CRCF control
register.
Bypass
The CRCF filter can be used in normal operation or bypassed
using the CRCF bypass bit in the CRCF control register. When
the CRCF filter is bypassed, no scaling is applied and the output
of the filter is the same as the input to the CRCF filter.
Rev. A | Page 36 of 80
AD6636
Maximum Number of Taps Calculated
The output rate of the CRCF filter is given by
f CRCF =
f DRCF
M CRCF
where:
Note that each write or read access increments the internal
RAM address. Therefore, all coefficients should be read first
before reading them back. Also, for debugging purposes, each
RAM address can be written individually by making the start
and stop addresses the same. Therefore, to program one RAM
location, the user writes the address of the RAM location to
both the start and stop address registers, and then writes the
coefficient memory register.
fDRCF is the data rate out of the DRCF filter and into the CRCF
filter.
Programming CRCF Registers for a Symmetrical Filter
MCRCF is the decimation rate in the CRCF filter.
To program the CRCF registers for a symmetrical filter:
The CRCF filter consists of two multipliers (one each for the I
and Q paths). Each multiplier, working at the high speed clock
rate (PLL clock), can multiply (or tap once). Therefore, the
maximum number of filter taps that can be calculated
(symmetrical or asymmetrical filter) is given by
1.
Write NTAPS – 1 in the CRCF taps register, where NTAPS
is the number of filter taps. The absolute maximum value
for NTAPS is 128 in symmetrical filter mode.
2.
Write ceil(64 – NTAPS/2) to the CRCF coefficient offset
register, where the ceil function takes the closest integer
greater than or equal to the argument.
3.
Write 1 to the symmetrical filter bit in the CRCF control
register.
4.
In the CRCF start address register, write the start address
for the coefficient RAM, typically equal to the coefficient
offset register.
5.
In the CRCF stop address register, write the stop
address for the coefficient RAM, typically equal to
⎛f
Maximum Number of Taps = ceil⎜⎜ PLLCLK
⎝ f CRCF
⎞
⎟ −1
⎟
⎠
where:
fPLLCLK is the high speed internal processing clock generated by
the PLL clock multiplier.
fCRCF is the output rate of the CRCF filter as calculated previously.
Programming CRCF Registers for an Asymmetrical Filter
ceil(NTAPS/2) – 1
To program the CRCF registers for an asymmetrical filter:
1.
Write NTAPS – 1 in the CRCF taps register, where NTAPS
is the number of filter taps. The absolute maximum value
for NTAPS is 64 in asymmetrical filter mode.
2.
Write 0 in the CRCF coefficient offset register.
3.
Write 0 in the symmetrical filter bit in the CRCF control
register.
4.
In the CRCF start address register, write the start address
for the coefficient RAM, typically equal to the coefficient
offset register.
5.
In the CRCF stop address register, write the stop address
for the coefficient RAM, typically equal to
Coefficient Offset + NTAPS – 1
6.
Write all coefficients in reverse order (start with last
coefficient) to the CRCF coefficient memory register. In
8-bit microport mode or serial port mode, write the lower
byte of the memory register first and then the higher byte.
In 16-bit microport mode, write the lower 16-bits of the
CRCF memory register first and then the high four bits.
After each write access to the CRCF coefficient memory
register, the internal RAM address is incremented starting
with the start address and ending with the stop address.
6.
Write all coefficients to the CRCF coefficient memory
register, starting with middle of the filter and working
towards the end of the filter. When coefficients are
numbered 0 to NTAPS – 1, the middle coefficient is given
by the coefficient number ceil(NTAPS/2). In 8-bit
microport mode or serial port mode, write the lower byte
of the memory register first and then the higher byte. In
16-bit microport mode, write the lower 16-bits of the
CRCF memory register first and then the high four bits.
After each write access to the CRCF coefficient memory
register, the internal RAM address is incremented starting
with the start address and ending with the stop address.
Note that each write or read access increments the internal
RAM address. Therefore, all coefficients should be written first
before reading them back. Also, for debugging purposes, each
RAM address can be written individually by making the start
and stop addresses the same. Therefore, to program one RAM
location, the user writes the address of the RAM location to
both the start and stop address registers, and then writes the
coefficient memory register.
Rev. A | Page 37 of 80
AD6636
INTERPOLATING HALF-BAND FILTER
OUTPUT DATA ROUTER
The AD6636 has interpolating half-band FIR filters that
immediately follow the CRCF programmable FIR filters and
precede the second data router. Each interpolating half-band
filter takes 22-bit I and 22-bit Q data from the preceding CRCF
and outputs rounded 22-bit I and 22-bit Q data to the second
data router. A 10-tap fixed-coefficient filter is implemented in
this stage.
The output data router circuit precedes the six AGCs of the
final output block and immediately follows the interpolating
half-band filters. This block consists of two subblocks. The first
subblock is responsible for combining (interleaving) data from
more than one channel into a single stream of data.
The maximum input rate into this block is 17 MHz. Consequently, the maximum output is constrained to 34 MHz. The
normalized coefficients used in the implementation and the
10-bit decimal equivalent value of the coefficients are listed in
Table 22. Other coefficients are 0.
Interleaving Data
In some cases, filtering using a single channel is insufficient.
For such setups, it is advantageous to combine the filtering
resources of more than one channel.
Table 22. Interpolating HB Filter Fixed Coefficients
Coefficient
Number
C1, C11
C3, C9
C5, C7
C6
Normalized
Coefficient
+0.02734375
−0.12890625
+0.603515625
+1
Decimal Coefficient
(10-Bit)
+14
−66
+309
+512
The half-band filters interpolate the incoming data by 2×. For a
channel running at 2× the chip rate, the half-band can be used
to output channel data at 4× the chip rate. The interpolation
operation creates an image of the baseband signal, which is
filtered out by the half-band filter.
The image rejection of this filter is about 55 dB, but is still
sufficient, because the image is from the desired signal, not an
interfering signal. Note that the interpolating half-band filter
can be enabled by writing a Logic 1 to Bit 9 of the MRCF
control registers.
The frequency response of the interpolating half-band FIR is
shown in Figure 37 with respect to the chip rate. The input rate to
this filter is 2× the chip rate, and the output rate is 4× the chip rate.
0
0.75
1.25
–20
INTERPOLATING
HALFBAND
FILTER RESPONSE
dBc
–40
The second subblock can perform two special functions, either
complex filter completion or biphase filtering. The combined
data is passed on to the AGCs.
Multiple channels can be set up to work on the ADC input port
data with the same NCO and filter setups. The decimation
phase values in one of the RCF filters are set such that the
channel filters are exactly out of phase with each other. In the
data router, these multiple channels are interleaved (combined)
to form a single stream of data. Because each individual channel
is decimated more than it would be if a single channel were
filtering, a larger number of filter taps can be calculated.
For example, two channels need to work together to produce a
filter at an output rate of 10 MHz when the input rate is
100 MHz. Each channel is decimated by a factor of 20 (total
decimation) to achieve the desired output rate of 5 MHz each.
This compares to a decimation of 10, if a single channel were
filtering.
The same coefficients are programmed in both channels’ RCF
filters, and the decimation phases are set to 0 and 1. The
decimation phases can be set to 0 for one channel and 1 for the
second channel in the pair. This causes the first channel to
produce the even outputs of the filter, and the second to
produce the odd outputs of the filter. The streams can then be
recombined (interleaved) to produce the desired 10 MHz
output rate. The benefit is that now each channel’s RCF has
time to calculate twice as many taps because it has a lower
output rate.
–53
–60
–100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
FREQUENCY AS FRACTION OF INPUT RATE
04998-0-037
–80
Figure 37. Interpolating Half-Band Frequency Response
Rev. A | Page 38 of 80
AD6636
CH0
STR0
AGC0
AGC0
CH1
AGC1
STR1
AGC1
PARALLEL
PORT A
CH2
STR2
AGC2
AGC2
COMPLEX
FILTER
COMPLETION
STREAM
CONTROL
CH3
STR3
PARALLEL
PORT B
AGC3
AGC3
CH4
STR4
PARALLEL
PORT C
AGC4
AGC4
STR5
AGC5
04998-0-038
CH5
AGC5
Figure 38. Output Data Router Block Diagram
The interleaving function is a simple time-multiplexing
function, with a lower data rate on the input side and a higher
data rate on the output side. The output data rate is the sum of
all input stream data rates that are combined.
The calculated terms include:
The channels that need to be combined are programmable with
sufficient flexibility. Table 23 gives the combinations that are
possible using a 4-bit word (stream control bits) in the Parallel
Port Control 2 register.
Using these terms, the complex filter is completed by applying
After interleaving of data (see the Output Data Router section),
the data is passed to the second subblock, in which either
complex filter completion or biphase filtering can be performed.
Complex Filter Completion
In normal operation, each individual channel’s filter performs
real coefficient, complex data filtering.
Two channels are used to perform complex coefficient data
filtering. One channel is loaded with the real part (in-phase) of
the coefficients; the other channel is loaded with the imaginary
part (quadrature) of the coefficients.
•
(ICi, QCi) from first channel
•
(Icq, QCq) from the second channel
(I + jQ) (Ci + jCq) = (ICi − QCq) + j(ICq + QCi)
The channels to be combined can be programmed using a 3-bit
complex control word in the Parallel Output Control 2 register.
The values for the 3-bit control word and the corresponding
settings are listed in Table 24.
These outputs go to the six available AGCs. Not all AGCs need
to be used in the different applications, so unused AGCs can be
bypassed and the output data streams ignored by the parallel
output ports. For example, if Stream 0 and Stream 1 are
combined for a complex filter, AGC1 can be bypassed, because
Stream 1 is already combined into Stream 0 and sent to AGC0.
Table 23. Stream Control Bit Combinations
Stream Control Bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Any other state
Output Streams
Ch 0/Ch 1 combined, Ch 2, Ch 3, Ch 4, Ch 5 independent
Ch 0/Ch 1/Ch 2 combined, Ch 3, Ch 4, Ch5 independent
Ch 0/Ch 1/Ch 2/Ch 3 combined; Ch 4, Ch 5 independent
Ch 0/Ch 1/Ch 2/Ch 3/Ch 4 combined; Ch 5 independent
Ch 0/Ch 1/Ch 2/Ch 3/Ch 4/Ch 5 combined
Ch 0/Ch 1/Ch 2 combined, Ch 3/Ch 4/Ch 5 combined
Ch 0/Ch 1 combined, Ch 2/Ch 3 combined, Ch 4/Ch 5 combined
Ch 0/Ch 1 combined, Ch 2/Ch 3 combined, Ch 4, Ch 5 independent
Ch 0/Ch 1/Ch 2 combined, Ch 3/Ch 4 combined, Ch 5 independent
Ch 0/Ch 1/Ch 2/Ch 3 combined, Ch 4/Ch 5 combined.
Independent channels
Rev. A | Page 39 of 80
No. of Streams
5
4
3
2
1
2
3
3
3
2
6
AD6636
Table 24. Definitions for Complex Control Register Selections
Complex Control Word
000
001
010
011
101
110
111
Data Routing
No complex filters
Stream 0/Stream 1 combined
Stream 0/Stream 1 combined,
Stream 2/Stream 3 combined
Stream 0/Stream 1 combined,
Stream 2/Stream 3 combined,
Stream 4/Stream 5 combined
Stream 0/Stream 1 Combined
Stream 0/Stream 1 combined,
Stream 2/Stream 3 combined
Stream 0/Stream 1 combined,
Stream 2/Stream 3 combined,
Stream 4/Stream 5 combined
Comments
Stream control register controls AGC usage.
Allows Ch 0 and Ch 1 to form a complex filter.
Allows Ch 0 and Ch 1 to form a complex filter and Ch 2 and Ch 3 to
form a complex filter.
Allows Ch 0 and Ch 1 to form a complex filter, Ch 2 and Ch 3 to form a
complex filter, and Ch 4 and Ch 5 to form a complex filter.
Allows Ch 0 and Ch 1 to form a biphase filter.
Allows Ch 0 and Ch 1 to form a biphase filter, and Ch 2 and Ch 3 to
form a biphase filter.
Allows Ch 0 and Ch 1 to form a biphase filter, Ch 2 and Ch 3 to form a
biphase filter, and Ch 4 and Ch 5 to form a biphase filter.
Biphase Filtering Option
The second special function that can be performed by the
second subblock of the output data router is called the biphase
filtering option. With this option, the AD6636 can be used to
process data from ADCs that run faster than the input clock
frequency by using two channels or two streams to form a
biphase filter.
For example, a 300 MHz ADC can be used with a clock rate of
150 MHz driving the ADC. The ADC data can be decimated by
2 to produce even and odd data streams of data. The even
stream can be clocked into ADC Input Port A, and the odd
stream can be clocked into ADC Input Port B. These input
ports drive separate channels or separate groups of channels.
The filters of the RCF can be designed to place a 300 MHz
sample time difference (1/300 MHz = 3.3 ns) between the even
and odd path filters.
After the channel-filter coefficients have appropriate delay, a
complex addition of the odd and even sample channels can be
performed to create a single filter. This equivalent filter looks
like a single channel with a 300 MHz input rate, even though
the clock rate of the chip runs at only 150 MHz.
Users can program certain streams to be summed using the
biphase filtering option. This option can be programmed using
the same 3-bit complex control word in the Parallel Output
Control 2 register. The values for the 3-bit control word and
their corresponding settings are listed in Table 24.
AUTOMATIC GAIN CONTROL
The AD6636 is equipped with six independent automatic gain
control (AGC) loops that directly follow the second data router
and immediately precede the parallel output ports. Each AGC
circuit has 96 dB of range. It is important that the decimating
filters of the AD6636 preceding the AGC reject unwanted
signals so that each AGC loop is operating on the carrier of
interest only, and carriers at other frequencies do not affect the
ranging of the loop.
The AGC compresses the 22-bit complex output from the
second data router into a programmable word size of 4 bits to
8 bits, 10 bits, 12 bits, or 16 bits. Because the small signals from
the lower bits are pushed in to higher bits by adding gain, the
clipping of the lower bits does not compromise the SNR of the
signal of interest.
The AGC maintains a constant mean power on the output
despite the level of the signal of interest, allowing operation in
environments where the dynamic range of the signal exceeds
the dynamic range of the output resolution. The output width of
the AGC is set by writing a 3-bit AGC word length word in the
AGC control register of the individual channel’s memory map.
A biphase filter summation is implemented by
Output = (Ie × Ce + Io × Co) + j(Qe × Ce + Qo × Co)
where:
Ie × Ce, Qe × Ce are even in-phase and quadrature-phase
samples from one stream.
Io × Co and Qo × Co are odd in-phase and quadrature-phase
samples from the other stream.
Ce and Co are the even and odd coefficients, which differ by
1 high speed sample time (300 MHz in the previous example).
The AGC can be bypassed, if needed, and, when bypassed, the
22-bit complex input word is still truncated to a 16-bit value
that is output through the parallel port output. The six AGCs
available on the AD6636 are programmable through the six
channel memory maps. AGCs corresponding to individual
channels can be bypassed by writing Logic 1 to AGC bypass bit
in the AGC control register.
Rev. A | Page 40 of 80
AD6636
I
Q
22
BITS
CLIP
GAIN MULTIPLIER
CLIP
I
PROGRAMMABLE
BIT WIDTH
Q
USED ONLY FOR
DESIRED CLIPPING
LEVEL MODE
MEAN SQUARE (I2 + Q2)
AVERAGE 1 – 16384 SAMPLES
DECIMATE 1 – 4096 SAMPLES
SQUARE ROOT
log2(x)
2×
POWER OF 2
E ERROR
THRESHOLD
R DESIRED
ERROR
04998-0-039
K × z –1
1 – (1 + P) × z –1 + P × z –2
K1 GAIN
K2 GAIN
P POLE
Figure 39. Block Diagram of the AGC
Three sources of error can be introduced by the AGC function:
underflow, overflow, and modulation. Underflow is caused by
truncation of bits below the output range. Overflow is caused by
clipping errors when the output signal exceeds the output range.
Modulation error occurs when the output gain varies while
receiving data.
The desired signal level should be set based on the probability
density function of the signal, so that the errors due to underflow and overflow are balanced. The gain and damping values
of the loop filter should be set so that the AGC is fast enough to
track long-term amplitude variations of the signal that may
cause excessive underflow or overflow but slow enough to avoid
excessive loss of amplitude information due to the modulation
of the signal.
AGC Loop
The AGC loop is implemented using a log-linear architecture. It
contains four basic operations: power calculation, error calculation, loop filtering, and gain multiplication.
The AGC can be configured to operate in either desired signal
level mode or desired clipping level mode. The mode is set by
the AGC clipping error bit of the AGC control register. The
AGC adjusts the gain of the incoming data according to how far
it is from a given desired signal level or desired clipping level,
depending on the selected mode of operation.
Two datapaths to the AGC loop are provided: one before the
clipping circuitry and one after the clipping circuitry, as shown
in Figure 39. For the desired signal level mode, only the I/Q
path from before the clipping is used. For the desired clipping
level mode, the difference of the I/Q signals from before and
after the clipping circuitry is used.
Desired Signal Level Mode
In this mode of operation, the AGC strives to maintain the
output signal at a programmable set level. The desired signal
level mode is selected by writing Logic 0 into the AGC mode bit
of the AGC control register. The loop finds the square (or
power) of the incoming complex data signal by squaring I and
Q and adding them.
The AGC loop has an average and decimate block. This average
and decimate operation takes place on power samples and
before the square root operation. This block can be programmed to average from 1 to 16,384 power samples, and the
decimate section can be programmed to update the AGC once
every 1 to 4,096 samples. The limitation on the averaging
operation is that the number of averaged power samples should
be a multiple of the decimation value (1×, 2×, 3×, or 4×).
The averaging and decimation effectively means that the AGC
can operate over averaged power of 1 to 16,384 output samples.
Updating the AGC once every 1 to 4,096 samples and operating
on average power facilitates the implementation of the loop
filter with slow time constants, where the AGC error converges
slowly and makes infrequent gain adjustments. It is also useful
when the user wants to keep the gain scaling constant over a
frame of data or a stream of symbols.
Due to the limitation that the number of average samples must
be a multiple of the decimation value, only the multiple
numbers 1, 2, 3, or 4 are programmed. This is set using the
AGC average samples word in the AGC average sample register.
These averaged samples are then decimated with decimation
ratios programmable from 1 to 4,096. This decimation ratio is
defined in the 12-bit AGC update decimation register.
Rev. A | Page 41 of 80
AD6636
The average and decimate operations are tied together and
implemented using a first-order CIC filter and FIFO registers.
Gain and bit growth are associated with CIC filters and depend
on the decimation ratio. To compensate for the gain associated
with these operations, attenuation scaling is provided before the
CIC filter.
The request signal level should also compensate for errors, if
any, due to the CIC scaling, as explained previously in this
section. Therefore, the request signal level is offset by the
amount of error induced in CIC, given by
This scaling operation accounts for the division associated with
the averaging operation as well as the traditional bit growth in
CIC filters. Because this scaling is implemented as a bit-shift
operation, only coarse scaling is possible. Fine scaling is
implemented as an offset in the request level, as explained later
in this section. The attenuation scaling SCIC is programmable
from 0 to 14 using a 4-bit CIC scale word in the AGC average
samples register and is given by
where Offset is in dB.
Offset = 10 × log(MCIC × Navg) − SCIC × 3.01 dB
Continuing the previous example, this offset is given by
Offset = 72.24 − 69.54 = 2.7 dB
So the request signal level is given by
⎡ (DSL − Offset ) ⎤
R = −ceil ⎢
⎥⎦ × 0.094 dBFS
0.094
⎣
SCIC = ceil [log2(MCIC × Navg)]
where:
where:
R is the request signal level.
MCIC is the decimation ratio (1 to 4,096).
DSL (desired signal level) is the output signal level that the user
desires.
NAVG is the number of averaged samples programmed as a
multiple of the decimation ratio (1, 2, 3, or 4).
For example, if a decimation ratio MCIC is 1,000 and Navg is 3
(decimation of 1,000 and averaging of 3,000 samples), then the
actual gain due to averaging and decimation is 3,000 or
69.54 dB (log2 (3000)). Because attenuation is implemented as a
bit-shift operation, only multiples of 6.02 dB attenuations are
possible. SCIC in this case is 12, corresponding to 72.24 dB. This
way, SCIC scaling always attenuates more than is sufficient to
compensate for the gain in the average and decimate sections
and, therefore, prevents overflows in the AGC loop. However, it
is also evident that the SCIC scaling induces a gain error (the
difference between gain due to CIC and attenuation provided
by scaling) of up to 6.02 dB. This error should be compensated
for in the request signal level, as explained later in this section.
A Base 2 logarithm is applied to the output from the average
and decimate section. These decimated power samples are
converted to rms signal samples by applying a square root
operation. This square root is implemented using a simple shift
operation in the logarithmic domain. The rms samples obtained
are subtracted from the request signal level R specified in the
AGC desired level register, leaving an error term to be
processed by the loop filter, G(z).
The user sets this programmable request signal level R according to the output signal level that is desired. The request signal
level R is programmable from −0 dB to −23.99 dB in steps of
0.094 dB.
Therefore, in the previous example, if the desired signal level is
−13.8 dB, the request level R is programmed to be −16.54 dB,
compensating for the offset.
This request signal level is programmed in the 8-bit AGC
desired level register. This register has a floating-point representation, where the 2 MSBs are exponent bits and the 6 LSBs are
mantissa bits. The exponent is in steps of 6.02 dB, and the
mantissa is in steps of 0.094 dB. For example, a 10’100101 value
represents 2 × 6.02 + 37 × 0.094 = 15.518 dB.
The AGC provides a programmable second-order loop filter.
The programmable parameters gain 1 (K1), gain 2 (K2), error
threshold E, and pole P completely define the loop filter
characteristics. The error term after subtracting the request
signal level is processed by the loop filter, G(z). The open-loop
poles of the second-order loop filter are 1 and P, respectively.
The loop filter parameters, pole P and gain K, allow the
adjustment of the filter time constant that determines the
window for calculating the peak-to-average ratio.
Depending on the value of the error term that is obtained after
subtracting the request signal level from the actual signal level,
either gain value, K1 or K2, is used. If the error is less than the
programmable threshold E, K1, or K2 is used. This allows a fast
loop when the error term is high (large convergence steps
required) and a slower loop function when error term is smaller
(almost converged).
Rev. A | Page 42 of 80
AD6636
The open-loop gain used in the second-order loop G(z) is given
by one of the following equations:
The time constants can also be derived from settling times as
given by
If Error < Error Threshold,
τ=
K = K1
If Error > Error Threshold,
K = K2
The open-loop transfer function for the filter, including the gain
parameter, is
G(z ) =
Kz −1
1 − (1 + P )z −1 + Pz −2
If the AGC is properly configured in terms of offset in request
level, then there are no gains in the AGC loop except for the
filter gain K. Under these circumstances, a closed-loop
expression for the AGC loop is given by
G closed ( z ) =
G(z )
Kz −1
=
1 + G( z ) 1 + (K − 1 − P )z −1 + Pz −2
The gain parameters K1, K2, and pole P are programmable
through AGC loop gain 1, 2, and AGC pole location registers
from 0 to 0.996 in steps of 0.0039 using 8-bit representation. For
example, 1000 1001 represent (137/256 = 0.535156). The error
threshold value is programmable between 0 dB and 96.3 dB in
steps of 0.024 dB. This value is programmed in the 12-bit AGC
error threshold register, using floating-point representation. It
consists of four exponent bits and eight mantissa bits. Exponent
bits are in steps of 6.02 dB and mantissa bits are in steps of
0.024 dB. For example, 0111’10001001 represents 7 × 6.02 +
137 × 0.024 = 45.428 dB.
The user defines the open-loop pole P and gain K, which also
directly impact the placement of the closed-loop poles and filter
characteristics. These closed-loop poles, P1, P2, are the roots of
the denominator of the previous closed-loop transfer function
and are given by
(1 + P − K ) ± (1 + P − K )
2
P1 , P2 =
− 4P
2
Typically, the AGC loop performance is defined in terms of its time
constant or settling time. In this case, the closed-loop poles should
be set to meet the time constants required by the AGC loop.
The relationship between the time constant and the closed-loop
poles that can be used for this purpose is
2% settling time
4
or
5% settling time
3
MCIC (CIC decimation is from 1 to 4,096) and either the settling
time or time constant are chosen by the user. The sample rate is
the sample rate of the stream coming into the AGC. If channels
were interleaved in the output data router, then the combined
sample rate into the AGC should be considered. This rate
should be used in the calculation of poles in the previous
equation, where the sample rate is mentioned.
The loop filter output corresponds to the signal gain that is
updated by the AGC. Because all computation in the loop filter
is done in logarithmic domain (to the Base 2) of the samples,
the signal gain is generated using the exponent (power of 2) of
the loop filter output.
The gain multiplier gives the product of the signal gain with
both the I and Q data entering the AGC section. This signal
gain is applied as a coarse 4-bit scaling and then as a fine scale
8-bit multiplier. Therefore, the applied signal gain is from 0 dB
to 96.3 dB in steps of 0.024 dB. The initial signal gain is
programmable using the AGC signal gain register. This register
is again a 4 exponent + 8 mantissa bit floating-point
representation similar to the error threshold. This is taken as
the initial gain value before the AGC loop starts operating.
The products of the gain multiplier are the AGC scaled outputs
with a 19-bit representation. These are in turn used as I and Q
for calculating the power, and the AGC error and loop are
filtered to produce the signal gain for the next set of samples.
These AGC-scaled outputs can be programmed to have 4-, 5-,
6-, 7-, 8-, 10-, 12-, or 16-bit widths by using the AGC output
word length word in the AGC control register. The AGC-scaled
outputs are truncated to the required bit widths by using the
clipping circuitry, as shown in Figure 39.
Average Samples Setting
Though it is complicated to express the exact effect of the
number of averaging samples by using equations, intuitively it
has a smoothing effect on the way the AGC loop addresses a
sudden increase or a spike in the signal level. If averaging of
four samples is used, the AGC addresses a sudden increase in
signal level more slowly compared to no averaging. The same
applies to the manner in which the AGC addresses a sudden
decrease in the signal level.
Desired Clipping Level Mode
P1, 2
⎡
⎤
M CIC
⎥
= exp ⎢
⎢⎣ Sample Rate × τ1, 2 ⎥⎦
where τ 1, 2 are the time constants corresponding to poles P1, 2.
Each AGC can be configured so that the loop locks onto a
desired clipping level or a desired signal level. Desired clipping
level mode is selected by writing Logic 1 in the AGC clipping
error mode bit in the AGC control register. For signals that tend
to exceed the bounds of the peak-to-average ratio, the desired
Rev. A | Page 43 of 80
AD6636
clipping level option provides a way to prevent truncating those
signals and still provide an AGC that attacks quickly and settles
to the desired output level. The signal path for this mode of
operation is shown with dotted lines in Figure 39; the operation
is similar to the desired signal level mode.
First, the data from the gain multiplier is truncated to a lower
resolution (4 bits, 5 bits, 6 bits, 7 bits, 8 bits, 10 bits, 12 bits, or
16 bits) as set by the AGC output word length word in the AGC
control register. An error term (for both I and Q) is generated
that is the difference between the signals before and after
truncation. This term is passed to the complex squared
magnitude block, for averaging and decimating the update
samples and taking their square root to find rms samples as in
desired signal level mode. In place of the request desired signal
level, a desired clipping level is subtracted, leaving an error term
to be processed by the second-order loop filter.
The rest of the loop operates the same way as the desired signal
level mode. This way, the truncation error is calculated and the
AGC loop operates to maintain a constant truncation error
level. The only register setting that is different from the desired
signal level mode settings is that the desired clipping level is
stored in the AGC desired level registers instead of in the
request signal level.
AGC Synchronization
When the AGC output is connected to a RAKE receiver, the
RAKE receiver can synchronize the average and update section
to update the average power for AGC error calculation and loop
filtering. This external sync signal synchronizes the AGC
changes to the RAKE receiver and makes sure that the AGC
gain word does not change over a symbol period, which,
therefore, provides a more accurate estimation. This synchronization can be accomplished by setting the appropriate bits of
the AGC control register.
Sync Process
Regardless of how a sync signal is received, the syncing process
is the same. When a sync is received, a start hold-off counter is
loaded with the 16-bit value in the AGC hold-off register, which
initiates the countdown. The countdown is based on the ADC
input clock. When the count reaches 1, a sync is initiated. When
a sync is initiated, the CIC decimation filter dumps the current
value to the square root, error estimation, and loop filter blocks.
After dumping the current value, it starts working toward the
next update value. Additionally on a sync, AGC can be
initialized if the initialize AGC on sync bit is set in the AGC
control register. During initialization, the CIC accumulator is
cleared and new values for CIC decimation, number of
averaging samples, CIC scale, signal gain, open-loop gains K1
and K2, and pole parameter P are loaded from their respective
registers. When the initialize on sync bit is cleared, these
parameters are not loaded from the registers.
This sync process is also initiated when a channel comes out of
sleep by using the start sync to the NCO. An additional feature
is the first sync only bit in the AGC control register. When this
bit is set, the first sync initiates the process only and the
remaining sync signals are ignored. This is useful when syncing
using a pin sync. A sync is required on the first pulse on this pin
only. These additional features make AGC synchronization
more flexible and applicable to varied circumstances.
PARALLEL PORT OUTPUT
The AD6636 incorporates three independent 16-bit parallel
ports for output data transfer. The three parallel output ports
share a common clock, PCLK. Each port consists of a 16-bit
data bus, a REQuest signal, an ACKnowledge signal, three
channel indicator pins, one I/Q indicator pin, one gain word
indicator pin, and a common shared PCLK pin. The parallel
ports can be configured to function in master or slave mode. By
default, the parallel ports are in slave mode on power-up.
Sync Select Alternatives
The AGC can receive a sync as follows:
•
Channel sync: The sync signal is used to synchronize the
NCO of the channel under consideration.
•
Pin sync: Select one of the four SYNC pins.
•
Sync now bit: Through the AGC control register.
When the channel sync select bit of the AGC control register is
Logic 1, the AGC receives the SYNC signal used by the NCO of
the corresponding channel for the start. When this bit is
Logic 0, the pin sync defined by the 2-bit SYNC pin select word
in the AGC control register is used to provide the sync to the
AGC. Apart from these two methods, the AGC control register
also has a sync now bit that can be used to provide a sync to
the AGC by writing to this register through the microport or
serial port.
Each parallel port can output data from any or all of the AGCs,
using the 1-bit enable bit for each AGC in the parallel port
control register. Even when the AGC is not required for a
certain channel, the AGC can be bypassed, but the data is still
received from the bypassed AGC. The parallel port
functionality is programmable through the two parallel port
control registers.
Each parallel port can be programmed individually to operate
in either interleaved I/Q mode or parallel I/Q mode. The mode
is selected using a 1-bit data format bit in the parallel port
control register. In both modes, the AGC gain word output can
be enabled using a 1-bit append gain bit in the parallel port
control register for individual output ports. There are six enable
bits per output port, one for each AGC in the corresponding
parallel port.
Rev. A | Page 44 of 80
AD6636
Interleaved I/Q Mode
data bus on the next PCLK rising edge after PxREQ is driven
logic high. The PxIQ signal also goes high to indicate that I data
is available on the data bus. The next PCLK cycle brings the
Q data onto the data bus. In this cycle, the PxIQ signal is driven
low. When I data and Q data are output, the channel indicator
pins PxCH[2:0] indicate the data source (AGC number).
Parallel port channel mode is selected by writing 0 to the data
format bit for the parallel port in consideration. In this mode, I
and Q words from the AGC are output on the same 16-bit data
bus on a time-multiplexed basis. The 16-bit I word is output
followed by the 16-bit Q word. The specific AGCs output by the
port are selected by setting individual bits for each of the AGCs
in the parallel port control register. Figure 40 shows the timing
diagram for the interleaved I/Q mode.
Figure 40 is the timing diagram for interleaved I/Q mode with
the AGC gain word disabled. Figure 41 is a similar timing
diagram with the AGC gain word. I and Q data are as explained
for Figure 40. In the PCLK cycle after the Q data, the AGC gain
word is output on the data bus and the PxGAIN signal is pulled
high to indicate that the gain word is available on the parallel
port. Therefore, a minimum of three or four PCLK cycles are
required to output one sample of output data on the parallel
port without or with the AGC gain word, respectively.
When an output data sample is available for output from an
AGC, the parallel port initiates the transfer by pulling the
PxREQ signal high. In response, the processor receiving the
data needs to pull the PxACK signal high, acknowledging that it
is ready to receive the signal. In Figure 40, PxACK is already
pulled high and, therefore, the 16-bit I data is output on the
PCLKn
PxACK
tDPREQ
PxREQ
tDPP
Px [15:0]
I [15:0]
Q [15:0]
tDPIC
PxIQ
tDPCH
PxCH [2:0]
04998-0-040
PxCH [2:0] = CHANNEL NO.
LOGIC LOW ‘0’
PxGAIN
Figure 40. Interleaved I/Q Mode Without an AGC Gain Word
PCLK
PxACK
tDPREQ
PxREQ
tDPP
Px [15:0]
I[15:0]
Q[15:0]
0000 +
GAIN [11:0]
tDPIQ
PxIQ
tDPCH
PxCH [2:0] = CHANNEL NO.
tDPGAIN
PxGAIN
Figure 41. Interleaved I/Q Mode with an AGC Gain Word
Rev. A | Page 45 of 80
04998-0-041
PxCH [2:0]
AD6636
Parallel IQ Mode
The PACH[2:0] and PBCH[2:0] pins provide a 3-bit binary value
indicating the source (AGC number) of the data currently being
output. Figure 42 is the timing diagram for parallel I/Q mode.
In this mode, eight bits of I data and eight bits of Q data are
output on the data bus simultaneously during one PCLK cycle.
The I byte is the most significant byte of the port, while the
Q byte is the least significant byte. The PAIQ and PBIQ output
indicator pins are set high during the PCLK cycle. Note that if
data from multiple AGCs are output consecutively, the PAIQ
and PBIQ output indicator pins remain high until data from all
channels is output.
When an output data sample is available for output from an
AGC, the parallel port initiates the transfer by pulling the
PxREQ signal high. In response, the processor receiving the
data needs to pull the PxACK signal high, acknowledging that it
is ready to receive the signal.
PCLK
PxACK
tDPREQ
PxREQ
tDPP
I [15:8]
Q [15:8]
Px [15:0]
tDPIQ
PxIQ
tDPCH
PxCH [2:0]
04998-0-042
PxCH [2:0] =
AGC NO.
LOGIC LOW 0
PxGAIN
Figure 42. Parallel I/Q Mode Without an AGC Gain Word
PCLK
PxACK
tDPREQ
PxREQ
tDPP
Px [15:0]
I [15:8]
Q [15:8]
0000 +
GAIN [11:0]
tDPIQ
PxIQ
tDPCH
PxCH [2:0] = CHANNEL NO.
tDPGAIN
PxGAIN
Figure 43. Parallel I/Q Mode with an AGC Gain Word
Rev. A | Page 46 of 80
04998-0-043
PxCH [2:0]
AD6636
In Figure 42, the PxACK is already pulled high and, therefore,
the 8-bit I data and 8-bit Q data are simultaneously output on
the data bus on the next PCLK rising edge after PxREQ is
driven logic high. The PxIQ signal also goes high to indicate
that I/Q data is available on the data bus. When I/Q data is
being output, the channel indicator pins PxCH[2:0] indicate the
data source (AGC number).
Figure 42 is the timing diagram for interleaved I/Q mode with
the AGC gain word disabled. Figure 43 is a similar timing
diagram with the AGC gain word enabled. I and Q data are as
shown in Figure 39. In the PCLK cycle after the I/Q data, the
AGC gain word is output on the data bus, and the PxGAIN
signal is pulled high to indicate that the gain word is available
on the parallel port. During this PCLK cycle, the PxIQ signal is
pulled low to indicate that I/Q data is not available on the data
bus. Therefore, in parallel I/Q mode, a minimum of two PCLK
cycles is required to output one sample of output data on the
parallel port without and with the AGC gain word, respectively.
The order of data output is dependent on when data arrives at
the port, which is a function of total decimation rate, DRCF/
CRCF decimation phase, and start hold-off values. Priority
order from highest to lowest is AGCs 0, 1, 2, 3, 4, and 5 for both
parallel I/Q and interleaved modes of output.
Master/Slave PCLK Modes
The parallel ports can operate in either master or slave mode.
The mode is set via the PCLK master mode bit in the Parallel
Port Control 2 register. The parallel ports power up in slave
mode to avoid possible contentions on the PCLK pin.
In master mode, PCLK is an output derived by dividing
PLL_CLK down by the PCLK divisor. The PCLK divisor can
have a value of 1, 2, 4, or 8, depending on the 2-bit PCLK
divisor word setting in the Parallel Port Control 2 register. The
highest PLCK rate in master mode is 200 MHz. Master mode is
selected by setting the PCLK master mode bit in the Parallel
Port Control 2 register.
PCLK Rate =
PLL_CLK Rate
PCLK Divisor
In slave mode, external circuitry provides the PCLK signal.
Slave mode PCLK signals can be either synchronous or
asynchronous. The maximum slave mode PCLK frequency is
also 200 MHz.
Parallel Port Pin Functions
Table 25 describes the functions of the pins used by the parallel ports.
Table 25. Parallel Port Pin Functions
Mnemonic
PCLK
I/O
I/O
PAREQ, PBREQ,
PCREQ
O
PAACK, PBACK,
PCACK
I
PAIQ, PBIQ,
PCIQ
PAGAIN,
PBGAIN,
PCGAIN
PACH[2:0],
PBCH[2:0],
PCCH[2:0]
PADATA[15:0],
PBDATA[15:0],
PCDATA[15:0]
Function
PCLK can operate as a master or as a slave. This setting is dependent on the 1-bit PCLK master mode bit in the
Parallel Port Control 2 register. As an output (master mode), the maximum frequency is CLK/N, where CLK is
AD6636 clock and N is an integer divisor of 1, 2, 4, or 8. As an input (slave mode), it can be asynchronous or
synchronous relative to the AD6636 CLK. This pin powers up as an input to avoid possible contentions.
Parallel port output pins change on the rising edge of PCLK.
Active high output. Synchronous to PCLK. A logic high on this pin indicates that data is available to be shifted
out of the port. When an acknowledge signal is received, data starts shifting out and this pin remains high until
all pending data has been shifted out.
Active high asynchronous input. Applying a logic low on this pin inhibits parallel port data shifting. Applying
a logic high to this pin when REQ is high causes the parallel port to shift out data according to the programmed
data mode.
ACK is sampled on the rising edge of PCLK. Assuming that REQ is asserted, the latency from the assertion of ACK
to data appearing at the parallel port output is no more than 1.5 PCLK cycles. ACK can be held high continuously;
in this case, when data becomes available, shifting begins 1 PCLK cycle after the assertion of REQ (see Figure 40,
Figure 41, Figure 42, and Figure 43).
High whenever I data is present on the parallel port data bus; otherwise low. In parallel I/Q mode, both I data
and Q data are available at the same time and, therefore, the PxIQ signal is pulled high.
High whenever the AGC gain word is present on the parallel port data bus; otherwise low.
These pins identify data in both of the parallel port modes. The 3-bit value identifies the source of the data
(AGC number) on the parallel port when it is being shifted out.
Parallel output port data bus. Output format is twos complement. In parallel I/Q mode, 8-bit data is present;
in interleaved I/Q mode, 16-bit data is available.
Rev. A | Page 47 of 80
AD6636
USER-CONFIGURABLE, BUILT-IN SELF-TEST (BIST)
Start with Soft Sync
Each channel of AD6636 includes a BIST block. The BIST,
along with an internal test signal (pseudorandom test input
signal), can be used to generate a signature. This signature can
be compared with a known good device and an untested device
to see if the untested device is functional.
The AD6636 can synchronize channels or chips under microprocessor control. The start hold-off counter, in conjunction
with the soft start enable bit and the channel enable bits, enables
this synchronization.
BIST timer bits in the BIST control register can be programmed
with a timer value that determines the number of clock cycles
that the output of the channels (output of AGC) have
accumulated. When the disable signature generation bit is
written with Logic 0, the BIST timer is counted down and a
signature register is written with the accumulated output of the
AD6636 channel.
When the BIST timer expires, the signature register for I and Q
paths can be read back to compare it with the signature register
from a known good device.
To synchronize the start of multiple channels via microprocessor control:
1.
Write the channel enable register to enable one or more
channels, if the channels are inactive.
2.
Write the NCO start hold-off counter register(s) with the
appropriate value (greater than 0 and less than 216).
3.
Write 0x00 to the soft synchronization configuration
register.
4.
Write the soft sync channel enable bit(s) and soft start
synchronization enable bit high in the soft synchronization
configuration register. This starts the countdown by the
start hold-off counter. When the count reaches 1, the
channels are activated or resynchronized.
CHIP SYNCHRONIZATION
The AD6636 offers two types of synchronization: start sync and
hop sync. Start sync is used to bring individual channels out of
sleep after programming. It can also be used while AD6636 is
operational to resynchronize the internal clocks. Hop sync is
used to change or update the NCO frequency tuning word and
the NCO phase offset word.
Two methods can be used to initiate a start sync or hop sync:
Note that when using SPI or SPORT for programming these
registers, the last step in the above procedure needs to be
repeated. Therefore, the soft synchronization configuration
register is written twice.
Start with Pin Sync
•
Soft sync is provided by the memory map registers and is
applied to channels directly through the microport or serial
port interface.
Four sync pins (0, 1, 2, and 3) provide very accurate synchronization among channels. Each channel can be programmed to
monitor any of the four sync pins.
•
Pin sync is provided using four hard-wired SYNC[3:0] pins.
Each channel is programmed to listen to one of these SYNC
pins and do a start sync or a hop sync when a signal is
received on these pins.
To start the channels with a pin sync:
The pin synchronization configuration register (Address 0x04)
is used to make pin synchronization even more flexible. The
part can be programmed to be edge-sensitive or level-sensitive
for SYNC pins. In edge-sensitive mode, a rising edge on the
SYNC pins is recognized as a synchronization event.
Start
Start refers to the startup of an individual channel or chip, or of
multiple chips. If a channel is not used, it should be put into
sleep mode to reduce power dissipation. Following a hard reset
(low pulse on the RESET pin), all channels are placed into sleep
mode. Alternatively, channels can be put to sleep manually by
writing 0 to the sleep register.
1.
Write the channel register to enable one more channels, if
the channels are inactive.
2.
Write the NCO start hold-off counter register(s) with the
appropriate value (greater than 0 and less than 216 ).
3.
Program the channel NCO control registers to monitor the
appropriate SYNC pins.
4.
Write the start synchronization enable bit and SYNC pin
enable bits high in the pin synchronization configuration
register. This starts the countdown of the start hold-off
counter. When the count reaches 1, the channels are
activated or resynchronized.
Hop
Hop is a jump from one NCO frequency and/or phase offset to
a new NCO frequency and/or phase offset. This change in
frequency and/or phase offset can be synchronized via
microprocessor control (soft sync) or via an external sync signal
(pin sync).
Rev. A | Page 48 of 80
AD6636
Hop with Soft Sync
SERIAL PORT CONTROL
The AD6636 can synchronize a change in NCO frequency
and/or phase offset of multiple channels or chips under
microprocessor control. The NCO hop hold-off counter, in
conjunction with the soft hop enable bit and the channel enable
bits, enables this synchronization.
The AD6636 serial port allows all memory to be accessed
(programmed or readback) serially in one-byte words. Either
serial port or microport can be used (but not both) at any given
time. Serial port control is selected using the SMODE pin (0 =
microport, 1 = serial port). Two serial port modes are available.
An SPI-compatible port is provided as well as a SPORT. The
choice of SPI or SPORT mode is selected using the MODE pin
(0 = SPI, 1 = SPORT).
To synchronize the hop of multiple channels via microprocessor
control:
1.
Write the NCO frequency register(s) or phase offset
register(s) to the new value.
2.
Write the NCO frequency hold-off counter register(s) with
the appropriate value (greater than 0 and less than 216).
3.
Write 0x00 to the soft synchronization configuration
register.
4.
Write the soft hop synchronization enable bit and the
corresponding soft sync channel enable bits high in the soft
synchronization configuration register. This starts the
countdown by the frequency hold-off counter. When the
count reaches 1, the new frequency and/or phase offset is
loaded into the NCO.
Each individual byte of serial data (address, instruction, and
data) may be shifted in either MSB first or LSB first using the
MSB_FIRST pin (1 = MSB first, 0 = LSB first). The serial chip
select (SCS) pin is brought low to access the device for serial
control. When the SCS pin is held high, serial programming is
inhibited.
Hardware Interface
The pins described in Table 26 comprise the physical interface
between the user’s programming device and the serial port of
the AD6636. All serial pins are inputs except for SDO, which is
an open-drain output and should be pulled high by an external
pull-up resistor (suggested value 1 kΩ).
A complete read or write cycle requires a minimum of three
bytes to transfer, consisting of address word, instruction word,
and data-word(s). As many as 127 data-words can be
transferred during a block transfer cycle. All address,
instruction, and data-word(s) must be formatted LSB first or
MSB first to match the state of the MSB_FIRST pin.
Note that when using SPI or SPORT for programming these
registers, the last step in the above procedure needs to be
repeated. Therefore, the soft synchronization configuration
register is written twice.
Hop with Pin Sync
Four sync pins (0, 1, 2 and 3) provide very accurate synchronization among channels. Each channel can be programmed to
look at any of the four sync pins.
To control the hop of channel NCO frequencies:
1.
Write the NCO frequency register(s) or phase offset
register(s) to the new value.
2.
Write the NCO frequency hold-off counter(s) to the
appropriate value (greater than 0 and less than 216).
3.
Program the channel NCO control registers to monitor the
appropriate SYNC pins.
4.
Write the hop synchronization enable bit and SYNC pin
enable bits high in the pin synchronization configuration
register. This enables the countdown of the frequency
hold-off counter. When the reaches 1, the new frequency
and/or phase offset is loaded into the NCO.
The first word for serial transfer is the internal register address.
In LSB first mode, the address is the lower-most address for the
block transfer (subsequent addresses are generated by internal
increment). In MSB first, the address is highest address for the
block transfer (subsequent addresses are generated by internal
decrement).
The second word of serial transfer contains a one-bit read/write
indicator (1 = read, 0 = write), and seven bits to define the
number of data bytes to be transferred (N). For a single data
byte transfer (N = 1); one byte is shifted into SDI for a write
transfer, or shifted out of SDO for a read transfer, and the cycle
is complete. For a block transfer, N write/read operations are
performed, and the internal register address increments
(MSB_FIRST = 0) or decrements (MSB_FIRST = 1) after each
data byte is clocked into SDI for a write operation, or after each
data byte is clocked out of SDO for a read operation.
Rev. A | Page 49 of 80
AD6636
Figure 44 to Figure 47 illustrate a three byte block transfer
through the serial port. Read and write operations with
MSB_FIRST high and low are shown. Note that the figures
show the sequence for write/read transfer, and actual data
should be shifted in or out based upon the status of the
MSB_FIRST pin. The operation details are common to both SPI
and SPORT modes, except for the use of framing signals and
timing. Individual mode details follow. In single-byte transfer
mode, the count in the second byte is reduced to 1, and the
number of data bytes is reduced to 1.
Table 26. Serial Port Pins
Pin
SCLK
MSB_FIRST
STFS
SRFS
SDI
SDO
SCS
SMODE
MODE
Function
Serial Clock in Both SPI and SPORT Modes. Should have a rise/fall time of 3 ns maximum.
Indicates whether the first bit shifted in or out of the serial port is the MSB (1) or LSB (0) for both instruction and
data-words. Also indicates if the first instruction word (address) is a block start or a block end for multiple byte
transfers. This pin also controls the functionality when programming indirectly addressed registers.
Serial Transmit Frame Sync in SPORT Mode. STFS is not used in SPI mode.
Serial Receive Frame Sync in SPORT Mode. SRFS is not used in SPI mode.
Serial Data Input in Both Modes. Serial data is clocked in on the rising edge of SCLK.
Serial Data Output in Both Modes. Serial data is clocked out on the rising edge of SCLK.
Active-Low Serial Chip Select in Both Modes.
Serial Mode. Part is programmed through the serial port when this pin is high.
Mode Pin. Selects between SPI (0) and SPORT (1) modes.
MSBFIRST
SCS
BLOCK END ADDRESS WR + COUNT (3)
SDI
0xaa
0x03
DATA TO BLOCK END
ADDRESS
DATA TO BLOCK END
ADDRESS – 1
DATA TO BLOCK END
ADDRESS – 2
aa
aa – 1
aa – 2
04998-0-053
SDO
MODE
Figure 44. Serial Write of Three Bytes with MSB_FIRST = 1 (All Words are Written MSB First)
MSBFIRST
SCS
SDI
BLOCK START
ADDRESS
WR + COUNT (3)
0xaa
0x03
DATA TO BLOCK START DATA TO BLOCK START DATA TO BLOCK START
ADDRESS
ADDRESS + 1
ADDRESS + 2
aa
aa + 1
aa + 2
04998-0-054
SDO
MODE
Figure 45. Serial Write of Three Bytes with MSB_FIRST = 0 (All Words are Written LSB First)
Rev. A | Page 50 of 80
AD6636
MSBFIRST
SCS
SDI
BLOCK END
ADDRESS
RD + COUNT (3)
0xaa
0x83
DATA FROM BLOCK END
ADDRESS
aa
DATA FROM BLOCK END
ADDRESS – 2
aa – 1
aa – 2
04998-0-055
SDO
DATA FROM BLOCK END
ADDRESS – 1
MODE
Figure 46. Serial Read of Three Bytes with MSB_FIRST = 1 (All Words are Written or Read MSB First)
MSBFIRST
SCS
SDI
BLOCK START
ADDRESS
RD + COUNT (3)
0xaa
0x83
DATA FROM BLOCK START
ADDRESS
aa
DATA FROM BLOCK START
ADDRESS + 2
aa + 1
aa + 2
04998-0-056
SDO
DATA FROM BLOCK START
ADDRESS + 1
MODE
Figure 47. Serial Read of Three Bytes with MSB_FIRST = 0 (All Words are Written or Read LSB First)
Rev. A | Page 51 of 80
AD6636
SPI Mode Timing
SPI Write
In SPI mode, the SCLK should run only when data is being
transferred and SCS is logic low. If SCLK runs when SCS is logic
high, the internal shift register continues to run and instruction
words or data are lost. No external framing is necessary. The
SCS pin can be pulled low once for each byte of transfer, or kept
low for the whole length of the transfer.
Data on the SDI pin is registered on the rising edge of SCLK.
During a write, the serial port accumulates eight input bits
of data before transferring one byte to the internal registers.
Figure 48 and Figure 49 show one byte block transfer for
writing in MSB_FIRST and LSB_FIRST modes.
MSBFIRST
SCLK
SCS
SMODE
BLOCK END ADDRESS
SDI
A7
A6
A5
A4
A3
A2
A1
WRITE
A0
0
BLOCK COUNT (Nx)
N6
N5
N4
N3
N2
N1
N0
D7
D6
D5
D4
D3
D2
D1
D0
D0
D1
D2
D3
D4
D5
D6
D7
04998-0-057
SDO
MODE
Figure 48. SPI Write MSB_FIRST = 1
MSBFIRST
SCLK
SCS
SMODE
BLOCK END ADDRESS
SDI
A0
A1
A2
A3
A4
A5
A6
BLOCK COUNT (Nx)
A7
N0
N1
N2
N3
N4
N5
WRITE
N6
0
04998-0-058
SDO
MODE
Figure 49. SPI Write MSB_FIRST = 0
Rev. A | Page 52 of 80
AD6636
SPI Read
During a typical read operation, a one-byte address and onebyte instruction are written to the serial port to instruct the
internal control logic as to which registers are to be accessed.
Register readback data shifts out on the rising edge of SCLK.
The SDO pin is in a high impedance state at all times except
during a read cycle.
MSBFIRST
SCLK
SCS
SMODE
BLOCK END ADDRESS
SDI
A7
A6
A5
A4
A3
A2
A1
READ
A0
1
BLOCK COUNT (Nx)
N6
N5
N4
N3
N2
N1
N0
D7
D6
D5
D4
D3
D2
D1
D0
04998-0-059
SDO
MODE
Figure 50. SPI Read MSB_FIRST = 1
MSBFIRST
SCLK
SCS
SMODE
BLOCK START ADDRESS
SDI
A0
A1
A2
A3
A4
A5
A6
BLOCK COUNT (Nx)
A7
N0
N1
N2
N3
N4
N5
SDO
READ
N6
1
D1
D2
D3
D4
D5
D6
D7
04998-0-060
D0
MODE
Figure 51. SPI Read MSB_FIRST = 0
Rev. A | Page 53 of 80
AD6636
SPORT Mode Timing
SPORT Write
In SPORT mode, the SCLK continuously runs, and the external
SRFS and STFS signals are used to frame the data. Incoming
framing signals SRFS (receive) and STFS (transmit) are sampled
on the falling edges of SCLK. All input and output data must be
transmitted or received in 8-bit segments starting with the
rising edge after SRFS or STFS is sampled.
Serial data is sampled on the rising edge of SCLK. The data
should be MSB or LSB first, depending on the polarity of the
MSB_FIRST pin. The serial port begins to sample data on the
rising edge of SCLK after SRFS is detected on the falling edge of
SCLK. Once all 8 bits of one byte are shifted in, the data is
transferred to the internal bus.
MSBFIRST
SCLK
SCS
SMODE
SRFS
BLOCK START ADDRESS
SDI
A7
A6
A5
A4
A3
A2
A1
WRITE
A0
0
BLOCK COUNT (Nx)
N6
N5
N4
N3
N2
N1
N0
D7
D6
D5
D4
D3
D2
D1
D0
STFS
04998-0-061
SDO
MODE
Figure 52. SPORT Write MSB_FIRST = 1
MSBFIRST
SCLK
SCS
SMODE
SRFS
BLOCK START ADDRESS
SDI
A0
A1
A2
A3
A4
A5
A6
BLOCK COUNT (Nx)
A7
N0
N1
N2
N3
N4
N5
WRITE
N6
0
D0
D1
D2
D3
D4
D5
D6
D7
STFS
04998-0-062
SDO
MODE
Figure 53. SPORT Write MSB_FIRST = 0
Rev. A | Page 54 of 80
AD6636
readback. STFS must be asserted for every 8-bit readback and is
sampled on the falling edge of SCLK. Data is shifted out on the
rising edge of SCLK. The SDO pin is in a high impedance state
at all times except during a read operation.
SPORT Read
For a typical SPORT read operation, the user must write an
address byte and instruction byte to the serial port to instruct
the internal control logic as to which registers are to be
MSBFIRST
SCLK
SCS
SMODE
SRFS
BLOCK START ADDRESS
SDI
A7
A6
A5
A4
A3
A2
A1
READ
A0
1
BLOCK COUNT (Nx)
N6
N5
N4
N3
N2
N1
N0
STFS
D7
D6
D5
D4
D3
D2
D1
D0
D0
D1
D2
D3
D4
D5
D6
D7
04998-0-063
SDO
MODE
Figure 54. SPORT Read MSB_FIRST = 1
MSBFIRST
SCLK
SCS
SMODE
SRFS
BLOCK START ADDRESS
SDI
A0
A1
A2
A3
A4
A5
A6
BLOCK COUNT (Nx)
A7
N0
N1
N2
N3
N4
N5
READ
N6
1
STFS
04998-0-064
SDO
MODE
Figure 55. SPORT Read MSB_FIRST = 0
Rev. A | Page 55 of 80
AD6636
Programming Indirect Addressed Registers Using
Serial Port
MSB_FIRST Mode Using Single-Byte Block Transfers
This section gives examples for programming CRCF coefficient
RAM (with an indirect addressing scheme) using the serial port
(either SPI or SPORT modes). Though the following specific
examples are for CRCF coefficient RAM programming, they can
be extended to other indirect addressed registers such as DRCF
coefficient RAM. There are four possible programming scenarios,
and examples are given for all scenarios using two commands:
SerialWrite (data) and SerialRead. These commands signify an 8bit write to, or an 8-bit read from, the serial port (SPI or SPORT).
SerialWrite (8-bit number): This is an 8-bit write to SPI or
SPORT. In SPI mode, the SCLK is toggled eight times while SCS is
pulled low. In SPORT mode, SCS is pulled low, SRFS is held high
for one SCLK cycle, and eight bits of data are shifted into the SDI
pin following the SRFS pulse. Though the 8-bit number argument
shown in the following code is always shown MSB_FIRST, it is
written with MSB shifting into the device first in MSB_FIRST
mode, and it is written with LSB shifting into the device first in
LSB_FIRST mode.
SerialRead(): This is an 8-bit read from the SDO pin in SPI or
SPORT modes. In SPI mode, the SCLK toggles eight times while
SCS is low. In SPORT mode, SCS is pulled low, STFS is held high
for one SCLK cycle, and then the eight bits of data that shifted out
on SDO following the STFS pulse are read. The data shifted out
should be interpreted based on the polarity of the MSB_FIRST
pin.
SerialWrite(0x98); //CRCF Start Address
SerialWrite(0x01);
SerialWrite(0x00);
SerialWrite(0x99); //CRCF Final Address
SerialWrite(0x01);
SerialWrite(N-1); //N is the number of coefficients
for (i=0 ; i < N; i++) {
//writing registers
SerialWrite(0x9E);
//MSB written first
SerialWrite(0x01);
//data bits[23:16]
SerialWrite(coeff[i] >> 16 & 0xFF);
SerialWrite(0x9D);
SerialWrite(0x01);
//data bits[15:8]
SerialWrite(coeff[i] >> 8 & 0xFF);
SerialWrite(0x9C);
//LSB written last
SerialWrite(0x01);
//data bits[7:0]
SerialWrite(coeff[i] & 0xFF);
}
SerialWrite(0x98); //CRCF Start Address
SerialWrite(0x01);
SerialWrite(0x00);
SerialWrite(0x99); //CRCF Final Address
SerialWrite(0x01);
SerialWrite(N-1); //N is the number of coefficients
for (i=0 ; i < N; i++) {
//reading registers
SerialWrite(0x9E);
//MSB readback first
SerialWrite(0x81);
//data bits[23:16]
Coeff[i] = SerialRead() 16 & 0xFF);
//data bits[15:8]
SerialWrite(coeff[i] >> 8 & 0xFF);
//data bits[7:0]
SerialWrite(coeff[i] & 0xFF);
LSB_FIRST Mode Using Single-Byte Block Transfers
SerialWrite(0x98); //CRCF Start Address
SerialWrite(0x01);
SerialWrite(0x00);
SerialWrite(0x99); //CRCF Final Address
SerialWrite(0x01);
SerialWrite(N-1); //N is the number of coefficients
for (i=0 ; i < N; i++) {
// writing registers
SerialWrite(0x9C);
//LSB written first
SerialWrite(0x01);
//data bits[7:0]
SerialWrite(coeff[i] & 0xFF);
}
SerialWrite(0x99); //CRCF Final Address
SerialWrite(0x02);
SerialWrite(N-1); //N is the number of coefficients
SerialWrite(0x00);
for (i=0 ; i < N; i++) {
SerialWrite(0x9D);
SerialWrite(0x01);
//data bits[15:8]
SerialWrite(coeff[i] >> 8 & 0xFF);
SerialWrite(0x9E);
SerialWrite(0x83);
//data bits[23:16]
Coeff[i] = SerialRead() 16 & 0xFF);
}
//reading registers
}
SerialWrite(0x98); //CRCF Start Address
SerialWrite(0x01);
SerialWrite(0x00);
LSB_FIRST Mode Using Multibyte Block Transfers
SerialWrite(0x99); //CRCF Final Address
SerialWrite(0x01);
SerialWrite(N-1); //N is the number of coefficients
for (i=0 ; i < N; i++) {
SerialWrite(0x9C);
SerialWrite(0x81);
//data bits[7:0]
Coeff[i] = SerialRead();
//reading registers
SerialWrite(0x98); //CRCF Start Address
SerialWrite(0x02);
SerialWrite(0x00);
SerialWrite(N-1); //N is the number of coefficients
for (i=0 ; i < N; i++) {
//writing registers
SerialWrite(0x9C);
SerialWrite(0x03);
//data bits[7:0]
SerialWrite(coeff[i] & 0xFF);
//data bits[15:8]
SerialWrite(coeff[i] >> 8 & 0xFF);
//data bits[23:16]
SerialWrite(coeff[i] >> 16 & 0xFF);
//LSB readback first
SerialWrite(0x9D);
SerialWrite(0x81);
//data bits[15:8]
Coeff[i] |= SerialRead()
