AD6641-500EBZ

Quick Start Guide for testing the AD6641 Customer Evaluation Board With the HSC-ADC-EVALCZ Figure 1: AD6641 ADC Evaluation Board – HSC ADC EVALC Data Capture Board Equipment Needed ► Analog signal source and antialiasing filter ► Analog Clock Source ► PC running Windows XP or Vista ► USB 2.0 port recommended (USB 1.1-compatible) ► AD6641 evaluation board ► HSC-ADC-EVALCZ FPGA Based Data Capture Kit Documents Needed ► AD6641 Datasheet ► HSC-ADC-EVALCZ FPGA Based Data Capture Kit Datasheet ► VisualAnalog User Manual ► High Speed ADC SPI Control Software User Manual, AN-878 ► Interface to High Speed ADC via SPI Control Port User Manual, AN-877 A. Arrants 1 Software Needed (place attached files in directories listed below) ► VisualAnalog version 1.9.13.2 or higher o AD6641_FFT_FIFO.vac canvas for VisualAnalog located at “C:\Program Files\Analog Devices\VisualAnalog\Templates” ► SPIController version 1.0.57.3 or higher o AD6641_12Bit_500MSspiR03.cfg and AD6641_12Bit_500MSspiR03.cal located at “C:\ProgramData\Analog Devices\SPIController\Cfgs” for Vista or “C:\Documents and Settings\All Users\Application Data\Analog Devices\SPIController\Cfgs” for Windows XP. ► ad6641_fifo.bin FPGA configuration file located at “C:\Program Files\Analog Devices\VisualAnalog\Hardware\HSC_ADC_EVALC”. All documents and software are available at http://www.analog.com/fifo. For any questions please send an email to highspeed.converters@analog.com. Testing 1. Connect the AD6641 evaluation board to the HSC-ADC-EVALCZ boards together as shown in Figure 1. 2. Connect one 6V, 2A switching power supply (such as the CUI EPS060250UH-PHP-SZ supplied) to the AD6641 board. 3. Connect one 5V, 3A (6V, 2A can optionally be used) switching power supply (such as the CUI KSAFD0500300W1US supplied) to the HSC-ADC-EVALCZ board. 4. Connect the HSC-ADC-EVALCZ board to the PC with a USB cable. (Connect to J6.) 5. On the ADC evaluation board, make sure that jumpers are on headers J300 – J303 to connect the power supplies. Connect pins 1 to 2 of P200 and pins 2 to 3 of P400 to connect the SPI bus to the ADC. 6. On the ADC evaluation board, provide a clean, low jitter clock source to connector J200 at the desired ADC conversion rate 7. On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal at connector J100. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable to connect the signal generator. For best results use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K&L band-pass filters.) 8. Open VisualAnalog on the PC. Under “New” tab, select AD6641 folder and the FFT template, then click Open. 9. Expand the Canvas if necessary by clicking on the “Expand Canvas” button. Click the “Settings” button of the “ADC Data Capture” block, click on the “Capture Board” tab. The Program File should be ad6641_fifo.bin, use the browse button if not already displayed. Click the “Program” Button. The ‘DONE’ LED should illuminate on the HSC-ADCEVALCZ board indicating that the FPGA has been correctly programmed. On the General A. Arrants 2 tab, in the Output Data dialog box, set the Length to 16384. On the Device tab, set Output Mode to SDR and select Output Port to be SPORT. A. Arrants 3 10. Start the SPI Controller software. If prompted for a configuration file, select the AD6641_12Bit_500MSspiR03.cfg file. If not, check the title bar of the window to see which configuration is loaded. If necessary, choose “Cfg Open” from the “File” menu and select the above configuration file. Note that the CHIP ID(1) field may be filled whether the correct SPI Controller configuration file is loaded or not. Note: SPI Controller can be started from the “Tools” menu in VisualAnalog, but first make sure that it is installed. Select “External Tools” from the “Tools” menu in VisualAnalog. If SPI Controller is not shown, click the Add button on the External Tools from the “Tools” menu in VisualAnalog window. Under “Display Text:” enter “SPI Controller”. Then, enter the path to the SPI controller executable. 11. Click the New DUT button ( ) in SPI Controller. On the Customer 2 tab, set the following options: Fill Count = 255, Dump Operation = Master, Readback Mode = SPORT. 12. Return to the VisualAnalog window and click the Run button ( ). 13. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) 14. If desired, click on File>Save Form as in the FFT window to save the FFT plot. A. Arrants 4 Troubleshooting ► The FFT plot appears abnormal...  If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary.  In VisualAnalog, Click on the Settings button in the “Input Formatter” block. Check that “Number Format” is set to the correct encoding (offset binary by default). Repeat for the other channel.  If DC Spurs appear in the “FFT” plot from VisualAnalog? See Figure 2. DC Spurs Figure 2: DC Spurs on FFT Add a ferrite core to ALL switching power supplies used in the evaluation platform, like Digi-Key Part number: 240-2287-ND (M/N: LFB360230-300). See Figure 3. A. Arrants 5 Figure 3: Power supply modification to SPU15A-103 switching power supply. Otherwise, email the HSC Applications Group at highspeed.converters@analog.com and ask for Part Number: EPS060250UH-P5P-SZ, CUI Inc. switching power supply. This switching power supply has a ferrite core built into the DC lead to snub any switching noise. ► The FFT plot appears normal, but performance is poor.  Make sure you are using an appropriate filter on the analog input.  Make sure the signal generators for the clock and the analog input are clean (low phase noise).  If you are using non-coherent sampling, change the analog input frequency slightly.  Make sure the SPI config file matches the product being evaluated. ► The FFT window remains blank after the Run button is clicked.  Make sure the evaluation board is securely connected to the HSC-ADC-EVALCZ board  Repeat steps 10 through 16.  Make sure the FPGA has been programmed by verifying that the ‘DONE’ LED is illuminated on the HSC-ADC-EVALCZ board. If this LED is not illuminated make sure the U4 switch on the board is in the correct position for USB CONFIG.  Make sure the correct FPGA program was installed. ► VisualAnalog indicates that the “FIFO capture timed out.”  Make sure all power and USB connections are secure.  Repeat steps 11 through 16.  Probe the DCOA test point on the evaluation board and confirm a clock signal is present at the ADC sampling rate. Revision: 0 A. Arrants 6