AD6645ASQ-80

a FEATURES 80 MSPS Guaranteed Sample Rate SNR = 75 dB, fIN 15 MHz @ 80 MSPS SNR = 72 dB, fIN 200 MHz @ 80 MSPS SFDR = 89 dBc, fIN 70 MHz @ 80 MSPS 100 dB Multitone SFDR IF Sampling to 200 MHz Sampling Jitter 0.1 ps 1.5 W Power Dissipation Differential Analog Inputs Pin-Compatible to AD6644 Two’s Complement Digital Output Format 3.3 V CMOS-Compatible DataReady for Output Latching APPLICATIONS Multichannel, Multimode Receivers Base Station Infrastructure AMPS, IS-136, CDMA, GSM, WCDMA Single Channel Digital Receivers Antenna Array Processing Communications Instrumentation Radar, Infrared Imaging Instrumentation PRODUCT DESCRIPTION 14-Bit, 80 MSPS A/D Converter AD6645 generation in a wideband ADC family, preceded by the AD9042 (12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling), and the AD6644 (14-bit, 40 MSPS/65 MSPS). Designed for multichannel, multimode receivers, the AD6645 is part of Analog Device’s SoftCell™ transceiver chipset. The AD6645 maintains 100 dB multitone, spurious-free dynamic range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the ADC. Noise performance is exceptional; typical signal-tonoise ratio is 74.5 dB through the first Nyquist band. The AD6645 is built on Analog Devices’ high-speed complementary bipolar process (XFCB) and uses an innovative, multipass circuit architecture. Units are available in a thermally enhanced 52lead PowerQuad 4® (LQFP_ED) specified from –40∞C to +85∞C. PRODUCT HIGHLIGHTS 1. IF Sampling The AD6645 maintains outstanding ac performance up to input frequencies of 200 MHz. Suitable for multicarrier 3G wideband cellular IF sampling receivers. 2. Pin Compatibility The ADC has the same footprint and pin layout as the AD6644, 14-Bit 40 MSPS/65 MSPS ADC. 3. SFDR Performance and Oversampling Multitone SFDR performance of –100 dBc can reduce the requirements of high-end RF components and allows the use of receive signal processors such as the AD6620 or AD6624/ AD6624A. The AD6645 is a high-speed, high-performance, monolithic 14-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS-compatible digital outputs. It is the fourth FUNCTIONAL BLOCK DIAGRAM AVCC DVCC AD6645 AIN AIN A1 TH1 TH2 A2 TH3 TH4 TH5 ADC3 ADC1 VREF 2.4V 5 ENCODE ENCODE INTERNAL TIMING DAC1 ADC2 5 DAC2 6 DIGITAL ERROR CORRECTION LOGIC GND DMID OVR DRY D13 MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB SoftCell is a trademark of Analog Devices, Inc. PowerQuad 4 is a registered trademark of Amkor Technology, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD6645–SPECIFICATIONS DC SPECIFICATIONS (AV Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION (PSRR) REFERENCE OUT (VREF)1 ANALOG INPUTS (AIN, AIN) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance POWER SUPPLY Supply Voltages AVCC DVCC Supply Current I AVCC (AVCC = 5.0 V) I DVCC (DVCC = 3.3 V) Rise Time2 AVCC POWER CONSUMPTION Full Full Full Full Full Full Full 25∞C Full Full Full 25∞C II II II II V V V V V V V V CC = 5 V, DVCC = 3.3 V; TMIN = –40 C, TMAX = +85 C, unless otherwise noted.) Temp Test Level Min AD6645ASQ-80 Typ 14 Guaranteed +1.2 0 ± 0.25 ± 0.5 1.5 48 ± 1.0 2.4 2.2 1 1.5 Max Unit Bits –10 –10 –1.0 +10 +10 +1.5 mV % FS LSB LSB ppm/∞C ppm/∞C mV/V V V p-p kW pF Full Full Full Full Full Full II II II II IV II 4.75 3.0 5.0 3.3 275 32 5.25 3.6 320 45 TBD V V mA mA ms W 1.5 1.75 NOTES 1 VREF is provided for setting the common-mode offset of a differential amplifier such as the AD8138 when a dc-coupled analog input is required. VREF should be buffered if used to drive additional circuit functions. 2 Specified for dc supplies with linear rise-time characteristics. The use of dc supplies with linear rise-times of 10 pF will degrade performance. Specifications subject to change without notice. –2– REV. 0 AD6645 AC SPECIFICATIONS1 otherwise noted.) Parameter (Conditions) SNR Analog Input @ –1 dBFS 15.5 MHz 30.5 MHz 70.0 MHz 150.0 MHz 200.0 MHz 15.5 MHz 30.5 MHz 70.0 MHz 150.0 MHz 200.0 MHz (AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; TMIN = –40 C, TMAX = +85 C, unless AD6645ASQ-80 Typ 75.0 74.5 73.5 73.0 72.0 75.0 74.5 73.0 68.5 62.5 93.0 93.0 89.0 70.0 63.5 96.0 95.0 90.0 90.0 88.0 100 100 90 270 Temp 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C 25∞C Test Level V II II V V V II V V V V II V V V V II V V V V V V V Min Max Unit dB dB dB dB dB dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS dBc MHz 72.5 72.0 SINAD Analog Input @ –1 dBFS 72.5 WORST HARMONIC (2nd or 3rd) Analog Input 15.5 MHz @ –1 dBFS 30.5 MHz 70.0 MHz 150.0 MHz 200.0 MHz WORST HARMONIC (4th or HIGHER) Analog Input 15.5 MHz @ –1 dBFS 30.5 MHz 70.0 MHz 150.0 MHz 200.0 MHz TWO TONE SFDR @ 30.5 MHz2, 3 55.0 MHz2, 4 TWO TONE IMD REJECTION3, 4 F1, F2 @ –7 dBFS ANALOG INPUT BANDWIDTH 85.0 85.0 NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. 2 Analog input signal power swept from –10 dBFS to –100 dBFS. 3 F1 = 30.5 MHz, F2 = 31.5 MHz. 4 F1 = 55.25 MHz, F2 = 56.25 MHz. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Parameter (Conditions) Maximum Conversion Rate Minimum Conversion Rate ENCODE Pulsewidth High (tENCH)* ENCODE Pulsewidth Low (tENCL)* (AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; TMIN = –40 C, TMAX = +85 C, unless otherwise noted.) Temp Full Full Full Full Test Level II IV IV IV Min 80 30 5.625 5.625 AD6645ASQ-80 Typ Max Unit MSPS MSPS ns ns *Several timing parameters are a function of t ENCL and tENCH. Specifications subject to change without notice. REV. 0 –3– AD6645 SWITCHING SPECIFICATIONS (continued) Parameter (Conditions) ENCODE Input Parameters Encode Period1 @ 80 MSPS Encode Pulsewidth High2 @ 80 MSPS Encode Pulsewidth Low @ 80 MSPS ENCODE/DataReady Encode Rising to DataReady Falling Encode Rising to DataReady Rising @ 80 MSPS (50% Duty Cycle) ENCODE/DATA (D13:0), OVR ENC to DATA Falling Low ENC to DATA Rising Low ENCODE to DATA Delay (Hold Time)3 ENCODE to DATA Delay (Setup Time)4 Encode = 80 MSPS (50% Duty Cycle) DataReady (DRY )/DATA, OVR DataReady to DATA Delay (Hold Time)2 Encode = 80 MSPS (50% Duty Cycle) DataReady to DATA Delay (Setup Time)2 Encode = 80 MSPS (50% Duty Cycle) APERTURE DELAY APERTURE UNCERTAINTY (Jitter) 5 1 (AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; TMIN = –40 C, TMAX = +85 C, CLOAD = 10 pF, unless otherwise noted.) Temp Full Full Full Full Full Full Full Full Full Full Full Full Full 25∞C 25∞C Test Level V V V V V V V V V V V V 6.6 V 2.1 V V 1.0 7.3 2.4 1.4 1.4 5.3 Min AD6645ASQ-80 Typ 12.5 6.25 6.25 2.0 tENCH + tDR 8.3 4.7 3.0 3.0 tENC – tE_FL 7.6 Note 6 7.2 Note 6 3.6 –500 0.1 3.1 9.4 7.0 4.7 4.7 10.0 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns 7.9 ns 5.1 ps ps rms Name tENC tENCH tENCL tDR tE_DR tE_FL tE_RL tH_E tS_E tH_DR tS_DR tA tJ NOTES 1 Several timing parameters are a function of t ENC and tENCH. 2 To compensate for a change in duty cycle for t H_DR and tS_DR use the following equation: NewtH_DR = (tH_DR – % Change(tENCH)) NewtS_DR = (tS_DR – % Change(t ENCH)) 3 ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the Analog-to-Digital Converter, t E_RL = tH_E. 4 ENCODE TO DATA Delay (Setup Time) is calculated relative to 80 MSPS (50% duty cycle). To calculate t S_E for a given encode, use the following equation: NewtS_E = tENC(NEW) – tENC + tS_E (i.e., for 40 MSPS: Newt S_E(TYP) = 25 ¥ 10–9 – 15.38 ¥ 10–9 + 9.8 ¥ 10–9 = 19.4 ¥ 10 –9). 5 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY. 6 DataReady to DATA Delay (t H_DR and tS_DR) is calculated relative to 80 MSPS (50% duty cycle) and is dependent on t ENC and duty cycle. To calculate t H_DR and tS_DR for a given encode, use the following equations: NewtH_DR = tENC(NEW)/2 – tENCH + tH_DR (i.e., for 40 MSPS: NewtH_DR(TYP) = 12.5 ¥ 10–9 – 6.25 ¥ 10–9 + 7.2 ¥ 10–9 = 13.45 ¥ 10–9 NewtS_DR = tENC(NEW)/2 – tENCH + tS_DR (i.e., for 40 MSPS: NewtS_DR(TYP) = 12.5 ¥ 10–9 – 6.25 ¥ 10–9 + 3.6 ¥ 10–9 = 9.85 ¥ 10–9 Specifications subject to change without notice. tA N+3 N AIN N+1 N+2 t ENC ENC, ENC N t ENCH N+1 t ENCL N+2 N+3 N+4 N+4 t E_RL D[13:0], OVR t E_FL N–3 N–2 t E_DR N–1 t S_E N t H_E DRY t S_DR t DR t H_DR Figure 1. Timing Diagram –4– REV. 0 AD6645 ABSOLUTE MAXIMUM RATINGS * Parameter ELECTRICAL AVCC Voltage DVCC Voltage Analog Input Voltage Analog Input Current Digital Input Voltage Digital Output Current ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Min 0 0 0 0 Max 7 7 AVCC 25 AVCC 4 +85 150 300 +150 Unit V V V mA V mA ∞C ∞C ∞C ∞C –40 –65 *Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. THERMAL CHARACTERISTICS 52-Lead PowerQuad 4 . . . . . . . . . . . . . . . . . . . . . . LQFP_ED JA = 23∞C/W . . . . . . . . . . . . . . . Soldered Slug, No Airflow JA = 17∞C/W . . . . . . . . Soldered Slug, 200 LFPM Airflow JA = 30∞C/W . . . . . . . . . . . . . Unsoldered Slug, No Airflow JA = 24∞C/W . . . . . . Unsoldered Slug, 200 LFPM Airflow JC = 2∞C/W . . . . . . . . . . . . . Bottom of Package (Heatslug) Typical Four-Layer JEDEC Board Horizontal Orientation EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at 25∞C and guaranteed by design and characterization at temperature extremes. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. ORDERING GUIDE Model AD6645ASQ-80 AD6645/PCB Temperature Range –40∞C to +85∞C (Ambient) 25∞C Package Description Package Option 52-Lead PowerQuad 4 (LQFP_ED) SQ-52 Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6645 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– AD6645 PIN CONFIGURATION DRY D13 (MSB) D9 D8 DVCC GND D12 D11 D10 D6 52 51 50 49 48 47 46 45 44 43 42 41 40 D7 D5 D4 39 D3 38 D2 37 D1 36 D0 (LSB) 35 DMID 34 GND 33 DVCC 32 OVR 31 DNC 30 AV CC 29 GND 28 AV CC 27 GND DVCC 1 GND 2 VREF 3 GND 4 ENC 5 ENC 6 GND 7 AVCC 8 AVCC 9 GND 10 AIN 11 AIN 12 GND 13 PIN 1 IDENTIFIER AD6645 TOP VIEW (Not to Scale) 14 15 16 17 18 19 20 21 22 23 24 25 26 C1 GND AVCC GND AVCC GND AVCC GND C2 GND AVCC DNC = DO NOT CONNECT PIN FUNCTION DESCRIPTIONS Pin No. 1, 33, 43 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 3 5 6 Mnemonic DVCC GND Function 3.3 V Power Supply (Digital) Output Stage Only Ground VREF ENC ENC 2.4 V Reference. Bypass to ground with a 0.1 mF microwave chip capacitor. Encode Input. Conversion initiated on rising edge. Complement of ENC, Differential Input 5 V Analog Power Supply Analog Input Complement of AIN, Differential Analog Input Internal Voltage Reference. Bypass to ground with a 0.1 mF chip capacitor. Internal Voltage Reference. Bypass to ground with a 0.1 mF chip capacitor. Do not connect this pin. Over-Range Bit. A logic-level high indicates analog input exceeds ± FS. Output Data Voltage Midpoint. Approximately equal to (DVCC)/2. Digital Output Bit (Least Significant Bit); Two’s Complement Digital Output Bits in Two’s Complement Digital Output Bit (Most Significant Bit); Two’s Complement DataReady Output 8, 9, 14, 16, 18, AVCC 22, 26, 28, 30 11 12 20 24 31 32 35 36 37–41, 44–50 51 52 AIN AIN C1 C2 DNC OVR* DMID D0 (LSB) D1–D5, D6–D12 D13 (MSB) DRY *The functionality of the Over-Range bit is specified for a temperature range of 25∞C to 85∞C only. –6– GND AVCC REV. 0 AD6645 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth Minimum Conversion Rate The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Noise (For Any Range Within the ADC) Ê FS dBm – SNR dBc - Signal dBFS ˆ Á ˜ ¯ 10 The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) VNOISE = | Z | ¥ 0.001 ¥ 10 Ë The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range Where Z is the input impedance, FS is the full scale of the device for the frequency in question; SNR is the value for the particular input level; and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. Output Propagation Delay The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. Then the difference is computed between both peak measurements. Differential Nonlinearity The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Power Supply Rise Time The time from when the dc supply is initiated, until the supply output reaches the minimum specified operating voltage for the ADC. The dc level is measured at supply pin(s) of the ADC. Signal-to-Noise-and-Distortion (SINAD) The deviation of any code width from an ideal 1 LSB step. Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic “1” state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these specs define an acceptable ENCODE duty cycle. Full-Scale Input Power The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) Expressed in dBm. Computed using the following equation: PowerFull Scale È V 2Full Scale rms Í |Z | Input = 10 log Í Í 0.001 Í Í Î ù ú ú ú ú ú û The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale). Two Tone Intermodulation Distortion Rejection Harmonic Distortion, 2 nd The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two Tone SFDR The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, 3 rd The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Worst Other Spur The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc. REV. 0 –7– AD6645 EQUIVALENT CIRCUITS VCH AVCC DVCC AIN 500 VCL VCH AVCC 500 AIN BUF T/H CURRENT MIRROR BUF VREF BUF T/H DVCC VCL VREF D0–D13, OVR, DRY Figure 2. Analog Input Stage LOADS AVCC AVCC 10k ENC 10k AVCC AVCC 10k ENC 10k CURRENT MIRROR Figure 5. Digital Output Stage AVCC AVCC LOADS 2.4V Figure 3. Encode Inputs AVCC 100 A VREF VREF Figure 6. 2.4 V Reference AVCC AVCC DVCC 10k CURRENT MIRROR C1, C2 DMID 10k Figure 4. Compensation Pin, C1 or C2 Figure 7. DMID Reference –8– REV. 0 Typical Performance Characteristics–AD6645 0 –10 –20 –30 –40 –50 dBFS 0 ENCODE = 80MSPS AIN = 2.2MHz @ –1dBFS SNR = 75.0dB SFDR = 93.0dBc –10 –20 –30 –40 –50 ENCODE = 80MSPS AIN = 69.1MHz @ –1dBFS SNR = 73.5dB SFDR = 89.0dBc –70 –80 –90 2 3 5 4 6 dBFS –60 –60 –70 –80 –90 2 6 5 3 4 –100 –110 –120 –130 0 5 –100 –110 –120 10 15 20 25 FREQUENCY – MHz 30 35 40 –130 0 5 10 15 20 25 FREQUENCY – MHz 30 35 40 TPC 1. Single Tone @ 2.2 MHz TPC 4. Single Tone @ 69.1 MHz 0 –10 –20 –30 –40 –50 dBFS 0 ENCODE = 80MSPS AIN = 15.5MHz @ –1dBFS SNR = 75.0dB SFDR = 93.0dBc –10 –20 –30 –40 –50 ENCODE = 80MSPS AIN = 150MHz @ –1dBFS SNR = 73.0dB SFDR = 70.0dBc dBFS –60 –70 –80 –90 –100 –110 –120 –130 0 5 10 15 20 25 FREQUENCY – MHz 30 35 40 5 6 4 2 3 –60 –70 –80 –90 –100 –110 –120 –130 0 5 10 15 20 25 FREQUENCY – MHz 30 35 40 6 2 4 5 3 TPC 2. Single Tone @ 15.5 MHz TPC 5. Single Tone @ 150 MHz 0 –10 –20 –30 –40 –50 ENCODE = 80MSPS AIN = 29.5MHz @ –1dBFS SNR = 74.5dB SFDR = 93.0dBc 0 –10 –20 –30 –40 –50 dBFS ENCODE = 80MSPS AIN = 200MHz @ –1dBFS SNR = 72.0dB SFDR = 64.0dBc dBFS –60 –70 –80 –90 3 5 6 2 4 –60 –70 –80 –90 –100 –110 –120 2 4 5 3 6 –100 –110 –120 –130 0 5 10 15 20 25 FREQUENCY – MHz 30 35 40 –130 0 5 10 15 20 25 FREQUENCY – MHz 30 35 40 TPC 3. Single Tone @ 29.5 MHz TPC 6. Single Tone @ 200 MHz REV. 0 –9– AD6645 75.5 75.0 74.5 T = +85 C SNR – dB HARMONICS – dBc 100 95 T = –40 C 90 85 80 WORST OTHER SPUR 74.0 T = +25 C 73.5 73.0 72.5 ENCODE = 80MSPS @ AIN = –1dBFS TEMP = –40 C, +25 C, +85 C 72.0 0 10 20 30 40 FREQUENCY – MHz 50 60 70 HARMONICS (2ND, 3RD) 75 70 65 60 ENCODE = 80MSPS @ AIN = –1dBFS TEMP = 25 C 0 20 40 60 80 100 120 140 ANALOG FREQUENCY – MHz 160 180 200 TPC 7. Noise vs. Analog Frequency TPC 10. Harmonics vs. Analog Frequency (IF) 94 WORST CASE SPURIOUS – dBFS AND dBc 120 110 100 90 80 70 60 50 40 30 20 10 0 –90 –80 –70 –60 –50 –40 –30 –20 ANALOG INPUT POWER LEVEL – dBFS –10 0 SFDR = 90dB REFERENCE LINE dBc ENCODE = 80MSPS AIN = 30.5MHz dBFS 92 WORST CASE HARMONIC – dBc 90 88 86 84 82 80 ENCODE = 80MSPS @ AIN = –1dBFS TEMP = –40 C, +25 C, +85 C 0 10 20 30 40 50 ANALOG INPUT FREQUENCY – MHz T = +25 C T = –40 C, +85 C 60 70 TPC 8. Harmonics vs. Analog Frequency TPC 11. Single Tone SFDR @ 30.5 MHz 76 WORST CASE SPURIOUS – dBFS AND dBc 120 110 100 90 80 70 60 50 40 30 20 10 0 –90 –80 –70 –60 –50 –40 –30 –20 ANALOG INPUT POWER LEVEL – dBFS –10 0 dBc SFDR = 90dB REFERENCE LINE ENCODE = 80MSPS AIN = 69.1MHz dBFS 75 74 SNR – dB 73 72 71 ENCODE = 80MSPS @ AIN = –1dBFS TEMP = 25 C 70 0 20 40 60 80 100 120 140 ANALOG FREQUENCY – MHz 160 180 200 TPC 9. Noise vs. Analog Frequency (IF) TPC 12. Single Tone SFDR @ 69.1 MHz –10– REV. 0 AD6645 0 ENCODE = 80MSPS –10 AIN = 30.5MHz, –20 31.5MHz (–7dBFS) NO DITHER –30 –40 –50 0 ENCODE = 80MSPS –10 AIN = 55.25MHz, 56.25MHz (–7dBFS) –20 NO DITHER –30 –40 –50 dBFS –70 F 2 –80 – F –90 1 –100 –110 –120 –130 0 5 2 F 1 + F 2 2 F 2 + F 1 F 1 + F 2 2 F 1 – F 2 2 F 2 – F 1 dBFS –60 –60 F –80 2 – –90 F –100 1 –110 –120 –70 2 F 1 + F 2 2 F 2 + F 1 2 F 1 – F 2 2 F 2 – F 1 F 1 + F 2 10 15 20 25 FREQUENCY – MHz 30 35 40 –130 0 5 10 15 20 25 FREQUENCY – MHz 30 35 40 TPC 13. Two Tones @ 30.5 MHz and 31.5 MHz TPC 16. Two Tone SFDR @ 55.25 MHz and 56.25 MHz 110 WORST CASE SPURIOUS – dBFS AND dBc WORST CASE SPURIOUS – dBFS AND dBc 110 100 dBFS 90 80 70 60 50 40 30 20 10 0 –77 –67 –57 –47 –37 –27 –17 INPUT POWER LEVEL – F1 = F2 dBFS –7 SFDR = 90dB REFERENCE LINE ENCODE = 80MSPS F1 = 55.25MHz F2 = 56.25MHz 100 90 80 70 dBc 60 50 40 30 20 10 0 –77 –67 –57 –47 –37 –27 –17 INPUT POWER LEVEL – F1 = F2 dBFS –7 SFDR = 90dB REFERENCE LINE ENCODE = 80MSPS F1 = 30.5MHz F2 = 31.5MHz dBFS dBc TPC 14. Two Tone SFDR @ 30.5 MHz and 31.5 MHz TPC 17. Two Tone SFDR @ 55.25 MHz and 56.25 MHz 100 95 90 85 80 75 70 65 15 SNR @ AIN = 2.2MHz WORST SPUR @ AIN = 2.2MHz 95 WORST SPUR @ AIN = 69.1MHz SNR, WORST CASE SPURIOUS – dB AND dBc SNR, WORST CASE SPURIOUS – dB AND dBc 90 85 80 75 SNR @ AIN = 69.1MHz 70 30 45 60 75 ENCODE FREQUENCY – MHz 90 105 65 15 30 45 60 75 ENCODE FREQUENCY – MHz 90 105 TPC 15. SNR, Worst Spurious vs. Encode @ 2.2 MHz TPC 18. SNR, Worst Spurious vs. Encode @ 69.1 MHz REV. 0 –11– AD6645 0 –10 –20 –30 –40 –50 dBFS dBFS ENCODE = 80.0MSPS AIN = 30.5MHz @ –29.5 dBFS NO DITHER 0 ENCODE = 80.0MSPS –10 AIN = 30.5MHz @ –29.5dBFS WITH DITHER @ –19.2 dBm –20 –30 –40 –50 –60 –70 –80 6 –90 4 –100 –110 –120 5 5 10 3 2 6 4 –60 –70 –80 –90 2 –100 –110 –120 –130 0 5 10 3 5 15 20 25 FREQUENCY – MHz 30 35 40 –130 0 15 20 25 FREQUENCY – MHz 30 35 40 TPC 19. 1 M FFT without Dither TPC 22. 1 M FFT with Dither 110 100 ENCODE = 80.0MSPS AIN = 30.5MHz NO DITHER WORST-CASE SPURIOUS dBc 110 ENCODE = 80.0MSPS 100 AIN = 30.5MHz WITH DITHER @ –19.2 dBm 90 80 70 60 50 40 30 20 10 80 70 60 50 40 30 20 10 0 WORST-CASE SPURIOUS dBc 90 80 70 60 50 40 30 20 10 SFDR = 90 dB REFERENCE LINE SFDR = 100 dB REFERENCE LINE SFDR = 90 dB REFERENCE LINE 0 dBFS 90 0 dBFS –90 –80 –70 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT LEVEL ANALOG INPUT LEVEL TPC 20. SFDR without Dither TPC 23. SFDR with Dither 0 –10 –20 –30 –40 –50 ENCODE = 76.8MSPS AIN = 69.1MHz @ –1dBFS SNR = 73.5dB SFDR = 89.0dBc 0 –10 –20 –30 –40 –50 ENCODE = 76.8MSPS AIN = WCDMA @ 69.1MHz dBFS dBFS 3 2 6 4 5 –60 –70 –80 –90 –100 –110 –120 –130 0 5 10 15 20 25 FREQUENCY – MHz 30 35 40 –60 –70 –80 –90 –100 –110 –120 –130 0 5 10 15 20 25 FREQUENCY – MHz 30 35 40 2 3 6 4 5 TPC 21. Single Tone 69.1 MHz: Encode = 76.8 MSPS TPC 24. WCDMA Tone 69.1 MHz: Encode = 76.8 MSPS –12– REV. 0 AD6645 0 –10 –20 –30 –40 –50 dBFS 0 ENCODE = 76.8MSPS AIN = 2WCDMA @ 59.6MHz –10 –20 –30 –40 –50 dBFS ENCODE = 76.8MSPS AIN = WCDMA @ 140MHz –60 –70 –80 –90 –60 –70 –80 –90 –100 –110 –120 –130 0 5 10 15 20 25 FREQUENCY – MHz 30 35 40 –100 –110 –120 –130 0 5 6 5 4 2 3 10 15 20 25 FREQUENCY – MHz 30 35 40 TPC 25. 2 WCDMA Carriers @ AIN = 59.6 MHz: Encode = 76.8 MSPS 0 –10 –20 –30 –40 –50 ENCODE = 61.44MSPS AIN = 4WCDMA @ 46.08MHz TPC 27. WCDMA Tone 140 MHz: Encode = 76.8 MSPS 0 –10 –20 –30 –40 –50 dBFS ENCODE = 61.44MSPS AIN = WCDMA @ 190MHz dBFS –60 –70 –80 –90 –60 –70 –80 –90 –100 –110 –120 –130 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 FREQUENCY – MHz –100 –110 –120 –130 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 FREQUENCY – MHz 2 3 6 4 5 TPC 26. 4 WCDMA Carriers @ AIN = 46.08 MHz: Encode = 61.44 MSPS TPC 28. WCDMA Tone 190 MHz: Encode = 61.44 MSPS REV. 0 –13– AD6645 THEORY OF OPERATION The AD6645 analog-to-digital converter (ADC) employs a three stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size. As shown in the functional block diagram, the AD6645 has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing ± 0.55 V around this reference (see Figure 2). Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V peak-to-peak. Both analog inputs are buffered prior to the first track-and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter, DAC1. DAC1 requires 14 bits of precision, which is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1. The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The second DAC requires 10 bits of precision, which is met by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4. TH5 drives a final 6-bit ADC3. The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as two’s complement. APPLYING THE AD6645 Encoding the AD6645 If a low jitter clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown below. The MC100EL16 (or same family) from ON-SEMI offers excellent jitter performance. VT 0.1 F ENCODE ECL/ PECL AD6645 ENCODE 0.1 F VT Figure 9. Differential ECL for Encode Driving the Analog Inputs As with most new high-speed, high dynamic range analog-todigital converters, the analog input to the AD6645 is differential. Differential inputs improve on-chip performance as signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection to stray signals such as ground and power noise. Second, they provide good rejection to common-mode signals such as local oscillator feed-through. The AD6645 analog input voltage range is offset from ground by 2.4 V. Each analog input connects through a 500 W resistor to the 2.4 V bias voltage and to the input of a differential buffer (Figure 2). The resistor network on the input properly biases the followers for maximum linearity and range. Therefore, the analog source driving the AD6645 should be ac-coupled to the input pins. Since the differential input impedance of the AD6645 is 1 kW, the analog input power requirement is only –2 dBm, simplifying the driver amplifier in many cases. To take full advantage of this high input impedance, a 20:1 transformer would be required. This is a large ratio and could result in unsatisfactory performance. In this case, a lower step-up ratio could be used. The recommended method for driving the analog input of the AD6645 is to use a 4:1 RF transformer. For example, if RT were set to 60.4 W and RS were set to 25 W, along with a 4:1 impedance ratio transformer, the input would match to a 50 W source with a full-scale drive of 4.8 dBm. Series resistors (RS) on the secondary side of the transformer should be used to isolate the transformer from A/D. This will limit the amount of dynamic current from the A/D flowing back into the secondary of the transformer. The 50 W impedance matching can also be incorporated on the secondary side of the transformer as shown in the evaluation board schematic (Figure 13). ANALOG INPUT SIGNAL RT RS 0.1 F ADT4-1WT RS AIN The AD6645 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3–4 dB with 70 MHz analog input signals when using a high jitter clock source. See AN-501, “Aperture Uncertainty and ADC System Performance” for complete details. For optimum performance, the AD6645 must be clocked differentially. The encode signal is usually ac-coupled into the ENC and ENC pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Shown below is one preferred method for clocking the AD6645. The clock source (low jitter) is converted from single-ended to differential using a RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6645 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD6645, and limits the noise presented to the encode inputs. CLOCK SOURCE T1-4T ENCODE 0.1 F AD6645 AIN Figure 10. Transformer-Coupled Analog Input Circuit AD6645 ENCODE HSMS2812 DIODES In applications where dc-coupling is required, a differential output op amp such as the AD8138 from Analog Devices can be used to drive the AD6645 (Figure 11). The AD8138 op amp provides single-ended-to-differential conversion, which reduces overall system cost and minimizes layout requirements. –14– REV. 0 Figure 8. Crystal Clock Oscillator, Differential Encode AD6645 CF Grounding 499 5V VIN 499 VOCM 499 25 AIN AD8138 25 AD6645 AIN VREF DIGITAL OUTPUTS 499 CF Figure 11. DC-Coupled Analog Input Circuit Power Supplies For optimum performance, it is highly recommended that a common ground be utilized between the analog and digital power planes. The primary concern with splitting grounds is that dynamic currents may be forced to travel significant distances in the system before recombining back at the common source ground. This can result in a large and undesirable ground loop. The most common place for this to occur is on the digital outputs of the ADC. Ground loops can contribute to digital noise being coupled back onto the ADC front end. This can manifest itself as either harmonic spurs, or very high order spurious products that can cause excessive spikes on the noise floor. This noise coupling is less likely to occur at lower clock speeds since the digital noise has more time to settle between samples. In general, splitting the analog and digital grounds can frequently contribute to undesirable EMI-RFI and should therefore be avoided. Conversely, if not properly implemented, common grounding can actually impose additional noise issues since the digital ground currents are riding on top of the analog ground currents in close proximity to the ADC input. To minimize the potential for noise coupling further, it is highly recommended that multiple ground return traces/vias be placed such that the digital output currents do not flow back towards the analog front end, but are routed quickly away from the ADC. This does not require a split in the ground plane and can be accomplished by simply placing substantial ground connections directly back to the supply at a point between the analog front end and the digital outputs. The judicious use of ceramic chip capacitors between the power supply and ground planes will also help suppress digital noise. The layout should incorporate enough bulk capacitance to supply the peak current requirements during switching periods. Layout Information Care should be taken when selecting a power source. The use of linear dc supplies with rise-times of