14-Bit, 80 MSPS/105 MSPS
A/D Converter
AD6645
Data Sheet
FEATURES
provides CMOS-compatible digital outputs. It is the fourth
generation in a wideband ADC family, preceded by the AD9042
(12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling),
and the AD6644 (14-bit, 40 MSPS/65 MSPS).
SNR = 75 dB, fIN 15 MHz, up to 105 MSPS
SNR = 72 dB, fIN 200 MHz, up to 105 MSPS
SFDR = 89 dBc, fIN 70 MHz, up to 105 MSPS
100 dBFS multitone SFDR
IF sampling to 200 MHz
Sampling jitter: 0.1 ps
1.5 W power dissipation
Differential analog inputs
Pin compatible to AD6644
Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
Designed for multichannel, multimode receivers, the AD6645 is
part of the Analog Devices, Inc., SoftCell® transceiver chipset.
The AD6645 maintains 100 dB multitone, spurious-free dynamic
range (SFDR) through the second Nyquist band. This breakthrough
performance eases the burden placed on multimode digital
receivers (software radios) that are typically limited by the ADC.
Noise performance is exceptional; typical signal-to-noise ratio
(SNR) is 74.5 dB through the first Nyquist band.
The AD6645 is built on the Analog Devices extra fast
complementary bipolar (XFCB) process and uses an innovative,
multipass circuit architecture. Units are available in a 52-lead
exposed pad (TQFP_EP) package specified from −40°C to
+85°C at 80 MSPS and −10°C to +85°C at 105 MSPS.
APPLICATIONS
Multichannel, multimode receivers
Base station infrastructures
AMPS, IS-136, CDMA, GSM, W-CDMA
Single channel digital receivers
Antenna array processing
Communications instrumentation
Radars, infrared imaging
Instrumentation
PRODUCT HIGHLIGHTS
1.
2.
GENERAL DESCRIPTION
3.
The AD6645 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter (ADC). All necessary functions,
including track-and-hold (T/H) and reference, are included on the
chip to provide a complete conversion solution. The AD6645
IF Sampling. The AD6645 maintains outstanding ac
performance up to input frequencies of 200 MHz, suitable
for multicarrier 3G wideband cellular IF sampling receivers.
Pin Compatibility. The ADC has the same footprint and
pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC.
SFDR Performance and Oversampling. Multitone SFDR
performance of 100 dBFS can reduce the requirements of
high end RF components.
FUNCTIONAL BLOCK DIAGRAM
AVCC
DVCC
AD6645
AIN
VREF
A1
TH1
TH2
A2
ADC1
2.4V
TH3
TH4
DAC1
TH5
ADC2
5
ENCODE
ENCODE
6
DAC2
5
INTERNAL
TIMING
GND
ADC3
DIGITAL ERROR CORRECTION LOGIC
DMID
OVR
DRY
D13
MSB
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
02647-001
AIN
Figure 1.
Rev. E
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Tel: 781.329.4700 ©2002–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD6645
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Explanation of Test Levels ............................................................7
Applications ....................................................................................... 1
ESD Caution...................................................................................7
General Description ......................................................................... 1
Pin Configuration and Function Descriptions..............................8
Product Highlights ........................................................................... 1
Typical Performance Characteristics ..............................................9
Functional Block Diagram .............................................................. 1
Equivalent Circuits ......................................................................... 14
Revision History ............................................................................... 2
Terminology .................................................................................... 15
Specifications..................................................................................... 3
Theory of Operation ...................................................................... 17
DC Specifications ......................................................................... 3
Applying the AD6645 ................................................................ 17
Digital Specifications ................................................................... 4
Layout Information ........................................................................ 19
AC Specifications.......................................................................... 4
Jitter Considerations .................................................................. 19
Switching Specifications .............................................................. 5
Outline Dimensions ....................................................................... 24
Absolute Maximum Ratings ............................................................ 7
Ordering Guide .......................................................................... 24
Thermal Resistance ...................................................................... 7
REVISION HISTORY
9/2017—Rev. D to Rev. E
Changes to General Description and Product Highlights .......... 1
Changes to Operating Temperature Parameter, Table 5.............. 7
Changes to Table 6 ............................................................................ 7
Changes to Ordering Guide .......................................................... 24
10/2008—Rev. C to Rev. D
Added TQFP_EP Package ............................................ Throughout
Renamed Thermal Characteristics Section Thermal Resistance
Section ................................................................................................ 7
Added Table 6; Renumbered Sequentially .................................... 7
Moved Equivalent Circuits Section .............................................. 14
Moved Terminology Section ......................................................... 15
Changes to Table 9 .......................................................................... 20
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
7/2003—Rev. A to Rev. B.
Changes to Title ................................................................................1
Changes to Features ..........................................................................1
Changes to Product Description .....................................................1
Changes to Specifications .................................................................3
Changes to Absolute Maximum Ratings ........................................7
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions ....................................................... 20
6/2002—Rev. 0 to Rev. A.
Change to DC Specifications ...........................................................3
12/2006—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Specifications ................................................................ 3
Changes to Jitter Considerations Section .................................... 19
Changes to Table 8, Bill of Materials ............................................ 20
Changes to Figure 43, Evaluation Board Schematic .................. 21
Changes to Figure 44 and Figure 46............................................. 22
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
Rev. E | Page 2 of 24
Data Sheet
AD6645
SPECIFICATIONS
DC SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
POWER SUPPLY REJECTION RATIO
(PSRR)
REFERENCE OUT (VREF) 1
ANALOG INPUTS (AIN, AIN)
Differential Input Voltage Range
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
Supply Voltages
AVCC
DVCC
Supply Current
IAVCC (AVCC = 5.0 V)
IDVCC (DVCC = 3.3 V)
Rise Time 2
AVCC
POWER CONSUMPTION
Temp
Test Level
AD6645ASQ-80/AD6645ASV-80
Min
Typ
Max
14
Full
Full
Full
Full
Full
II
II
II
II
V
−10
−10
−1.0
Full
Full
25°C
V
V
V
1.5
48
±1.0
1.5
48
±1.0
ppm/°C
ppm/°C
mV/V
Full
V
2.4
2.4
V
Full
Full
25°C
V
V
2.2
1
1.5
2.2
1
1.5
V p-p
kΩ
pF
Full
Full
II
II
Full
Full
Full
Full
4.75
3.0
Guaranteed
+1.2
+10
0
+10
±0.25
+1.5
±0.5
5.0
3.3
5.25
3.6
II
II
275
32
IV
II
1.5
AD6645ASQ-105/AD6645ASV-105
Min
Typ
Max
14
−10
−10
−1.0
4.75
3.0
Guaranteed
+1.2
+10
0
+10
±0.5
+1.5
±1.5
Unit
Bits
mV
% FS
LSB
LSB
5.0
3.3
5.25
3.6
V
V
320
45
275
32
320
45
mA
mA
250
1.75
5.0
1.5
250
1.75
ms
W
VREF is provided for setting the common-mode offset of a differential amplifier, such as the AD8138, when a dc-coupled analog input is required. VREF should be
buffered if used to drive additional circuit functions.
2
Specified for dc supplies with linear rise time characteristics.
1
Rev. E | Page 3 of 24
AD6645
Data Sheet
DIGITAL SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted.
Table 2.
Parameter
ENCODE INPUTS (ENCODE, ENCODE)
Differential Input Voltage 1
Differential Input Resistance
Differential Input Capacitance
LOGIC OUTPUTS (D13 to D0, DRY, OVR)
Logic Compatibility
Logic 1 Voltage (DVCC = 3.3 V) 2
Logic 0 Voltage (DVCC = 3.3 V)2
Output Coding
DMID
1
2
Temp
Test
Level
AD6645ASQ-80/AD6645ASV-80
Min Typ
Max
AD6645ASQ-105/AD6645ASV-105
Min Typ
Max
Full
25°C
25°C
IV
V
V
0.4
0.4
Full
Full
II
II
2.85
Full
V
10
2.5
V p-p
kΩ
pF
10
2.5
CMOS
DVCC − 2
0.2
Twos complement
DVCC/2
2.85
0.5
Unit
CMOS
DVCC − 2
0.2
Twos complement
DVCC/2
0.5
V
V
V
All ac specifications tested by driving ENCODE and ENCODE differentially.
Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrades performance.
AC SPECIFICATIONS
All ac specifications tested by driving ENCODE and ENCODE differentially. AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and
TMAX at rated speed grade, unless otherwise noted.
Table 3.
Parameter
SNR
Analog Input @ −1 dBFS
SINAD
Analog Input @ −1 dBFS
WORST HARMONIC (SECOND OR THIRD)
Analog Input @ −1 dBFS
Temp
Test
Level
25°C
Full
25°C
Full
25°C
25°C
V
II
I
II
V
V
25°C
Full
25°C
Full
25°C
25°C
V
II
I
V
V
V
25°C
Full
25°C
Full
25°C
25°C
V
II
I
V
V
V
AD6645ASQ-80/
AD6645ASV-80
Min
Typ
Max
AD6645ASQ-105/
AD6645ASV-105
Min
Typ
Max
75.0
74.5
75.0
72.5
72.0
72.5
73.5
73.0
72.0
72.5
72.0
75.0
74.5
75.0
72.5
73.0
68.5
62.5
85.0
93.0
93.0
Rev. E | Page 4 of 24
74.5
73.0
67.5
62.5
93.1
85.0
89.0
70.0
63.5
74.5
73.5
73.0
72.0
93.0
87.0
70.0
63.5
Unit
Conditions
dB
dB
dB
dB
dB
dB
At 15.5 MHz
At 30.5 MHz
At 37.7 MHz
At 70.0 MHz
At 150.0 MHz
At 200.0 MHz
dB
dB
dB
dB
dB
dB
At 15.5 MHz
At 30.5 MHz
At 37.7 MHz
At 70.0 MHz
At 150.0 MHz
At 200.0 MHz
dBc
dBc
dBc
dBc
dBc
dBc
At 15.5 MHz
At 30.5 MHz
At 37.7 MHz
At 70.0 MHz
At 150.0 MHz
At 200.0 MHz
Data Sheet
AD6645
Parameter
WORST HARMONIC (FOURTH OR HIGHER)
Analog Input @ −1 dBFS
TWO-TONE SFDR
TWO-TONE IMD REJECTION2, 3
F1, F2 @ −7 dBFS
ANALOG INPUT BANDWIDTH
Temp
Test
Level
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
V
II
I
V
V
V
V
V
V
25°C
25°C
V
V
AD6645ASQ-80/
AD6645ASV-80
Min
Typ
Max
AD6645ASQ-105/
AD6645ASV-105
Min
Typ
Max
96.0
95.0
96.0
85.0
Unit
Conditions
At 15.5 MHz
At 30.5 MHz
At 37.7 MHz
At 70.0 MHz
At 150.0 MHz
At 200.0 MHz
At 30.5 MHz 1, 2
At 55.0 MHz1, 3
At 70.0 MHz1, 4
90.0
90.0
88.0
100
100
95.0
90.0
90.0
88.0
98.0
98.0
98.0
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
dBFS
90
270
90
270
dBc
MHz
86.0
Analog input signal power swept from −10 dBFS to −100 dBFS.
F1 = 30.5 MHz, F2 = 31.5 MHz.
3
F1 = 55.25 MHz, F2 = 56.25 MHz.
4
F1 = 69.1 MHz, F2 = 71.1 MHz.
1
2
SWITCHING SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless otherwise noted.
Table 4.
Parameter
ENCODE INPUT PARAMETERS 1
Maximum Conversion Rate
Minimum Conversion Rate
ENCODE Pulse Width High, tENCH 2
Symbol
Temp
Test
Level
tENC
Full
Full
Full
Full
Full
Full
Full
II
IV
IV
V
IV
V
V
Full
Full
Full
V
V
V
Full
Full
Full
Full
V
V
V
V
ENCODE Pulse Width Low, tENCL2
ENCODE Period1
ENCODE/DATA-READY
ENCODE Rising to Data-Ready Falling
ENCODE Rising to Data-Ready Rising
50% Duty Cycle
ENCODE/DATA (D13:0), OVR
ENCODE to DATA Falling Low
ENCODE to DATA Rising Low 3
ENCODE to DATA Delay3 (Hold Time)
ENCODE to DATA Delay (Setup Time)
tDR
tE_DR
tE_FL
tE_RL
tH_E
tS_E
AD6645ASQ-80/
AD6645ASV-80
Min
Typ
Max
AD6645ASQ-105/
AD6645ASV-105
Min
Typ
Max
80
105
30
5.625
30
4.286
6.25
4.75
5.625
4.286
6.25
12.5
1.0
7.3
2.4
1.4
1.4
tENC −
tE_FL(max)
4.75
9.5
2.0
tENCH + tDR
8.3
3.1
1.0
9.4
5.7
4.7
3.0
3.0
7.0
4.7
4.7
2.4
1.4
1.4
tENC −
tE_FL(max)
tENC −
tE_FL(typ)
50% Duty Cycle
Full
V
5.3
Rev. E | Page 5 of 24
7.6
2.0
tENCH + tDR
6.75
3.1
7.9
4.7
3.0
3.0
7.0
4.7
4.7
tENC −
tE_FL(typ)
tENC −
tE_FL(min)
10.0
2.3
4.8
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tENC −
tE_FL(min)
7.0
ns
ns
AD6645
Data Sheet
Parameter
DATA-READY (DRY 4)/DATA(D13:0),, OVR
Data-Ready to DATA Delay (Hold Time)
50% Duty Cycle
Data-Ready to DATA Delay (Setup Time)
50% Duty Cycle
APERTURE DELAY
APERTURE UNCERTAINTY (JITTER)
Symbol
Temp
Test
Level
tH_DR
Full
Full
Full
Full
25°C
25°C
V
V
V
V
V
V
tS_DR
tA
tJ
AD6645ASQ-80/
AD6645ASV-80
Min
Typ
Max
AD6645ASQ-105/
AD6645ASV-105
Min
Typ
Max
Note 5 5
7.2
Note 55
3.6
−500
0.1
Note 55
5.7
Note 55
2.1
−500
6.6
2.1
7.9
5.1
5.1
0.6
6.4
ns
3.5
ns
ps
ps rms
0.1
Several timing parameters are a function of tENC and tENCH.
Several timing parameters are a function of tENCL and tENCH.
ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the ADC, tE_RL = tH_E.
4
DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.
5
Data-ready to DATA Delay (tH_DR and tS_DR) is calculated relative to rated speed grade and is dependent on tENC and duty cycle.
1
2
3
tA
N+3
N
AIN
N+1
N+2
tE_RL
D[13:0], OVR
tENCH
tENC
N
tENCL
N+1
tE_FL
N+4
N+2
N+3
tE_DR
N–3
N–1
N–2
tS_DR
DRY
tDR
Figure 2. Timing Diagram
Rev. E | Page 6 of 24
N+4
tS_E
tH_E
N
tH_DR
02647-002
ENCODE,
ENCODE
Unit
Data Sheet
AD6645
ABSOLUTE MAXIMUM RATINGS
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order
approximation of TJ by the equation
Table 5.
Parameter
Electrical
AVCC Voltage
DVCC Voltage
Analog Input Voltage
Analog Input Current
Digital Input Voltage
Digital Output Current
Environmental
Operating Temperature Range (Ambient)
AD6645-80
AD6645-105
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
Rating
TJ = TA + (θJA × PD)
0 V to 7 V
0 V to 7 V
0 V to AVCC
25 mA
0 V to AVCC
4 mA
where:
TA is the ambient temperature (°C).
PD is the power dissipation (W).
EXPLANATION OF TEST LEVELS
−40°C to +85°C
−10°C to +85°C
150°C
300°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
I.
100% production tested.
II.
100% production tested at 25°C and guaranteed by design
and characterization at temperature extremes.
III.
Sample tested only.
IV.
Parameter is guaranteed by design and characterization
testing.
V.
Parameter is a typical value only.
ESD CAUTION
THERMAL RESISTANCE
The heat sink of the AD6645ASVZ, 52-lead TQFP_EP (SV-52-1)
package must be soldered to the PCB GND plane to meet thermal
specifications.
Table 6. Thermal Characteristics
Package Type
52-Lead TQFP_EP
θJA (0 m/sec airflow)1, 2, 3
θJMA (1.0 m/sec airflow)2, 3, 4, 5
θJC6, 7
Rating
23°C/W, soldered heat sink
17°C/W, soldered heat sink
2°C/W, soldered heat sink
Per JEDEC JESD51-2 (heat sink soldered to PCB).
2S2P JEDEC test board.
3
Values of θJA are provided for package comparison and PCB design
considerations.
4
Per JEDEC JESD51-6 (heat sink soldered to PCB).
5
Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the
more metal that is directly in contact with the package leads from metal
traces, throughholes, ground, and power planes, the more θJA is reduced.
6
Per MIL-STD-883, Method 1012.1.
7
Values of θJC are provided for package comparison and PCB design
considerations when an external heat sink is required.
1
2
Rev. E | Page 7 of 24
AD6645
Data Sheet
D4
D5
GND
DVCC
D6
D7
D8
D9
D10
D11
D12
D13 (MSB)
DRY
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
52 51 50 49 48 47 46 45 44 43 42 41 40
DVCC 1
39 D3
PIN 1
IDENTIFIER
GND 2
38 D2
VREF 3
37 D1
GND 4
36 D0 (LSB)
ENCODE 5
35 DMID
AD6645
ENCODE 6
AVCC 8
AVCC
34 GND
TOP VIEW
(Not to Scale)
GND 7
33 DVCC
32 OVR
31 DNC
9
GND 10
30 AVCC
AIN 11
29 GND
AIN 12
28 AVCC
GND 13
27 GND
NOTES
1. DNC = DO NOT CONNECT.
2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND.
02647-003
AVCC
GND
C2
GND
AVCC
GND
C1
GND
AVCC
GND
AVCC
GND
AVCC
14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin Number
1, 33, 43
2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25,
27, 29, 34, 42
3
5
6
8, 9, 14, 16, 18, 22, 26, 28, 30
11
12
20
24
31
32
35
36
37 to 41, 44 to 50
51
52
53 (EPAD)
Mnemonic
DVCC
GND
Description
3.3 V Power Supply (Digital) Output Stage Only.
Ground.
VREF
ENCODE
ENCODE
AVCC
AIN
AIN
C1
C2
DNC
OVR
DMID
D0 (LSB)
D1 to D5, D6 to D12
D13 (MSB)
DRY
Exposed Paddle (EPAD)
2.4 V Reference. Bypass to ground with a 0.1 µF microwave chip capacitor.
Encode Input. Conversion initiated on rising edge.
Complement of ENCODE, Differential Input.
5 V Analog Power Supply.
Analog Input.
Complement of AIN, Differential Analog Input.
Internal Voltage Reference. Bypass to ground with a 0.1 µF chip capacitor.
Internal Voltage Reference. Bypass to ground with a 0.1 µF chip capacitor.
Do not connect this pin.
Overrange Bit. A logic level high indicates analog input exceeds ±FS.
Output Data Voltage Midpoint. Approximately equal to (DVCC)/2.
Digital Output Bit (Least Significant Bit); Twos Complement.
Digital Output Bits in Twos Complement.
Digital Output Bit (Most Significant Bit); Twos Complement.
Data-Ready Output.
Exposed Pad. Connect the exposed pad to GND.
Rev. E | Page 8 of 24
Data Sheet
AD6645
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
ENCODE = 80MSPS
AIN = 2.2MHz @ –1dBFS
SNR = 75.0dB
SFDR = 93.0dBc
–10
–20
–30
–30
–40
–40
AMPLITUDE (dBFS)
–50
–60
–70
–80
–90
3
2
5
–100
6
4
–110
–60
–70
–80
–90
6
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
–130
0
5
–20
–30
–30
–40
–40
–50
–60
–70
–80
3
5
–100
6
–110
40
–60
3
–70
2
–80
–90
4
5
6
–110
–120
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
–130
0
5
–20
–40
AMPLITUDE (dBFS)
–30
–40
–50
–60
–70
–80
3
2
5
–100
35
40
40
ENCODE = 80MSPS
AIN = 200MHz @ –1dBFS
SNR = 72.0dB
SFDR = 64.0dBc
–10
–30
–90
30
0
ENCODE = 80MSPS
AIN = 29.5MHz @ –1dBFS
SNR = 74.5dB
SFDR = 93.0dBc
–20
15
20
25
FREQUENCY (MHz)
Figure 8. Single Tone @ 150 MHz
0
–10
10
02647-014
0
02647-011
–120
Figure 5. Single Tone @ 15.5 MHz
AMPLITUDE (dBFS)
35
–50
–100
2
4
30
ENCODE = 80MSPS
AIN = 150MHz @ –1dBFS
SNR = 73.0dB
SFDR = 70.0dBc
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
ENCODE = 80MSPS
AIN = 15.5MHz @ –1dBFS
SNR = 75.0dB
SFDR = 93.0dBc
–90
15
20
25
FREQUENCY (MHz)
Figure 7. Single Tone @ 69.1 MHz
0
–20
10
02647-013
0
02647-010
–120
–10
6
–50
–60
3
–70
2
–80
4
–90
6
5
–100
4
–110
–110
–120
–120
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
–130
02647-012
–130
4
5
–110
Figure 4. Single Tone @ 2.2 MHz
–130
3
2
–100
–120
–130
–50
02647-015
AMPLITUDE (dBFS)
–20
ENCODE = 80MSPS
AIN = 69.1MHz @ –1dBFS
SNR = 73.5dB
SFDR = 89.0dBc
–10
0
5
10
15
20
25
FREQUENCY (MHz)
30
Figure 9. Single Tone @ 200 MHz
Figure 6. Single Tone @ 29.5 MHz
Rev. E | Page 9 of 24
35
AD6645
Data Sheet
100
75.5
95
75.0
T = –40°C
HARMONICS (dBc)
T = +85°C
T = +25°C
73.5
73.0
85
80
HARMONICS
(SECOND, THIRD)
75
70
72.5
65
10
20
30
40
FREQUENCY (MHz)
50
60
70
02647-016
0
60
ENCODE = 80MSPS @ AIN = –1dBFS
TEMP = 25°C
0
20
Figure 10. Signal-to-Noise Ratio (SNR) vs. Frequency
180
200
T = –40°C, +85°C
88
86
84
ENCODE = 80MSPS @ AIN = –1dBFS
TEMP = –40°C, +25°C, +85°C
10
20
30
40
50
ANALOG INPUT FREQUENCY (MHz)
60
70
dBFS
100
90
80
ENCODE = 80MSPS
AIN = 30.5MHz
70
dBc
60
50
SFDR = 90dB
REFERENCE LINE
40
30
20
10
0
–90
02647-017
0
110
–80
Figure 11. Worst-Case Harmonics vs. Analog Input Frequency
–70
–60
–50
–40
–30
–20
ANALOG INPUT POWER LEVEL (dBFS)
–10
0
02647-020
WORST-CASE SPURIOUS (dBFS AND dBc)
WORST-CASE HARMONIC (dBc)
T = +25°C
90
82
Figure 14. Single-Tone SFDR @ 30.5 MHz
76
WORST CASE SPURIOUS (dBFS AND dBc)
120
75
74
73
72
71
ENCODE = 80MSPS @ AIN = –1dBFS
TEMP = 25°C
0
20
40
60
80
100 120 140
ANALOG FREQUENCY (MHz)
160
180
200
110
dBFS
100
90
80
ENCODE = 80MSPS
AIN = 69.1MHz
70
Figure 12. Signal-to-Noise Ratio (SNR) vs. Analog Frequency (IF)
dBc
60
50
SFDR = 90dB
REFERENCE LINE
40
30
20
10
0
–90
02647-018
SNR (dB)
160
120
92
70
60
80
100 120 140
ANALOG FREQUENCY (MHz)
Figure 13. Harmonics vs. Analog Frequency (IF)
94
80
40
02647-019
ENCODE = 80MSPS @ AIN = –1dBFS
TEMP = –40°C, +25°C, +85°C
–80
–70
–60
–50
–40
–30
–20
ANALOG INPUT POWER LEVEL (dBFS)
Figure 15. Single-Tone SFDR @ 69.1 MHz
Rev. E | Page 10 of 24
–10
0
02647-021
SNR (dB)
74.0
72.0
WORST OTHER SPUR
90
74.5
AD6645
0
ENCODE = 80MSPS
–10 AIN = 30.5MHz,
31.5MHz (–7dBFS)
–20 NO DITHER
–30
0
ENCODE = 80MSPS
–10 AIN = 55.25MHz,
56.25MHz (–7dBFS)
–20 NO DITHER
–40
–40
–50
–110
–120
–120
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
–130
02647-022
0
Figure 16. Two-Tone SFDR @ 30.5 MHz and 31.5 MHz
dBc
60
SFDR = 90dB
REFERENCE LINE
50
40
30
20
10
30
35
40
–67
–57
–47
–37
–27
–17
INPUT POWER LEVEL (F1 = F2 dBFS)
–7
100
dBFS
90
80
ENCODE = 80MSPS
F1 = 55.25MHz
F2 = 56.25MHz
70
dBc
60
SFDR = 90dB
REFERENCE LINE
50
40
30
20
10
0
–77
–67
–57
–47
–37
–27
–17
INPUT POWER LEVEL (F1 = F2 dBFS)
–7
Figure 20. Two-Tone SFDR @ 55.25 MHz and 56.25 MHz
Figure 17. Two-Tone SFDR @ 30.5 MHz and 31.5 MHz
95
SNR, WORST-CASE SPURIOUS (dB AND dBc)
100
WORST SPUR @ AIN = 2.2MHz
95
90
85
80
SNR @ AIN = 2.2MHz
75
30
45
60
75
ENCODE FREQUENCY (MHz)
90
105
02647-024
70
WORST SPUR @ AIN = 69.1MHz
90
85
80
75
SNR @ AIN = 69.1MHz
70
65
15
30
45
60
75
ENCODE FREQUENCY (MHz)
90
105
Figure 21. SNR, Worst-Case Spurious vs. Encode @ 69.1 MHz
Figure 18. SNR, Worst-Case Spurious vs. Encode @ 2.2 MHz
Rev. E | Page 11 of 24
02647-027
0
–77
SNR, WORST-CASE SPURIOUS (dB AND dBc)
15
20
25
FREQUENCY (MHz)
02647-026
WORST-CASE SPURIOUS (dBFS AND dBc)
ENCODE = 80MSPS
F1 = 30.5MHz
F2 = 31.5MHz
02647-023
WORST-CASE SPURIOUS (dBFS AND dBc)
dBFS
70
65
15
10
110
100
80
5
Figure 19. Two-Tone SFDR @ 55.25 MHz and 56.25 MHz
110
90
0
02647-025
–90
–100
2F1 – F2
–80
–110
–130
2F1 + F2
2F2 + F1
–70
2F2 – F1
–60
F1 + F2
–100
2F1 – F2
–90
F1 + F2
–80
2F1 + F2
2F2 + F1
–70
2F2 – F1
–60
F2 – F1
AMPLITUDE (dBFS)
–30
–50
F2 – F1
AMPLITUDE (dBFS)
Data Sheet
AD6645
–20
–30
–30
–40
–40
AMPLITUDE (dBFS)
–50
–60
–70
–80
2
–90
6
–100
–110
–60
–70
–80
–90
–100
4
3
5
–50
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
–130
02647-028
0
5
110
ENCODE = 80.0MSPS
AIN = 30.5MHz
NO DITHER
100
90
WORST-CASE SPURIOUS (dBc)
WORST-CASE SPURIOUS (dBc)
100
80
70
60
50
40
SFDR = 90dB
REFERENCE LINE
30
20
10
30
35
40
–10
0
ENCODE = 80.0MSPS
AIN = 30.5MHz
WITH DITHER @ –19.2dBm
90
80
70
60
SFDR = 100dB
REFERENCE LINE
50
40
SFDR = 90dB
REFERENCE LINE
30
20
80
70
60
50
40
30
20
ANALOG INPUT LEVEL (dBFS)
10
0
02647-029
10
0
90
0
–90
–80
Figure 23. SFDR Without Dither
0
–20
0
–40
AMPLITUDE (dBFS)
–30
–50
–60
–70
–80
3
5
2
6
–110
–50
–60
–70
–80
–90
–100
4
2
–110
–120
3
6
4
5
–120
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
02647-030
–130
ENCODE = 76.8MSPS
AIN = W-CDMA @ 69.1MHz
–20
–40
–100
–60
–50
–40
–30
–20
ANALOG INPUT LEVEL (dBFS)
–10
–30
–90
–70
Figure 26. SFDR with Dither
ENCODE = 76.8MSPS
AIN = 69.1MHz @ –1dBFS
SNR = 73.5dB
SFDR = 89.0dBc
–10
AMPLITUDE (dBFS)
15
20
25
FREQUENCY (MHz)
Figure 25. 1 M Sample FFT with Dither
Figure 22. 1 M Sample FFT Without Dither
110
10
02647-032
–130
6
3
5
–120
–120
4
2
–110
Figure 24. Single Tone @ 69.1 MHz, Encode = 76.8 MSPS
–130
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
Figure 27. W-CDMA Tone @ 69.1 MHz, Encode = 76.8 MSPS
Rev. E | Page 12 of 24
02647-033
AMPLITUDE (dBFS)
0
ENCODE = 80.0MSPS
–10 AIN = 30.5MHz @ –29.5dBFS
WITH DITHER @ –19.2 dBm
–20
ENCODE = 80.0MSPS
AIN = 30.5MHz @ –29.5dBFS
NO DITHER
–10
02647-031
0
Data Sheet
Data Sheet
AD6645
–20
–30
–30
–40
–40
AMPLITUDE (dBFS)
–20
–50
–60
–70
–80
–90
–60
–70
–80
–90
–100
–110
–110
–120
–120
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
–130
0
–30
–40
–40
AMPLITUDE (dBFS)
–20
–50
–60
–70
–80
–90
15
20
25
FREQUENCY (MHz)
30
35
40
ENCODE = 61.44MSPS
AIN = W-CDMA @ 190MHz
–70
–80
–90
–110
–120
–120
02647-035
–110
7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0
FREQUENCY (MHz)
3
–60
–100
5.0
2
–50
–100
2.5
10
0
–30
0
5
4
–10
–20
–130
5
Figure 30. W-CDMA Tone @ 140 MHz, Encode = 76.8 MSPS
ENCODE = 61.44MSPS
AIN = 4W-CDMA @ 46.08MHz
–10
0
6
Figure 29. Four W-CDMA Carriers @ 46.08 MHz, Encode = 61.44 MSPS
Rev. E | Page 13 of 24
–130
2
0
2.5
5.0
3
6
4
5
7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0
FREQUENCY (MHz)
Figure 31. W-CDMA Tone @ 190 MHz, Encode = 61.44 MSPS
02647-037
0
Figure 28. Two W-CDMA Carriers @ 59.6 MHz, Encode = 76.8 MSPS
AMPLITUDE (dBFS)
–50
–100
–130
ENCODE = 76.8MSPS
AIN = W-CDMA @ 140MHz
–10
02647-034
AMPLITUDE (dBFS)
0
ENCODE = 76.8MSPS
AIN = 2W-CDMA @ 59.6MHz
02647-036
0
–10
AD6645
Data Sheet
EQUIVALENT CIRCUITS
DVCC
VCH AVCC
AIN
CURRENT
MIRROR
T/H
BUF
500Ω
VCL
VREF
BUF
VCH AVCC
500Ω
T/H
BUF
DVCC
02647-004
AIN
VCL
D0 TO D13,
OVR, DRY
VREF
Figure 32. Analog Input Stage
LOADS
AVCC
AVCC
AVCC
AVCC
10kΩ
10kΩ
CURRENT
MIRROR
ENCODE
10kΩ
02647-007
ENCODE
10kΩ
Figure 35. Digital Output Stage
AVCC
02647-005
LOADS
Figure 33. Encode Inputs
AVCC
2.4V
VREF
AVCC
VREF
02647-008
100µA
Figure 36. 2.4 V Reference
AVCC
AVCC
DVCC
10kΩ
CURRENT
MIRROR
Figure 34. Compensation Pin, C1 or C2
10kΩ
02647-009
02647-006
DMID
C1, C2
Figure 37. DMID Reference
Rev. E | Page 14 of 24
Data Sheet
AD6645
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
encode command and the instant at which the analog input is
sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. The peak differential
voltage is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180° out of
phase. The peak-to-peak differential is computed by rotating the
inputs’ phase 180°and taking the peak measurement again. The
difference is then computed between both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
encode pulse should be left in a high state to achieve rated
performance; pulse width low is the minimum time that
the encode pulse should be left in a low state. See timing
implications of changing tENCH in Table 4. At a given clock rate,
these specifications define an acceptable encode duty cycle.
Full-Scale Input Power
The full-scale input power is expressed in dBm and can be
calculated by using the following equation:
V 2Full − Scale rms
Z Input
Power
= 10 log
Full − Scale
0.001
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Noise (for Any Range Within the ADC)
VNOISE =
− SNRdBc − SignaldBFS
FS
Z × 0.001 × 10 dBm
10
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below
full scale. This value includes both thermal noise and quantization noise.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio (PSSR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Power Supply Rise Time
The time from when the dc supply is initiated until the supply
output reaches the minimum specified operating voltage for the
ADC. The dc level is measured at the supply pin(s) of the ADC.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc.
Rev. E | Page 15 of 24
AD6645
Data Sheet
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may or may not be a harmonic. May be reported in dBc (that is,
degrades as signal level is lowered) or dBFS (always related back
to converter full scale).
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product, and may be reported in
dBc (that is, degrades as signal level is lowered) or in dBFS
(always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product, reported in dBc.
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonics), reported in dBc.
Rev. E | Page 16 of 24
Data Sheet
AD6645
CLOCK
SOURCE
The AD6645 ADC employs a three-stage subrange architecture.
This design approach achieves the required accuracy and speed
while maintaining low power and small die size.
Both analog inputs are buffered prior to the first track-and-hold,
TH1. The high state of the encode pulse places TH1 in hold
mode. The held value of TH1 is applied to the input of a 5-bit
coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter, DAC1. DAC1 requires 14 bits of precision
that is achieved through laser trimming. The output of DAC1 is
subtracted from the delayed analog signal at the input of TH3 to
generate a first residue signal. TH2 provides an analog pipeline
delay to compensate for the digital delay of ADC1.
The first residual signal is applied to a second conversion stage
consisting of a 5-bit ADC2, a 5-bit DAC2, and a pipeline TH4.
The second DAC requires 10 bits of precision, which is met by
the process with no trim. The input to TH5 is a second residual
signal generated by subtracting the quantized output of DAC2
from the first residual signal held by TH4. TH5 drives a final
6-bit ADC3.
The digital outputs from ADC1, ADC2, and ADC3 are added
together and corrected in the digital error correction logic to
generate the final output data. The result is a 14-bit parallel
digital CMOS-compatible word, coded as twos complement.
APPLYING THE AD6645
Encoding the AD6645
The AD6645 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Maintaining 14-bit accuracy places a premium on encode clock
phase noise. SNR performance can easily degrade by 3 dB to
4 dB with 70 MHz analog input signals when using a high jitter
clock source. See the AN-501 application note, Aperture
Uncertainty and ADC System Performance, for complete details.
For optimum performance, the AD6645 must be clocked
differentially. The encode signal is usually ac-coupled into the
ENCODE and ENCODE pins via a transformer or capacitors.
These pins are biased internally and require no additional bias.
Figure 38 shows one preferred method for clocking the AD6645.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit excessive amplitude
swings from the clock into the AD6645 to approximately 0.8 V p-p
differential. This helps to prevent the large voltage swings of the
clock from feeding through to other portions of the AD6645
and limits the noise presented to the encode inputs.
ENCODE
AD6645
HSMS2812
DIODES
ENCODE
Figure 38. Crystal Clock Oscillator, Differential Encode
If a low jitter clock is available, another option is to ac-couple a
differential ECL/PECL signal to the encode input pins, as
shown in Figure 39. The MC100EL16 (or same family) from
ON Semiconductor offers excellent jitter performance.
VT
0.1µF
ENCODE
ECL/
PECL
AD6645
0.1µF
ENCODE
VT
02647-039
As shown in the functional block diagram (see Figure 1), the
AD6645 has complementary analog input pins, AIN and AIN.
Each analog input is centered at 2.4 V and should swing ±0.55 V
around this reference (see Figure 32). Because AIN and AIN are
180° out of phase, the differential analog input signal is 2.2 V p-p.
T1-4T
0.1µF
02647-038
THEORY OF OPERATION
Figure 39. Differential ECL for Encode
Driving the Analog Inputs
As with most new high speed, high dynamic range ADCs, the
analog input to the AD6645 is differential. Differential inputs
improve on-chip performance as signals are processed through
attenuation and gain stages. Most of the improvement is a result
of differential analog stages having high rejection of even-order
harmonics. There are also benefits at the PCB level. First,
differential inputs have high common-mode rejection of stray
signals, such as ground and power noise. Second, they provide
good rejection of common-mode signals, such as local oscillator
feedthrough.
The AD6645 analog input voltage range is offset from ground
by 2.4 V. Each analog input connects through a 500 Ω resistor to
the 2.4 V bias voltage and to the input of a differential buffer (see
Figure 32). The resistor network on the input properly biases the
followers for maximum linearity and range. Therefore, the analog
source driving the AD6645 should be ac-coupled to the input pins.
Because the differential input impedance of the AD6645 is 1 kΩ,
the analog input power requirement is only −2 dBm, simplifying
the driver amplifier in many cases. To take full advantage of this
high input impedance, a 20:1 RF transformer is required. This is a
large ratio and can result in unsatisfactory performance. In this
case, a lower step-up ratio can be used. The recommended method
for driving the differential analog input of the AD6645 is to use
a 4:1 RF transformer. For example, if RT is set to 60.4 Ω and RS is set
to 25 Ω, along with a 4:1 impedance ratio transformer, the input
would match to a 50 Ω source with a full-scale drive of 4.8 dBm.
Series resistors (RS) on the secondary side of the transformer
should be used to isolate the transformer from the A/D.
Rev. E | Page 17 of 24
AD6645
Data Sheet
This limits the amount of dynamic current from the A/D
flowing back into the secondary of the transformer. The 50 Ω
impedance matching can also be incorporated on the secondary
side of the transformer, as shown in the evaluation board
schematic (see Figure 43).
RS
ADT4-1WT
AIN
RT
RS
AD6645
AIN
0.1µF
02647-040
ANALOG INPUT
SIGNAL
Figure 40. Transformer-Coupled Analog Input Circuit
In applications where dc coupling is required, a differential
output op amp, such as the AD8138, can be used to drive the
AD6645 (see Figure 41). The AD8138 op amp provides singleended-to-differential conversion, which reduces overall system
cost and minimizes layout requirements.
CF
Grounding
5V
499Ω
VIN
499Ω
VOCM
To minimize capacitive loading, there should be only one gate
on each output pin. An example of this is shown in the evaluation
board schematic of Figure 43. The digital outputs of the AD6645
have a constant output slew rate of 1 V/ns. A typical CMOS gate
combined with a PCB trace have a load of approximately 10 pF.
Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns)of
dynamic current per bit flow in or out of the device. A full-scale
transition can cause up to 140 mA (14 bits ×10 mA/bit) of current
to flow through the output stages. Place the series resistors as close
to the AD6645 as possible to limit the amount of current that can
flow into the output stage. These switching currents are confined
between ground and DVCC. Standard TTL gates should be avoided
because they can add appreciably to the dynamic switching
currents of the AD6645. Note that extra capacitive loading
increases output timing and invalidates timing specifications.
Digital output timing is guaranteed for output loads up to
10 pF. Digital output states for given analog input levels are
shown in Table 8.
25Ω
AD8138
AD6645
25Ω
499Ω
AIN
AIN
VREF
DIGITAL
OUTPUTS
02647-041
499Ω
CF
Figure 41. DC-Coupled Analog Input Circuit
Power Supplies
Care should be taken when selecting a power source. The use of
linear dc supplies with rise times of
